hpm_qeiv2_drv.h

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/*
 * Copyright (c) 2023-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_QEIV2_DRV_H
#define HPM_QEIV2_DRV_H
 
#include "hpm_common.h"
#include "hpm_soc_ip_feature.h"
#include "hpm_qeiv2_regs.h"
#define QEIV2_EVENT_WDOG_FLAG_MASK              (1U << 31U) 
#define QEIV2_EVENT_HOME_FLAG_MASK              (1U << 30U) 
#define QEIV2_EVENT_POSITION_COMPARE_FLAG_MASK  (1U << 29U) 
#define QEIV2_EVENT_Z_PHASE_FLAG_MASK           (1U << 28U) 
#define QEIV2_EVENT_Z_MISS_FLAG_MASK            (1U << 27U) 
#define QEIV2_EVENT_WIDTH_TIME_FLAG_MASK        (1U << 26U) 
#define QEIV2_EVENT_POSITION2_COMPARE_FLAG_MASK (1U << 25U) 
#define QEIV2_EVENT_DIR_CHG_FLAG_MASK           (1U << 24U) 
#define QEIV2_EVENT_CYCLE0_FLAG_MASK            (1U << 23U) 
#define QEIV2_EVENT_CYCLE1_FLAG_MASK            (1U << 22U) 
#define QEIV2_EVENT_PULSE0_FLAG_MASK            (1U << 21U) 
#define QEIV2_EVENT_PULSE1_FLAG_MASK            (1U << 20U) 
#define QEIV2_EVENT_HOME2_FLAG_MASK             (1U << 19U) 
#define QEIV2_EVENT_FAULT_FLAG_MASK             (1U << 18U) 
typedef enum qeiv2_work_mode {
    qeiv2_work_mode_abz    = 0, 
    qeiv2_work_mode_pd     = 1, 
    qeiv2_work_mode_ud     = 2, 
    qeiv2_work_mode_uvw    = 3, 
    qeiv2_work_mode_single = 4, 
    qeiv2_work_mode_sin    = 5, 
    qeiv2_work_mode_sincos = 6, 
} qeiv2_work_mode_t;
 
typedef enum qeiv2_spd_tmr_content {
    qeiv2_spd_tmr_as_spd_tm    = 0, 
    qeiv2_spd_tmr_as_pos_angle = 1, 
} qeiv2_spd_tmr_content_t;
 
typedef enum qeiv2_rotate_dir {
    qeiv2_rotate_dir_forward = 0,
    qeiv2_rotate_dir_reverse = 1,
} qeiv2_rotate_dir_t;     
typedef enum qeiv2_position_dir {
    qeiv2_pos_dir_decrease = 0,
    qeiv2_pos_dir_increase = 1,
} qeiv2_position_dir_t;     
typedef enum qeiv2_z_count_work_mode {
    qeiv2_z_count_inc_on_z_input_assert  = 0, 
    qeiv2_z_count_inc_on_phase_count_max = 1, 
} qeiv2_z_count_work_mode_t;
 
typedef enum qeiv2_counter_type {
    qeiv2_counter_type_z     = 0, 
    qeiv2_counter_type_phase = 1, 
    qeiv2_counter_type_speed = 2, 
    qeiv2_counter_type_timer = 3, 
} qeiv2_counter_type_t;
 
typedef enum qeiv2_filter_mode {
    qeiv2_filter_mode_bypass = 0, 
    qeiv2_filter_mode_burr   = 4, 
    qeiv2_filter_mode_delay,      
    qeiv2_filter_mode_peak,       
    qeiv2_filter_mode_valley,     
} qeiv2_filter_mode_t;
 
typedef enum qeiv2_filter_phase {
    qeiv2_filter_phase_a = 0, 
    qeiv2_filter_phase_b,     
    qeiv2_filter_phase_z,     
    qeiv2_filter_phase_h,     
    qeiv2_filter_phase_h2,    
    qeiv2_filter_phase_f,     
} qeiv2_filter_phase_t;       
typedef enum qeiv2_uvw_pos_opt {
    qeiv2_uvw_pos_opt_current = 0,   
    qeiv2_uvw_pos_opt_next,          
} qeiv2_uvw_pos_opt_t;
 
typedef enum qeiv2_uvw_pos_sel {
    qeiv2_uvw_pos_sel_low = 0,
    qeiv2_uvw_pos_sel_high,
    qeiv2_uvw_pos_sel_edge
} qeiv2_uvw_pos_sel_t;       
#define QEIV2_UVW_POS_OPT_CUR_SEL_LOW                  0u
#define QEIV2_UVW_POS_OPT_CUR_SEL_HIGH                 1u
#define QEIV2_UVW_POS_OPT_CUR_SEL_EDGE                 2u
#define QEIV2_UVW_POS_OPT_NEX_SEL_LOW                  0u
#define QEIV2_UVW_POS_OPT_NEX_SEL_HIGH                 3u
 
typedef enum qeiv2_uvw_pos_idx {
    qeiv2_uvw_pos0 = 0,
    qeiv2_uvw_pos1,
    qeiv2_uvw_pos2,
    qeiv2_uvw_pos3,
    qeiv2_uvw_pos4,
    qeiv2_uvw_pos5,
} qeiv2_uvw_pos_idx_t;       
#if defined(HPM_IP_FEATURE_QEIV2_ADC_SW_INJECT) && HPM_IP_FEATURE_QEIV2_ADC_SW_INJECT
typedef enum qeiv2_adc_sw_inject_en {
    qeiv2_sw_inject_adcx = QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_MASK,
    qeiv2_sw_inject_adcx_adcy = QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_MASK | QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_MASK,
} qeiv2_adc_sw_inject_en_t;       
#endif
 
typedef struct {
    uint32_t phcnt_cmp_value;
    bool ignore_rotate_dir;
    qeiv2_rotate_dir_t rotate_dir;
    bool ignore_zcmp;
    uint32_t zcmp_value;
} qeiv2_phcnt_cmp_match_config_t;
 
typedef struct {
    uint32_t pos_cmp_value;
    bool ignore_pos_dir;
    qeiv2_position_dir_t pos_dir;
} qeiv2_pos_cmp_match_config_t;
 
typedef struct {
    qeiv2_uvw_pos_opt_t pos_opt;
    qeiv2_uvw_pos_sel_t u_pos_sel[6];
    qeiv2_uvw_pos_sel_t v_pos_sel[6];
    qeiv2_uvw_pos_sel_t w_pos_sel[6];
    uint32_t pos_cfg[6];
} qeiv2_uvw_config_t;
 
typedef struct {
    uint8_t adc_select;
    uint8_t adc_channel;
    int16_t param0;
    int16_t param1;
    uint32_t offset;
} qeiv2_adc_config_t;
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void qeiv2_load_counter_to_read_registers(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->CR |= QEIV2_CR_READ_MASK;
}
 
static inline void qeiv2_config_z_phase_counter_mode(QEIV2_Type *qeiv2_x, qeiv2_z_count_work_mode_t mode)
{
    qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ZCNTCFG_MASK) | QEIV2_CR_ZCNTCFG_SET(mode);
}
 
static inline void qeiv2_config_phmax_phparam(QEIV2_Type *qeiv2_x, uint32_t phmax)
{
    uint32_t tmp;
 
    if (phmax > 0u) {
        phmax--;
    }
    qeiv2_x->PHCFG = QEIV2_PHCFG_PHMAX_SET(phmax);
    if (phmax == 0u) {
        qeiv2_x->PHASE_PARAM = 0xFFFFFFFFu;
    } else {
        tmp = (0x80000000u / (phmax + 1u));
        tmp <<= 1u;
        qeiv2_x->PHASE_PARAM = QEIV2_PHASE_PARAM_PHASE_PARAM_SET(tmp);
    }
}
 
static inline void qeiv2_config_z_phase_calibration(QEIV2_Type *qeiv2_x, uint32_t phidx, bool enable, qeiv2_work_mode_t mode)
{
    uint32_t tmp = qeiv2_x->CR;
    qeiv2_x->PHIDX = QEIV2_PHIDX_PHIDX_SET(phidx);
    if (enable) {
        tmp |= QEIV2_CR_PHCALIZ_MASK;
    } else {
        tmp &= ~QEIV2_CR_PHCALIZ_MASK;
    }
    if (enable && ((mode == qeiv2_work_mode_sin) || (mode == qeiv2_work_mode_sincos))) {
        tmp |= QEIV2_CR_Z_ONLY_EN_MASK;
    } else {
        tmp &= ~QEIV2_CR_Z_ONLY_EN_MASK;
    }
    qeiv2_x->CR = tmp;
}
 
static inline void qeiv2_pause_counter(QEIV2_Type *qeiv2_x, uint32_t counter_mask, bool enable)
{
    if (enable) {
        qeiv2_x->CR |= counter_mask;
    } else {
        qeiv2_x->CR &= ~counter_mask;
    }
}
 
static inline void qeiv2_pause_pos_counter_on_fault(QEIV2_Type *qeiv2_x, bool enable)
{
    if (enable) {
        qeiv2_x->CR |= QEIV2_CR_FAULTPOS_MASK;
    } else {
        qeiv2_x->CR &= ~QEIV2_CR_FAULTPOS_MASK;
    }
}
 
static inline void qeiv2_enable_snap(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->CR |= QEIV2_CR_SNAPEN_MASK;
}
 
static inline void qeiv2_disable_snap(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->CR &= ~QEIV2_CR_SNAPEN_MASK;
}
 
static inline void qeiv2_reset_counter(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->CR |= QEIV2_CR_RSTCNT_MASK;
}
 
static inline void qeiv2_release_counter(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->CR &= ~QEIV2_CR_RSTCNT_MASK;
}
 
static inline void qeiv2_select_spd_tmr_register_content(QEIV2_Type *qeiv2_x, qeiv2_spd_tmr_content_t content)
{
    qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_RD_SEL_MASK) | QEIV2_CR_RD_SEL_SET(content);
}
 
static inline bool qeiv2_check_spd_tmr_as_pos_angle(QEIV2_Type *qeiv2_x)
{
    return ((qeiv2_x->CR & QEIV2_CR_RD_SEL_MASK) != 0) ? true : false;
}
 
static inline void qeiv2_set_work_mode(QEIV2_Type *qeiv2_x, qeiv2_work_mode_t mode)
{
    qeiv2_x->CR = (qeiv2_x->CR & ~QEIV2_CR_ENCTYP_MASK) | QEIV2_CR_ENCTYP_SET(mode);
}
 
static inline void qeiv2_config_wdog(QEIV2_Type *qeiv2_x, uint32_t timeout, uint8_t clr_phcnt, bool enable)
{
    uint32_t tmp;
    tmp = QEIV2_WDGCFG_WDGTO_SET(timeout) | QEIV2_WDGCFG_WDOG_CFG_SET(clr_phcnt);
    if (enable) {
        tmp |= QEIV2_WDGCFG_WDGEN_MASK;
    } else {
        tmp &= ~QEIV2_WDGCFG_WDGEN_MASK;
    }
    qeiv2_x->WDGCFG = tmp;
}
 
static inline void qeiv2_enable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
{
    qeiv2_x->TRGOEN |= event_mask;
}
 
static inline void qeiv2_disable_trig_out_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
{
    qeiv2_x->TRGOEN &= ~event_mask;
}
 
static inline void qeiv2_enable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
{
    qeiv2_x->READEN |= event_mask;
}
 
static inline void qeiv2_disable_load_read_trigger_event(QEIV2_Type *qeiv2_x, uint32_t event_mask)
{
    qeiv2_x->READEN &= ~event_mask;
}
 
static inline void qeiv2_enable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask)
{
    qeiv2_x->DMAEN |= mask;
}
 
static inline void qeiv2_disable_dma_request(QEIV2_Type *qeiv2_x, uint32_t mask)
{
    qeiv2_x->DMAEN &= ~mask;
}
 
static inline void qeiv2_clear_status(QEIV2_Type *qeiv2_x, uint32_t mask)
{
    qeiv2_x->SR = mask;
}
 
static inline uint32_t qeiv2_get_status(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->SR;
}
 
static inline bool qeiv2_get_bit_status(QEIV2_Type *qeiv2_x, uint32_t mask)
{
    return ((qeiv2_x->SR & mask) == mask) ? true : false;
}
 
static inline void qeiv2_enable_irq(QEIV2_Type *qeiv2_x, uint32_t mask)
{
    qeiv2_x->IRQEN |= mask;
}
 
static inline void qeiv2_disable_irq(QEIV2_Type *qeiv2_x, uint32_t mask)
{
    qeiv2_x->IRQEN &= ~mask;
}
 
static inline uint32_t qeiv2_get_current_count(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
{
    return *(&qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z + type);
}
 
static inline uint32_t qeiv2_get_current_phase_phcnt(QEIV2_Type *qeiv2_x)
{
    return QEIV2_COUNT_PH_PHCNT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
}
 
static inline bool qeiv2_get_current_phase_a_level(QEIV2_Type *qeiv2_x)
{
    return QEIV2_COUNT_PH_ASTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
}
 
static inline bool qeiv2_get_current_phase_b_level(QEIV2_Type *qeiv2_x)
{
    return QEIV2_COUNT_PH_BSTAT_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
}
 
static inline bool qeiv2_get_current_phase_dir(QEIV2_Type *qeiv2_x)
{
    return QEIV2_COUNT_PH_DIR_GET(qeiv2_get_current_count(qeiv2_x, qeiv2_counter_type_phase));
}
 
 
static inline uint32_t qeiv2_get_count_on_read_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
{
    return *(&(qeiv2_x->COUNT[QEIV2_COUNT_READ].Z) + type);
}
 
static inline uint32_t qeiv2_get_count_on_snap0_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
{
    return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP0].Z + type);
}
 
static inline uint32_t qeiv2_get_count_on_snap1_event(QEIV2_Type *qeiv2_x, qeiv2_counter_type_t type)
{
    return *(&qeiv2_x->COUNT[QEIV2_COUNT_SNAP1].Z + type);
}
 
static inline void qeiv2_set_z_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
{
    qeiv2_x->ZCMP = QEIV2_ZCMP_ZCMP_SET(cmp);
}
 
static inline void qeiv2_set_phcnt_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
{
    qeiv2_x->PHCMP = QEIV2_PHCMP_PHCMP_SET(cmp);
}
 
static inline void qeiv2_set_spd_pos_cmp_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
{
    qeiv2_x->SPDCMP = QEIV2_SPDCMP_SPDCMP_SET(cmp);
}
 
static inline void qeiv2_set_cmp_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp,
                                        bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir)
{
    qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & (~(QEIV2_MATCH_CFG_ZCMPDIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK | QEIV2_MATCH_CFG_SPDCMPDIS_MASK
                                                | QEIV2_MATCH_CFG_DIRCMPDIS_MASK | QEIV2_MATCH_CFG_DIRCMP_MASK
                                                | QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK)))
                        | QEIV2_MATCH_CFG_ZCMPDIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(ignore_phcmp)
                        | QEIV2_MATCH_CFG_SPDCMPDIS_SET(ignore_spdposcmp)
                        | QEIV2_MATCH_CFG_DIRCMPDIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP_SET(rotate_dir)
                        | QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(pos_dir);
}
 
static inline void qeiv2_set_z_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
{
    qeiv2_x->ZCMP2 = QEIV2_ZCMP2_ZCMP2_SET(cmp);
}
 
static inline void qeiv2_set_phcnt_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
{
    qeiv2_x->PHCMP2 = QEIV2_PHCMP2_PHCMP2_SET(cmp);
}
 
static inline void qeiv2_set_spd_pos_cmp2_value(QEIV2_Type *qeiv2_x, uint32_t cmp)
{
    qeiv2_x->SPDCMP2 = QEIV2_SPDCMP2_SPDCMP2_SET(cmp);
}
 
static inline void qeiv2_set_cmp2_match_option(QEIV2_Type *qeiv2_x, bool ignore_zcmp, bool ignore_phcmp, bool ignore_spdposcmp,
                                        bool ignore_rotate_dir, qeiv2_rotate_dir_t rotate_dir, bool ignore_pos_dir, qeiv2_position_dir_t pos_dir)
{
    qeiv2_x->MATCH_CFG = (qeiv2_x->MATCH_CFG & ~(QEIV2_MATCH_CFG_ZCMP2DIS_MASK | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK | QEIV2_MATCH_CFG_SPDCMP2DIS_MASK
                                               | QEIV2_MATCH_CFG_DIRCMP2DIS_MASK | QEIV2_MATCH_CFG_DIRCMP2_MASK
                                               | QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK | QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK))
                        | QEIV2_MATCH_CFG_ZCMP2DIS_SET(ignore_zcmp) | QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(ignore_phcmp)
                        | QEIV2_MATCH_CFG_SPDCMP2DIS_SET(ignore_spdposcmp)
                        | QEIV2_MATCH_CFG_DIRCMP2DIS_SET(ignore_rotate_dir) | QEIV2_MATCH_CFG_DIRCMP2_SET(rotate_dir)
                        | QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(!ignore_pos_dir) | QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(pos_dir);
}
 
static inline void qeiv2_config_abz_uvw_signal_edge(QEIV2_Type *qeiv2_x, bool siga_en, bool sigb_en, bool sigz_en, bool posedge_en, bool negedge_en)
{
    qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~(QEIV2_QEI_CFG_SIGA_EN_MASK | QEIV2_QEI_CFG_SIGB_EN_MASK | QEIV2_QEI_CFG_SIGZ_EN_MASK
                                           | QEIV2_QEI_CFG_POSIDGE_EN_MASK | QEIV2_QEI_CFG_NEGEDGE_EN_MASK))
                     | (QEIV2_QEI_CFG_SIGA_EN_SET(siga_en) | QEIV2_QEI_CFG_SIGB_EN_SET(sigb_en) | QEIV2_QEI_CFG_SIGZ_EN_SET(sigz_en)
                     | QEIV2_QEI_CFG_POSIDGE_EN_SET(posedge_en) | QEIV2_QEI_CFG_NEGEDGE_EN_SET(negedge_en));
}
 
static inline void qeiv2_set_pulse0_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num)
{
    qeiv2_x->PULSE0_NUM = QEIV2_PULSE0_NUM_PULSE0_NUM_SET(pulse_num);
}
 
static inline uint32_t qeiv2_get_pulse0_cycle_snap0(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->CYCLE0_SNAP0;
}
 
static inline uint32_t qeiv2_get_pulse0_cycle_snap1(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->CYCLE0_SNAP1;
}
 
static inline void qeiv2_set_pulse1_num(QEIV2_Type *qeiv2_x, uint32_t pulse_num)
{
    qeiv2_x->PULSE1_NUM = QEIV2_PULSE1_NUM_PULSE1_NUM_SET(pulse_num);
}
 
static inline uint32_t qeiv2_get_pulse1_cycle_snap0(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->CYCLE1_SNAP0;
}
 
static inline uint32_t qeiv2_get_pulse1_cycle_snap1(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->CYCLE1_SNAP1;
}
 
static inline void qeiv2_set_cycle0_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num)
{
    qeiv2_x->CYCLE0_NUM = QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(cycle_num);
}
 
static inline uint32_t qeiv2_get_cycle0_pulse_snap0(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE0_SNAP0;
}
 
static inline uint32_t qeiv2_get_cycle0_pulse_snap1(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE0_SNAP1;
}
 
static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap0(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE0CYCLE_SNAP0;
}
 
static inline uint32_t qeiv2_get_cycle0_pulse0cycle_snap1(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE0CYCLE_SNAP1;
}
 
static inline void qeiv2_set_cycle1_num(QEIV2_Type *qeiv2_x, uint32_t cycle_num)
{
    qeiv2_x->CYCLE1_NUM = QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(cycle_num);
}
 
#if defined(HPM_IP_FEATURE_QEIV2_ONESHOT_MODE) && HPM_IP_FEATURE_QEIV2_ONESHOT_MODE
static inline void qeiv2_disable_cycle0_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK;
}
 
static inline void qeiv2_enable_cycle0_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK;
}
 
static inline void qeiv2_disable_cycle1_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK;
}
 
static inline void qeiv2_enable_cycle1_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK;
}
 
static inline void qeiv2_disable_pulse0_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK;
}
 
static inline void qeiv2_enable_pulse0_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK;
}
 
static inline void qeiv2_disable_pulse1_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK;
}
 
static inline void qeiv2_enable_pulse1_oneshot_mode(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK;
}
#endif
 
#if defined(HPM_IP_FEATURE_QEIV2_SW_RESTART_TRG) && HPM_IP_FEATURE_QEIV2_SW_RESTART_TRG
static inline void qeiv2_disable_trig_cycle0(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK;
}
 
static inline void qeiv2_enable_trig_cycle0(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK;
}
 
static inline void qeiv2_disable_trig_cycle1(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK;
}
 
static inline void qeiv2_enable_trig_cycle1(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK;
}
 
static inline void qeiv2_disable_trig_pulse0(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK;
}
 
static inline void qeiv2_enable_trig_pulse0(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK;
}
 
static inline void qeiv2_disable_trig_pulse1(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK;
}
 
static inline void qeiv2_enable_trig_pulse1(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK;
}
 
static inline void qeiv2_sw_restart_cycle0(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK;
}
 
static inline void qeiv2_sw_restart_cycle1(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK;
}
 
static inline void qeiv2_sw_restart_pulse0(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK;
}
 
static inline void qeiv2_sw_restart_pulse1(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK;
}
#endif
 
static inline uint32_t qeiv2_get_cycle1_pulse_snap0(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE1_SNAP0;
}
 
static inline uint32_t qeiv2_get_cycle1_pulse_snap1(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE1_SNAP1;
}
 
static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap0(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE1CYCLE_SNAP0;
}
 
static inline uint32_t qeiv2_get_cycle1_pulse1cycle_snap1(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PULSE1CYCLE_SNAP1;
}
 
static inline void qeiv2_clear_counter_when_dir_chg(QEIV2_Type *qeiv2_x, bool enable)
{
    if (enable) {
        qeiv2_x->QEI_CFG |= QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK;
    } else {
        qeiv2_x->QEI_CFG &= ~QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK;
    }
}
 
static inline void qeiv2_config_adcx(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable)
{
    uint32_t tmp;
    tmp = QEIV2_ADCX_CFG0_X_ADCSEL_SET(config->adc_select) | QEIV2_ADCX_CFG0_X_CHAN_SET(config->adc_channel);
    qeiv2_x->ADCX_CFG1 = QEIV2_ADCX_CFG1_X_PARAM1_SET(config->param1) | QEIV2_ADCX_CFG1_X_PARAM0_SET(config->param0);
    qeiv2_x->ADCX_CFG2 = QEIV2_ADCX_CFG2_X_OFFSET_SET(config->offset);
    if (enable) {
        tmp |= QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK;
    } else {
        tmp &= ~QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK;
    }
    qeiv2_x->ADCX_CFG0 = tmp;
}
 
static inline void qeiv2_config_adcy(QEIV2_Type *qeiv2_x, qeiv2_adc_config_t *config, bool enable)
{
    uint32_t tmp;
    tmp = QEIV2_ADCY_CFG0_Y_ADCSEL_SET(config->adc_select) | QEIV2_ADCY_CFG0_Y_CHAN_SET(config->adc_channel);
    qeiv2_x->ADCY_CFG1 = QEIV2_ADCY_CFG1_Y_PARAM1_SET(config->param1) | QEIV2_ADCY_CFG1_Y_PARAM0_SET(config->param0);
    qeiv2_x->ADCY_CFG2 = QEIV2_ADCY_CFG2_Y_OFFSET_SET(config->offset);
    if (enable) {
        tmp |= QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK;
    } else {
        tmp &= ~QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK;
    }
    qeiv2_x->ADCY_CFG0 = tmp;
}
 
void qeiv2_config_adcx_adcy_param(QEIV2_Type *qeiv2_x, float tan_delta, float cos_delta, float x_magnification, float y_magnification);
 
static inline void qeiv2_set_adc_xy_delay(QEIV2_Type *qeiv2_x, uint32_t delay)
{
    qeiv2_x->CAL_CFG = QEIV2_CAL_CFG_XY_DELAY_SET(delay);
}
 
static inline void qeiv2_set_position_threshold(QEIV2_Type *qeiv2_x, uint32_t threshold)
{
    qeiv2_x->POS_THRESHOLD = QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(threshold);
}
 
static inline void qeiv2_set_uvw_position_opt(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_opt_t opt)
{
    qeiv2_x->QEI_CFG = (qeiv2_x->QEI_CFG & ~QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) | QEIV2_QEI_CFG_UVW_POS_OPT0_SET(opt);
}
 
static inline void qeiv2_set_uvw_position_sel(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint8_t u_pos_sel, uint8_t v_pos_sel,
                                             uint8_t w_pos_sel, bool enable)
{
    uint32_t tmp;
    tmp = QEIV2_UVW_POS_CFG_U_POS_SEL_SET(u_pos_sel)
        | QEIV2_UVW_POS_CFG_V_POS_SEL_SET(v_pos_sel)
        | QEIV2_UVW_POS_CFG_W_POS_SEL_SET(w_pos_sel);
    if (enable) {
        tmp |= QEIV2_UVW_POS_CFG_POS_EN_MASK;
    } else {
        tmp &= ~QEIV2_UVW_POS_CFG_POS_EN_MASK;
    }
    qeiv2_x->UVW_POS_CFG[idx] = tmp;
}
 
static inline void qeiv2_set_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_pos_idx_t idx, uint32_t pos)
{
    qeiv2_x->UVW_POS[idx] = pos;
}
 
static inline void qeiv2_set_z_phase(QEIV2_Type *qeiv2_x, uint32_t cnt)
{
    qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z = cnt;
}
 
static inline uint32_t qeiv2_get_z_phase(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->COUNT[QEIV2_COUNT_CURRENT].Z;
}
 
static inline void qeiv2_set_phase_cnt(QEIV2_Type *qeiv2_x, uint32_t cnt)
{
    qeiv2_x->PHASE_CNT = cnt;
}
 
static inline uint32_t qeiv2_get_phase_cnt(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->PHASE_CNT;
}
 
static inline void qeiv2_update_phase_cnt(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value)
{
    qeiv2_x->PHASE_UPDATE = QEIV2_PHASE_UPDATE_INC_SET(inc) | QEIV2_PHASE_UPDATE_DEC_SET(dec) | QEIV2_PHASE_UPDATE_VALUE_SET(value);
}
 
static inline void qeiv2_set_position(QEIV2_Type *qeiv2_x, uint32_t pos)
{
    qeiv2_x->POSITION = pos;
}
 
static inline uint32_t qeiv2_get_postion(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->POSITION;
}
 
static inline void qeiv2_update_position(QEIV2_Type *qeiv2_x, bool inc, bool dec, uint32_t value)
{
    qeiv2_x->POSITION_UPDATE = QEIV2_POSITION_UPDATE_INC_SET(inc) | QEIV2_POSITION_UPDATE_DEC_SET(dec) | QEIV2_POSITION_UPDATE_VALUE_SET(value);
}
 
static inline uint32_t qeiv2_get_angle(QEIV2_Type *qeiv2_x)
{
    return qeiv2_x->ANGLE;
}
 
static inline void qeiv2_config_position_timeout(QEIV2_Type *qeiv2_x, uint32_t tm, bool enable)
{
    uint32_t tmp;
    tmp = QEIV2_POS_TIMEOUT_TIMEOUT_SET(tm);
    if (enable) {
        tmp |= QEIV2_POS_TIMEOUT_ENABLE_MASK;
    } else {
        tmp &= ~QEIV2_POS_TIMEOUT_ENABLE_MASK;
    }
    qeiv2_x->POS_TIMEOUT = tmp;
}
 
#if defined (HPM_IP_FEATURE_QEIV2_SIN_TOGI) && HPM_IP_FEATURE_QEIV2_SIN_TOGI
static inline void qeiv2_set_togi_enable(QEIV2_Type *qeiv2_x, bool enable)
{
    qeiv2_x->TOGI_CFG0 = (qeiv2_x->TOGI_CFG0 & ~QEIV2_TOGI_CFG0_SIN_TOGI_MASK) | QEIV2_TOGI_CFG0_SIN_TOGI_SET(enable);
}
 
void qeiv2_config_togi_w_param(QEIV2_Type *qeiv2_x, uint32_t signal_hz, uint32_t adc_sample_rate);
#endif
 
#if defined(HPM_IP_FEATURE_QEIV2_POS_ADJ) && HPM_IP_FEATURE_QEIV2_POS_ADJ
static inline void qeiv2_set_position_adjust_value(QEIV2_Type *qeiv2_x, int32_t pos_adj)
{
    qeiv2_x->POS_ADJ = QEIV2_POS_ADJ_POS_ADJ_SET(pos_adj);
}
#endif
 
#if defined(HPM_IP_FEATURE_QEIV2_ADC_SW_INJECT) && HPM_IP_FEATURE_QEIV2_ADC_SW_INJECT
static inline void qeiv2_enable_adc_sw_inject(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->ADC_INJECT_CTRL |= QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_MASK;
}
 
static inline void qeiv2_disable_adc_sw_inject(QEIV2_Type *qeiv2_x)
{
    qeiv2_x->ADC_INJECT_CTRL &= ~QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_MASK;
}
 
static inline void qeiv2_inject_sw_adc(QEIV2_Type *qeiv2_x, uint32_t adcx, uint32_t adcy, qeiv2_adc_sw_inject_en_t en)
{
    qeiv2_x->ADCX_VAL_SW = adcx;
    qeiv2_x->ADCY_VAL_SW = adcy;
    qeiv2_x->ADC_INJECT_CTRL |= en;
}
 
static inline bool qeiv2_is_pos_calc_finished(QEIV2_Type *qeiv2_x)
{
    return (QEIV2_CALC_STATE_STATE_GET(qeiv2_x->CALC_STATE) == 0) ? true : false;
}
#endif
 
hpm_stat_t qeiv2_config_phcnt_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config);
 
hpm_stat_t qeiv2_config_position_cmp_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config);
 
hpm_stat_t qeiv2_config_phcnt_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_phcnt_cmp_match_config_t *config);
 
hpm_stat_t qeiv2_config_position_cmp2_match_condition(QEIV2_Type *qeiv2_x, qeiv2_pos_cmp_match_config_t *config);
 
void qeiv2_get_uvw_position_defconfig(qeiv2_uvw_config_t *config);
 
hpm_stat_t qeiv2_config_uvw_position(QEIV2_Type *qeiv2_x, qeiv2_uvw_config_t *config);
 
void qeiv2_config_filter(QEIV2_Type *qeiv2_x, qeiv2_filter_phase_t phase, bool outinv, qeiv2_filter_mode_t mode, bool sync, uint32_t filtlen);
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_QEIV2_DRV_H */