hpm_tsw_drv.h

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/*
 * Copyright (c) 2023-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_TSW_DRV_H
#define HPM_TSW_DRV_H
 
/*---------------------------------------------------------------------
 * Includes
 *--------------------------------------------------------------------*/
#include "hpm_common.h"
#include "hpm_soc_feature.h"
#include "hpm_tsw_regs.h"
 
/*---------------------------------------------------------------------
 *  Macro Constant Declarations
 *-------------------------------------------------------------------*/
#define MAC_LO(mac) (uint32_t)(mac[0] | (mac[1] << 8) | (mac[2] << 16) | (mac[3] << 24))
#define MAC_HI(mac) (uint32_t)(mac[4] | (mac[5] << 8))
 
#define MAC_MDIO_CTRL_OP_WR (0x01)
#define MAC_MDIO_CTRL_OP_RD (0x02)
 
#ifndef TSW_SEND_DESC_COUNT
#define TSW_SEND_DESC_COUNT (16U)
#endif
 
#ifndef TSW_RECV_DESC_COUNT
#define TSW_RECV_DESC_COUNT (16U)
#endif
 
#ifndef TSW_SEND_BUFF_LEN
#define TSW_SEND_BUFF_LEN   (1536U)
#endif
 
#ifndef TSW_RECV_BUFF_LEN
#define TSW_RECV_BUFF_LEN   (1536U)
#endif
 
#ifndef TSW_NS_IN_ONE_SEC
#define TSW_NS_IN_ONE_SEC   (1000000000UL)
#endif
 
#ifndef TSW_BUS_FREQ
#define TSW_BUS_FREQ        (100000000UL)
#endif
/*---------------------------------------------------------------------
 *  Typedef Struct Declarations
 *-------------------------------------------------------------------*/
typedef struct {
    union {
        uint32_t tx_hdr0;
        struct {
            uint32_t dest_port: 8; 
            uint32_t          : 8; 
            uint32_t queue    : 3; 
            uint32_t utag     : 3; 
            uint32_t          : 6; 
            uint32_t htype    : 4; 
        } tx_hdr0_bm;
    };
 
    union {
        uint32_t tx_hdr1;
        struct {
            uint32_t cb: 32; 
        } tx_hdr1_bm;
    };
 
    uint32_t tx_hdr2; 
    uint32_t tx_hdr3; 
} tx_hdr_desc_t;
 
typedef struct {
  uint8_t   id;
  uint8_t  *buffer;
  uint16_t  length;
} tsw_frame_t;
 
typedef struct {
    bool    soe;
    bool    irq;
    uint8_t maxlen;
} tsw_dma_config_t;
 
typedef struct {
    uint16_t admin_list_length;
    uint16_t oper_list_length;
} tsw_shap_tas_listlen_t;
 
 
typedef struct  {
    uint8_t     state;      
    uint8_t     op;         
    uint32_t    interval;   
} tsw_tas_controllist_entry_t;
 
typedef struct {
    tsw_tas_controllist_entry_t *entry;
    uint32_t entry_count;
    uint32_t cycle_time;     
    uint32_t base_time_ns;   
    uint32_t base_time_sec;  
} tsw_tas_config_t;
 
typedef struct {
    uint8_t integer;
    uint16_t fract;
} tsw_cbs_config_t;
 
typedef struct {
    uint32_t    tstamplo;
    uint32_t    tstamphi;
    uint8_t     tqueue;
    uint8_t     tuser;
} tsw_tsf_t;
 
/*---------------------------------------------------------------------
 *  Typedef Enum Declarations
 *-------------------------------------------------------------------*/
typedef enum {
  tsw_port_speed_10mbps   = 2,
  tsw_port_speed_100mbps  = 3,
  tsw_port_speed_1000mbps = 0
} tsw_port_speed_t;
 
typedef enum {
  tsw_port_phy_itf_mii   = 0,
  tsw_port_phy_itf_rmii  = 4,
  tsw_port_phy_itf_rgmii = 1
} tsw_port_phy_itf_t;
 
typedef enum {
  tsw_dst_port_null = 0,
  tsw_dst_port_cpu  = 1 << 0,
  tsw_dst_port_1    = 1 << 1,
  tsw_dst_port_2    = 1 << 2,
  tsw_dst_port_3    = 1 << 3,
} tsw_dst_t;
 
typedef enum {
  tsw_cpu_send_to_lookup    = 0x00,
  tsw_cpu_send_to_port_1    = 0x01,
  tsw_cpu_send_to_port_2    = 0x02,
  tsw_cpu_send_to_port_3    = 0x03,
  tsw_cpu_send_to_all_ports = 0x80
} tsw_cpu_send_to_port_t;
 
typedef enum {
  tsw_mac_mode_mii = 0,
  tsw_mac_mode_gmii
} tsw_mac_mode_t;
 
typedef enum {
    tsw_pps_ctrl_pps = 0,
    tsw_pps_ctrl_bin_2hz_digital_1hz,
    tsw_pps_ctrl_bin_4hz_digital_2hz,
    tsw_pps_ctrl_bin_8hz_digital_4hz,
    tsw_pps_ctrl_bin_16hz_digital_8hz,
    tsw_pps_ctrl_bin_32hz_digital_16hz,
    tsw_pps_ctrl_bin_64hz_digital_32hz,
    tsw_pps_ctrl_bin_128hz_digital_64hz,
    tsw_pps_ctrl_bin_256hz_digital_128hz,
    tsw_pps_ctrl_bin_512hz_digital_256hz,
    tsw_pps_ctrl_bin_1024hz_digital_512hz,
    tsw_pps_ctrl_bin_2048hz_digital_1024hz,
    tsw_pps_ctrl_bin_4096hz_digital_2048hz,
    tsw_pps_ctrl_bin_8192hz_digital_4096hz,
    tsw_pps_ctrl_bin_16384hz_digital_8192hz,
    tsw_pps_ctrl_bin_32768hz_digital_16384hz
} tsw_pps_ctrl_t;
 
typedef enum {
  tsw_shap_tas_aclist_op_set_gate_states = 0,
  tsw_shap_tas_aclist_op_set_and_hold_mac,
  tsw_shap_tas_aclist_op_set_and_release_mac
} tsw_shap_tas_alist_op_t;
 
typedef enum {
    tsw_shap_tas_aclist_state_open_queueu_0 = 1 << 0,
    tsw_shap_tas_aclist_state_open_queueu_1 = 1 << 1,
    tsw_shap_tas_aclist_state_open_queueu_2 = 1 << 2,
    tsw_shap_tas_aclist_state_open_queueu_3 = 1 << 3,
    tsw_shap_tas_aclist_state_open_queueu_4 = 1 << 4,
    tsw_shap_tas_aclist_state_open_queueu_5 = 1 << 5,
    tsw_shap_tas_aclist_state_open_queueu_6 = 1 << 6,
    tsw_shap_tas_aclist_state_open_queueu_7 = 1 << 7,
    tsw_shap_tas_aclist_state_open_queueu_all = 0xff,
} tsw_shap_tas_aclist_state_open_queue_t;
 
typedef enum {
  tsw_traffic_queue_0 = 0,
  tsw_traffic_queue_1,
  tsw_traffic_queue_2,
  tsw_traffic_queue_3,
  tsw_traffic_queue_4,
  tsw_traffic_queue_5,
  tsw_traffic_queue_6,
  tsw_traffic_queue_7
} tsw_traffic_queue_t;
 
#if defined __cplusplus
extern "C" {
#endif /* __cplusplus */
/*---------------------------------------------------------------------
 * Exported Functions
 *-------------------------------------------------------------------*/
void tsw_get_default_dma_config(tsw_dma_config_t *config);
 
void tsw_init_send(TSW_Type *ptr, tsw_dma_config_t *config);
 
void tsw_init_recv(TSW_Type *ptr, tsw_dma_config_t *config);
 
hpm_stat_t tsw_send_frame(TSW_Type *ptr, uint8_t *buffer, uint16_t length, uint8_t id);
 
hpm_stat_t tsw_commit_recv_desc(TSW_Type *ptr, uint8_t *buffer, uint16_t length, uint8_t id);
 
hpm_stat_t tsw_recv_frame(TSW_Type *ptr, tsw_frame_t *frame);
 
void tsw_mac_lookup_bypass(TSW_Type *ptr, uint8_t dst_port);
 
void tsw_set_cam_vlan_port(TSW_Type *ptr);
 
hpm_stat_t tsw_ep_set_mdio_config(TSW_Type *ptr, uint8_t port, uint8_t clk_div);
 
hpm_stat_t tsw_ep_mdio_read(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint16_t *data);
 
hpm_stat_t tsw_ep_mdio_write(TSW_Type *ptr, uint8_t port, uint32_t phy_addr, uint32_t reg_addr, uint16_t data);
 
hpm_stat_t tsw_ep_enable_mac_ctrl(TSW_Type *ptr, uint8_t port, uint8_t mac_type);
 
hpm_stat_t tsw_ep_disable_mac_ctrl(TSW_Type *ptr, uint8_t port, uint8_t mac_type);
 
hpm_stat_t tsw_ep_enable_all_mac_ctrl(TSW_Type *ptr, uint8_t mac_type);
 
hpm_stat_t tsw_ep_disable_all_mac_ctrl(TSW_Type *ptr, uint8_t mac_type);
 
hpm_stat_t tsw_ep_set_mac_addr(TSW_Type *ptr, uint8_t port, uint8_t *mac_addr, bool promisc);
 
hpm_stat_t tsw_ep_set_mac_mode(TSW_Type *ptr, uint8_t port, uint8_t gmii);
 
void tsw_port_gpr(TSW_Type *ptr, uint8_t port, uint8_t speed, uint8_t itf, uint8_t tx_dly, uint8_t rx_dly);
 
void tsw_set_port_speed(TSW_Type *ptr, uint8_t port, uint8_t speed);
 
void tsw_set_port_interface(TSW_Type *ptr, uint8_t port, uint8_t itf);
 
void tsw_set_port_clock_delay(TSW_Type *ptr, uint8_t port, uint8_t tx_dly, uint8_t rx_dly);
 
void tsw_set_internal_frame_action(TSW_Type *ptr, uint8_t dest_port);
 
void tsw_set_broadcast_frame_action(TSW_Type *ptr, uint8_t dest_port);
 
void tsw_set_unknown_frame_action(TSW_Type *ptr, uint8_t dest_port);
 
void tsw_set_lookup_table(TSW_Type *ptr, uint16_t entry_num, uint8_t dest_port, uint64_t dest_mac);
 
void tsw_clear_cam(TSW_Type *ptr);
 
void tsw_enable_store_forward_mode(TSW_Type *ptr, uint8_t port);
 
void tsw_disable_store_forward_mode(TSW_Type *ptr, uint8_t port);
 
hpm_stat_t tsw_get_rtc_time_increment(TSW_Type *ptr, uint32_t *increment);
 
hpm_stat_t tsw_set_rtc_time_increment(TSW_Type *ptr, uint32_t increment);
 
hpm_stat_t tsw_get_rtc_current_time(TSW_Type *ptr, uint32_t *sec, uint32_t *nsec);
 
hpm_stat_t tsw_get_rtc_offset(TSW_Type *ptr, int64_t *sec, uint32_t *nsec);
 
hpm_stat_t tsw_set_rtc_offset(TSW_Type *ptr, int64_t sec, uint32_t nsec);
 
hpm_stat_t tsw_set_rtc_offset_change(TSW_Type *ptr, uint32_t change);
 
hpm_stat_t tsw_set_tsync_timer_hclkdiv(TSW_Type *ptr, uint8_t port, uint32_t host_clkdiv);
 
hpm_stat_t tsw_tsync_timer_control(TSW_Type *ptr, uint8_t port, uint8_t index, uint32_t period, uint32_t enable);
 
hpm_stat_t tsw_tsync_timer_interrupt_enable(TSW_Type *ptr, uint8_t port);
 
hpm_stat_t tsw_tsync_update_data(TSW_Type *ptr, uint8_t port, uint32_t bin, uint32_t binofs, uint32_t srcaddr, uint8_t lenbytes);
 
hpm_stat_t tsw_tsync_update_len(TSW_Type *ptr, uint8_t port, uint32_t bin, uint8_t lenbytes, uint8_t tqueue);
 
hpm_stat_t tsw_tsync_trigger_tx(TSW_Type *ptr, uint8_t port, uint32_t bin);
 
hpm_stat_t tsw_tsync_get_txtimestamp(TSW_Type *ptr, uint8_t port, uint32_t bin, uint32_t *timestamplo, uint32_t *timestamphi);
 
hpm_stat_t tsw_tsync_get_rxtimestamp(TSW_Type *ptr, uint8_t port, uint32_t *timestamplo, uint32_t *timestamphi);
 
hpm_stat_t tsw_tsync_disable_current_events(TSW_Type *ptr, uint8_t port, uint32_t *disabled);
 
hpm_stat_t tsw_tsync_get_rxstatus(TSW_Type *ptr, uint8_t port, uint8_t *ov, uint8_t *avnxt, uint8_t *rxsel);
 
hpm_stat_t tsw_tsync_next_rxbuffer(TSW_Type *ptr, uint8_t port);
 
hpm_stat_t tsw_tsync_clear_overflow(TSW_Type *ptr, uint8_t port);
 
hpm_stat_t tsw_tsync_get_txdone(TSW_Type *ptr, uint8_t port, uint32_t *done);
 
hpm_stat_t tsw_tsync_clear_txdone(TSW_Type *ptr, uint8_t port, uint32_t done);
 
hpm_stat_t tsw_tsync_get_tmrdone(TSW_Type *ptr, uint8_t port, uint32_t *done);
 
hpm_stat_t tsw_shap_get_tas_listlen(TSW_Type *ptr, uint8_t port, tsw_shap_tas_listlen_t *listlen);
 
hpm_stat_t tsw_shap_set_tas_cycletime(TSW_Type *ptr, uint8_t port, uint32_t cycle_time);
 
hpm_stat_t tsw_shap_set_tas_controllist(TSW_Type *ptr, uint8_t port, uint32_t index, tsw_tas_controllist_entry_t *entry);
 
hpm_stat_t tsw_shap_get_tas_controllist(TSW_Type *ptr, uint8_t port, uint32_t index, tsw_tas_controllist_entry_t *entry);
 
hpm_stat_t tsw_shap_set_tas_max_sdu_ticks(TSW_Type *ptr, uint8_t port, uint8_t index, uint32_t ticks);
 
hpm_stat_t tsw_shap_get_tas_max_sdu_ticks(TSW_Type *ptr, uint8_t port, uint8_t index, uint32_t *ticks);
 
hpm_stat_t tsw_set_pps_tod_output(TSW_Type *ptr);
 
hpm_stat_t tsw_shap_enable_tas(TSW_Type *ptr, uint8_t port);
 
hpm_stat_t tsw_shap_disable_tas(TSW_Type *ptr, uint8_t port);
 
hpm_stat_t tsw_shap_set_tas_listlen(TSW_Type *ptr, uint8_t port, uint32_t listlen);
 
hpm_stat_t tsw_shap_set_tas_cycletime(TSW_Type *ptr, uint8_t port, uint32_t cycle_time);
 
hpm_stat_t tsw_shap_set_tas_basetime(TSW_Type *ptr, uint8_t port, uint32_t basetime_sec, uint32_t basetime_ns);
 
hpm_stat_t tsw_shap_tas_change_config(TSW_Type *ptr, uint8_t port);
 
hpm_stat_t tsw_shap_get_tas_crsr(TSW_Type *ptr, uint8_t port, uint32_t *crsr);
 
hpm_stat_t tsw_shap_set_tas(TSW_Type *ptr, uint8_t port, tsw_tas_config_t *config);
 
hpm_stat_t tsw_shap_set_cbs(TSW_Type *ptr, uint8_t port, uint8_t index, tsw_cbs_config_t *config);
 
hpm_stat_t tsw_get_txtimestampfifo_used(TSW_Type *ptr, uint8_t port, uint32_t *count);
 
hpm_stat_t tsw_get_txtimestampfifo_entry(TSW_Type *ptr, uint8_t port, tsw_tsf_t *entry);
 
#if defined __cplusplus
}
#endif /* __cplusplus */
#endif /* HPM_TSW_DRV_H */