HPM SDK
HPMicro Software Development Kit
hpm_soc_feature.h
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1 /*
2  * Copyright (c) 2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef HPM_SOC_FEATURE_H
9 #define HPM_SOC_FEATURE_H
10 
11 #include "hpm_soc.h"
12 #include "hpm_soc_ip_feature.h"
13 
14 /*
15  * PLIC feature
16  */
17 #define PLIC_SUPPORT_EDGE_TRIGGER (1)
18 
19 /*
20  * PMP/PMA Feature
21  */
22 #define PMP_SUPPORT_PMA (0)
23 
24 /*
25  * I2C Section
26  */
27 #define I2C_SOC_FIFO_SIZE (4U)
28 #define I2C_SOC_TRANSFER_COUNT_MAX (4096U)
29 
30 /*
31  * PMIC Section
32  */
33 #define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U)
34 #define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U)
35 #define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125)
36 #define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U)
37 #define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U)
38 #define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U)
39 
40 /*
41  * PLLCTL Section
42  */
43 #define PLLCTL_SOC_PLL_MAX_COUNT (2U)
44 /* PLL reference clock in hz */
45 #define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL)
46 /* only PLL1 and PLL2 have DIV0, DIV1 */
47 #define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
48 #define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
49 
50 
51 /*
52  * PWM Section
53  */
54 #define PWM_SOC_PWM_MAX_COUNT (8U)
55 #define PWM_SOC_CMP_MAX_COUNT (24U)
56 #define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U)
57 
58 /*
59  * DMA Section
60  */
61 #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (DMA_TRANSFER_WIDTH_WORD)
62 #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (DMA_NUM_TRANSFER_PER_BURST_128T)
63 #define DMA_SOC_CHANNEL_NUM (32U)
64 #define DMA_SOC_MAX_COUNT (1U)
65 #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (DMAMUX_MUXCFG_HDMA_MUX0 + n)
66 #define DMA_SOC_HAS_IDLE_FLAG (1U)
67 
68 /*
69  * DMAMUX Section
70  */
71 #define DMAMUX_SOC_WRITEONLY (1U)
72 
73 /*
74  * USB Section
75  */
76 #define USB_SOC_MAX_COUNT (1U)
77 
78 #define USB_SOC_DCD_QTD_NEXT_INVALID (1U)
79 #define USB_SOC_DCD_QHD_BUFFER_COUNT (5U)
80 #define USB_SOC_DCD_MAX_ENDPOINT_COUNT (16U)
81 #ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT
82 #define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U)
83 #endif
84 #define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT)
85 #define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U)
86 #define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U)
87 
88 #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U)
89 
90 /*
91  * ADC Section
92  */
93 #define ADC_SOC_IP_VERSION (3U)
94 #define ADC_SOC_SEQ_MAX_LEN (16U)
95 #define ADC_SOC_SEQ_HCFG_EN (1U)
96 #define ADC_SOC_MAX_TRIG_CH_LEN (4U)
97 #define ADC_SOC_MAX_TRIG_CH_NUM (11U)
98 #define ADC_SOC_DMA_ADDR_ALIGNMENT (4U)
99 #define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U)
100 #define ADC_SOC_BUSMODE_ENABLE_CTRL_SUPPORT (1U)
101 #define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U)
102 #define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (16777216U)
103 #define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U)
104 
105 #define ADC16_SOC_PARAMS_LEN (34U)
106 #define ADC16_SOC_MAX_CH_NUM (15U)
107 #define ADC16_SOC_MAX_SAMPLE_VALUE (65535U)
108 #define ADC16_SOC_MAX_CONV_CLK_NUM (21U)
109 #define ADC_SOC_NO_HW_TRIG_SRC (1U)
110 
111 /*
112  * SYSCTL Section
113  */
114 #define SYSCTL_SOC_CPU_GPR_COUNT (14U)
115 #define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U)
116 
117 /*
118  * PTPC Section
119  */
120 #define PTPC_SOC_TIMER_MAX_COUNT (2U)
121 
122 /*
123  * SDP Section
124  */
125 #define SDP_REGISTER_DESCRIPTOR_COUNT (1U)
126 #define SDP_HAS_SM3_SUPPORT (1U)
127 #define SDP_HAS_SM4_SUPPORT (1U)
128 
129 /*
130  * SOC Privilege mode
131  */
132 #define SOC_HAS_S_MODE (0U)
133 
134 /*
135  * UART Section
136  */
137 #define UART_SOC_FIFO_SIZE (16U)
138 #define UART_SOC_OVERSAMPLE_MAX (30U) /* only support 30 oversample rate for rx idle detection */
139 
140 /*
141  * SPI Section
142  */
143 #define SPI_SOC_TRANSFER_COUNT_MAX (0xFFFFFFFFU)
144 #define SPI_SOC_FIFO_DEPTH (8U)
145 
146 /*
147  * OTP Section
148  */
149 #define OTP_SOC_UUID_IDX (88U)
150 #define OTP_SOC_UUID_LEN (16U) /* in bytes */
151 
152 /*
153  * PWM Section
154  */
155 #define PWM_SOC_HRPWM_SUPPORT (0U)
156 #define PWM_SOC_SHADOW_TRIG_SUPPORT (0U)
157 #define PWM_SOC_TIMER_RESET_SUPPORT (1U)
158 
159 /*
160  * TRGM section
161  */
162 #define TRGM_SOC_HAS_FILTER_SHIFT (1U)
163 #define TRGM_SOC_HAS_DMAMUX_EN (1U)
164 #define TRGM_SOC_HAS_ADC_MATRIX_SEL (1U)
165 #define TRGM_SOC_HAS_DAC_MATRIX_SEL (1U)
166 #define TRGM_SOC_HAS_POS_MATRIX_SEL (1U)
167 
168 /*
169  * MCAN Section
170  */
171 #define MCAN_SOC_MAX_COUNT (0U)
172 #define MCAN_SOC_MSG_BUF_IN_IP (0U)
173 #define MCAN_SOC_MSG_BUF_IN_AHB_RAM (1U)
174 #define CAN_SOC_MAX_COUNT MCAN_SOC_MAX_COUNT
175 
176 /*
177  * EWDG Section
178  */
179 #define EWDG_SOC_CLK_DIV_VAL_MAX (5U)
180 #define EWDG_SOC_OVERTIME_REG_WIDTH (16U)
181 #define EWDG_SOC_SUPPORT_TIMEOUT_INTERRUPT (1)
182 #define EWDG_TIMEOUT_INTERRUPT_REQUIRE_EDGE_TRIGGER (1)
183 
184 /*
185  * Sync Timer
186  */
187 #define SYNT_SOC_HAS_TIMESTAMP (1U)
188 
189 /*
190  * GPIO
191  */
192 #define GPIO_SOC_HAS_EDGE_BOTH_INTERRUPT (1U)
193 
194 
195 #endif /* HPM_SOC_FEATURE_H */
hpm_soc.h
hpm_soc_ip_feature.h