HPM SDK
HPMicro Software Development Kit
hpm_dmamux_src.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_DMAMUX_SRC_H
10 #define HPM_DMAMUX_SRC_H
11 
12 /* dma mux definitions */
13 #define HPM_DMA_SRC_GPTMR0_0 (0x0UL) /* GPTMR0 Channel 0 */
14 #define HPM_DMA_SRC_GPTMR0_1 (0x1UL) /* GPTMR0 Channel 1 */
15 #define HPM_DMA_SRC_GPTMR0_2 (0x2UL) /* GPTMR0 Channel 2 */
16 #define HPM_DMA_SRC_GPTMR0_3 (0x3UL) /* GPTMR0 Channel 3 */
17 #define HPM_DMA_SRC_GPTMR1_0 (0x4UL) /* GPTMR1 Channel 0 */
18 #define HPM_DMA_SRC_GPTMR1_1 (0x5UL) /* GPTMR1 Channel 1 */
19 #define HPM_DMA_SRC_GPTMR1_2 (0x6UL) /* GPTMR1 Channel 2 */
20 #define HPM_DMA_SRC_GPTMR1_3 (0x7UL) /* GPTMR1 Channel 3 */
21 #define HPM_DMA_SRC_GPTMR2_0 (0x8UL) /* GPTMR2 channel 0 */
22 #define HPM_DMA_SRC_GPTMR2_1 (0x9UL) /* GPTMR2 Channel 1 */
23 #define HPM_DMA_SRC_GPTMR2_2 (0xAUL) /* GPTMR2 Channel 2 */
24 #define HPM_DMA_SRC_GPTMR2_3 (0xBUL) /* GPTMR2 Channel 3 */
25 #define HPM_DMA_SRC_GPTMR3_0 (0xCUL) /* GPTMR3 channel 0 */
26 #define HPM_DMA_SRC_GPTMR3_1 (0xDUL) /* GPTMR3 Channel 1 */
27 #define HPM_DMA_SRC_GPTMR3_2 (0xEUL) /* GPTMR3 Channel 2 */
28 #define HPM_DMA_SRC_GPTMR3_3 (0xFUL) /* GPTMR3 Channel 3 */
29 #define HPM_DMA_SRC_UART0_RX (0x14UL) /* UART0 Receive */
30 #define HPM_DMA_SRC_UART0_TX (0x15UL) /* UART0 Transmit */
31 #define HPM_DMA_SRC_UART1_RX (0x16UL) /* UART1 Receive */
32 #define HPM_DMA_SRC_UART1_TX (0x17UL) /* UART1 Transmit */
33 #define HPM_DMA_SRC_UART2_RX (0x18UL) /* UART2 Receive */
34 #define HPM_DMA_SRC_UART2_TX (0x19UL) /* UART2 Transmit */
35 #define HPM_DMA_SRC_UART3_RX (0x1AUL) /* UART3 Receive */
36 #define HPM_DMA_SRC_UART3_TX (0x1BUL) /* UART3 Transmit */
37 #define HPM_DMA_SRC_UART4_RX (0x1CUL) /* UART4 Receive */
38 #define HPM_DMA_SRC_UART4_TX (0x1DUL) /* UART4 Transmit */
39 #define HPM_DMA_SRC_UART5_RX (0x1EUL) /* UART5 Receive */
40 #define HPM_DMA_SRC_UART5_TX (0x1FUL) /* UART5 Transmit */
41 #define HPM_DMA_SRC_UART6_RX (0x20UL) /* UART6 Receive */
42 #define HPM_DMA_SRC_UART6_TX (0x21UL) /* UART6 Transmit */
43 #define HPM_DMA_SRC_UART7_RX (0x22UL) /* UART7 Receive */
44 #define HPM_DMA_SRC_UART7_TX (0x23UL) /* UART7 Transmit */
45 #define HPM_DMA_SRC_I2C0 (0x24UL) /* I2C0 */
46 #define HPM_DMA_SRC_I2C1 (0x25UL) /* I2C1 */
47 #define HPM_DMA_SRC_I2C2 (0x26UL) /* I2C2 */
48 #define HPM_DMA_SRC_I2C3 (0x27UL) /* I2C3 */
49 #define HPM_DMA_SRC_SPI0_RX (0x28UL) /* SPI0 Receive */
50 #define HPM_DMA_SRC_SPI0_TX (0x29UL) /* SPI0 Transmit */
51 #define HPM_DMA_SRC_SPI1_RX (0x2AUL) /* SPI1 Receive */
52 #define HPM_DMA_SRC_SPI1_TX (0x2BUL) /* SPI1 Transmit */
53 #define HPM_DMA_SRC_SPI2_RX (0x2CUL) /* SPI2 Receive */
54 #define HPM_DMA_SRC_SPI2_TX (0x2DUL) /* SPI2 Transmit */
55 #define HPM_DMA_SRC_SPI3_RX (0x2EUL) /* SPI3 Receive */
56 #define HPM_DMA_SRC_SPI3_TX (0x2FUL) /* SPI3 Transmit */
57 #define HPM_DMA_SRC_MCAN0 (0x30UL) /* CAN0 */
58 #define HPM_DMA_SRC_MCAN1 (0x31UL) /* CAN1 */
59 #define HPM_DMA_SRC_MCAN2 (0x32UL) /* CAN2 */
60 #define HPM_DMA_SRC_MCAN3 (0x33UL) /* CAN3 */
61 #define HPM_DMA_SRC_MOT_0 (0x34UL) /* TRGM0 DMA request 0 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
62 #define HPM_DMA_SRC_MOT_1 (0x35UL) /* TRGM0 DMA request 1 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
63 #define HPM_DMA_SRC_MOT_2 (0x36UL) /* TRGM0 DMA request 2 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
64 #define HPM_DMA_SRC_MOT_3 (0x37UL) /* TRGM0 DMA request 3 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
65 #define HPM_DMA_SRC_MOT_4 (0x38UL) /* TRGM0 DMA request 4 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
66 #define HPM_DMA_SRC_MOT_5 (0x39UL) /* TRGM0 DMA request 5 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
67 #define HPM_DMA_SRC_MOT_6 (0x3AUL) /* TRGM0 DMA request 6 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
68 #define HPM_DMA_SRC_MOT_7 (0x3BUL) /* TRGM0 DMA request 7 (contains DMA requests for PWM0, PWM1, QEI0, QEI1, MMC0, MMC1, SEI0, SEI1) */
69 #define HPM_DMA_SRC_XPI0_RX (0x3CUL) /* XPI0 Receive */
70 #define HPM_DMA_SRC_XPI0_TX (0x3DUL) /* XPI0 Transmit */
71 #define HPM_DMA_SRC_DAC0 (0x3EUL) /* DAC0 */
72 #define HPM_DMA_SRC_DAC1 (0x3FUL) /* DAC1 */
73 #define HPM_DMA_SRC_ACMP0 (0x40UL) /* ACMP0 */
74 #define HPM_DMA_SRC_ACMP1 (0x41UL) /* ACMP1 */
75 
76 
77 
78 #endif /* HPM_DMAMUX_SRC_H */