HPM SDK
HPMicro Software Development Kit
hpm_interrupt.h
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1 /*
2  * Copyright (c) 2023-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef HPM_INTERRUPT_H
9 #define HPM_INTERRUPT_H
10 #include "hpm_common.h"
11 #include "hpm_csr_drv.h"
12 #include "hpm_plic_drv.h"
13 
20 #define M_MODE 0
21 #define S_MODE 1
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26 
27 /* Machine mode API: these APIs are supposed to be called at machine mode */
28 
34 ATTR_ALWAYS_INLINE static inline void enable_global_irq(uint32_t mask)
35 {
36  set_csr(CSR_MSTATUS, mask);
37 }
38 
45 ATTR_ALWAYS_INLINE static inline uint32_t disable_global_irq(uint32_t mask)
46 {
47  return read_clear_csr(CSR_MSTATUS, mask);
48 }
49 
55 ATTR_ALWAYS_INLINE static inline void restore_global_irq(uint32_t mask)
56 {
57  set_csr(CSR_MSTATUS, mask);
58 }
59 
64 ATTR_ALWAYS_INLINE static inline void enable_irq_from_intc(void)
65 {
66  set_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
67 }
68 
73 ATTR_ALWAYS_INLINE static inline void disable_irq_from_intc(void)
74 {
75  clear_csr(CSR_MIE, CSR_MIE_MEIE_MASK);
76 }
77 
81 ATTR_ALWAYS_INLINE static inline void enable_mchtmr_irq(void)
82 {
83  set_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
84 }
85 
90 ATTR_ALWAYS_INLINE static inline void disable_mchtmr_irq(void)
91 {
92  clear_csr(CSR_MIE, CSR_MIE_MTIE_MASK);
93 }
94 
95 /*
96  * CPU Machine SWI control
97  *
98  * Machine SWI (MSIP) is connected to PLICSW irq 1.
99  */
100 #define PLICSWI 1
101 
106 ATTR_ALWAYS_INLINE static inline void intc_m_init_swi(void)
107 {
108  __plic_enable_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
109 }
110 
111 
116 ATTR_ALWAYS_INLINE static inline void intc_m_enable_swi(void)
117 {
118  set_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
119 }
120 
121 
126 ATTR_ALWAYS_INLINE static inline void intc_m_disable_swi(void)
127 {
128  clear_csr(CSR_MIE, CSR_MIE_MSIE_MASK);
129 }
130 
131 
136 ATTR_ALWAYS_INLINE static inline void intc_m_trigger_swi(void)
137 {
138  __plic_set_irq_pending(HPM_PLICSW_BASE, PLICSWI);
139 }
140 
145 ATTR_ALWAYS_INLINE static inline void intc_m_claim_swi(void)
146 {
147  __plic_claim_irq(HPM_PLICSW_BASE, 0);
148 }
149 
154 ATTR_ALWAYS_INLINE static inline void intc_m_complete_swi(void)
155 {
156  __plic_complete_irq(HPM_PLICSW_BASE, HPM_PLIC_TARGET_M_MODE, PLICSWI);
157 }
158 
159 /*
160  * @brief Enable IRQ for machine mode
161  *
162  * @param[in] irq Interrupt number
163  */
164 #define intc_m_enable_irq(irq) \
165  intc_enable_irq(HPM_PLIC_TARGET_M_MODE, irq)
166 
167 /*
168  * @brief Disable IRQ for machine mode
169  *
170  * @param[in] irq Interrupt number
171  */
172 #define intc_m_disable_irq(irq) \
173  intc_disable_irq(HPM_PLIC_TARGET_M_MODE, irq)
174 
175 #define intc_m_set_threshold(threshold) \
176  intc_set_threshold(HPM_PLIC_TARGET_M_MODE, threshold)
177 
178 #define intc_m_get_threshold() \
179  intc_get_threshold(HPM_PLIC_TARGET_M_MODE)
180 
181 /*
182  * @brief Complete IRQ for machine mode
183  *
184  * @param[in] irq Interrupt number
185  */
186 #define intc_m_complete_irq(irq) \
187  intc_complete_irq(HPM_PLIC_TARGET_M_MODE, irq)
188 
189 /*
190  * @brief Claim IRQ for machine mode
191  *
192  */
193 #define intc_m_claim_irq() intc_claim_irq(HPM_PLIC_TARGET_M_MODE)
194 
195 /*
196  * @brief Enable IRQ for machine mode with priority
197  *
198  * @param[in] irq Interrupt number
199  * @param[in] priority Priority of interrupt
200  */
201 #define intc_m_enable_irq_with_priority(irq, priority) \
202  do { \
203  intc_set_irq_priority(irq, priority); \
204  intc_m_enable_irq(irq); \
205  } while (0)
206 
207 /*
208  * @brief Enable specific interrupt
209  *
210  * @param[in] target Target to handle specific interrupt
211  * @param[in] irq Interrupt number
212  */
213 ATTR_ALWAYS_INLINE static inline void intc_enable_irq(uint32_t target, uint32_t irq)
214 {
215  __plic_enable_irq(HPM_PLIC_BASE, target, irq);
216 }
217 
224 ATTR_ALWAYS_INLINE static inline void intc_set_irq_priority(uint32_t irq, uint32_t priority)
225 {
226  __plic_set_irq_priority(HPM_PLIC_BASE, irq, priority);
227 }
228 
235 ATTR_ALWAYS_INLINE static inline void intc_disable_irq(uint32_t target, uint32_t irq)
236 {
237  __plic_disable_irq(HPM_PLIC_BASE, target, irq);
238 }
239 
246 ATTR_ALWAYS_INLINE static inline void intc_set_threshold(uint32_t target, uint32_t threshold)
247 {
248  __plic_set_threshold(HPM_PLIC_BASE, target, threshold);
249 }
250 
256 ATTR_ALWAYS_INLINE static inline uint32_t intc_get_threshold(uint32_t target)
257 {
258  return __plic_get_threshold(HPM_PLIC_BASE, target);
259 }
260 
267 ATTR_ALWAYS_INLINE static inline uint32_t intc_claim_irq(uint32_t target)
268 {
269  return __plic_claim_irq(HPM_PLIC_BASE, target);
270 }
271 
279 ATTR_ALWAYS_INLINE static inline void intc_complete_irq(uint32_t target, uint32_t irq)
280 {
281  __plic_complete_irq(HPM_PLIC_BASE, target, irq);
282 }
283 
284 /*
285  * Vectored based irq install and uninstall
286  */
287 /* Machine mode */
288 extern int __vector_table[];
289 
290 extern void default_irq_entry(void);
291 
299 ATTR_ALWAYS_INLINE static inline void install_isr(uint32_t irq, uint32_t isr)
300 {
301  __vector_table[irq] = isr;
302 }
303 
310 ATTR_ALWAYS_INLINE static inline void uninstall_isr(uint32_t irq)
311 {
312  __vector_table[irq] = (int) default_irq_entry;
313 }
314 
315 /*
316  * Inline nested irq entry/exit macros
317  */
318 /*
319  * @brief Save CSR
320  * @param[in] r Target CSR to be saved
321  */
322 #define SAVE_CSR(r) register long __##r = read_csr(r);
323 
324 /*
325  * @brief Restore macro
326  *
327  * @param[in] r Target CSR to be restored
328  */
329 #define RESTORE_CSR(r) write_csr(r, __##r);
330 
331 #if defined(SUPPORT_PFT_ARCH) && SUPPORT_PFT_ARCH
332 #define SAVE_MXSTATUS() SAVE_CSR(CSR_MXSTATUS)
333 #define RESTORE_MXSTATUS() RESTORE_CSR(CSR_MXSTATUS)
334 #else
335 #define SAVE_MXSTATUS()
336 #define RESTORE_MXSTATUS()
337 #endif
338 
339 #ifdef __riscv_flen
340 #define SAVE_FCSR() register int __fcsr = read_fcsr();
341 #define RESTORE_FCSR() write_fcsr(__fcsr);
342 #else
343 #define SAVE_FCSR()
344 #define RESTORE_FCSR()
345 #endif
346 
347 #ifdef __riscv_dsp
348 #define SAVE_UCODE() SAVE_CSR(CSR_UCODE)
349 #define RESTORE_UCODE() RESTORE_CSR(CSR_UCODE)
350 #else
351 #define SAVE_UCODE()
352 #define RESTORE_UCODE()
353 #endif
354 
355 #ifdef __riscv_flen
356 #if __riscv_flen == 32
357 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 FPU caller registers */
358 #define CONTEXT_REG_NUM (4 * (16 + 4 + 20))
359 #else /* __riscv_flen = 64 */
360 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS + 20 DFPU caller */
361 #define CONTEXT_REG_NUM (4*(16 + 4 + 20*2))
362 #endif
363 
364 #else
365 /* RV32I caller registers + MCAUSE + MEPC + MSTATUS */
366 #define CONTEXT_REG_NUM (4 * (16 + 4))
367 #endif
368 
369 #ifdef __riscv_flen
370 /*
371  * Save FPU caller registers:
372  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
373  */
374 #if __riscv_flen == 32
375 #ifdef __ICCRISCV__
376 #define SAVE_FPU_CONTEXT() { \
377  __asm volatile("\n\
378  c.fswsp ft0, 20*4\n\
379  c.fswsp ft1, 21*4 \n\
380  c.fswsp ft2, 22*4 \n\
381  c.fswsp ft3, 23*4 \n\
382  c.fswsp ft4, 24*4 \n\
383  c.fswsp ft5, 25*4 \n\
384  c.fswsp ft6, 26*4 \n\
385  c.fswsp ft7, 27*4 \n\
386  c.fswsp fa0, 28*4 \n\
387  c.fswsp fa1, 29*4 \n\
388  c.fswsp fa2, 30*4 \n\
389  c.fswsp fa3, 31*4 \n\
390  c.fswsp fa4, 32*4 \n\
391  c.fswsp fa5, 33*4 \n\
392  c.fswsp fa6, 34*4 \n\
393  c.fswsp fa7, 35*4 \n\
394  c.fswsp ft8, 36*4 \n\
395  c.fswsp ft9, 37*4 \n\
396  c.fswsp ft10, 38*4 \n\
397  c.fswsp ft11, 39*4 \n");\
398 }
399 
400 /*
401  * Restore FPU caller registers:
402  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
403  */
404 #define RESTORE_FPU_CONTEXT() { \
405  __asm volatile("\n\
406  c.flwsp ft0, 20*4\n\
407  c.flwsp ft1, 21*4 \n\
408  c.flwsp ft2, 22*4 \n\
409  c.flwsp ft3, 23*4 \n\
410  c.flwsp ft4, 24*4 \n\
411  c.flwsp ft5, 25*4 \n\
412  c.flwsp ft6, 26*4 \n\
413  c.flwsp ft7, 27*4 \n\
414  c.flwsp fa0, 28*4 \n\
415  c.flwsp fa1, 29*4 \n\
416  c.flwsp fa2, 30*4 \n\
417  c.flwsp fa3, 31*4 \n\
418  c.flwsp fa4, 32*4 \n\
419  c.flwsp fa5, 33*4 \n\
420  c.flwsp fa6, 34*4 \n\
421  c.flwsp fa7, 35*4 \n\
422  c.flwsp ft8, 36*4 \n\
423  c.flwsp ft9, 37*4 \n\
424  c.flwsp ft10, 38*4 \n\
425  c.flwsp ft11, 39*4 \n");\
426 }
427 #else /* __ICCRISCV__ not defined */
428 #define SAVE_FPU_CONTEXT() { \
429  __asm volatile("\n\
430  c.fswsp ft0, 20*4(sp)\n\
431  c.fswsp ft1, 21*4(sp) \n\
432  c.fswsp ft2, 22*4(sp) \n\
433  c.fswsp ft3, 23*4(sp) \n\
434  c.fswsp ft4, 24*4(sp) \n\
435  c.fswsp ft5, 25*4(sp) \n\
436  c.fswsp ft6, 26*4(sp) \n\
437  c.fswsp ft7, 27*4(sp) \n\
438  c.fswsp fa0, 28*4(sp) \n\
439  c.fswsp fa1, 29*4(sp) \n\
440  c.fswsp fa2, 30*4(sp) \n\
441  c.fswsp fa3, 31*4(sp) \n\
442  c.fswsp fa4, 32*4(sp) \n\
443  c.fswsp fa5, 33*4(sp) \n\
444  c.fswsp fa6, 34*4(sp) \n\
445  c.fswsp fa7, 35*4(sp) \n\
446  c.fswsp ft8, 36*4(sp) \n\
447  c.fswsp ft9, 37*4(sp) \n\
448  c.fswsp ft10, 38*4(sp) \n\
449  c.fswsp ft11, 39*4(sp) \n");\
450 }
451 
452 /*
453  * Restore FPU caller registers:
454  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
455  */
456 #define RESTORE_FPU_CONTEXT() { \
457  __asm volatile("\n\
458  c.flwsp ft0, 20*4(sp)\n\
459  c.flwsp ft1, 21*4(sp) \n\
460  c.flwsp ft2, 22*4(sp) \n\
461  c.flwsp ft3, 23*4(sp) \n\
462  c.flwsp ft4, 24*4(sp) \n\
463  c.flwsp ft5, 25*4(sp) \n\
464  c.flwsp ft6, 26*4(sp) \n\
465  c.flwsp ft7, 27*4(sp) \n\
466  c.flwsp fa0, 28*4(sp) \n\
467  c.flwsp fa1, 29*4(sp) \n\
468  c.flwsp fa2, 30*4(sp) \n\
469  c.flwsp fa3, 31*4(sp) \n\
470  c.flwsp fa4, 32*4(sp) \n\
471  c.flwsp fa5, 33*4(sp) \n\
472  c.flwsp fa6, 34*4(sp) \n\
473  c.flwsp fa7, 35*4(sp) \n\
474  c.flwsp ft8, 36*4(sp) \n\
475  c.flwsp ft9, 37*4(sp) \n\
476  c.flwsp ft10, 38*4(sp) \n\
477  c.flwsp ft11, 39*4(sp) \n");\
478 }
479 #endif
480 #else /*__riscv_flen == 64*/
481 #ifdef __ICCRISCV__
482 #define SAVE_FPU_CONTEXT() { \
483  __asm volatile("\n\
484  c.fsdsp ft0, 20*4\n\
485  c.fsdsp ft1, 22*4 \n\
486  c.fsdsp ft2, 24*4 \n\
487  c.fsdsp ft3, 26*4 \n\
488  c.fsdsp ft4, 28*4 \n\
489  c.fsdsp ft5, 30*4 \n\
490  c.fsdsp ft6, 32*4 \n\
491  c.fsdsp ft7, 34*4 \n\
492  c.fsdsp fa0, 36*4 \n\
493  c.fsdsp fa1, 38*4 \n\
494  c.fsdsp fa2, 40*4 \n\
495  c.fsdsp fa3, 42*4 \n\
496  c.fsdsp fa4, 44*4 \n\
497  c.fsdsp fa5, 46*4 \n\
498  c.fsdsp fa6, 48*4 \n\
499  c.fsdsp fa7, 50*4 \n\
500  c.fsdsp ft8, 52*4 \n\
501  c.fsdsp ft9, 54*4 \n\
502  c.fsdsp ft10, 56*4 \n\
503  c.fsdsp ft11, 58*4 \n");\
504 }
505 
506 /*
507  * Restore FPU caller registers:
508  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
509  */
510 #define RESTORE_FPU_CONTEXT() { \
511  __asm volatile("\n\
512  c.fldsp ft0, 20*4\n\
513  c.fldsp ft1, 22*4 \n\
514  c.fldsp ft2, 24*4 \n\
515  c.fldsp ft3, 26*4 \n\
516  c.fldsp ft4, 28*4 \n\
517  c.fldsp ft5, 30*4 \n\
518  c.fldsp ft6, 32*4 \n\
519  c.fldsp ft7, 34*4 \n\
520  c.fldsp fa0, 36*4 \n\
521  c.fldsp fa1, 38*4 \n\
522  c.fldsp fa2, 40*4 \n\
523  c.fldsp fa3, 42*4 \n\
524  c.fldsp fa4, 44*4 \n\
525  c.fldsp fa5, 46*4 \n\
526  c.fldsp fa6, 48*4 \n\
527  c.fldsp fa7, 50*4 \n\
528  c.fldsp ft8, 52*4 \n\
529  c.fldsp ft9, 54*4 \n\
530  c.fldsp ft10, 56*4 \n\
531  c.fldsp ft11, 58*4 \n");\
532 }
533 #else
534 #define SAVE_FPU_CONTEXT() { \
535  __asm volatile("\n\
536  c.fsdsp ft0, 20*4(sp)\n\
537  c.fsdsp ft1, 22*4(sp) \n\
538  c.fsdsp ft2, 24*4(sp) \n\
539  c.fsdsp ft3, 26*4(sp) \n\
540  c.fsdsp ft4, 28*4(sp) \n\
541  c.fsdsp ft5, 30*4(sp) \n\
542  c.fsdsp ft6, 32*4(sp) \n\
543  c.fsdsp ft7, 34*4(sp) \n\
544  c.fsdsp fa0, 36*4(sp) \n\
545  c.fsdsp fa1, 38*4(sp) \n\
546  c.fsdsp fa2, 40*4(sp) \n\
547  c.fsdsp fa3, 42*4(sp) \n\
548  c.fsdsp fa4, 44*4(sp) \n\
549  c.fsdsp fa5, 46*4(sp) \n\
550  c.fsdsp fa6, 48*4(sp) \n\
551  c.fsdsp fa7, 50*4(sp) \n\
552  c.fsdsp ft8, 52*4(sp) \n\
553  c.fsdsp ft9, 54*4(sp) \n\
554  c.fsdsp ft10, 56*4(sp) \n\
555  c.fsdsp ft11, 58*4(sp) \n");\
556 }
557 
558 /*
559  * Restore FPU caller registers:
560  * NOTE: To simplify the logic, the FPU caller registers are always stored at word offset 20 in the stack
561  */
562 #define RESTORE_FPU_CONTEXT() { \
563  __asm volatile("\n\
564  c.fldsp ft0, 20*4(sp)\n\
565  c.fldsp ft1, 22*4(sp) \n\
566  c.fldsp ft2, 24*4(sp) \n\
567  c.fldsp ft3, 26*4(sp) \n\
568  c.fldsp ft4, 28*4(sp) \n\
569  c.fldsp ft5, 30*4(sp) \n\
570  c.fldsp ft6, 32*4(sp) \n\
571  c.fldsp ft7, 34*4(sp) \n\
572  c.fldsp fa0, 36*4(sp) \n\
573  c.fldsp fa1, 38*4(sp) \n\
574  c.fldsp fa2, 40*4(sp) \n\
575  c.fldsp fa3, 42*4(sp) \n\
576  c.fldsp fa4, 44*4(sp) \n\
577  c.fldsp fa5, 46*4(sp) \n\
578  c.fldsp fa6, 48*4(sp) \n\
579  c.fldsp fa7, 50*4(sp) \n\
580  c.fldsp ft8, 52*4(sp) \n\
581  c.fldsp ft9, 54*4(sp) \n\
582  c.fldsp ft10, 56*4(sp) \n\
583  c.fldsp ft11, 58*4(sp) \n");\
584 }
585 #endif
586 #endif
587 #else
588 #define SAVE_FPU_CONTEXT()
589 #define RESTORE_FPU_CONTEXT()
590 #endif
591 
592 #ifdef __ICCRISCV__
596 #define SAVE_CALLER_CONTEXT() { \
597  __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
598  __asm volatile("\n\
599  c.swsp ra, 0*4 \n\
600  c.swsp t0, 1*4 \n\
601  c.swsp t1, 2*4 \n\
602  c.swsp t2, 3*4 \n\
603  c.swsp s1, 4*4 \n\
604  c.swsp a0, 5*4 \n\
605  c.swsp a1, 6*4 \n\
606  c.swsp a2, 7*4 \n\
607  c.swsp a3, 8*4 \n\
608  c.swsp a4, 9*4 \n\
609  c.swsp a5, 10*4 \n\
610  c.swsp a6, 11*4 \n\
611  c.swsp a7, 12*4 \n\
612  c.swsp s2, 13*4 \n\
613  c.swsp s3, 14*4 \n\
614  c.swsp s4, 15*4 \n\
615  c.swsp t3, 16*4 \n\
616  c.swsp t4, 17*4 \n\
617  c.swsp t5, 18*4 \n\
618  c.swsp t6, 19*4"); \
619  SAVE_FPU_CONTEXT(); \
620 }
621 
625 #define RESTORE_CALLER_CONTEXT() { \
626  __asm volatile("\n\
627  c.lwsp ra, 0*4 \n\
628  c.lwsp t0, 1*4 \n\
629  c.lwsp t1, 2*4 \n\
630  c.lwsp t2, 3*4 \n\
631  c.lwsp s1, 4*4 \n\
632  c.lwsp a0, 5*4 \n\
633  c.lwsp a1, 6*4 \n\
634  c.lwsp a2, 7*4 \n\
635  c.lwsp a3, 8*4 \n\
636  c.lwsp a4, 9*4 \n\
637  c.lwsp a5, 10*4 \n\
638  c.lwsp a6, 11*4 \n\
639  c.lwsp a7, 12*4 \n\
640  c.lwsp s2, 13*4 \n\
641  c.lwsp s3, 14*4 \n\
642  c.lwsp s4, 15*4 \n\
643  c.lwsp t3, 16*4 \n\
644  c.lwsp t4, 17*4 \n\
645  c.lwsp t5, 18*4 \n\
646  c.lwsp t6, 19*4 \n");\
647  RESTORE_FPU_CONTEXT(); \
648  __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
649 }
650 #else
654 #define SAVE_CALLER_CONTEXT() { \
655  __asm volatile("addi sp, sp, %0" : : "i"(-CONTEXT_REG_NUM) :);\
656  __asm volatile("\n\
657  c.swsp ra, 0*4(sp) \n\
658  c.swsp t0, 1*4(sp) \n\
659  c.swsp t1, 2*4(sp) \n\
660  c.swsp t2, 3*4(sp) \n\
661  c.swsp s1, 4*4(sp) \n\
662  c.swsp a0, 5*4(sp) \n\
663  c.swsp a1, 6*4(sp) \n\
664  c.swsp a2, 7*4(sp) \n\
665  c.swsp a3, 8*4(sp) \n\
666  c.swsp a4, 9*4(sp) \n\
667  c.swsp a5, 10*4(sp) \n\
668  c.swsp a6, 11*4(sp) \n\
669  c.swsp a7, 12*4(sp) \n\
670  c.swsp s2, 13*4(sp) \n\
671  c.swsp s3, 14*4(sp) \n\
672  c.swsp s4, 15*4(sp) \n\
673  c.swsp t3, 16*4(sp) \n\
674  c.swsp t4, 17*4(sp) \n\
675  c.swsp t5, 18*4(sp) \n\
676  c.swsp t6, 19*4(sp)"); \
677  SAVE_FPU_CONTEXT(); \
678 }
679 
683 #define RESTORE_CALLER_CONTEXT() { \
684  __asm volatile("\n\
685  c.lwsp ra, 0*4(sp) \n\
686  c.lwsp t0, 1*4(sp) \n\
687  c.lwsp t1, 2*4(sp) \n\
688  c.lwsp t2, 3*4(sp) \n\
689  c.lwsp s1, 4*4(sp) \n\
690  c.lwsp a0, 5*4(sp) \n\
691  c.lwsp a1, 6*4(sp) \n\
692  c.lwsp a2, 7*4(sp) \n\
693  c.lwsp a3, 8*4(sp) \n\
694  c.lwsp a4, 9*4(sp) \n\
695  c.lwsp a5, 10*4(sp) \n\
696  c.lwsp a6, 11*4(sp) \n\
697  c.lwsp a7, 12*4(sp) \n\
698  c.lwsp s2, 13*4(sp) \n\
699  c.lwsp s3, 14*4(sp) \n\
700  c.lwsp s4, 15*4(sp) \n\
701  c.lwsp t3, 16*4(sp) \n\
702  c.lwsp t4, 17*4(sp) \n\
703  c.lwsp t5, 18*4(sp) \n\
704  c.lwsp t6, 19*4(sp) \n");\
705  RESTORE_FPU_CONTEXT(); \
706  __asm volatile("addi sp, sp, %0" : : "i"(CONTEXT_REG_NUM) :);\
707 }
708 #endif
709 
710 #ifdef __riscv_flen
711 #define SAVE_FPU_STATE() { \
712  __asm volatile("frcsr s1\n"); \
713 }
714 
715 #define RESTORE_FPU_STATE() { \
716  __asm volatile("fscsr s1\n"); \
717 }
718 #else
719 #define SAVE_FPU_STATE()
720 #define RESTORE_FPU_STATE()
721 #endif
722 
723 #ifdef __riscv_dsp
724 /*
725  * Save DSP context
726  * NOTE: DSP context registers are stored at word offset 41 in the stack
727  */
728 #define SAVE_DSP_CONTEXT() { \
729  __asm volatile("csrrs s4, %0, x0\n" ::"i"(CSR_UCODE):); \
730 }
731 /*
732  * @brief Restore DSP context
733  * @note DSP context registers are stored at word offset 41 in the stack
734  */
735 #define RESTORE_DSP_CONTEXT() {\
736  __asm volatile("csrw %0, s4\n" ::"i"(CSR_UCODE):); \
737 }
738 
739 #else
740 #define SAVE_DSP_CONTEXT()
741 #define RESTORE_DSP_CONTEXT()
742 #endif
743 
744 /*
745  * @brief Enter Nested IRQ Handling
746  * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
747  * MCAUSE - word offset 16 (not used in the vectored mode)
748  * EPC - word offset 17
749  * MSTATUS = word offset 18
750  * MXSTATUS = word offset 19
751  */
752 #define ENTER_NESTED_IRQ_HANDLING_M() { \
753  __asm volatile("\n\
754  csrr s2, mepc \n\
755  csrr s3, mstatus \n");\
756  SAVE_FPU_STATE(); \
757  SAVE_DSP_CONTEXT(); \
758  __asm volatile("csrsi mstatus, 8"); \
759 }
760 
761 /*
762  * @brief Complete IRQ Handling
763  */
764 #define COMPLETE_IRQ_HANDLING_M(irq_num) { \
765  __asm volatile("csrci mstatus, 8"); \
766  __asm volatile("lui a4, 0xe4200"); \
767  __asm volatile("li a3, %0" : : "i" (irq_num) :); \
768  __asm volatile("sw a3, 4(a4)"); \
769 }
770 
771 /*
772  * @brief Exit Nested IRQ Handling
773  * @note To simplify the logic, Nested IRQ related registers are stored in the stack as below:
774  * MCAUSE - word offset 16 (not used in the vectored mode)
775  * EPC - word offset 17
776  * MSTATUS = word offset 18
777  * MXSTATUS = word offset 19
778  */
779 #define EXIT_NESTED_IRQ_HANDLING_M() { \
780  __asm volatile("\n\
781  csrw mstatus, s3 \n\
782  csrw mepc, s2 \n");\
783  RESTORE_FPU_STATE(); \
784  RESTORE_DSP_CONTEXT(); \
785 }
786 
787 /* @brief Nested IRQ entry macro : Save CSRs and enable global irq. */
788 #define NESTED_IRQ_ENTER() \
789  SAVE_CSR(CSR_MEPC) \
790  SAVE_CSR(CSR_MSTATUS) \
791  SAVE_MXSTATUS() \
792  SAVE_FCSR() \
793  SAVE_UCODE() \
794  set_csr(CSR_MSTATUS, CSR_MSTATUS_MIE_MASK);
795 
796 /* @brief Nested IRQ exit macro : Restore CSRs */
797 #define NESTED_IRQ_EXIT() \
798  RESTORE_CSR(CSR_MSTATUS) \
799  RESTORE_CSR(CSR_MEPC) \
800  RESTORE_MXSTATUS() \
801  RESTORE_FCSR() \
802  RESTORE_UCODE()
803 
804 #ifdef __cplusplus
805 #define HPM_EXTERN_C extern "C"
806 #else
807 #define HPM_EXTERN_C
808 #endif
809 
810 #define ISR_NAME_M(irq_num) default_isr_##irq_num
817 #if !defined(USE_NONVECTOR_MODE) || (USE_NONVECTOR_MODE == 0)
818 #if defined(CONFIG_FREERTOS) && CONFIG_FREERTOS
819 #define FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num) irq_handler_wrapper_##irq_num
820 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
821 void isr(void) __attribute__((section(".isr_vector"))); \
822 HPM_EXTERN_C void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) __attribute__((section(".isr_vector"))); \
823 void FREERTOS_VECTOR_ISR_WRAPPER_NAME(irq_num)(void) \
824 { \
825  isr();\
826 }
827 #else
828 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
829 void isr(void) __attribute__((section(".isr_vector")));\
830 HPM_EXTERN_C HPM_ATTR_MACHINE_INTERRUPT void ISR_NAME_M(irq_num)(void);\
831 HPM_ATTR_MACHINE_INTERRUPT void ISR_NAME_M(irq_num)(void) \
832 { \
833  SAVE_CALLER_CONTEXT(); \
834  ENTER_NESTED_IRQ_HANDLING_M();\
835  __asm volatile("la t1, %0\n\t" : : "i" (isr) : );\
836  __asm volatile("jalr t1\n");\
837  COMPLETE_IRQ_HANDLING_M(irq_num);\
838  EXIT_NESTED_IRQ_HANDLING_M();\
839  RESTORE_CALLER_CONTEXT();\
840  __asm volatile("fence io, io");\
841 }
842 #endif
843 #else
844 #define SDK_DECLARE_EXT_ISR_M(irq_num, isr) \
845 void isr(void) __attribute__((section(".isr_vector")));\
846 HPM_EXTERN_C void ISR_NAME_M(irq_num)(void) __attribute__((section(".isr_vector")));\
847 void ISR_NAME_M(irq_num)(void) \
848 { \
849  isr(); \
850 }
851 #endif
852 
853 
859 #define SDK_DECLARE_MCHTMR_ISR(isr) \
860 void isr(void) __attribute__((section(".isr_vector")));\
861 HPM_EXTERN_C void mchtmr_isr(void) __attribute__((section(".isr_vector"))); \
862 void mchtmr_isr(void) \
863 { \
864  isr();\
865 }
866 
872 #define SDK_DECLARE_SWI_ISR(isr)\
873 void isr(void) __attribute__((section(".isr_vector")));\
874 HPM_EXTERN_C void swi_isr(void) __attribute__((section(".isr_vector"))); \
875 void swi_isr(void) \
876 { \
877  isr();\
878 }
879 
880 
881 #ifdef __cplusplus
882 }
883 #endif
884 
888 #endif /* HPM_INTERRUPT_H */
CSR_MIE_MEIE_MASK
#define CSR_MIE_MEIE_MASK
Definition: hpm_csr_regs.h:734
CSR_MSTATUS
#define CSR_MSTATUS
Definition: hpm_csr_regs.h:21
CSR_MIE_MTIE_MASK
#define CSR_MIE_MTIE_MASK
Definition: hpm_csr_regs.h:758
CSR_MIE
#define CSR_MIE
Definition: hpm_csr_regs.h:23
CSR_MIE_MSIE_MASK
#define CSR_MIE_MSIE_MASK
Definition: hpm_csr_regs.h:782
HPM_PLICSW_BASE
#define HPM_PLICSW_BASE
Definition: hpm_soc.h:52
HPM_PLIC_BASE
#define HPM_PLIC_BASE
Definition: hpm_soc.h:38
intc_complete_irq
static ATTR_ALWAYS_INLINE void intc_complete_irq(uint32_t target, uint32_t irq)
Complete IRQ.
Definition: hpm_interrupt.h:279
enable_global_irq
static ATTR_ALWAYS_INLINE void enable_global_irq(uint32_t mask)
Enable global IRQ with mask.
Definition: hpm_interrupt.h:34
intc_m_disable_swi
static ATTR_ALWAYS_INLINE void intc_m_disable_swi(void)
Disable software interrupt.
Definition: hpm_interrupt.h:126
disable_irq_from_intc
static ATTR_ALWAYS_INLINE void disable_irq_from_intc(void)
Disable IRQ from interrupt controller.
Definition: hpm_interrupt.h:73
intc_set_irq_priority
static ATTR_ALWAYS_INLINE void intc_set_irq_priority(uint32_t irq, uint32_t priority)
Set interrupt priority.
Definition: hpm_interrupt.h:224
intc_disable_irq
static ATTR_ALWAYS_INLINE void intc_disable_irq(uint32_t target, uint32_t irq)
Disable specific interrupt.
Definition: hpm_interrupt.h:235
intc_m_trigger_swi
static ATTR_ALWAYS_INLINE void intc_m_trigger_swi(void)
Trigger software interrupt.
Definition: hpm_interrupt.h:136
install_isr
static ATTR_ALWAYS_INLINE void install_isr(uint32_t irq, uint32_t isr)
Install ISR for certain IRQ for ram based vector table.
Definition: hpm_interrupt.h:299
enable_irq_from_intc
static ATTR_ALWAYS_INLINE void enable_irq_from_intc(void)
Enable IRQ from interrupt controller.
Definition: hpm_interrupt.h:64
restore_global_irq
static ATTR_ALWAYS_INLINE void restore_global_irq(uint32_t mask)
Restore global IRQ with mask.
Definition: hpm_interrupt.h:55
intc_enable_irq
static ATTR_ALWAYS_INLINE void intc_enable_irq(uint32_t target, uint32_t irq)
Definition: hpm_interrupt.h:213
disable_mchtmr_irq
static ATTR_ALWAYS_INLINE void disable_mchtmr_irq(void)
Disable machine timer IRQ.
Definition: hpm_interrupt.h:90
intc_m_init_swi
static ATTR_ALWAYS_INLINE void intc_m_init_swi(void)
Initialize software interrupt.
Definition: hpm_interrupt.h:106
intc_m_enable_swi
static ATTR_ALWAYS_INLINE void intc_m_enable_swi(void)
Enable software interrupt.
Definition: hpm_interrupt.h:116
intc_m_complete_swi
static ATTR_ALWAYS_INLINE void intc_m_complete_swi(void)
Complete software interrupt.
Definition: hpm_interrupt.h:154
intc_get_threshold
static ATTR_ALWAYS_INLINE uint32_t intc_get_threshold(uint32_t target)
Get interrupt threshold.
Definition: hpm_interrupt.h:256
intc_set_threshold
static ATTR_ALWAYS_INLINE void intc_set_threshold(uint32_t target, uint32_t threshold)
Set interrupt threshold.
Definition: hpm_interrupt.h:246
uninstall_isr
static ATTR_ALWAYS_INLINE void uninstall_isr(uint32_t irq)
Uninstall ISR for certain IRQ for ram based vector table.
Definition: hpm_interrupt.h:310
intc_claim_irq
static ATTR_ALWAYS_INLINE uint32_t intc_claim_irq(uint32_t target)
Claim IRQ.
Definition: hpm_interrupt.h:267
intc_m_claim_swi
static ATTR_ALWAYS_INLINE void intc_m_claim_swi(void)
Claim software interrupt.
Definition: hpm_interrupt.h:145
disable_global_irq
static ATTR_ALWAYS_INLINE uint32_t disable_global_irq(uint32_t mask)
Disable global IRQ with mask and return mstatus.
Definition: hpm_interrupt.h:45
enable_mchtmr_irq
static ATTR_ALWAYS_INLINE void enable_mchtmr_irq(void)
Enable machine timer IRQ.
Definition: hpm_interrupt.h:81
hpm_plic_drv.h
default_irq_entry
void default_irq_entry(void)
PLICSWI
#define PLICSWI
Definition: hpm_interrupt.h:100
HPM_PLIC_TARGET_M_MODE
#define HPM_PLIC_TARGET_M_MODE
Definition: hpm_plic_drv.h:17
hpm_common.h
hpm_csr_drv.h
set_csr
#define set_csr(csr_num, bit)
set bits in csr
Definition: riscv_core.h:58
clear_csr
#define clear_csr(csr_num, bit)
clear bits in csr
Definition: riscv_core.h:30
read_clear_csr
#define read_clear_csr(csr_num, bit)
read and clear bits in csr
Definition: riscv_core.h:40