HPM SDK
HPMicro Software Development Kit
hpm_dmav2_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_DMAV2_H
10 #define HPM_DMAV2_H
11 
12 typedef struct {
13  __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */
14  __R uint32_t IDMISC; /* 0x4: ID Misc */
15  __R uint8_t RESERVED1[8]; /* 0x8 - 0xF: Reserved */
16  __R uint32_t DMACFG; /* 0x10: DMAC Configuration Register */
17  __W uint32_t DMACTRL; /* 0x14: DMAC Control Register */
18  __W uint32_t CHABORT; /* 0x18: Channel Abort Register */
19  __R uint8_t RESERVED2[8]; /* 0x1C - 0x23: Reserved */
20  __RW uint32_t INTHALFSTS; /* 0x24: Harlf Complete Interrupt Status */
21  __W uint32_t INTTCSTS; /* 0x28: Trans Complete Interrupt Status Register */
22  __W uint32_t INTABORTSTS; /* 0x2C: Abort Interrupt Status Register */
23  __W uint32_t INTERRSTS; /* 0x30: Error Interrupt Status Register */
24  __R uint32_t CHEN; /* 0x34: Channel Enable Register */
25  __R uint8_t RESERVED3[8]; /* 0x38 - 0x3F: Reserved */
26  struct {
27  __RW uint32_t CTRL; /* 0x40: Channel Control Register */
28  __RW uint32_t TRANSIZE; /* 0x44: Channel Transfer Size Register */
29  __RW uint32_t SRCADDR; /* 0x48: Channel Source Address Low Part Register */
30  __RW uint32_t CHANREQCTRL; /* 0x4C: Channel DMA Request Control Register */
31  __RW uint32_t DSTADDR; /* 0x50: Channel Destination Address Low Part Register */
32  __R uint8_t RESERVED0[4]; /* 0x54 - 0x57: Reserved */
33  __RW uint32_t LLPOINTER; /* 0x58: Channel Linked List Pointer Low Part Register */
34  __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */
35  } CHCTRL[32];
36 } DMAV2_Type;
37 
38 
39 /* Bitfield definition for register: IDMISC */
40 /*
41  * DMASTATE (RO)
42  *
43  * DMA state machine
44  * localparam ST_IDLE = 3'b000;
45  * localparam ST_READ = 3'b001;
46  * localparam ST_READ_ACK = 3'b010;
47  * localparam ST_WRITE = 3'b011;
48  * localparam ST_WRITE_ACK = 3'b100;
49  * localparam ST_LL = 3'b101;
50  * localparam ST_END = 3'b110;
51  * localparam ST_END_WAIT = 3'b111;
52  */
53 #define DMAV2_IDMISC_DMASTATE_MASK (0xE000U)
54 #define DMAV2_IDMISC_DMASTATE_SHIFT (13U)
55 #define DMAV2_IDMISC_DMASTATE_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_DMASTATE_MASK) >> DMAV2_IDMISC_DMASTATE_SHIFT)
56 
57 /*
58  * CURCHAN (RO)
59  *
60  * current channel in used
61  */
62 #define DMAV2_IDMISC_CURCHAN_MASK (0x1F00U)
63 #define DMAV2_IDMISC_CURCHAN_SHIFT (8U)
64 #define DMAV2_IDMISC_CURCHAN_GET(x) (((uint32_t)(x) & DMAV2_IDMISC_CURCHAN_MASK) >> DMAV2_IDMISC_CURCHAN_SHIFT)
65 
66 /* Bitfield definition for register: DMACFG */
67 /*
68  * CHAINXFR (RO)
69  *
70  * Chain transfer
71  * 0x0: Chain transfer is not configured
72  * 0x1: Chain transfer is configured
73  */
74 #define DMAV2_DMACFG_CHAINXFR_MASK (0x80000000UL)
75 #define DMAV2_DMACFG_CHAINXFR_SHIFT (31U)
76 #define DMAV2_DMACFG_CHAINXFR_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHAINXFR_MASK) >> DMAV2_DMACFG_CHAINXFR_SHIFT)
77 
78 /*
79  * REQSYNC (RO)
80  *
81  * DMA request synchronization.
82  * The DMA request synchronization should be configured to avoid signal integrity problems when the request signal is not clocked by the system bus clock,
83  * which the DMA control logic operates in. If the request synchronization is not configured, the request signal is sampled directly without synchronization.
84  * 0x0: Request synchronization is not configured
85  * 0x1: Request synchronization is configured
86  */
87 #define DMAV2_DMACFG_REQSYNC_MASK (0x40000000UL)
88 #define DMAV2_DMACFG_REQSYNC_SHIFT (30U)
89 #define DMAV2_DMACFG_REQSYNC_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQSYNC_MASK) >> DMAV2_DMACFG_REQSYNC_SHIFT)
90 
91 /*
92  * DATAWIDTH (RO)
93  *
94  * AXI bus data width
95  * 0x0: 32 bits
96  * 0x1: 64 bits
97  * 0x2: 128 bits
98  * 0x3: 256 bits
99  */
100 #define DMAV2_DMACFG_DATAWIDTH_MASK (0x3000000UL)
101 #define DMAV2_DMACFG_DATAWIDTH_SHIFT (24U)
102 #define DMAV2_DMACFG_DATAWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_DATAWIDTH_MASK) >> DMAV2_DMACFG_DATAWIDTH_SHIFT)
103 
104 /*
105  * ADDRWIDTH (RO)
106  *
107  * AXI bus address width
108  * 0x18: 24 bits
109  * 0x19: 25 bits
110  * ...
111  * 0x40: 64 bits
112  * Others: Invalid
113  */
114 #define DMAV2_DMACFG_ADDRWIDTH_MASK (0xFE0000UL)
115 #define DMAV2_DMACFG_ADDRWIDTH_SHIFT (17U)
116 #define DMAV2_DMACFG_ADDRWIDTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_ADDRWIDTH_MASK) >> DMAV2_DMACFG_ADDRWIDTH_SHIFT)
117 
118 /*
119  * CORENUM (RO)
120  *
121  * DMA core number
122  * 0x0: 1 core
123  * 0x1: 2 cores
124  */
125 #define DMAV2_DMACFG_CORENUM_MASK (0x10000UL)
126 #define DMAV2_DMACFG_CORENUM_SHIFT (16U)
127 #define DMAV2_DMACFG_CORENUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CORENUM_MASK) >> DMAV2_DMACFG_CORENUM_SHIFT)
128 
129 /*
130  * BUSNUM (RO)
131  *
132  * AXI bus interface number
133  * 0x0: 1 AXI bus
134  * 0x1: 2 AXI busses
135  */
136 #define DMAV2_DMACFG_BUSNUM_MASK (0x8000U)
137 #define DMAV2_DMACFG_BUSNUM_SHIFT (15U)
138 #define DMAV2_DMACFG_BUSNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_BUSNUM_MASK) >> DMAV2_DMACFG_BUSNUM_SHIFT)
139 
140 /*
141  * REQNUM (RO)
142  *
143  * Request/acknowledge pair number
144  * 0x0: 0 pair
145  * 0x1: 1 pair
146  * 0x2: 2 pairs
147  * ...
148  * 0x10: 16 pairs
149  */
150 #define DMAV2_DMACFG_REQNUM_MASK (0x7C00U)
151 #define DMAV2_DMACFG_REQNUM_SHIFT (10U)
152 #define DMAV2_DMACFG_REQNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_REQNUM_MASK) >> DMAV2_DMACFG_REQNUM_SHIFT)
153 
154 /*
155  * FIFODEPTH (RO)
156  *
157  * FIFO depth
158  * 0x4: 4 entries
159  * 0x8: 8 entries
160  * 0x10: 16 entries
161  * 0x20: 32 entries
162  * Others: Invalid
163  */
164 #define DMAV2_DMACFG_FIFODEPTH_MASK (0x3F0U)
165 #define DMAV2_DMACFG_FIFODEPTH_SHIFT (4U)
166 #define DMAV2_DMACFG_FIFODEPTH_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_FIFODEPTH_MASK) >> DMAV2_DMACFG_FIFODEPTH_SHIFT)
167 
168 /*
169  * CHANNELNUM (RO)
170  *
171  * Channel number
172  * 0x1: 1 channel
173  * 0x2: 2 channels
174  * ...
175  * 0x8: 8 channels
176  * Others: Invalid
177  */
178 #define DMAV2_DMACFG_CHANNELNUM_MASK (0xFU)
179 #define DMAV2_DMACFG_CHANNELNUM_SHIFT (0U)
180 #define DMAV2_DMACFG_CHANNELNUM_GET(x) (((uint32_t)(x) & DMAV2_DMACFG_CHANNELNUM_MASK) >> DMAV2_DMACFG_CHANNELNUM_SHIFT)
181 
182 /* Bitfield definition for register: DMACTRL */
183 /*
184  * RESET (WO)
185  *
186  * Software reset control. Write 1 to this bit to reset the DMA core and disable all channels.
187  * Note: The software reset may cause the in-completion of AXI transaction.
188  */
189 #define DMAV2_DMACTRL_RESET_MASK (0x1U)
190 #define DMAV2_DMACTRL_RESET_SHIFT (0U)
191 #define DMAV2_DMACTRL_RESET_SET(x) (((uint32_t)(x) << DMAV2_DMACTRL_RESET_SHIFT) & DMAV2_DMACTRL_RESET_MASK)
192 #define DMAV2_DMACTRL_RESET_GET(x) (((uint32_t)(x) & DMAV2_DMACTRL_RESET_MASK) >> DMAV2_DMACTRL_RESET_SHIFT)
193 
194 /* Bitfield definition for register: CHABORT */
195 /*
196  * CHABORT (WO)
197  *
198  * Write 1 to bit n to abort channel n. The bits should only be set when the corresponding channels are enabled.
199  * Otherwise, the writes will be ignored for channels that are not enabled. (N: Number of channels)
200  */
201 #define DMAV2_CHABORT_CHABORT_MASK (0xFFFFFFFFUL)
202 #define DMAV2_CHABORT_CHABORT_SHIFT (0U)
203 #define DMAV2_CHABORT_CHABORT_SET(x) (((uint32_t)(x) << DMAV2_CHABORT_CHABORT_SHIFT) & DMAV2_CHABORT_CHABORT_MASK)
204 #define DMAV2_CHABORT_CHABORT_GET(x) (((uint32_t)(x) & DMAV2_CHABORT_CHABORT_MASK) >> DMAV2_CHABORT_CHABORT_SHIFT)
205 
206 /* Bitfield definition for register: INTHALFSTS */
207 /*
208  * STS (RW)
209  *
210  * half transfer done irq status
211  */
212 #define DMAV2_INTHALFSTS_STS_MASK (0xFFFFFFFFUL)
213 #define DMAV2_INTHALFSTS_STS_SHIFT (0U)
214 #define DMAV2_INTHALFSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTHALFSTS_STS_SHIFT) & DMAV2_INTHALFSTS_STS_MASK)
215 #define DMAV2_INTHALFSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTHALFSTS_STS_MASK) >> DMAV2_INTHALFSTS_STS_SHIFT)
216 
217 /* Bitfield definition for register: INTTCSTS */
218 /*
219  * STS (W1C)
220  *
221  * The terminal count status, one bit per channel. The terminal count status is set when a channel transfer finishes without the abort or error event.
222  * 0x0: Channel n has no terminal count status
223  * 0x1: Channel n has terminal count status
224  */
225 #define DMAV2_INTTCSTS_STS_MASK (0xFFFFFFFFUL)
226 #define DMAV2_INTTCSTS_STS_SHIFT (0U)
227 #define DMAV2_INTTCSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTTCSTS_STS_SHIFT) & DMAV2_INTTCSTS_STS_MASK)
228 #define DMAV2_INTTCSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTTCSTS_STS_MASK) >> DMAV2_INTTCSTS_STS_SHIFT)
229 
230 /* Bitfield definition for register: INTABORTSTS */
231 /*
232  * STS (W1C)
233  *
234  * The abort status of channel, one bit per channel. The abort status is set when a channel transfer is aborted.
235  * 0x0: Channel n has no abort status
236  * 0x1: Channel n has abort status
237  */
238 #define DMAV2_INTABORTSTS_STS_MASK (0xFFFFFFFFUL)
239 #define DMAV2_INTABORTSTS_STS_SHIFT (0U)
240 #define DMAV2_INTABORTSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTABORTSTS_STS_SHIFT) & DMAV2_INTABORTSTS_STS_MASK)
241 #define DMAV2_INTABORTSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTABORTSTS_STS_MASK) >> DMAV2_INTABORTSTS_STS_SHIFT)
242 
243 /* Bitfield definition for register: INTERRSTS */
244 /*
245  * STS (W1C)
246  *
247  * The error status, one bit per channel. The error status is set when a channel transfer encounters the following error events:
248  * - Bus error
249  * - Unaligned address
250  * - Unaligned transfer width
251  * - Reserved configuration
252  * 0x0: Channel n has no error status
253  * 0x1: Channel n has error status
254  */
255 #define DMAV2_INTERRSTS_STS_MASK (0xFFFFFFFFUL)
256 #define DMAV2_INTERRSTS_STS_SHIFT (0U)
257 #define DMAV2_INTERRSTS_STS_SET(x) (((uint32_t)(x) << DMAV2_INTERRSTS_STS_SHIFT) & DMAV2_INTERRSTS_STS_MASK)
258 #define DMAV2_INTERRSTS_STS_GET(x) (((uint32_t)(x) & DMAV2_INTERRSTS_STS_MASK) >> DMAV2_INTERRSTS_STS_SHIFT)
259 
260 /* Bitfield definition for register: CHEN */
261 /*
262  * CHEN (RO)
263  *
264  * Alias of the Enable field of all ChnCtrl registers
265  */
266 #define DMAV2_CHEN_CHEN_MASK (0xFFFFFFFFUL)
267 #define DMAV2_CHEN_CHEN_SHIFT (0U)
268 #define DMAV2_CHEN_CHEN_GET(x) (((uint32_t)(x) & DMAV2_CHEN_CHEN_MASK) >> DMAV2_CHEN_CHEN_SHIFT)
269 
270 /* Bitfield definition for register of struct array CHCTRL: CTRL */
271 /*
272  * INFINITELOOP (RW)
273  *
274  * set to loop current config infinitely
275  */
276 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK (0x80000000UL)
277 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT (31U)
278 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK)
279 #define DMAV2_CHCTRL_CTRL_INFINITELOOP_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INFINITELOOP_MASK) >> DMAV2_CHCTRL_CTRL_INFINITELOOP_SHIFT)
280 
281 /*
282  * HANDSHAKEOPT (RW)
283  *
284  * 0: one request to transfer one burst
285  * 1: one request to transfer all the data defined in ch_tts
286  */
287 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK (0x40000000UL)
288 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT (30U)
289 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK)
290 #define DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_MASK) >> DMAV2_CHCTRL_CTRL_HANDSHAKEOPT_SHIFT)
291 
292 /*
293  * PRIORITY (RW)
294  *
295  * Channel priority level
296  * 0x0: Lower priority
297  * 0x1: Higher priority
298  */
299 #define DMAV2_CHCTRL_CTRL_PRIORITY_MASK (0x20000000UL)
300 #define DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT (29U)
301 #define DMAV2_CHCTRL_CTRL_PRIORITY_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK)
302 #define DMAV2_CHCTRL_CTRL_PRIORITY_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_PRIORITY_MASK) >> DMAV2_CHCTRL_CTRL_PRIORITY_SHIFT)
303 
304 /*
305  * BURSTOPT (RW)
306  *
307  * set to change burst_size definition
308  */
309 #define DMAV2_CHCTRL_CTRL_BURSTOPT_MASK (0x10000000UL)
310 #define DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT (28U)
311 #define DMAV2_CHCTRL_CTRL_BURSTOPT_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK)
312 #define DMAV2_CHCTRL_CTRL_BURSTOPT_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_BURSTOPT_MASK) >> DMAV2_CHCTRL_CTRL_BURSTOPT_SHIFT)
313 
314 /*
315  * SRCBURSTSIZE (RW)
316  *
317  * Source burst size. This field indicates the number of transfers before DMA channel re-arbitration.
318  * The burst transfer byte number is (SrcBurstSize * SrcWidth).
319  * 0x0: 1 transfer
320  * 0x1: 2 transfers
321  * 0x2: 4 transfers
322  * 0x3: 8 transfers
323  * 0x4: 16 transfers
324  * 0x5: 32 transfers
325  * 0x6: 64 transfers
326  * 0x7: 128 transfers
327  * 0x8: 256 transfers
328  * 0x9:512 transfers
329  * 0xa: 1024 transfers
330  * 0xb - 0xf: Reserved, setting this field with a reserved value triggers the error exception
331  */
332 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK (0xF000000UL)
333 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT (24U)
334 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK)
335 #define DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_MASK) >> DMAV2_CHCTRL_CTRL_SRCBURSTSIZE_SHIFT)
336 
337 /*
338  * SRCWIDTH (RW)
339  *
340  * Source transfer width
341  * 0x0: Byte transfer
342  * 0x1: Half-word transfer
343  * 0x2: Word transfer
344  * 0x3: Double word transfer
345  * 0x4: Quad word transfer
346  * 0x5: Eight word transfer
347  * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception
348  */
349 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK (0xE00000UL)
350 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT (21U)
351 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK)
352 #define DMAV2_CHCTRL_CTRL_SRCWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_SRCWIDTH_SHIFT)
353 
354 /*
355  * DSTWIDTH (RW)
356  *
357  * Destination transfer width.
358  * Both the total transfer byte number and the burst transfer byte number should be aligned to the destination transfer width;
359  * otherwise the error event will be triggered.
360  * For example, destination transfer width should be set as byte transfer if total transfer byte is not aligned to half-word.
361  * See field SrcBurstSize above for the definition of burst transfer byte number and section 3.2.8 for the definition of the total transfer byte number.
362  * 0x0: Byte transfer
363  * 0x1: Half-word transfer
364  * 0x2: Word transfer
365  * 0x3: Double word transfer
366  * 0x4: Quad word transfer
367  * 0x5: Eight word transfer
368  * 0x6 - 0x7: Reserved, setting this field with a reserved value triggers the error exception
369  */
370 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK (0x1C0000UL)
371 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT (18U)
372 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK)
373 #define DMAV2_CHCTRL_CTRL_DSTWIDTH_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTWIDTH_MASK) >> DMAV2_CHCTRL_CTRL_DSTWIDTH_SHIFT)
374 
375 /*
376  * SRCMODE (RW)
377  *
378  * Source DMA handshake mode
379  * 0x0: Normal mode
380  * 0x1: Handshake mode
381  * Normal mode is enabled and started by software set Enable bit;
382  * Handshake mode is enabled by software set Enable bit, started by hardware dma request from DMAMUX block
383  */
384 #define DMAV2_CHCTRL_CTRL_SRCMODE_MASK (0x20000UL)
385 #define DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT (17U)
386 #define DMAV2_CHCTRL_CTRL_SRCMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK)
387 #define DMAV2_CHCTRL_CTRL_SRCMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCMODE_MASK) >> DMAV2_CHCTRL_CTRL_SRCMODE_SHIFT)
388 
389 /*
390  * DSTMODE (RW)
391  *
392  * Destination DMA handshake mode
393  * 0x0: Normal mode
394  * 0x1: Handshake mode
395  * the difference bewteen Source/Destination handshake mode is:
396  * the dma block will response hardware request after read in Source handshake mode;
397  * the dma block will response hardware request after write in Destination handshake mode;
398  * NOTE: can't set SrcMode and DstMode at same time, otherwise result unknown.
399  */
400 #define DMAV2_CHCTRL_CTRL_DSTMODE_MASK (0x10000UL)
401 #define DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT (16U)
402 #define DMAV2_CHCTRL_CTRL_DSTMODE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK)
403 #define DMAV2_CHCTRL_CTRL_DSTMODE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTMODE_MASK) >> DMAV2_CHCTRL_CTRL_DSTMODE_SHIFT)
404 
405 /*
406  * SRCADDRCTRL (RW)
407  *
408  * Source address control
409  * 0x0: Increment address
410  * 0x1: Decrement address
411  * 0x2: Fixed address
412  * 0x3: Reserved, setting the field with this value triggers the error exception
413  */
414 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK (0xC000U)
415 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT (14U)
416 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK)
417 #define DMAV2_CHCTRL_CTRL_SRCADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_SRCADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_SRCADDRCTRL_SHIFT)
418 
419 /*
420  * DSTADDRCTRL (RW)
421  *
422  * Destination address control
423  * 0x0: Increment address
424  * 0x1: Decrement address
425  * 0x2: Fixed address
426  * 0x3: Reserved, setting the field with this value triggers the error exception
427  */
428 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK (0x3000U)
429 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT (12U)
430 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK)
431 #define DMAV2_CHCTRL_CTRL_DSTADDRCTRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_DSTADDRCTRL_MASK) >> DMAV2_CHCTRL_CTRL_DSTADDRCTRL_SHIFT)
432 
433 /*
434  * INTHALFCNTMASK (RW)
435  *
436  * Channel half interrupt mask
437  * 0x0: Allow the half interrupt to be triggered
438  * 0x1: Disable the half interrupt
439  */
440 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK (0x10U)
441 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT (4U)
442 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK)
443 #define DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTHALFCNTMASK_SHIFT)
444 
445 /*
446  * INTABTMASK (RW)
447  *
448  * Channel abort interrupt mask
449  * 0x0: Allow the abort interrupt to be triggered
450  * 0x1: Disable the abort interrupt
451  */
452 #define DMAV2_CHCTRL_CTRL_INTABTMASK_MASK (0x8U)
453 #define DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT (3U)
454 #define DMAV2_CHCTRL_CTRL_INTABTMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK)
455 #define DMAV2_CHCTRL_CTRL_INTABTMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTABTMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTABTMASK_SHIFT)
456 
457 /*
458  * INTERRMASK (RW)
459  *
460  * Channel error interrupt mask
461  * 0x0: Allow the error interrupt to be triggered
462  * 0x1: Disable the error interrupt
463  */
464 #define DMAV2_CHCTRL_CTRL_INTERRMASK_MASK (0x4U)
465 #define DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT (2U)
466 #define DMAV2_CHCTRL_CTRL_INTERRMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK)
467 #define DMAV2_CHCTRL_CTRL_INTERRMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTERRMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTERRMASK_SHIFT)
468 
469 /*
470  * INTTCMASK (RW)
471  *
472  * Channel terminal count interrupt mask
473  * 0x0: Allow the terminal count interrupt to be triggered
474  * 0x1: Disable the terminal count interrupt
475  */
476 #define DMAV2_CHCTRL_CTRL_INTTCMASK_MASK (0x2U)
477 #define DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT (1U)
478 #define DMAV2_CHCTRL_CTRL_INTTCMASK_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK)
479 #define DMAV2_CHCTRL_CTRL_INTTCMASK_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_INTTCMASK_MASK) >> DMAV2_CHCTRL_CTRL_INTTCMASK_SHIFT)
480 
481 /*
482  * ENABLE (RW)
483  *
484  * Channel enable bit
485  * 0x0: Disable
486  * 0x1: Enable
487  */
488 #define DMAV2_CHCTRL_CTRL_ENABLE_MASK (0x1U)
489 #define DMAV2_CHCTRL_CTRL_ENABLE_SHIFT (0U)
490 #define DMAV2_CHCTRL_CTRL_ENABLE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CTRL_ENABLE_SHIFT) & DMAV2_CHCTRL_CTRL_ENABLE_MASK)
491 #define DMAV2_CHCTRL_CTRL_ENABLE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CTRL_ENABLE_MASK) >> DMAV2_CHCTRL_CTRL_ENABLE_SHIFT)
492 
493 /* Bitfield definition for register of struct array CHCTRL: TRANSIZE */
494 /*
495  * TRANSIZE (RW)
496  *
497  * Total transfer size from source. The total number of transferred bytes is (TranSize * SrcWidth). This register is cleared when the DMA transfer is done.
498  * If a channel is enabled with zero total transfer size, the error event will be triggered and the transfer will be terminated.
499  */
500 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK (0xFFFFFFFUL)
501 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT (0U)
502 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK)
503 #define DMAV2_CHCTRL_TRANSIZE_TRANSIZE_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_TRANSIZE_TRANSIZE_MASK) >> DMAV2_CHCTRL_TRANSIZE_TRANSIZE_SHIFT)
504 
505 /* Bitfield definition for register of struct array CHCTRL: SRCADDR */
506 /*
507  * SRCADDRL (RW)
508  *
509  * Low part of the source starting address. When the transfer completes, the value of {SrcAddrH,SrcAddrL} is updated to the ending address.
510  * This address must be aligned to the source transfer size; otherwise, an error event will be triggered.
511  */
512 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK (0xFFFFFFFFUL)
513 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT (0U)
514 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK)
515 #define DMAV2_CHCTRL_SRCADDR_SRCADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_SRCADDR_SRCADDRL_MASK) >> DMAV2_CHCTRL_SRCADDR_SRCADDRL_SHIFT)
516 
517 /* Bitfield definition for register of struct array CHCTRL: CHANREQCTRL */
518 /*
519  * SRCREQSEL (RW)
520  *
521  * Source DMA request select. Select the request/ack handshake pair that the source device is connected to.
522  */
523 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK (0x1F000000UL)
524 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT (24U)
525 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK)
526 #define DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_SRCREQSEL_SHIFT)
527 
528 /*
529  * DSTREQSEL (RW)
530  *
531  * Destination DMA request select. Select the request/ack handshake pair that the destination device is connected to.
532  */
533 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK (0x1F0000UL)
534 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT (16U)
535 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK)
536 #define DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_MASK) >> DMAV2_CHCTRL_CHANREQCTRL_DSTREQSEL_SHIFT)
537 
538 /* Bitfield definition for register of struct array CHCTRL: DSTADDR */
539 /*
540  * DSTADDRL (RW)
541  *
542  * Low part of the destination starting address. When the transfer completes, the value of {DstAddrH,DstAddrL} is updated to the ending address.
543  * This address must be aligned to the destination transfer size; otherwise the error event will be triggered.
544  */
545 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK (0xFFFFFFFFUL)
546 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT (0U)
547 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK)
548 #define DMAV2_CHCTRL_DSTADDR_DSTADDRL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_DSTADDR_DSTADDRL_MASK) >> DMAV2_CHCTRL_DSTADDR_DSTADDRL_SHIFT)
549 
550 /* Bitfield definition for register of struct array CHCTRL: LLPOINTER */
551 /*
552  * LLPOINTERL (RW)
553  *
554  * Low part of the pointer to the next descriptor. The pointer must be double word aligned.
555  */
556 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK (0xFFFFFFF8UL)
557 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT (3U)
558 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SET(x) (((uint32_t)(x) << DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK)
559 #define DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_GET(x) (((uint32_t)(x) & DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_MASK) >> DMAV2_CHCTRL_LLPOINTER_LLPOINTERL_SHIFT)
560 
561 
562 
563 /* CHCTRL register group index macro definition */
564 #define DMAV2_CHCTRL_CH0 (0UL)
565 #define DMAV2_CHCTRL_CH1 (1UL)
566 #define DMAV2_CHCTRL_CH2 (2UL)
567 #define DMAV2_CHCTRL_CH3 (3UL)
568 #define DMAV2_CHCTRL_CH4 (4UL)
569 #define DMAV2_CHCTRL_CH5 (5UL)
570 #define DMAV2_CHCTRL_CH6 (6UL)
571 #define DMAV2_CHCTRL_CH7 (7UL)
572 #define DMAV2_CHCTRL_CH8 (8UL)
573 #define DMAV2_CHCTRL_CH9 (9UL)
574 #define DMAV2_CHCTRL_CH10 (10UL)
575 #define DMAV2_CHCTRL_CH11 (11UL)
576 #define DMAV2_CHCTRL_CH12 (12UL)
577 #define DMAV2_CHCTRL_CH13 (13UL)
578 #define DMAV2_CHCTRL_CH14 (14UL)
579 #define DMAV2_CHCTRL_CH15 (15UL)
580 #define DMAV2_CHCTRL_CH16 (16UL)
581 #define DMAV2_CHCTRL_CH17 (17UL)
582 #define DMAV2_CHCTRL_CH18 (18UL)
583 #define DMAV2_CHCTRL_CH19 (19UL)
584 #define DMAV2_CHCTRL_CH20 (20UL)
585 #define DMAV2_CHCTRL_CH21 (21UL)
586 #define DMAV2_CHCTRL_CH22 (22UL)
587 #define DMAV2_CHCTRL_CH23 (23UL)
588 #define DMAV2_CHCTRL_CH24 (24UL)
589 #define DMAV2_CHCTRL_CH25 (25UL)
590 #define DMAV2_CHCTRL_CH26 (26UL)
591 #define DMAV2_CHCTRL_CH27 (27UL)
592 #define DMAV2_CHCTRL_CH28 (28UL)
593 #define DMAV2_CHCTRL_CH29 (29UL)
594 #define DMAV2_CHCTRL_CH30 (30UL)
595 #define DMAV2_CHCTRL_CH31 (31UL)
596 
597 
598 #endif /* HPM_DMAV2_H */
DMAV2_Type
Definition: hpm_dmav2_regs.h:12