HPM SDK
HPMicro Software Development Kit
hpm_qeiv2_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_QEIV2_H
10 #define HPM_QEIV2_H
11 
12 typedef struct {
13  __RW uint32_t CR; /* 0x0: Control register */
14  __RW uint32_t PHCFG; /* 0x4: Phase configure register */
15  __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */
16  __RW uint32_t PHIDX; /* 0xC: Phase index register */
17  __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */
18  __RW uint32_t READEN; /* 0x14: Read event enable register */
19  __RW uint32_t ZCMP; /* 0x18: Z comparator */
20  __RW uint32_t PHCMP; /* 0x1C: Phase comparator */
21  __RW uint32_t SPDCMP; /* 0x20: Speed comparator */
22  __RW uint32_t DMAEN; /* 0x24: DMA request enable register */
23  __RW uint32_t SR; /* 0x28: Status register */
24  __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */
25  struct {
26  __RW uint32_t Z; /* 0x30: Z counter */
27  __R uint32_t PH; /* 0x34: Phase counter */
28  __RW uint32_t SPD; /* 0x38: Speed counter */
29  __R uint32_t TMR; /* 0x3C: Timer counter */
30  } COUNT[4];
31  __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */
32  __RW uint32_t ZCMP2; /* 0x80: Z comparator */
33  __RW uint32_t PHCMP2; /* 0x84: Phase comparator */
34  __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */
35  __RW uint32_t MATCH_CFG; /* 0x8C: */
36  __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */
37  __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */
38  __RW uint32_t QEI_CFG; /* 0x100: qei config register */
39  __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */
40  __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */
41  __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */
42  __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */
43  __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */
44  __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */
45  __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */
46  __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */
47  __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */
48  __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */
49  __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */
50  __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */
51  __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */
52  __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */
53  __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */
54  __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */
55  __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */
56  __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */
57  __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */
58  __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */
59  __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */
60  __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */
61  __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */
62  __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */
63  __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */
64  __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */
65  __R uint8_t RESERVED4[136]; /* 0x178 - 0x1FF: Reserved */
66  __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */
67  __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */
68  __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */
69  __R uint8_t RESERVED5[4]; /* 0x20C - 0x20F: Reserved */
70  __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */
71  __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */
72  __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */
73  __R uint8_t RESERVED6[4]; /* 0x21C - 0x21F: Reserved */
74  __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */
75  __R uint8_t RESERVED7[12]; /* 0x224 - 0x22F: Reserved */
76  __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */
77  __R uint8_t RESERVED8[4]; /* 0x234 - 0x237: Reserved */
78  __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */
79  __R uint8_t RESERVED9[4]; /* 0x23C - 0x23F: Reserved */
80  __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */
81  __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: uvw_pos0_cfg */
82  __R uint8_t RESERVED10[16]; /* 0x270 - 0x27F: Reserved */
83  __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */
84  __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */
85  __RW uint32_t POSITION; /* 0x288: position */
86  __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */
87  __R uint32_t ANGLE; /* 0x290: angle */
88  __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */
89 } QEIV2_Type;
90 
91 
92 /* Bitfield definition for register: CR */
93 /*
94  * READ (WO)
95  *
96  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0
97  */
98 #define QEIV2_CR_READ_MASK (0x80000000UL)
99 #define QEIV2_CR_READ_SHIFT (31U)
100 #define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK)
101 #define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT)
102 
103 /*
104  * ZCNTCFG (RW)
105  *
106  * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0
107  * 0- zcnt will increment or decrement when Z input assert
108  */
109 #define QEIV2_CR_ZCNTCFG_MASK (0x400000UL)
110 #define QEIV2_CR_ZCNTCFG_SHIFT (22U)
111 #define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK)
112 #define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT)
113 
114 /*
115  * PHCALIZ (RW)
116  *
117  * 1- phcnt will set to phidx when Z input assert(for abz digital signsl)
118  */
119 #define QEIV2_CR_PHCALIZ_MASK (0x200000UL)
120 #define QEIV2_CR_PHCALIZ_SHIFT (21U)
121 #define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK)
122 #define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT)
123 
124 /*
125  * Z_ONLY_EN (RW)
126  *
127  * 1- phcnt will set to phidx when Z input assert(for xy analog signal and digital z, also need set phcaliz)
128  */
129 #define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL)
130 #define QEIV2_CR_Z_ONLY_EN_SHIFT (20U)
131 #define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK)
132 #define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT)
133 
134 /*
135  * H2FDIR0 (RW)
136  *
137  */
138 #define QEIV2_CR_H2FDIR0_MASK (0x80000UL)
139 #define QEIV2_CR_H2FDIR0_SHIFT (19U)
140 #define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK)
141 #define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT)
142 
143 /*
144  * H2FDIR1 (RW)
145  *
146  */
147 #define QEIV2_CR_H2FDIR1_MASK (0x40000UL)
148 #define QEIV2_CR_H2FDIR1_SHIFT (18U)
149 #define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK)
150 #define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT)
151 
152 /*
153  * H2RDIR0 (RW)
154  *
155  */
156 #define QEIV2_CR_H2RDIR0_MASK (0x20000UL)
157 #define QEIV2_CR_H2RDIR0_SHIFT (17U)
158 #define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK)
159 #define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT)
160 
161 /*
162  * H2RDIR1 (RW)
163  *
164  */
165 #define QEIV2_CR_H2RDIR1_MASK (0x10000UL)
166 #define QEIV2_CR_H2RDIR1_SHIFT (16U)
167 #define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK)
168 #define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT)
169 
170 /*
171  * PAUSEPOS (RW)
172  *
173  * 1- pause position output valid when PAUSE assert
174  */
175 #define QEIV2_CR_PAUSEPOS_MASK (0x8000U)
176 #define QEIV2_CR_PAUSEPOS_SHIFT (15U)
177 #define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK)
178 #define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT)
179 
180 /*
181  * PAUSESPD (RW)
182  *
183  * 1- pause spdcnt when PAUSE assert
184  */
185 #define QEIV2_CR_PAUSESPD_MASK (0x4000U)
186 #define QEIV2_CR_PAUSESPD_SHIFT (14U)
187 #define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK)
188 #define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT)
189 
190 /*
191  * PAUSEPH (RW)
192  *
193  * 1- pause phcnt when PAUSE assert
194  */
195 #define QEIV2_CR_PAUSEPH_MASK (0x2000U)
196 #define QEIV2_CR_PAUSEPH_SHIFT (13U)
197 #define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK)
198 #define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT)
199 
200 /*
201  * PAUSEZ (RW)
202  *
203  * 1- pause zcnt when PAUSE assert
204  */
205 #define QEIV2_CR_PAUSEZ_MASK (0x1000U)
206 #define QEIV2_CR_PAUSEZ_SHIFT (12U)
207 #define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK)
208 #define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT)
209 
210 /*
211  * HFDIR0 (RW)
212  *
213  * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)
214  */
215 #define QEIV2_CR_HFDIR0_MASK (0x800U)
216 #define QEIV2_CR_HFDIR0_SHIFT (11U)
217 #define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK)
218 #define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT)
219 
220 /*
221  * HFDIR1 (RW)
222  *
223  * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)
224  */
225 #define QEIV2_CR_HFDIR1_MASK (0x400U)
226 #define QEIV2_CR_HFDIR1_SHIFT (10U)
227 #define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK)
228 #define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT)
229 
230 /*
231  * HRDIR0 (RW)
232  *
233  * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)
234  */
235 #define QEIV2_CR_HRDIR0_MASK (0x200U)
236 #define QEIV2_CR_HRDIR0_SHIFT (9U)
237 #define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK)
238 #define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT)
239 
240 /*
241  * HRDIR1 (RW)
242  *
243  * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)
244  */
245 #define QEIV2_CR_HRDIR1_MASK (0x100U)
246 #define QEIV2_CR_HRDIR1_SHIFT (8U)
247 #define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK)
248 #define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT)
249 
250 /*
251  * FAULTPOS (RW)
252  *
253  */
254 #define QEIV2_CR_FAULTPOS_MASK (0x40U)
255 #define QEIV2_CR_FAULTPOS_SHIFT (6U)
256 #define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK)
257 #define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT)
258 
259 /*
260  * SNAPEN (RW)
261  *
262  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert
263  */
264 #define QEIV2_CR_SNAPEN_MASK (0x20U)
265 #define QEIV2_CR_SNAPEN_SHIFT (5U)
266 #define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK)
267 #define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT)
268 
269 /*
270  * RSTCNT (RW)
271  *
272  * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx
273  */
274 #define QEIV2_CR_RSTCNT_MASK (0x10U)
275 #define QEIV2_CR_RSTCNT_SHIFT (4U)
276 #define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK)
277 #define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT)
278 
279 /*
280  * RD_SEL (RW)
281  *
282  * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read,
283  * width_snap0,width_snap1, timer_snap0, timer_snap1)
284  * 0 : same as hpm1000/500/500s;
285  * 1: use width for position; use timer for angle
286  */
287 #define QEIV2_CR_RD_SEL_MASK (0x8U)
288 #define QEIV2_CR_RD_SEL_SHIFT (3U)
289 #define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK)
290 #define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT)
291 
292 /*
293  * ENCTYP (RW)
294  *
295  * 000-abz; 001-pd; 010-ud; 011-UVW(hal)
296  * 100-single A; 101-single sin; 110: sin&cos
297  */
298 #define QEIV2_CR_ENCTYP_MASK (0x7U)
299 #define QEIV2_CR_ENCTYP_SHIFT (0U)
300 #define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK)
301 #define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT)
302 
303 /* Bitfield definition for register: PHCFG */
304 /*
305  * PHMAX (RW)
306  *
307  * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax
308  */
309 #define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL)
310 #define QEIV2_PHCFG_PHMAX_SHIFT (0U)
311 #define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK)
312 #define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT)
313 
314 /* Bitfield definition for register: WDGCFG */
315 /*
316  * WDGEN (RW)
317  *
318  * 1- enable wdog counter
319  */
320 #define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL)
321 #define QEIV2_WDGCFG_WDGEN_SHIFT (31U)
322 #define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK)
323 #define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT)
324 
325 /*
326  * WDOG_CFG (RW)
327  *
328  * define as stop if phase_cnt change is less than it
329  * if 0, then each change of phase_cnt will clear wdog counter;
330  * if 2, then phase_cnt change larger than 2 will clear wdog counter
331  */
332 #define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL)
333 #define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U)
334 #define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK)
335 #define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT)
336 
337 /*
338  * WDGTO (RW)
339  *
340  * watch dog timeout value
341  */
342 #define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL)
343 #define QEIV2_WDGCFG_WDGTO_SHIFT (0U)
344 #define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK)
345 #define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT)
346 
347 /* Bitfield definition for register: PHIDX */
348 /*
349  * PHIDX (RW)
350  *
351  * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1
352  */
353 #define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL)
354 #define QEIV2_PHIDX_PHIDX_SHIFT (0U)
355 #define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK)
356 #define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT)
357 
358 /* Bitfield definition for register: TRGOEN */
359 /*
360  * WDGFEN (RW)
361  *
362  * 1- enable trigger output when wdg flag set
363  */
364 #define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL)
365 #define QEIV2_TRGOEN_WDGFEN_SHIFT (31U)
366 #define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK)
367 #define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT)
368 
369 /*
370  * HOMEFEN (RW)
371  *
372  * 1- enable trigger output when homef flag set
373  */
374 #define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL)
375 #define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U)
376 #define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK)
377 #define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT)
378 
379 /*
380  * POSCMPFEN (RW)
381  *
382  * 1- enable trigger output when poscmpf flag set
383  */
384 #define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL)
385 #define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U)
386 #define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK)
387 #define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT)
388 
389 /*
390  * ZPHFEN (RW)
391  *
392  * 1- enable trigger output when zphf flag set
393  */
394 #define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL)
395 #define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U)
396 #define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK)
397 #define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT)
398 
399 /*
400  * ZMISSFEN (RW)
401  *
402  */
403 #define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL)
404 #define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U)
405 #define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK)
406 #define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT)
407 
408 /*
409  * WIDTHTMFEN (RW)
410  *
411  */
412 #define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL)
413 #define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U)
414 #define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK)
415 #define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT)
416 
417 /*
418  * POS2CMPFEN (RW)
419  *
420  */
421 #define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL)
422 #define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U)
423 #define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK)
424 #define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT)
425 
426 /*
427  * DIRCHGFEN (RW)
428  *
429  */
430 #define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL)
431 #define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U)
432 #define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK)
433 #define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT)
434 
435 /*
436  * CYCLE0FEN (RW)
437  *
438  */
439 #define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL)
440 #define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U)
441 #define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK)
442 #define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT)
443 
444 /*
445  * CYCLE1FEN (RW)
446  *
447  */
448 #define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL)
449 #define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U)
450 #define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK)
451 #define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT)
452 
453 /*
454  * PULSE0FEN (RW)
455  *
456  */
457 #define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL)
458 #define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U)
459 #define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK)
460 #define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT)
461 
462 /*
463  * PULSE1FEN (RW)
464  *
465  */
466 #define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL)
467 #define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U)
468 #define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK)
469 #define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT)
470 
471 /*
472  * HOME2FEN (RW)
473  *
474  */
475 #define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL)
476 #define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U)
477 #define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK)
478 #define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT)
479 
480 /*
481  * FAULTFEN (RW)
482  *
483  */
484 #define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL)
485 #define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U)
486 #define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK)
487 #define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT)
488 
489 /* Bitfield definition for register: READEN */
490 /*
491  * WDGFEN (RW)
492  *
493  * 1- load counters to their read registers when wdg flag set
494  */
495 #define QEIV2_READEN_WDGFEN_MASK (0x80000000UL)
496 #define QEIV2_READEN_WDGFEN_SHIFT (31U)
497 #define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK)
498 #define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT)
499 
500 /*
501  * HOMEFEN (RW)
502  *
503  * 1- load counters to their read registers when homef flag set
504  */
505 #define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL)
506 #define QEIV2_READEN_HOMEFEN_SHIFT (30U)
507 #define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK)
508 #define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT)
509 
510 /*
511  * POSCMPFEN (RW)
512  *
513  * 1- load counters to their read registers when poscmpf flag set
514  */
515 #define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL)
516 #define QEIV2_READEN_POSCMPFEN_SHIFT (29U)
517 #define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK)
518 #define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT)
519 
520 /*
521  * ZPHFEN (RW)
522  *
523  * 1- load counters to their read registers when zphf flag set
524  */
525 #define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL)
526 #define QEIV2_READEN_ZPHFEN_SHIFT (28U)
527 #define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK)
528 #define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT)
529 
530 /*
531  * ZMISSFEN (RW)
532  *
533  */
534 #define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL)
535 #define QEIV2_READEN_ZMISSFEN_SHIFT (27U)
536 #define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK)
537 #define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT)
538 
539 /*
540  * WIDTHTMFEN (RW)
541  *
542  */
543 #define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL)
544 #define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U)
545 #define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK)
546 #define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT)
547 
548 /*
549  * POS2CMPFEN (RW)
550  *
551  */
552 #define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL)
553 #define QEIV2_READEN_POS2CMPFEN_SHIFT (25U)
554 #define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK)
555 #define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT)
556 
557 /*
558  * DIRCHGFEN (RW)
559  *
560  */
561 #define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL)
562 #define QEIV2_READEN_DIRCHGFEN_SHIFT (24U)
563 #define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK)
564 #define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT)
565 
566 /*
567  * CYCLE0FEN (RW)
568  *
569  */
570 #define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL)
571 #define QEIV2_READEN_CYCLE0FEN_SHIFT (23U)
572 #define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK)
573 #define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT)
574 
575 /*
576  * CYCLE1FEN (RW)
577  *
578  */
579 #define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL)
580 #define QEIV2_READEN_CYCLE1FEN_SHIFT (22U)
581 #define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK)
582 #define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT)
583 
584 /*
585  * PULSE0FEN (RW)
586  *
587  */
588 #define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL)
589 #define QEIV2_READEN_PULSE0FEN_SHIFT (21U)
590 #define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK)
591 #define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT)
592 
593 /*
594  * PULSE1FEN (RW)
595  *
596  */
597 #define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL)
598 #define QEIV2_READEN_PULSE1FEN_SHIFT (20U)
599 #define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK)
600 #define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT)
601 
602 /*
603  * HOME2FEN (RW)
604  *
605  */
606 #define QEIV2_READEN_HOME2FEN_MASK (0x80000UL)
607 #define QEIV2_READEN_HOME2FEN_SHIFT (19U)
608 #define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK)
609 #define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT)
610 
611 /*
612  * FAULTFEN (RW)
613  *
614  */
615 #define QEIV2_READEN_FAULTFEN_MASK (0x40000UL)
616 #define QEIV2_READEN_FAULTFEN_SHIFT (18U)
617 #define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK)
618 #define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT)
619 
620 /* Bitfield definition for register: ZCMP */
621 /*
622  * ZCMP (RW)
623  *
624  * zcnt postion compare value
625  */
626 #define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL)
627 #define QEIV2_ZCMP_ZCMP_SHIFT (0U)
628 #define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK)
629 #define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT)
630 
631 /* Bitfield definition for register: PHCMP */
632 /*
633  * PHCMP (RW)
634  *
635  * phcnt position compare value
636  */
637 #define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL)
638 #define QEIV2_PHCMP_PHCMP_SHIFT (0U)
639 #define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK)
640 #define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT)
641 
642 /* Bitfield definition for register: SPDCMP */
643 /*
644  * SPDCMP (RW)
645  *
646  * spdcnt position compare value
647  */
648 #define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL)
649 #define QEIV2_SPDCMP_SPDCMP_SHIFT (0U)
650 #define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK)
651 #define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT)
652 
653 /* Bitfield definition for register: DMAEN */
654 /*
655  * WDGFEN (RW)
656  *
657  * 1- generate dma request when wdg flag set
658  */
659 #define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL)
660 #define QEIV2_DMAEN_WDGFEN_SHIFT (31U)
661 #define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK)
662 #define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT)
663 
664 /*
665  * HOMEFEN (RW)
666  *
667  * 1- generate dma request when homef flag set
668  */
669 #define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL)
670 #define QEIV2_DMAEN_HOMEFEN_SHIFT (30U)
671 #define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK)
672 #define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT)
673 
674 /*
675  * POSCMPFEN (RW)
676  *
677  * 1- generate dma request when poscmpf flag set
678  */
679 #define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL)
680 #define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U)
681 #define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK)
682 #define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT)
683 
684 /*
685  * ZPHFEN (RW)
686  *
687  * 1- generate dma request when zphf flag set
688  */
689 #define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL)
690 #define QEIV2_DMAEN_ZPHFEN_SHIFT (28U)
691 #define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK)
692 #define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT)
693 
694 /*
695  * ZMISSFEN (RW)
696  *
697  */
698 #define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL)
699 #define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U)
700 #define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK)
701 #define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT)
702 
703 /*
704  * WIDTHTMFEN (RW)
705  *
706  */
707 #define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL)
708 #define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U)
709 #define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK)
710 #define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT)
711 
712 /*
713  * POS2CMPFEN (RW)
714  *
715  */
716 #define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL)
717 #define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U)
718 #define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK)
719 #define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT)
720 
721 /*
722  * DIRCHGFEN (RW)
723  *
724  */
725 #define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL)
726 #define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U)
727 #define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK)
728 #define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT)
729 
730 /*
731  * CYCLE0FEN (RW)
732  *
733  */
734 #define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL)
735 #define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U)
736 #define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK)
737 #define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT)
738 
739 /*
740  * CYCLE1FEN (RW)
741  *
742  */
743 #define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL)
744 #define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U)
745 #define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK)
746 #define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT)
747 
748 /*
749  * PULSE0FEN (RW)
750  *
751  */
752 #define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL)
753 #define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U)
754 #define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK)
755 #define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT)
756 
757 /*
758  * PULSE1FEN (RW)
759  *
760  */
761 #define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL)
762 #define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U)
763 #define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK)
764 #define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT)
765 
766 /*
767  * HOME2FEN (RW)
768  *
769  */
770 #define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL)
771 #define QEIV2_DMAEN_HOME2FEN_SHIFT (19U)
772 #define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK)
773 #define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT)
774 
775 /*
776  * FAULTFEN (RW)
777  *
778  */
779 #define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL)
780 #define QEIV2_DMAEN_FAULTFEN_SHIFT (18U)
781 #define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK)
782 #define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT)
783 
784 /* Bitfield definition for register: SR */
785 /*
786  * WDGF (RW)
787  *
788  * watchdog flag
789  */
790 #define QEIV2_SR_WDGF_MASK (0x80000000UL)
791 #define QEIV2_SR_WDGF_SHIFT (31U)
792 #define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK)
793 #define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT)
794 
795 /*
796  * HOMEF (RW)
797  *
798  * home flag
799  */
800 #define QEIV2_SR_HOMEF_MASK (0x40000000UL)
801 #define QEIV2_SR_HOMEF_SHIFT (30U)
802 #define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK)
803 #define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT)
804 
805 /*
806  * POSCMPF (RW)
807  *
808  * postion compare match flag
809  */
810 #define QEIV2_SR_POSCMPF_MASK (0x20000000UL)
811 #define QEIV2_SR_POSCMPF_SHIFT (29U)
812 #define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK)
813 #define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT)
814 
815 /*
816  * ZPHF (RW)
817  *
818  * z input flag
819  */
820 #define QEIV2_SR_ZPHF_MASK (0x10000000UL)
821 #define QEIV2_SR_ZPHF_SHIFT (28U)
822 #define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK)
823 #define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT)
824 
825 /*
826  * ZMISSF (RW)
827  *
828  */
829 #define QEIV2_SR_ZMISSF_MASK (0x8000000UL)
830 #define QEIV2_SR_ZMISSF_SHIFT (27U)
831 #define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK)
832 #define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT)
833 
834 /*
835  * WIDTHTMF (RW)
836  *
837  */
838 #define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL)
839 #define QEIV2_SR_WIDTHTMF_SHIFT (26U)
840 #define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK)
841 #define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT)
842 
843 /*
844  * POS2CMPF (RW)
845  *
846  */
847 #define QEIV2_SR_POS2CMPF_MASK (0x2000000UL)
848 #define QEIV2_SR_POS2CMPF_SHIFT (25U)
849 #define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK)
850 #define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT)
851 
852 /*
853  * DIRCHGF (RW)
854  *
855  */
856 #define QEIV2_SR_DIRCHGF_MASK (0x1000000UL)
857 #define QEIV2_SR_DIRCHGF_SHIFT (24U)
858 #define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK)
859 #define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT)
860 
861 /*
862  * CYCLE0F (RW)
863  *
864  */
865 #define QEIV2_SR_CYCLE0F_MASK (0x800000UL)
866 #define QEIV2_SR_CYCLE0F_SHIFT (23U)
867 #define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK)
868 #define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT)
869 
870 /*
871  * CYCLE1F (RW)
872  *
873  */
874 #define QEIV2_SR_CYCLE1F_MASK (0x400000UL)
875 #define QEIV2_SR_CYCLE1F_SHIFT (22U)
876 #define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK)
877 #define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT)
878 
879 /*
880  * PULSE0F (RW)
881  *
882  */
883 #define QEIV2_SR_PULSE0F_MASK (0x200000UL)
884 #define QEIV2_SR_PULSE0F_SHIFT (21U)
885 #define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK)
886 #define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT)
887 
888 /*
889  * PULSE1F (RW)
890  *
891  */
892 #define QEIV2_SR_PULSE1F_MASK (0x100000UL)
893 #define QEIV2_SR_PULSE1F_SHIFT (20U)
894 #define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK)
895 #define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT)
896 
897 /*
898  * HOME2F (RW)
899  *
900  */
901 #define QEIV2_SR_HOME2F_MASK (0x80000UL)
902 #define QEIV2_SR_HOME2F_SHIFT (19U)
903 #define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK)
904 #define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT)
905 
906 /*
907  * FAULTF (RW)
908  *
909  */
910 #define QEIV2_SR_FAULTF_MASK (0x40000UL)
911 #define QEIV2_SR_FAULTF_SHIFT (18U)
912 #define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK)
913 #define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT)
914 
915 /* Bitfield definition for register: IRQEN */
916 /*
917  * WDGIE (RW)
918  *
919  * 1- generate interrupt when wdg flag set
920  */
921 #define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL)
922 #define QEIV2_IRQEN_WDGIE_SHIFT (31U)
923 #define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK)
924 #define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT)
925 
926 /*
927  * HOMEIE (RW)
928  *
929  * 1- generate interrupt when homef flag set
930  */
931 #define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL)
932 #define QEIV2_IRQEN_HOMEIE_SHIFT (30U)
933 #define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK)
934 #define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT)
935 
936 /*
937  * POSCMPIE (RW)
938  *
939  * 1- generate interrupt when poscmpf flag set
940  */
941 #define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL)
942 #define QEIV2_IRQEN_POSCMPIE_SHIFT (29U)
943 #define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK)
944 #define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT)
945 
946 /*
947  * ZPHIE (RW)
948  *
949  * 1- generate interrupt when zphf flag set
950  */
951 #define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL)
952 #define QEIV2_IRQEN_ZPHIE_SHIFT (28U)
953 #define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK)
954 #define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT)
955 
956 /*
957  * ZMISSE (RW)
958  *
959  */
960 #define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL)
961 #define QEIV2_IRQEN_ZMISSE_SHIFT (27U)
962 #define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK)
963 #define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT)
964 
965 /*
966  * WIDTHTME (RW)
967  *
968  */
969 #define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL)
970 #define QEIV2_IRQEN_WIDTHTME_SHIFT (26U)
971 #define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK)
972 #define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT)
973 
974 /*
975  * POS2CMPE (RW)
976  *
977  */
978 #define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL)
979 #define QEIV2_IRQEN_POS2CMPE_SHIFT (25U)
980 #define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK)
981 #define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT)
982 
983 /*
984  * DIRCHGE (RW)
985  *
986  */
987 #define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL)
988 #define QEIV2_IRQEN_DIRCHGE_SHIFT (24U)
989 #define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK)
990 #define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT)
991 
992 /*
993  * CYCLE0E (RW)
994  *
995  */
996 #define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL)
997 #define QEIV2_IRQEN_CYCLE0E_SHIFT (23U)
998 #define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK)
999 #define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT)
1000 
1001 /*
1002  * CYCLE1E (RW)
1003  *
1004  */
1005 #define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL)
1006 #define QEIV2_IRQEN_CYCLE1E_SHIFT (22U)
1007 #define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK)
1008 #define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT)
1009 
1010 /*
1011  * PULSE0E (RW)
1012  *
1013  */
1014 #define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL)
1015 #define QEIV2_IRQEN_PULSE0E_SHIFT (21U)
1016 #define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK)
1017 #define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT)
1018 
1019 /*
1020  * PULSE1E (RW)
1021  *
1022  */
1023 #define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL)
1024 #define QEIV2_IRQEN_PULSE1E_SHIFT (20U)
1025 #define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK)
1026 #define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT)
1027 
1028 /*
1029  * HOME2E (RW)
1030  *
1031  */
1032 #define QEIV2_IRQEN_HOME2E_MASK (0x80000UL)
1033 #define QEIV2_IRQEN_HOME2E_SHIFT (19U)
1034 #define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK)
1035 #define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT)
1036 
1037 /*
1038  * FAULTE (RW)
1039  *
1040  */
1041 #define QEIV2_IRQEN_FAULTE_MASK (0x40000UL)
1042 #define QEIV2_IRQEN_FAULTE_SHIFT (18U)
1043 #define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK)
1044 #define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT)
1045 
1046 /* Bitfield definition for register of struct array COUNT: Z */
1047 /*
1048  * ZCNT (RW)
1049  *
1050  * zcnt value
1051  */
1052 #define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL)
1053 #define QEIV2_COUNT_Z_ZCNT_SHIFT (0U)
1054 #define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK)
1055 #define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT)
1056 
1057 /* Bitfield definition for register of struct array COUNT: PH */
1058 /*
1059  * DIR (RO)
1060  *
1061  * 1- reverse rotation
1062  * 0- forward rotation
1063  */
1064 #define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL)
1065 #define QEIV2_COUNT_PH_DIR_SHIFT (30U)
1066 #define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT)
1067 
1068 /*
1069  * ASTAT (RO)
1070  *
1071  * 1- a input is high
1072  * 0- a input is low
1073  */
1074 #define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL)
1075 #define QEIV2_COUNT_PH_ASTAT_SHIFT (26U)
1076 #define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT)
1077 
1078 /*
1079  * BSTAT (RO)
1080  *
1081  * 1- b input is high
1082  * 0- b input is low
1083  */
1084 #define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL)
1085 #define QEIV2_COUNT_PH_BSTAT_SHIFT (25U)
1086 #define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT)
1087 
1088 /*
1089  * PHCNT (RO)
1090  *
1091  * phcnt value
1092  */
1093 #define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL)
1094 #define QEIV2_COUNT_PH_PHCNT_SHIFT (0U)
1095 #define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT)
1096 
1097 /* Bitfield definition for register of struct array COUNT: SPD */
1098 /*
1099  * DIR (RO)
1100  *
1101  * 1- reverse rotation
1102  * 0- forward rotation
1103  */
1104 #define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL)
1105 #define QEIV2_COUNT_SPD_DIR_SHIFT (31U)
1106 #define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT)
1107 
1108 /*
1109  * ASTAT (RO)
1110  *
1111  * 1- a input is high
1112  * 0- a input is low
1113  */
1114 #define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL)
1115 #define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U)
1116 #define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT)
1117 
1118 /*
1119  * BSTAT (RW)
1120  *
1121  * 1- b input is high
1122  * 0- b input is low
1123  */
1124 #define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL)
1125 #define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U)
1126 #define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK)
1127 #define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT)
1128 
1129 /*
1130  * SPDCNT (RO)
1131  *
1132  * spdcnt value
1133  */
1134 #define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL)
1135 #define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U)
1136 #define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT)
1137 
1138 /* Bitfield definition for register of struct array COUNT: TMR */
1139 /*
1140  * TMRCNT (RO)
1141  *
1142  * 32 bit free run timer
1143  */
1144 #define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL)
1145 #define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U)
1146 #define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT)
1147 
1148 /* Bitfield definition for register: ZCMP2 */
1149 /*
1150  * ZCMP2 (RW)
1151  *
1152  */
1153 #define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL)
1154 #define QEIV2_ZCMP2_ZCMP2_SHIFT (0U)
1155 #define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK)
1156 #define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT)
1157 
1158 /* Bitfield definition for register: PHCMP2 */
1159 /*
1160  * PHCMP2 (RW)
1161  *
1162  */
1163 #define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL)
1164 #define QEIV2_PHCMP2_PHCMP2_SHIFT (0U)
1165 #define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK)
1166 #define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT)
1167 
1168 /* Bitfield definition for register: SPDCMP2 */
1169 /*
1170  * SPDCMP2 (RW)
1171  *
1172  */
1173 #define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL)
1174 #define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U)
1175 #define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK)
1176 #define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT)
1177 
1178 /* Bitfield definition for register: MATCH_CFG */
1179 /*
1180  * ZCMPDIS (RW)
1181  *
1182  * 1- postion compare not include zcnt
1183  */
1184 #define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL)
1185 #define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U)
1186 #define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK)
1187 #define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT)
1188 
1189 /*
1190  * DIRCMPDIS (RW)
1191  *
1192  * 1- postion compare not include rotation direction
1193  */
1194 #define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL)
1195 #define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U)
1196 #define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK)
1197 #define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT)
1198 
1199 /*
1200  * DIRCMP (RW)
1201  *
1202  * 0- position compare need positive rotation
1203  * 1- position compare need negative rotation
1204  */
1205 #define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL)
1206 #define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U)
1207 #define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK)
1208 #define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT)
1209 
1210 /*
1211  * SPDCMPDIS (RW)
1212  *
1213  */
1214 #define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL)
1215 #define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U)
1216 #define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK)
1217 #define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT)
1218 
1219 /*
1220  * PHASE_MATCH_DIS (RW)
1221  *
1222  */
1223 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL)
1224 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U)
1225 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK)
1226 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT)
1227 
1228 /*
1229  * POS_MATCH_DIR (RW)
1230  *
1231  */
1232 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL)
1233 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U)
1234 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK)
1235 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT)
1236 
1237 /*
1238  * POS_MATCH_OPT (RW)
1239  *
1240  */
1241 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL)
1242 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U)
1243 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK)
1244 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT)
1245 
1246 /*
1247  * ZCMP2DIS (RW)
1248  *
1249  */
1250 #define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U)
1251 #define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U)
1252 #define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK)
1253 #define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT)
1254 
1255 /*
1256  * DIRCMP2DIS (RW)
1257  *
1258  */
1259 #define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U)
1260 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U)
1261 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK)
1262 #define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT)
1263 
1264 /*
1265  * DIRCMP2 (RW)
1266  *
1267  */
1268 #define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U)
1269 #define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U)
1270 #define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK)
1271 #define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT)
1272 
1273 /*
1274  * SPDCMP2DIS (RW)
1275  *
1276  */
1277 #define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U)
1278 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U)
1279 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK)
1280 #define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT)
1281 
1282 /*
1283  * PHASE_MATCH_DIS2 (RW)
1284  *
1285  */
1286 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U)
1287 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U)
1288 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK)
1289 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT)
1290 
1291 /*
1292  * POS_MATCH2_DIR (RW)
1293  *
1294  */
1295 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U)
1296 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U)
1297 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK)
1298 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT)
1299 
1300 /*
1301  * POS_MATCH2_OPT (RW)
1302  *
1303  */
1304 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U)
1305 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U)
1306 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK)
1307 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT)
1308 
1309 /* Bitfield definition for register array: FILT_CFG */
1310 /*
1311  * OUTINV (RW)
1312  *
1313  * 1- Filter will invert the output
1314  * 0- Filter will not invert the output
1315  */
1316 #define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL)
1317 #define QEIV2_FILT_CFG_OUTINV_SHIFT (16U)
1318 #define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK)
1319 #define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT)
1320 
1321 /*
1322  * MODE (RW)
1323  *
1324  * This bitfields defines the filter mode
1325  * 000-bypass;
1326  * 100-rapid change mode;
1327  * 101-delay filter mode;
1328  * 110-stable low mode;
1329  * 111-stable high mode
1330  */
1331 #define QEIV2_FILT_CFG_MODE_MASK (0xE000U)
1332 #define QEIV2_FILT_CFG_MODE_SHIFT (13U)
1333 #define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK)
1334 #define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT)
1335 
1336 /*
1337  * SYNCEN (RW)
1338  *
1339  * set to enable sychronization input signal with TRGM clock
1340  */
1341 #define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U)
1342 #define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U)
1343 #define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK)
1344 #define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT)
1345 
1346 /*
1347  * FILTLEN (RW)
1348  *
1349  * This bitfields defines the filter counter length.
1350  */
1351 #define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU)
1352 #define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U)
1353 #define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK)
1354 #define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT)
1355 
1356 /* Bitfield definition for register: QEI_CFG */
1357 /*
1358  * SPEED_DIR_CHG_EN (RW)
1359  *
1360  * clear counter if detect direction change
1361  */
1362 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U)
1363 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U)
1364 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK)
1365 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT)
1366 
1367 /*
1368  * UVW_POS_OPT0 (RW)
1369  *
1370  * set to output next area position for QEO use;
1371  * clr to output exact point position for MMC use
1372  */
1373 #define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U)
1374 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U)
1375 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK)
1376 #define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT)
1377 
1378 /*
1379  * NEGEDGE_EN (RW)
1380  *
1381  * bit4: negedge enable
1382  * bit3: posedge enable
1383  * bit2: W in hal enable
1384  * bit1: signal b(or V in hal) enable
1385  * bit0: signal a(or U in hal) enable
1386  * such as:
1387  * 01001: use posedge A
1388  * 11010: use both edge of signal B
1389  * 11111: use both edge of all HAL siganls
1390  */
1391 #define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U)
1392 #define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U)
1393 #define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK)
1394 #define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT)
1395 
1396 /*
1397  * POSIDGE_EN (RW)
1398  *
1399  */
1400 #define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U)
1401 #define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U)
1402 #define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK)
1403 #define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT)
1404 
1405 /*
1406  * SIGZ_EN (RW)
1407  *
1408  */
1409 #define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U)
1410 #define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U)
1411 #define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK)
1412 #define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT)
1413 
1414 /*
1415  * SIGB_EN (RW)
1416  *
1417  */
1418 #define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U)
1419 #define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U)
1420 #define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK)
1421 #define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT)
1422 
1423 /*
1424  * SIGA_EN (RW)
1425  *
1426  */
1427 #define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U)
1428 #define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U)
1429 #define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK)
1430 #define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT)
1431 
1432 /* Bitfield definition for register: PULSE0_NUM */
1433 /*
1434  * PULSE0_NUM (RW)
1435  *
1436  * for speed detection, will count the cycle number for configed pulse_num
1437  */
1438 #define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL)
1439 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U)
1440 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK)
1441 #define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT)
1442 
1443 /* Bitfield definition for register: PULSE1_NUM */
1444 /*
1445  * PULSE1_NUM (RW)
1446  *
1447  */
1448 #define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL)
1449 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U)
1450 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK)
1451 #define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT)
1452 
1453 /* Bitfield definition for register: CYCLE0_CNT */
1454 /*
1455  * CYCLE0_CNT (RO)
1456  *
1457  */
1458 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL)
1459 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U)
1460 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT)
1461 
1462 /* Bitfield definition for register: CYCLE0PULSE_CNT */
1463 /*
1464  * CYCLE0PULSE_CNT (RO)
1465  *
1466  */
1467 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL)
1468 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U)
1469 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT)
1470 
1471 /* Bitfield definition for register: CYCLE1_CNT */
1472 /*
1473  * CYCLE1_CNT (RO)
1474  *
1475  */
1476 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL)
1477 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U)
1478 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT)
1479 
1480 /* Bitfield definition for register: CYCLE1PULSE_CNT */
1481 /*
1482  * CYCLE1PULSE_CNT (RO)
1483  *
1484  */
1485 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL)
1486 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U)
1487 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT)
1488 
1489 /* Bitfield definition for register: CYCLE0_SNAP0 */
1490 /*
1491  * CYCLE0_SNAP0 (RO)
1492  *
1493  */
1494 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL)
1495 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U)
1496 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT)
1497 
1498 /* Bitfield definition for register: CYCLE0_SNAP1 */
1499 /*
1500  * CYCLE0_SNAP1 (RO)
1501  *
1502  */
1503 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL)
1504 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U)
1505 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT)
1506 
1507 /* Bitfield definition for register: CYCLE1_SNAP0 */
1508 /*
1509  * CYCLE1_SNAP0 (RO)
1510  *
1511  */
1512 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL)
1513 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U)
1514 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT)
1515 
1516 /* Bitfield definition for register: CYCLE1_SNAP1 */
1517 /*
1518  * CYCLE1_SNAP1 (RO)
1519  *
1520  */
1521 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL)
1522 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U)
1523 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT)
1524 
1525 /* Bitfield definition for register: CYCLE0_NUM */
1526 /*
1527  * CYCLE0_NUM (RW)
1528  *
1529  */
1530 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL)
1531 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U)
1532 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK)
1533 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT)
1534 
1535 /* Bitfield definition for register: CYCLE1_NUM */
1536 /*
1537  * CYCLE1_NUM (RW)
1538  *
1539  */
1540 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL)
1541 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U)
1542 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK)
1543 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT)
1544 
1545 /* Bitfield definition for register: PULSE0_CNT */
1546 /*
1547  * PULSE0_CNT (RO)
1548  *
1549  */
1550 #define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL)
1551 #define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U)
1552 #define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT)
1553 
1554 /* Bitfield definition for register: PULSE0CYCLE_CNT */
1555 /*
1556  * PULSE0CYCLE_CNT (RO)
1557  *
1558  */
1559 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL)
1560 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U)
1561 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT)
1562 
1563 /* Bitfield definition for register: PULSE1_CNT */
1564 /*
1565  * PULSE1_CNT (RO)
1566  *
1567  */
1568 #define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL)
1569 #define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U)
1570 #define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT)
1571 
1572 /* Bitfield definition for register: PULSE1CYCLE_CNT */
1573 /*
1574  * PULSE1CYCLE_CNT (RO)
1575  *
1576  */
1577 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL)
1578 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U)
1579 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT)
1580 
1581 /* Bitfield definition for register: PULSE0_SNAP0 */
1582 /*
1583  * PULSE0_SNAP0 (RO)
1584  *
1585  */
1586 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL)
1587 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U)
1588 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT)
1589 
1590 /* Bitfield definition for register: PULSE0CYCLE_SNAP0 */
1591 /*
1592  * PULSE0CYCLE_SNAP0 (RO)
1593  *
1594  */
1595 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1596 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U)
1597 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT)
1598 
1599 /* Bitfield definition for register: PULSE0_SNAP1 */
1600 /*
1601  * PULSE0_SNAP1 (RO)
1602  *
1603  */
1604 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL)
1605 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U)
1606 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT)
1607 
1608 /* Bitfield definition for register: PULSE0CYCLE_SNAP1 */
1609 /*
1610  * PULSE0CYCLE_SNAP1 (RO)
1611  *
1612  */
1613 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1614 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U)
1615 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT)
1616 
1617 /* Bitfield definition for register: PULSE1_SNAP0 */
1618 /*
1619  * PULSE1_SNAP0 (RO)
1620  *
1621  */
1622 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL)
1623 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U)
1624 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT)
1625 
1626 /* Bitfield definition for register: PULSE1CYCLE_SNAP0 */
1627 /*
1628  * PULSE1CYCLE_SNAP0 (RO)
1629  *
1630  */
1631 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1632 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U)
1633 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT)
1634 
1635 /* Bitfield definition for register: PULSE1_SNAP1 */
1636 /*
1637  * PULSE1_SNAP1 (RO)
1638  *
1639  */
1640 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL)
1641 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U)
1642 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT)
1643 
1644 /* Bitfield definition for register: PULSE1CYCLE_SNAP1 */
1645 /*
1646  * PULSE1CYCLE_SNAP1 (RO)
1647  *
1648  */
1649 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1650 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U)
1651 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT)
1652 
1653 /* Bitfield definition for register: ADCX_CFG0 */
1654 /*
1655  * X_ADCSEL (RW)
1656  *
1657  */
1658 #define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U)
1659 #define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U)
1660 #define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK)
1661 #define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT)
1662 
1663 /*
1664  * X_ADC_ENABLE (RW)
1665  *
1666  */
1667 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U)
1668 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U)
1669 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK)
1670 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT)
1671 
1672 /*
1673  * X_CHAN (RW)
1674  *
1675  */
1676 #define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU)
1677 #define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U)
1678 #define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK)
1679 #define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT)
1680 
1681 /* Bitfield definition for register: ADCX_CFG1 */
1682 /*
1683  * X_PARAM1 (RW)
1684  *
1685  */
1686 #define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL)
1687 #define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U)
1688 #define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK)
1689 #define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT)
1690 
1691 /*
1692  * X_PARAM0 (RW)
1693  *
1694  */
1695 #define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU)
1696 #define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U)
1697 #define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK)
1698 #define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT)
1699 
1700 /* Bitfield definition for register: ADCX_CFG2 */
1701 /*
1702  * X_OFFSET (RW)
1703  *
1704  */
1705 #define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL)
1706 #define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U)
1707 #define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK)
1708 #define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT)
1709 
1710 /* Bitfield definition for register: ADCY_CFG0 */
1711 /*
1712  * Y_ADCSEL (RW)
1713  *
1714  */
1715 #define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U)
1716 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U)
1717 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK)
1718 #define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT)
1719 
1720 /*
1721  * Y_ADC_ENABLE (RW)
1722  *
1723  */
1724 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U)
1725 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U)
1726 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK)
1727 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT)
1728 
1729 /*
1730  * Y_CHAN (RW)
1731  *
1732  */
1733 #define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU)
1734 #define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U)
1735 #define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK)
1736 #define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT)
1737 
1738 /* Bitfield definition for register: ADCY_CFG1 */
1739 /*
1740  * Y_PARAM1 (RW)
1741  *
1742  */
1743 #define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL)
1744 #define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U)
1745 #define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK)
1746 #define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT)
1747 
1748 /*
1749  * Y_PARAM0 (RW)
1750  *
1751  */
1752 #define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU)
1753 #define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U)
1754 #define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK)
1755 #define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT)
1756 
1757 /* Bitfield definition for register: ADCY_CFG2 */
1758 /*
1759  * Y_OFFSET (RW)
1760  *
1761  */
1762 #define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL)
1763 #define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U)
1764 #define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK)
1765 #define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT)
1766 
1767 /* Bitfield definition for register: CAL_CFG */
1768 /*
1769  * XY_DELAY (RW)
1770  *
1771  * valid x/y delay, larger than this delay will be treated as invalid data.
1772  * Default 1.25us@200MHz; max 80ms;
1773  */
1774 #define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL)
1775 #define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U)
1776 #define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK)
1777 #define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT)
1778 
1779 /* Bitfield definition for register: PHASE_PARAM */
1780 /*
1781  * PHASE_PARAM (RW)
1782  *
1783  */
1784 #define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL)
1785 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U)
1786 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK)
1787 #define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT)
1788 
1789 /* Bitfield definition for register: POS_THRESHOLD */
1790 /*
1791  * POS_THRESHOLD (RW)
1792  *
1793  */
1794 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL)
1795 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U)
1796 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK)
1797 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT)
1798 
1799 /* Bitfield definition for register array: UVW_POS */
1800 /*
1801  * UVW_POS0 (RW)
1802  *
1803  */
1804 #define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL)
1805 #define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U)
1806 #define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK)
1807 #define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT)
1808 
1809 /* Bitfield definition for register array: UVW_POS_CFG */
1810 /*
1811  * POS_EN (RW)
1812  *
1813  */
1814 #define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U)
1815 #define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U)
1816 #define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK)
1817 #define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT)
1818 
1819 /*
1820  * U_POS_SEL (RW)
1821  *
1822  */
1823 #define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U)
1824 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U)
1825 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK)
1826 #define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT)
1827 
1828 /*
1829  * V_POS_SEL (RW)
1830  *
1831  */
1832 #define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU)
1833 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U)
1834 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK)
1835 #define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT)
1836 
1837 /*
1838  * W_POS_SEL (RW)
1839  *
1840  */
1841 #define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U)
1842 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U)
1843 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK)
1844 #define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT)
1845 
1846 /* Bitfield definition for register: PHASE_CNT */
1847 /*
1848  * PHASE_CNT (RW)
1849  *
1850  */
1851 #define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL)
1852 #define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U)
1853 #define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK)
1854 #define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT)
1855 
1856 /* Bitfield definition for register: PHASE_UPDATE */
1857 /*
1858  * INC (WO)
1859  *
1860  * set to add value to phase_cnt
1861  */
1862 #define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL)
1863 #define QEIV2_PHASE_UPDATE_INC_SHIFT (31U)
1864 #define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK)
1865 #define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT)
1866 
1867 /*
1868  * DEC (WO)
1869  *
1870  * set to minus value from phase_cnt(set inc and dec same time willl act inc)
1871  */
1872 #define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL)
1873 #define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U)
1874 #define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK)
1875 #define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT)
1876 
1877 /*
1878  * VALUE (WO)
1879  *
1880  * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation
1881  */
1882 #define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
1883 #define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U)
1884 #define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK)
1885 #define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT)
1886 
1887 /* Bitfield definition for register: POSITION */
1888 /*
1889  * POSITION (RW)
1890  *
1891  */
1892 #define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL)
1893 #define QEIV2_POSITION_POSITION_SHIFT (0U)
1894 #define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK)
1895 #define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT)
1896 
1897 /* Bitfield definition for register: POSITION_UPDATE */
1898 /*
1899  * INC (WO)
1900  *
1901  * set to add value to position
1902  */
1903 #define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL)
1904 #define QEIV2_POSITION_UPDATE_INC_SHIFT (31U)
1905 #define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK)
1906 #define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT)
1907 
1908 /*
1909  * DEC (WO)
1910  *
1911  * set to minus value from position(set inc and dec same time willl act inc)
1912  */
1913 #define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL)
1914 #define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U)
1915 #define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK)
1916 #define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT)
1917 
1918 /*
1919  * VALUE (WO)
1920  *
1921  * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation
1922  */
1923 #define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
1924 #define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U)
1925 #define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK)
1926 #define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT)
1927 
1928 /* Bitfield definition for register: ANGLE */
1929 /*
1930  * ANGLE (RO)
1931  *
1932  */
1933 #define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL)
1934 #define QEIV2_ANGLE_ANGLE_SHIFT (0U)
1935 #define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT)
1936 
1937 /* Bitfield definition for register: POS_TIMEOUT */
1938 /*
1939  * ENABLE (RW)
1940  *
1941  * enable position timeout feature, if timeout, send valid again
1942  */
1943 #define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL)
1944 #define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U)
1945 #define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK)
1946 #define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT)
1947 
1948 /*
1949  * TIMEOUT (RW)
1950  *
1951  * postion timeout value
1952  */
1953 #define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL)
1954 #define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U)
1955 #define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK)
1956 #define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT)
1957 
1958 
1959 
1960 /* COUNT register group index macro definition */
1961 #define QEIV2_COUNT_CURRENT (0UL)
1962 #define QEIV2_COUNT_READ (1UL)
1963 #define QEIV2_COUNT_SNAP0 (2UL)
1964 #define QEIV2_COUNT_SNAP1 (3UL)
1965 
1966 /* FILT_CFG register group index macro definition */
1967 #define QEIV2_FILT_CFG_FILT_CFG_A (0UL)
1968 #define QEIV2_FILT_CFG_FILT_CFG_B (1UL)
1969 #define QEIV2_FILT_CFG_FILT_CFG_Z (2UL)
1970 #define QEIV2_FILT_CFG_FILT_CFG_H (3UL)
1971 #define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL)
1972 #define QEIV2_FILT_CFG_FILT_CFG_F (5UL)
1973 
1974 /* UVW_POS register group index macro definition */
1975 #define QEIV2_UVW_POS_UVW_POS0 (0UL)
1976 #define QEIV2_UVW_POS_UVW_POS1 (1UL)
1977 #define QEIV2_UVW_POS_UVW_POS2 (2UL)
1978 #define QEIV2_UVW_POS_UVW_POS3 (3UL)
1979 #define QEIV2_UVW_POS_UVW_POS4 (4UL)
1980 #define QEIV2_UVW_POS_UVW_POS5 (5UL)
1981 
1982 /* UVW_POS_CFG register group index macro definition */
1983 #define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL)
1984 #define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL)
1985 #define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL)
1986 #define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL)
1987 #define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL)
1988 #define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL)
1989 
1990 
1991 #endif /* HPM_QEIV2_H */
QEIV2_Type
Definition: hpm_qeiv2_regs.h:12