HPM SDK
HPMicro Software Development Kit
hpm_rdc_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_RDC_H
10 #define HPM_RDC_H
11 
12 typedef struct {
13  __RW uint32_t RDC_CTL; /* 0x0: rdc control */
14  __R uint32_t ACC_I; /* 0x4: accumulate result of i_channel */
15  __R uint32_t ACC_Q; /* 0x8: accumulate result of q_channel */
16  __RW uint32_t IN_CTL; /* 0xC: input channel selection */
17  __RW uint32_t OUT_CTL; /* 0x10: output channel selection */
18  __R uint8_t RESERVED0[32]; /* 0x14 - 0x33: Reserved */
19  __RW uint32_t EXC_TIMMING; /* 0x34: excitation signal timming setting */
20  __RW uint32_t EXC_SCALING; /* 0x38: amplitude scaling for excitation */
21  __RW uint32_t EXC_OFFSET; /* 0x3C: amplitude offset setting */
22  __RW uint32_t PWM_SCALING; /* 0x40: amplitude scaling for excitation */
23  __RW uint32_t PWM_OFFSET; /* 0x44: amplitude offset setting */
24  __RW uint32_t TRIG_OUT0_CFG; /* 0x48: Configuration for trigger out 0 in clock cycle */
25  __RW uint32_t TRIG_OUT1_CFG; /* 0x4C: Configuration for trigger out 1 in clock cycle */
26  __RW uint32_t PWM_DZ; /* 0x50: pwm dead zone control in clock cycle */
27  __RW uint32_t SYNC_OUT_CTRL; /* 0x54: synchronize output signal control */
28  __RW uint32_t EXC_SYNC_DLY; /* 0x58: trigger in delay timming in soc bus cycle */
29  __R uint8_t RESERVED1[20]; /* 0x5C - 0x6F: Reserved */
30  __RW uint32_t MAX_I; /* 0x70: max value of i_channel */
31  __RW uint32_t MIN_I; /* 0x74: min value of i_channel */
32  __RW uint32_t MAX_Q; /* 0x78: max value of q_channel */
33  __RW uint32_t MIN_Q; /* 0x7C: min value of q_channel */
34  __RW uint32_t THRS_I; /* 0x80: the offset setting for edge detection of the i_channel */
35  __RW uint32_t THRS_Q; /* 0x84: the offset setting for edge detection of the q_channel */
36  __RW uint32_t EDG_DET_CTL; /* 0x88: the control for edge detection */
37  __RW uint32_t ACC_SCALING; /* 0x8C: scaling for accumulation result */
38  __RW uint32_t EXC_PERIOD; /* 0x90: period of excitation */
39  __R uint8_t RESERVED2[12]; /* 0x94 - 0x9F: Reserved */
40  __RW uint32_t SYNC_DELAY_I; /* 0xA0: delay setting in clock cycle for synchronous signal */
41  __R uint8_t RESERVED3[4]; /* 0xA4 - 0xA7: Reserved */
42  __R uint32_t RISE_DELAY_I; /* 0xA8: delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data */
43  __R uint32_t FALL_DELAY_I; /* 0xAC: delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data */
44  __R uint32_t SAMPLE_RISE_I; /* 0xB0: sample value on rising edge of rectify signal */
45  __R uint32_t SAMPLE_FALL_I; /* 0xB4: sample value on falling edge of rectify signal */
46  __R uint32_t ACC_CNT_I; /* 0xB8: number of accumulation */
47  __R uint32_t SIGN_CNT_I; /* 0xBC: sample counter of opposite sign with rectify signal */
48  __RW uint32_t SYNC_DELAY_Q; /* 0xC0: delay setting in clock cycle for synchronous signal */
49  __R uint8_t RESERVED4[4]; /* 0xC4 - 0xC7: Reserved */
50  __R uint32_t RISE_DELAY_Q; /* 0xC8: delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data */
51  __R uint32_t FALL_DELAY_Q; /* 0xCC: delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data */
52  __R uint32_t SAMPLE_RISE_Q; /* 0xD0: sample value on rising edge of rectify signal */
53  __R uint32_t SAMPLE_FALL_Q; /* 0xD4: sample value on falling edge of rectify signal */
54  __R uint32_t ACC_CNT_Q; /* 0xD8: number of accumulation */
55  __R uint32_t SIGN_CNT_Q; /* 0xDC: sample counter of opposite sign with rectify signal */
56  __RW uint32_t AMP_MAX; /* 0xE0: the maximum of acc amplitude */
57  __RW uint32_t AMP_MIN; /* 0xE4: the minimum of acc amplitude */
58  __RW uint32_t INT_EN; /* 0xE8: the interrupt mask control */
59  __W uint32_t ADC_INT_STATE; /* 0xEC: the interrupt state */
60 } RDC_Type;
61 
62 
63 /* Bitfield definition for register: RDC_CTL */
64 /*
65  * TS_SEL (RW)
66  *
67  * Time stamp selection for accumulation
68  * 0: end of accumulation
69  * 1: start of accumulation
70  * 2: center of accumulation
71  */
72 #define RDC_RDC_CTL_TS_SEL_MASK (0x300000UL)
73 #define RDC_RDC_CTL_TS_SEL_SHIFT (20U)
74 #define RDC_RDC_CTL_TS_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_TS_SEL_SHIFT) & RDC_RDC_CTL_TS_SEL_MASK)
75 #define RDC_RDC_CTL_TS_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_TS_SEL_MASK) >> RDC_RDC_CTL_TS_SEL_SHIFT)
76 
77 /*
78  * ACC_LEN (RW)
79  *
80  * Accumulate time, support on the fly change
81  * 0：1 cycle
82  * 1：2 cycles
83  * …
84  * 255: 256 cycles
85  */
86 #define RDC_RDC_CTL_ACC_LEN_MASK (0xFF000UL)
87 #define RDC_RDC_CTL_ACC_LEN_SHIFT (12U)
88 #define RDC_RDC_CTL_ACC_LEN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_LEN_SHIFT) & RDC_RDC_CTL_ACC_LEN_MASK)
89 #define RDC_RDC_CTL_ACC_LEN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_LEN_MASK) >> RDC_RDC_CTL_ACC_LEN_SHIFT)
90 
91 /*
92  * RECTIFY_SEL (RW)
93  *
94  * Select reference point of rectify signal
95  * 0: 0 phase of internal exciting signal
96  * 1: 90 phase of internal exciting signal
97  * 2: 180 phase of internal exciting signal
98  * 3: 270 phase of internal exciting signal
99  * 4: use value on external pin
100  * 5: use invert value on external pin
101  */
102 #define RDC_RDC_CTL_RECTIFY_SEL_MASK (0x70U)
103 #define RDC_RDC_CTL_RECTIFY_SEL_SHIFT (4U)
104 #define RDC_RDC_CTL_RECTIFY_SEL_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_RECTIFY_SEL_SHIFT) & RDC_RDC_CTL_RECTIFY_SEL_MASK)
105 #define RDC_RDC_CTL_RECTIFY_SEL_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_RECTIFY_SEL_MASK) >> RDC_RDC_CTL_RECTIFY_SEL_SHIFT)
106 
107 /*
108  * ACC_EN (RW)
109  *
110  * Enable rdc accumulate
111  * 0: rdc disable
112  * 1: rdc enable
113  */
114 #define RDC_RDC_CTL_ACC_EN_MASK (0x4U)
115 #define RDC_RDC_CTL_ACC_EN_SHIFT (2U)
116 #define RDC_RDC_CTL_ACC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_ACC_EN_SHIFT) & RDC_RDC_CTL_ACC_EN_MASK)
117 #define RDC_RDC_CTL_ACC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_ACC_EN_MASK) >> RDC_RDC_CTL_ACC_EN_SHIFT)
118 
119 /*
120  * EXC_START (RW1C)
121  *
122  * Write 1 start excite signal, always read 0
123  * 0: no effect
124  * 1: start excite signal
125  */
126 #define RDC_RDC_CTL_EXC_START_MASK (0x2U)
127 #define RDC_RDC_CTL_EXC_START_SHIFT (1U)
128 #define RDC_RDC_CTL_EXC_START_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_START_SHIFT) & RDC_RDC_CTL_EXC_START_MASK)
129 #define RDC_RDC_CTL_EXC_START_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_START_MASK) >> RDC_RDC_CTL_EXC_START_SHIFT)
130 
131 /*
132  * EXC_EN (RW)
133  *
134  * Enable rdc excite signal
135  * 0: rdc disable
136  * 1: rdc enable
137  */
138 #define RDC_RDC_CTL_EXC_EN_MASK (0x1U)
139 #define RDC_RDC_CTL_EXC_EN_SHIFT (0U)
140 #define RDC_RDC_CTL_EXC_EN_SET(x) (((uint32_t)(x) << RDC_RDC_CTL_EXC_EN_SHIFT) & RDC_RDC_CTL_EXC_EN_MASK)
141 #define RDC_RDC_CTL_EXC_EN_GET(x) (((uint32_t)(x) & RDC_RDC_CTL_EXC_EN_MASK) >> RDC_RDC_CTL_EXC_EN_SHIFT)
142 
143 /* Bitfield definition for register: ACC_I */
144 /*
145  * ACC (RO)
146  *
147  * accumulate result of i_channel, this is a signed number
148  */
149 #define RDC_ACC_I_ACC_MASK (0xFFFFFFFFUL)
150 #define RDC_ACC_I_ACC_SHIFT (0U)
151 #define RDC_ACC_I_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_I_ACC_MASK) >> RDC_ACC_I_ACC_SHIFT)
152 
153 /* Bitfield definition for register: ACC_Q */
154 /*
155  * ACC (RO)
156  *
157  * accumulate result of q_channel, this is a signed number
158  */
159 #define RDC_ACC_Q_ACC_MASK (0xFFFFFFFFUL)
160 #define RDC_ACC_Q_ACC_SHIFT (0U)
161 #define RDC_ACC_Q_ACC_GET(x) (((uint32_t)(x) & RDC_ACC_Q_ACC_MASK) >> RDC_ACC_Q_ACC_SHIFT)
162 
163 /* Bitfield definition for register: IN_CTL */
164 /*
165  * PORT_Q_SEL (RW)
166  *
167  * Input port selection for q_channel,
168  * 0:sel port0
169  * 1:sel port1
170  */
171 #define RDC_IN_CTL_PORT_Q_SEL_MASK (0x100000UL)
172 #define RDC_IN_CTL_PORT_Q_SEL_SHIFT (20U)
173 #define RDC_IN_CTL_PORT_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_Q_SEL_SHIFT) & RDC_IN_CTL_PORT_Q_SEL_MASK)
174 #define RDC_IN_CTL_PORT_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_Q_SEL_MASK) >> RDC_IN_CTL_PORT_Q_SEL_SHIFT)
175 
176 /*
177  * CH_Q_SEL (RW)
178  *
179  * Input channel selection for q_channel
180  * 0: channel 0 selected
181  * 1: channel 1 selected
182  * …
183  * 31: channel 31 selected
184  */
185 #define RDC_IN_CTL_CH_Q_SEL_MASK (0x1F000UL)
186 #define RDC_IN_CTL_CH_Q_SEL_SHIFT (12U)
187 #define RDC_IN_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_Q_SEL_SHIFT) & RDC_IN_CTL_CH_Q_SEL_MASK)
188 #define RDC_IN_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_Q_SEL_MASK) >> RDC_IN_CTL_CH_Q_SEL_SHIFT)
189 
190 /*
191  * PORT_I_SEL (RW)
192  *
193  * Input port selection for i_channel,
194  * 0:sel port0
195  * 1:sel port1
196  */
197 #define RDC_IN_CTL_PORT_I_SEL_MASK (0x100U)
198 #define RDC_IN_CTL_PORT_I_SEL_SHIFT (8U)
199 #define RDC_IN_CTL_PORT_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_PORT_I_SEL_SHIFT) & RDC_IN_CTL_PORT_I_SEL_MASK)
200 #define RDC_IN_CTL_PORT_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_PORT_I_SEL_MASK) >> RDC_IN_CTL_PORT_I_SEL_SHIFT)
201 
202 /*
203  * CH_I_SEL (RW)
204  *
205  * Input channel selection for i_channel
206  * 0: channel 0 selected
207  * 1: channel 1 selected
208  * …
209  * 31: channel 31 selected
210  */
211 #define RDC_IN_CTL_CH_I_SEL_MASK (0x1FU)
212 #define RDC_IN_CTL_CH_I_SEL_SHIFT (0U)
213 #define RDC_IN_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_IN_CTL_CH_I_SEL_SHIFT) & RDC_IN_CTL_CH_I_SEL_MASK)
214 #define RDC_IN_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_IN_CTL_CH_I_SEL_MASK) >> RDC_IN_CTL_CH_I_SEL_SHIFT)
215 
216 /* Bitfield definition for register: OUT_CTL */
217 /*
218  * CH_Q_SEL (RW)
219  *
220  * Output channel selection for q_channel
221  */
222 #define RDC_OUT_CTL_CH_Q_SEL_MASK (0x1F00U)
223 #define RDC_OUT_CTL_CH_Q_SEL_SHIFT (8U)
224 #define RDC_OUT_CTL_CH_Q_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_Q_SEL_SHIFT) & RDC_OUT_CTL_CH_Q_SEL_MASK)
225 #define RDC_OUT_CTL_CH_Q_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_Q_SEL_MASK) >> RDC_OUT_CTL_CH_Q_SEL_SHIFT)
226 
227 /*
228  * CH_I_SEL (RW)
229  *
230  * Output channel selection for i_channel
231  */
232 #define RDC_OUT_CTL_CH_I_SEL_MASK (0x1FU)
233 #define RDC_OUT_CTL_CH_I_SEL_SHIFT (0U)
234 #define RDC_OUT_CTL_CH_I_SEL_SET(x) (((uint32_t)(x) << RDC_OUT_CTL_CH_I_SEL_SHIFT) & RDC_OUT_CTL_CH_I_SEL_MASK)
235 #define RDC_OUT_CTL_CH_I_SEL_GET(x) (((uint32_t)(x) & RDC_OUT_CTL_CH_I_SEL_MASK) >> RDC_OUT_CTL_CH_I_SEL_SHIFT)
236 
237 /* Bitfield definition for register: EXC_TIMMING */
238 /*
239  * SWAP (RW)
240  *
241  * Swap output of PWM and DAC
242  * 0: disable swap
243  * 1: swap output
244  */
245 #define RDC_EXC_TIMMING_SWAP_MASK (0x1000000UL)
246 #define RDC_EXC_TIMMING_SWAP_SHIFT (24U)
247 #define RDC_EXC_TIMMING_SWAP_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SWAP_SHIFT) & RDC_EXC_TIMMING_SWAP_MASK)
248 #define RDC_EXC_TIMMING_SWAP_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SWAP_MASK) >> RDC_EXC_TIMMING_SWAP_SHIFT)
249 
250 /*
251  * PWM_PRD (RW)
252  *
253  * Pwm period in samples，
254  * 0：1 sample period
255  * 1: 2 sample period
256  * ...
257  * 15: 16 sample period
258  */
259 #define RDC_EXC_TIMMING_PWM_PRD_MASK (0xF00000UL)
260 #define RDC_EXC_TIMMING_PWM_PRD_SHIFT (20U)
261 #define RDC_EXC_TIMMING_PWM_PRD_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_PWM_PRD_SHIFT) & RDC_EXC_TIMMING_PWM_PRD_MASK)
262 #define RDC_EXC_TIMMING_PWM_PRD_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_PWM_PRD_MASK) >> RDC_EXC_TIMMING_PWM_PRD_SHIFT)
263 
264 /*
265  * SMP_NUM (RW)
266  *
267  * Number of sample every excitation period
268  * 0: 4 point
269  * 1: 8 point
270  * …
271  * 8: 1024 point
272  */
273 #define RDC_EXC_TIMMING_SMP_NUM_MASK (0xF0000UL)
274 #define RDC_EXC_TIMMING_SMP_NUM_SHIFT (16U)
275 #define RDC_EXC_TIMMING_SMP_NUM_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_NUM_SHIFT) & RDC_EXC_TIMMING_SMP_NUM_MASK)
276 #define RDC_EXC_TIMMING_SMP_NUM_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_NUM_MASK) >> RDC_EXC_TIMMING_SMP_NUM_SHIFT)
277 
278 /*
279  * SMP_RATE (RW)
280  *
281  * The period for excitation sample in clock cycle，
282  * 0: not allowed
283  * 1: 1 cycle
284  * 2: 2 cycles
285  * …
286  * 65535 : 65535 cycles
287  */
288 #define RDC_EXC_TIMMING_SMP_RATE_MASK (0xFFFFU)
289 #define RDC_EXC_TIMMING_SMP_RATE_SHIFT (0U)
290 #define RDC_EXC_TIMMING_SMP_RATE_SET(x) (((uint32_t)(x) << RDC_EXC_TIMMING_SMP_RATE_SHIFT) & RDC_EXC_TIMMING_SMP_RATE_MASK)
291 #define RDC_EXC_TIMMING_SMP_RATE_GET(x) (((uint32_t)(x) & RDC_EXC_TIMMING_SMP_RATE_MASK) >> RDC_EXC_TIMMING_SMP_RATE_SHIFT)
292 
293 /* Bitfield definition for register: EXC_SCALING */
294 /*
295  * AMP_EXP (RW)
296  *
297  * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp
298  */
299 #define RDC_EXC_SCALING_AMP_EXP_MASK (0xF0U)
300 #define RDC_EXC_SCALING_AMP_EXP_SHIFT (4U)
301 #define RDC_EXC_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_EXP_SHIFT) & RDC_EXC_SCALING_AMP_EXP_MASK)
302 #define RDC_EXC_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_EXP_MASK) >> RDC_EXC_SCALING_AMP_EXP_SHIFT)
303 
304 /*
305  * AMP_MAN (RW)
306  *
307  * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp
308  */
309 #define RDC_EXC_SCALING_AMP_MAN_MASK (0xFU)
310 #define RDC_EXC_SCALING_AMP_MAN_SHIFT (0U)
311 #define RDC_EXC_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_EXC_SCALING_AMP_MAN_SHIFT) & RDC_EXC_SCALING_AMP_MAN_MASK)
312 #define RDC_EXC_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_EXC_SCALING_AMP_MAN_MASK) >> RDC_EXC_SCALING_AMP_MAN_SHIFT)
313 
314 /* Bitfield definition for register: EXC_OFFSET */
315 /*
316  * AMP_OFFSET (RW)
317  *
318  * Offset for excitation
319  */
320 #define RDC_EXC_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL)
321 #define RDC_EXC_OFFSET_AMP_OFFSET_SHIFT (0U)
322 #define RDC_EXC_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_EXC_OFFSET_AMP_OFFSET_SHIFT) & RDC_EXC_OFFSET_AMP_OFFSET_MASK)
323 #define RDC_EXC_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_EXC_OFFSET_AMP_OFFSET_MASK) >> RDC_EXC_OFFSET_AMP_OFFSET_SHIFT)
324 
325 /* Bitfield definition for register: PWM_SCALING */
326 /*
327  * N_POL (RW)
328  *
329  * Polarity of exc_n signal
330  * 0: high active
331  * 1: low active
332  */
333 #define RDC_PWM_SCALING_N_POL_MASK (0x2000U)
334 #define RDC_PWM_SCALING_N_POL_SHIFT (13U)
335 #define RDC_PWM_SCALING_N_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_N_POL_SHIFT) & RDC_PWM_SCALING_N_POL_MASK)
336 #define RDC_PWM_SCALING_N_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_N_POL_MASK) >> RDC_PWM_SCALING_N_POL_SHIFT)
337 
338 /*
339  * P_POL (RW)
340  *
341  * Polarity of exc_p signal
342  * 0: high active
343  * 1: low active
344  */
345 #define RDC_PWM_SCALING_P_POL_MASK (0x1000U)
346 #define RDC_PWM_SCALING_P_POL_SHIFT (12U)
347 #define RDC_PWM_SCALING_P_POL_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_P_POL_SHIFT) & RDC_PWM_SCALING_P_POL_MASK)
348 #define RDC_PWM_SCALING_P_POL_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_P_POL_MASK) >> RDC_PWM_SCALING_P_POL_SHIFT)
349 
350 /*
351  * DITHER (RW)
352  *
353  * Enable dither of pwm
354  * 0: disable
355  * 1: enable
356  */
357 #define RDC_PWM_SCALING_DITHER_MASK (0x100U)
358 #define RDC_PWM_SCALING_DITHER_SHIFT (8U)
359 #define RDC_PWM_SCALING_DITHER_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_DITHER_SHIFT) & RDC_PWM_SCALING_DITHER_MASK)
360 #define RDC_PWM_SCALING_DITHER_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_DITHER_MASK) >> RDC_PWM_SCALING_DITHER_SHIFT)
361 
362 /*
363  * AMP_EXP (RW)
364  *
365  * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp
366  */
367 #define RDC_PWM_SCALING_AMP_EXP_MASK (0xF0U)
368 #define RDC_PWM_SCALING_AMP_EXP_SHIFT (4U)
369 #define RDC_PWM_SCALING_AMP_EXP_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_EXP_SHIFT) & RDC_PWM_SCALING_AMP_EXP_MASK)
370 #define RDC_PWM_SCALING_AMP_EXP_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_EXP_MASK) >> RDC_PWM_SCALING_AMP_EXP_SHIFT)
371 
372 /*
373  * AMP_MAN (RW)
374  *
375  * Amplitude scaling for excitation, amplitude = [table value] x man / 2^exp
376  */
377 #define RDC_PWM_SCALING_AMP_MAN_MASK (0xFU)
378 #define RDC_PWM_SCALING_AMP_MAN_SHIFT (0U)
379 #define RDC_PWM_SCALING_AMP_MAN_SET(x) (((uint32_t)(x) << RDC_PWM_SCALING_AMP_MAN_SHIFT) & RDC_PWM_SCALING_AMP_MAN_MASK)
380 #define RDC_PWM_SCALING_AMP_MAN_GET(x) (((uint32_t)(x) & RDC_PWM_SCALING_AMP_MAN_MASK) >> RDC_PWM_SCALING_AMP_MAN_SHIFT)
381 
382 /* Bitfield definition for register: PWM_OFFSET */
383 /*
384  * AMP_OFFSET (RW)
385  *
386  * Offset for excitation
387  */
388 #define RDC_PWM_OFFSET_AMP_OFFSET_MASK (0xFFFFFFUL)
389 #define RDC_PWM_OFFSET_AMP_OFFSET_SHIFT (0U)
390 #define RDC_PWM_OFFSET_AMP_OFFSET_SET(x) (((uint32_t)(x) << RDC_PWM_OFFSET_AMP_OFFSET_SHIFT) & RDC_PWM_OFFSET_AMP_OFFSET_MASK)
391 #define RDC_PWM_OFFSET_AMP_OFFSET_GET(x) (((uint32_t)(x) & RDC_PWM_OFFSET_AMP_OFFSET_MASK) >> RDC_PWM_OFFSET_AMP_OFFSET_SHIFT)
392 
393 /* Bitfield definition for register: TRIG_OUT0_CFG */
394 /*
395  * ENABLE (RW)
396  *
397  * Enable trigger out0
398  * 0: disable
399  * 1: enable
400  */
401 #define RDC_TRIG_OUT0_CFG_ENABLE_MASK (0x100000UL)
402 #define RDC_TRIG_OUT0_CFG_ENABLE_SHIFT (20U)
403 #define RDC_TRIG_OUT0_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT0_CFG_ENABLE_MASK)
404 #define RDC_TRIG_OUT0_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_ENABLE_MASK) >> RDC_TRIG_OUT0_CFG_ENABLE_SHIFT)
405 
406 /*
407  * LEAD_TIM (RW)
408  *
409  * Lead time for trigger out0 from center of low level , this is a signed value
410  * …
411  * 2: 2 cycle befor center of low level
412  * 1: 1 cycle before center of low level
413  * 0: center of low level
414  * -1: 1cycle after center of low level
415  * -2: 2cycle after center of low level
416  */
417 #define RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK (0xFFFFFUL)
418 #define RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT (0U)
419 #define RDC_TRIG_OUT0_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK)
420 #define RDC_TRIG_OUT0_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT0_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT0_CFG_LEAD_TIM_SHIFT)
421 
422 /* Bitfield definition for register: TRIG_OUT1_CFG */
423 /*
424  * ENABLE (RW)
425  *
426  * Enable trigger out1
427  * 0: disable
428  * 1: enable
429  */
430 #define RDC_TRIG_OUT1_CFG_ENABLE_MASK (0x100000UL)
431 #define RDC_TRIG_OUT1_CFG_ENABLE_SHIFT (20U)
432 #define RDC_TRIG_OUT1_CFG_ENABLE_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_ENABLE_SHIFT) & RDC_TRIG_OUT1_CFG_ENABLE_MASK)
433 #define RDC_TRIG_OUT1_CFG_ENABLE_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_ENABLE_MASK) >> RDC_TRIG_OUT1_CFG_ENABLE_SHIFT)
434 
435 /*
436  * LEAD_TIM (RW)
437  *
438  * Lead time for trigger out0 from center of hight level , this is a signed value
439  * …
440  * 2: 2 cycle befor center of hight level
441  * 1: 1 cycle before center of hight level
442  * 0: center of hight level
443  * -1: 1cycle after center of hight level
444  * -2: 2cycle after center of hight level
445  */
446 #define RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK (0xFFFFFUL)
447 #define RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT (0U)
448 #define RDC_TRIG_OUT1_CFG_LEAD_TIM_SET(x) (((uint32_t)(x) << RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK)
449 #define RDC_TRIG_OUT1_CFG_LEAD_TIM_GET(x) (((uint32_t)(x) & RDC_TRIG_OUT1_CFG_LEAD_TIM_MASK) >> RDC_TRIG_OUT1_CFG_LEAD_TIM_SHIFT)
450 
451 /* Bitfield definition for register: PWM_DZ */
452 /*
453  * DZ_N (RW)
454  *
455  * Exc_n dead zone in clock cycle before swap
456  * 0: no dead zone
457  * 1: 1 cycle dead zone
458  * 2: 2 cycle dead zone
459  * …
460  */
461 #define RDC_PWM_DZ_DZ_N_MASK (0xFF00U)
462 #define RDC_PWM_DZ_DZ_N_SHIFT (8U)
463 #define RDC_PWM_DZ_DZ_N_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_N_SHIFT) & RDC_PWM_DZ_DZ_N_MASK)
464 #define RDC_PWM_DZ_DZ_N_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_N_MASK) >> RDC_PWM_DZ_DZ_N_SHIFT)
465 
466 /*
467  * DZ_P (RW)
468  *
469  * Exc_p dead zone in clock cycle before swap
470  * 0: no dead zone
471  * 1: 1 cycle dead zone
472  * 2: 2 cycle dead zone
473  * …
474  */
475 #define RDC_PWM_DZ_DZ_P_MASK (0xFFU)
476 #define RDC_PWM_DZ_DZ_P_SHIFT (0U)
477 #define RDC_PWM_DZ_DZ_P_SET(x) (((uint32_t)(x) << RDC_PWM_DZ_DZ_P_SHIFT) & RDC_PWM_DZ_DZ_P_MASK)
478 #define RDC_PWM_DZ_DZ_P_GET(x) (((uint32_t)(x) & RDC_PWM_DZ_DZ_P_MASK) >> RDC_PWM_DZ_DZ_P_SHIFT)
479 
480 /* Bitfield definition for register: SYNC_OUT_CTRL */
481 /*
482  * PWM_OUT_DLY (RO)
483  *
484  * Delay bettween the delyed trigger and the first pwm pulse in clock cycle
485  * 1: 1 cycle
486  * 2: 2 cycle
487  * …
488  */
489 #define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK (0xFFFF0000UL)
490 #define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT (16U)
491 #define RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_MASK) >> RDC_SYNC_OUT_CTRL_PWM_OUT_DLY_SHIFT)
492 
493 /*
494  * MIN2TRIG_EN (RW)
495  *
496  * Enable trigger out from the min point of exciting signal
497  * 1: enable
498  * 0: disable
499  */
500 #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK (0x20U)
501 #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT (5U)
502 #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK)
503 #define RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MIN2TRIG_EN_SHIFT)
504 
505 /*
506  * MAX2TRIG_EN (RW)
507  *
508  * Enable trigger out from the max point of exciting signal
509  * 1: enable
510  * 0: disable
511  */
512 #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK (0x10U)
513 #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT (4U)
514 #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK)
515 #define RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_MASK) >> RDC_SYNC_OUT_CTRL_MAX2TRIG_EN_SHIFT)
516 
517 /*
518  * SYNC_OUT_SEL (RW)
519  *
520  * Select output synchornize signal
521  * 0: 0 phase of internal exciting signal
522  * 1: 90 phase of internal exciting signal
523  * 2: 180 phase of internal exciting signal
524  * 3: 270 phase of internal exciting signal
525  */
526 #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK (0x3U)
527 #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT (0U)
528 #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SET(x) (((uint32_t)(x) << RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK)
529 #define RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_GET(x) (((uint32_t)(x) & RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_MASK) >> RDC_SYNC_OUT_CTRL_SYNC_OUT_SEL_SHIFT)
530 
531 /* Bitfield definition for register: EXC_SYNC_DLY */
532 /*
533  * DISABLE (RW)
534  *
535  * Disable hardware trigger input
536  * 0: enable
537  * 1: disable
538  */
539 #define RDC_EXC_SYNC_DLY_DISABLE_MASK (0x1000000UL)
540 #define RDC_EXC_SYNC_DLY_DISABLE_SHIFT (24U)
541 #define RDC_EXC_SYNC_DLY_DISABLE_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DISABLE_SHIFT) & RDC_EXC_SYNC_DLY_DISABLE_MASK)
542 #define RDC_EXC_SYNC_DLY_DISABLE_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DISABLE_MASK) >> RDC_EXC_SYNC_DLY_DISABLE_SHIFT)
543 
544 /*
545  * DELAY (RW)
546  *
547  * Trigger in delay timming in bus cycle from rising edge of trigger signal
548  * 0: 1 cycle
549  * 1: 2 cycle
550  * …
551  * 0xffffff: 2^24 cycle
552  */
553 #define RDC_EXC_SYNC_DLY_DELAY_MASK (0xFFFFFFUL)
554 #define RDC_EXC_SYNC_DLY_DELAY_SHIFT (0U)
555 #define RDC_EXC_SYNC_DLY_DELAY_SET(x) (((uint32_t)(x) << RDC_EXC_SYNC_DLY_DELAY_SHIFT) & RDC_EXC_SYNC_DLY_DELAY_MASK)
556 #define RDC_EXC_SYNC_DLY_DELAY_GET(x) (((uint32_t)(x) & RDC_EXC_SYNC_DLY_DELAY_MASK) >> RDC_EXC_SYNC_DLY_DELAY_SHIFT)
557 
558 /* Bitfield definition for register: MAX_I */
559 /*
560  * MAX (RWC)
561  *
562  * Max value of i_channel, write clear
563  */
564 #define RDC_MAX_I_MAX_MASK (0xFFFFFF00UL)
565 #define RDC_MAX_I_MAX_SHIFT (8U)
566 #define RDC_MAX_I_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_I_MAX_SHIFT) & RDC_MAX_I_MAX_MASK)
567 #define RDC_MAX_I_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_I_MAX_MASK) >> RDC_MAX_I_MAX_SHIFT)
568 
569 /*
570  * VALID (RWC)
571  *
572  * Max value valid, write clear
573  * 0: max value is not valid
574  * 1: max value is valid
575  */
576 #define RDC_MAX_I_VALID_MASK (0x1U)
577 #define RDC_MAX_I_VALID_SHIFT (0U)
578 #define RDC_MAX_I_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_I_VALID_SHIFT) & RDC_MAX_I_VALID_MASK)
579 #define RDC_MAX_I_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_I_VALID_MASK) >> RDC_MAX_I_VALID_SHIFT)
580 
581 /* Bitfield definition for register: MIN_I */
582 /*
583  * MIN (RWC)
584  *
585  * Min value of i_channel, write clear
586  */
587 #define RDC_MIN_I_MIN_MASK (0xFFFFFF00UL)
588 #define RDC_MIN_I_MIN_SHIFT (8U)
589 #define RDC_MIN_I_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_I_MIN_SHIFT) & RDC_MIN_I_MIN_MASK)
590 #define RDC_MIN_I_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_I_MIN_MASK) >> RDC_MIN_I_MIN_SHIFT)
591 
592 /*
593  * VALID (RWC)
594  *
595  * Min value valid, write clear
596  * 0: min value is not valid
597  * 1: min value is valid
598  */
599 #define RDC_MIN_I_VALID_MASK (0x1U)
600 #define RDC_MIN_I_VALID_SHIFT (0U)
601 #define RDC_MIN_I_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_I_VALID_SHIFT) & RDC_MIN_I_VALID_MASK)
602 #define RDC_MIN_I_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_I_VALID_MASK) >> RDC_MIN_I_VALID_SHIFT)
603 
604 /* Bitfield definition for register: MAX_Q */
605 /*
606  * MAX (RWC)
607  *
608  * Max value of q_channel, write clear
609  */
610 #define RDC_MAX_Q_MAX_MASK (0xFFFFFF00UL)
611 #define RDC_MAX_Q_MAX_SHIFT (8U)
612 #define RDC_MAX_Q_MAX_SET(x) (((uint32_t)(x) << RDC_MAX_Q_MAX_SHIFT) & RDC_MAX_Q_MAX_MASK)
613 #define RDC_MAX_Q_MAX_GET(x) (((uint32_t)(x) & RDC_MAX_Q_MAX_MASK) >> RDC_MAX_Q_MAX_SHIFT)
614 
615 /*
616  * VALID (RWC)
617  *
618  * Max value valid, write clear
619  * 0: max value is not valid
620  * 1: max value is valid
621  */
622 #define RDC_MAX_Q_VALID_MASK (0x1U)
623 #define RDC_MAX_Q_VALID_SHIFT (0U)
624 #define RDC_MAX_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MAX_Q_VALID_SHIFT) & RDC_MAX_Q_VALID_MASK)
625 #define RDC_MAX_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MAX_Q_VALID_MASK) >> RDC_MAX_Q_VALID_SHIFT)
626 
627 /* Bitfield definition for register: MIN_Q */
628 /*
629  * MIN (RWC)
630  *
631  * Min value of q_channel, write clear
632  */
633 #define RDC_MIN_Q_MIN_MASK (0xFFFFFF00UL)
634 #define RDC_MIN_Q_MIN_SHIFT (8U)
635 #define RDC_MIN_Q_MIN_SET(x) (((uint32_t)(x) << RDC_MIN_Q_MIN_SHIFT) & RDC_MIN_Q_MIN_MASK)
636 #define RDC_MIN_Q_MIN_GET(x) (((uint32_t)(x) & RDC_MIN_Q_MIN_MASK) >> RDC_MIN_Q_MIN_SHIFT)
637 
638 /*
639  * VALID (RWC)
640  *
641  * Min value valid, write clear
642  * 0: min value is not valid
643  * 1: min value is valid
644  */
645 #define RDC_MIN_Q_VALID_MASK (0x1U)
646 #define RDC_MIN_Q_VALID_SHIFT (0U)
647 #define RDC_MIN_Q_VALID_SET(x) (((uint32_t)(x) << RDC_MIN_Q_VALID_SHIFT) & RDC_MIN_Q_VALID_MASK)
648 #define RDC_MIN_Q_VALID_GET(x) (((uint32_t)(x) & RDC_MIN_Q_VALID_MASK) >> RDC_MIN_Q_VALID_SHIFT)
649 
650 /* Bitfield definition for register: THRS_I */
651 /*
652  * THRS (RW)
653  *
654  * The offset setting for edge detection of the i_channel, signed number
655  * …
656  * 2: the offset is 0x800000+2
657  * 1: the offset is 0x800000+1
658  * 0: the offset is 0x800000
659  * -1: the offset is 0x800000-1
660  * -2: the offset is 0x800000-2
661  * …
662  */
663 #define RDC_THRS_I_THRS_MASK (0xFFFFFF00UL)
664 #define RDC_THRS_I_THRS_SHIFT (8U)
665 #define RDC_THRS_I_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_I_THRS_SHIFT) & RDC_THRS_I_THRS_MASK)
666 #define RDC_THRS_I_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_I_THRS_MASK) >> RDC_THRS_I_THRS_SHIFT)
667 
668 /* Bitfield definition for register: THRS_Q */
669 /*
670  * THRS (RW)
671  *
672  * The offset setting for edge detection of the q_channel, signed number
673  * …
674  * 2: the offset is 0x800000+2
675  * 1: the offset is 0x800000+1
676  * 0: the offset is 0x800000
677  * -1: the offset is 0x800000-1
678  * -2: the offset is 0x800000-2
679  * …
680  */
681 #define RDC_THRS_Q_THRS_MASK (0xFFFFFF00UL)
682 #define RDC_THRS_Q_THRS_SHIFT (8U)
683 #define RDC_THRS_Q_THRS_SET(x) (((uint32_t)(x) << RDC_THRS_Q_THRS_SHIFT) & RDC_THRS_Q_THRS_MASK)
684 #define RDC_THRS_Q_THRS_GET(x) (((uint32_t)(x) & RDC_THRS_Q_THRS_MASK) >> RDC_THRS_Q_THRS_SHIFT)
685 
686 /* Bitfield definition for register: EDG_DET_CTL */
687 /*
688  * HOLD (RW)
689  *
690  * The minimum edge distance in sample
691  * 0:1 sample
692  * 1:2 sample
693  * 2:3 samples
694  * …
695  * 63:64 samples
696  */
697 #define RDC_EDG_DET_CTL_HOLD_MASK (0x3F0U)
698 #define RDC_EDG_DET_CTL_HOLD_SHIFT (4U)
699 #define RDC_EDG_DET_CTL_HOLD_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_HOLD_SHIFT) & RDC_EDG_DET_CTL_HOLD_MASK)
700 #define RDC_EDG_DET_CTL_HOLD_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_HOLD_MASK) >> RDC_EDG_DET_CTL_HOLD_SHIFT)
701 
702 /*
703  * FILTER (RW)
704  *
705  * The continuous positive or negative number for edge detection
706  * 0: 1
707  * 1: 2
708  * …
709  * 7: 8
710  */
711 #define RDC_EDG_DET_CTL_FILTER_MASK (0x7U)
712 #define RDC_EDG_DET_CTL_FILTER_SHIFT (0U)
713 #define RDC_EDG_DET_CTL_FILTER_SET(x) (((uint32_t)(x) << RDC_EDG_DET_CTL_FILTER_SHIFT) & RDC_EDG_DET_CTL_FILTER_MASK)
714 #define RDC_EDG_DET_CTL_FILTER_GET(x) (((uint32_t)(x) & RDC_EDG_DET_CTL_FILTER_MASK) >> RDC_EDG_DET_CTL_FILTER_SHIFT)
715 
716 /* Bitfield definition for register: ACC_SCALING */
717 /*
718  * TOXIC_LK (RW)
719  *
720  * Toxic accumulation data be removed control
721  * 1: enable
722  * 0: disable
723  */
724 #define RDC_ACC_SCALING_TOXIC_LK_MASK (0x100U)
725 #define RDC_ACC_SCALING_TOXIC_LK_SHIFT (8U)
726 #define RDC_ACC_SCALING_TOXIC_LK_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_TOXIC_LK_SHIFT) & RDC_ACC_SCALING_TOXIC_LK_MASK)
727 #define RDC_ACC_SCALING_TOXIC_LK_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_TOXIC_LK_MASK) >> RDC_ACC_SCALING_TOXIC_LK_SHIFT)
728 
729 /*
730  * ACC_SHIFT (RW)
731  *
732  * Accumulation value shift control, this is a sign number.
733  * 0: {acc[39],acc[38:8]}
734  * 1: {acc[39],acc[37:7]}
735  * 2: {acc[39],acc[36:6]}
736  * …
737  * 7: {acc[39],acc[31:1]}
738  * 8: {acc[39],acc[30:0]}
739  * 9: acc/2^9
740  * 10: acc/2^10
741  * …
742  * 15:acc/2^15
743  */
744 #define RDC_ACC_SCALING_ACC_SHIFT_MASK (0xFU)
745 #define RDC_ACC_SCALING_ACC_SHIFT_SHIFT (0U)
746 #define RDC_ACC_SCALING_ACC_SHIFT_SET(x) (((uint32_t)(x) << RDC_ACC_SCALING_ACC_SHIFT_SHIFT) & RDC_ACC_SCALING_ACC_SHIFT_MASK)
747 #define RDC_ACC_SCALING_ACC_SHIFT_GET(x) (((uint32_t)(x) & RDC_ACC_SCALING_ACC_SHIFT_MASK) >> RDC_ACC_SCALING_ACC_SHIFT_SHIFT)
748 
749 /* Bitfield definition for register: EXC_PERIOD */
750 /*
751  * EXC_PERIOD (RW)
752  *
753  * The num in clock cycle for period of excitation
754  * 0: invalid value
755  * 1:1 cycle
756  * 2:2 cycles
757  * …
758  */
759 #define RDC_EXC_PERIOD_EXC_PERIOD_MASK (0xFFFFFFFFUL)
760 #define RDC_EXC_PERIOD_EXC_PERIOD_SHIFT (0U)
761 #define RDC_EXC_PERIOD_EXC_PERIOD_SET(x) (((uint32_t)(x) << RDC_EXC_PERIOD_EXC_PERIOD_SHIFT) & RDC_EXC_PERIOD_EXC_PERIOD_MASK)
762 #define RDC_EXC_PERIOD_EXC_PERIOD_GET(x) (((uint32_t)(x) & RDC_EXC_PERIOD_EXC_PERIOD_MASK) >> RDC_EXC_PERIOD_EXC_PERIOD_SHIFT)
763 
764 /* Bitfield definition for register: SYNC_DELAY_I */
765 /*
766  * DELAY (RW)
767  *
768  * Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period.
769  * 0: invalid value
770  * 1: 1 cycles
771  * 2: 2 cycles
772  * ...
773  */
774 #define RDC_SYNC_DELAY_I_DELAY_MASK (0xFFFFFFFFUL)
775 #define RDC_SYNC_DELAY_I_DELAY_SHIFT (0U)
776 #define RDC_SYNC_DELAY_I_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_I_DELAY_SHIFT) & RDC_SYNC_DELAY_I_DELAY_MASK)
777 #define RDC_SYNC_DELAY_I_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_I_DELAY_MASK) >> RDC_SYNC_DELAY_I_DELAY_SHIFT)
778 
779 /* Bitfield definition for register: RISE_DELAY_I */
780 /*
781  * RISE_DELAY (RO)
782  *
783  * Delay value on rising edge of i_channel data
784  * 0: 1 cycle
785  * 1: 2 cycles
786  * …
787  */
788 #define RDC_RISE_DELAY_I_RISE_DELAY_MASK (0xFFFFFFFFUL)
789 #define RDC_RISE_DELAY_I_RISE_DELAY_SHIFT (0U)
790 #define RDC_RISE_DELAY_I_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_I_RISE_DELAY_MASK) >> RDC_RISE_DELAY_I_RISE_DELAY_SHIFT)
791 
792 /* Bitfield definition for register: FALL_DELAY_I */
793 /*
794  * FALL_DELAY (RO)
795  *
796  * Delay value on falling edge of i_channel data
797  * 0: 1 cycle
798  * 1: 2 cycles
799  * …
800  */
801 #define RDC_FALL_DELAY_I_FALL_DELAY_MASK (0xFFFFFFFFUL)
802 #define RDC_FALL_DELAY_I_FALL_DELAY_SHIFT (0U)
803 #define RDC_FALL_DELAY_I_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_I_FALL_DELAY_MASK) >> RDC_FALL_DELAY_I_FALL_DELAY_SHIFT)
804 
805 /* Bitfield definition for register: SAMPLE_RISE_I */
806 /*
807  * VALUE (RO)
808  *
809  * sample value on rising edge of rectify signal
810  */
811 #define RDC_SAMPLE_RISE_I_VALUE_MASK (0xFFFFFF00UL)
812 #define RDC_SAMPLE_RISE_I_VALUE_SHIFT (8U)
813 #define RDC_SAMPLE_RISE_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_I_VALUE_MASK) >> RDC_SAMPLE_RISE_I_VALUE_SHIFT)
814 
815 /* Bitfield definition for register: SAMPLE_FALL_I */
816 /*
817  * VALUE (RO)
818  *
819  * sample value on falling edge of rectify signal
820  */
821 #define RDC_SAMPLE_FALL_I_VALUE_MASK (0xFFFFFF00UL)
822 #define RDC_SAMPLE_FALL_I_VALUE_SHIFT (8U)
823 #define RDC_SAMPLE_FALL_I_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_I_VALUE_MASK) >> RDC_SAMPLE_FALL_I_VALUE_SHIFT)
824 
825 /* Bitfield definition for register: ACC_CNT_I */
826 /*
827  * CNT_NEG (RO)
828  *
829  * sample number during the negtive of rectify signal
830  * 1: 1
831  * 2: 2
832  * …
833  */
834 #define RDC_ACC_CNT_I_CNT_NEG_MASK (0xFFFF0000UL)
835 #define RDC_ACC_CNT_I_CNT_NEG_SHIFT (16U)
836 #define RDC_ACC_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_NEG_MASK) >> RDC_ACC_CNT_I_CNT_NEG_SHIFT)
837 
838 /*
839  * CNT_POS (RO)
840  *
841  * sample number during the positive of rectify signal
842  * 1: 1
843  * 2: 2
844  * …
845  */
846 #define RDC_ACC_CNT_I_CNT_POS_MASK (0xFFFFU)
847 #define RDC_ACC_CNT_I_CNT_POS_SHIFT (0U)
848 #define RDC_ACC_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_I_CNT_POS_MASK) >> RDC_ACC_CNT_I_CNT_POS_SHIFT)
849 
850 /* Bitfield definition for register: SIGN_CNT_I */
851 /*
852  * CNT_NEG (RO)
853  *
854  * Positive sample counter during negative rectify signal
855  */
856 #define RDC_SIGN_CNT_I_CNT_NEG_MASK (0xFFFF0000UL)
857 #define RDC_SIGN_CNT_I_CNT_NEG_SHIFT (16U)
858 #define RDC_SIGN_CNT_I_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_NEG_MASK) >> RDC_SIGN_CNT_I_CNT_NEG_SHIFT)
859 
860 /*
861  * CNT_POS (RO)
862  *
863  * Negative sample counter during positive rectify signal
864  */
865 #define RDC_SIGN_CNT_I_CNT_POS_MASK (0xFFFFU)
866 #define RDC_SIGN_CNT_I_CNT_POS_SHIFT (0U)
867 #define RDC_SIGN_CNT_I_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_I_CNT_POS_MASK) >> RDC_SIGN_CNT_I_CNT_POS_SHIFT)
868 
869 /* Bitfield definition for register: SYNC_DELAY_Q */
870 /*
871  * DELAY (RW)
872  *
873  * Delay in clock cycle for synchronous signal, the value shoud less than half of exc_period.exc_period.
874  * 0: invalid value
875  * 1: 1 cycles
876  * 2: 2 cycles
877  * ...
878  */
879 #define RDC_SYNC_DELAY_Q_DELAY_MASK (0xFFFFFFFFUL)
880 #define RDC_SYNC_DELAY_Q_DELAY_SHIFT (0U)
881 #define RDC_SYNC_DELAY_Q_DELAY_SET(x) (((uint32_t)(x) << RDC_SYNC_DELAY_Q_DELAY_SHIFT) & RDC_SYNC_DELAY_Q_DELAY_MASK)
882 #define RDC_SYNC_DELAY_Q_DELAY_GET(x) (((uint32_t)(x) & RDC_SYNC_DELAY_Q_DELAY_MASK) >> RDC_SYNC_DELAY_Q_DELAY_SHIFT)
883 
884 /* Bitfield definition for register: RISE_DELAY_Q */
885 /*
886  * RISE_DELAY (RO)
887  *
888  * Delay value on rising edge of q_channel data
889  * 0: 1 cycle
890  * 1: 2 cycles
891  * …
892  */
893 #define RDC_RISE_DELAY_Q_RISE_DELAY_MASK (0xFFFFFFFFUL)
894 #define RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT (0U)
895 #define RDC_RISE_DELAY_Q_RISE_DELAY_GET(x) (((uint32_t)(x) & RDC_RISE_DELAY_Q_RISE_DELAY_MASK) >> RDC_RISE_DELAY_Q_RISE_DELAY_SHIFT)
896 
897 /* Bitfield definition for register: FALL_DELAY_Q */
898 /*
899  * FALL_DELAY (RO)
900  *
901  * Delay value on falling edge of q_channel data
902  * 0: 1 cycle
903  * 1: 2 cycles
904  * …
905  */
906 #define RDC_FALL_DELAY_Q_FALL_DELAY_MASK (0xFFFFFFFFUL)
907 #define RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT (0U)
908 #define RDC_FALL_DELAY_Q_FALL_DELAY_GET(x) (((uint32_t)(x) & RDC_FALL_DELAY_Q_FALL_DELAY_MASK) >> RDC_FALL_DELAY_Q_FALL_DELAY_SHIFT)
909 
910 /* Bitfield definition for register: SAMPLE_RISE_Q */
911 /*
912  * VALUE (RO)
913  *
914  * sample value on rising edge of rectify signal
915  */
916 #define RDC_SAMPLE_RISE_Q_VALUE_MASK (0xFFFFFF00UL)
917 #define RDC_SAMPLE_RISE_Q_VALUE_SHIFT (8U)
918 #define RDC_SAMPLE_RISE_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_RISE_Q_VALUE_MASK) >> RDC_SAMPLE_RISE_Q_VALUE_SHIFT)
919 
920 /* Bitfield definition for register: SAMPLE_FALL_Q */
921 /*
922  * VALUE (RO)
923  *
924  * sample value on falling edge of rectify signal
925  */
926 #define RDC_SAMPLE_FALL_Q_VALUE_MASK (0xFFFFFF00UL)
927 #define RDC_SAMPLE_FALL_Q_VALUE_SHIFT (8U)
928 #define RDC_SAMPLE_FALL_Q_VALUE_GET(x) (((uint32_t)(x) & RDC_SAMPLE_FALL_Q_VALUE_MASK) >> RDC_SAMPLE_FALL_Q_VALUE_SHIFT)
929 
930 /* Bitfield definition for register: ACC_CNT_Q */
931 /*
932  * CNT_NEG (RO)
933  *
934  * sample number during the negtive of rectify signal
935  * 1: 1
936  * 2: 2
937  * …
938  */
939 #define RDC_ACC_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL)
940 #define RDC_ACC_CNT_Q_CNT_NEG_SHIFT (16U)
941 #define RDC_ACC_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_NEG_MASK) >> RDC_ACC_CNT_Q_CNT_NEG_SHIFT)
942 
943 /*
944  * CNT_POS (RO)
945  *
946  * sample number during the positive of rectify signal
947  * 1: 1
948  * 2: 2
949  * …
950  */
951 #define RDC_ACC_CNT_Q_CNT_POS_MASK (0xFFFFU)
952 #define RDC_ACC_CNT_Q_CNT_POS_SHIFT (0U)
953 #define RDC_ACC_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_ACC_CNT_Q_CNT_POS_MASK) >> RDC_ACC_CNT_Q_CNT_POS_SHIFT)
954 
955 /* Bitfield definition for register: SIGN_CNT_Q */
956 /*
957  * CNT_NEG (RO)
958  *
959  * Positive sample counter during negative rectify signal
960  */
961 #define RDC_SIGN_CNT_Q_CNT_NEG_MASK (0xFFFF0000UL)
962 #define RDC_SIGN_CNT_Q_CNT_NEG_SHIFT (16U)
963 #define RDC_SIGN_CNT_Q_CNT_NEG_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_NEG_MASK) >> RDC_SIGN_CNT_Q_CNT_NEG_SHIFT)
964 
965 /*
966  * CNT_POS (RO)
967  *
968  * Negative sample counter during positive rectify signal
969  */
970 #define RDC_SIGN_CNT_Q_CNT_POS_MASK (0xFFFFU)
971 #define RDC_SIGN_CNT_Q_CNT_POS_SHIFT (0U)
972 #define RDC_SIGN_CNT_Q_CNT_POS_GET(x) (((uint32_t)(x) & RDC_SIGN_CNT_Q_CNT_POS_MASK) >> RDC_SIGN_CNT_Q_CNT_POS_SHIFT)
973 
974 /* Bitfield definition for register: AMP_MAX */
975 /*
976  * MAX (RW)
977  *
978  * the maximum of acc amplitude
979  */
980 #define RDC_AMP_MAX_MAX_MASK (0xFFFFFFFFUL)
981 #define RDC_AMP_MAX_MAX_SHIFT (0U)
982 #define RDC_AMP_MAX_MAX_SET(x) (((uint32_t)(x) << RDC_AMP_MAX_MAX_SHIFT) & RDC_AMP_MAX_MAX_MASK)
983 #define RDC_AMP_MAX_MAX_GET(x) (((uint32_t)(x) & RDC_AMP_MAX_MAX_MASK) >> RDC_AMP_MAX_MAX_SHIFT)
984 
985 /* Bitfield definition for register: AMP_MIN */
986 /*
987  * MIN (RW)
988  *
989  * the minimum of acc amplitude
990  */
991 #define RDC_AMP_MIN_MIN_MASK (0xFFFFFFFFUL)
992 #define RDC_AMP_MIN_MIN_SHIFT (0U)
993 #define RDC_AMP_MIN_MIN_SET(x) (((uint32_t)(x) << RDC_AMP_MIN_MIN_SHIFT) & RDC_AMP_MIN_MIN_MASK)
994 #define RDC_AMP_MIN_MIN_GET(x) (((uint32_t)(x) & RDC_AMP_MIN_MIN_MASK) >> RDC_AMP_MIN_MIN_SHIFT)
995 
996 /* Bitfield definition for register: INT_EN */
997 /*
998  * INT_EN (RW)
999  *
1000  * enable interrupt output
1001  */
1002 #define RDC_INT_EN_INT_EN_MASK (0x80000000UL)
1003 #define RDC_INT_EN_INT_EN_SHIFT (31U)
1004 #define RDC_INT_EN_INT_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_INT_EN_SHIFT) & RDC_INT_EN_INT_EN_MASK)
1005 #define RDC_INT_EN_INT_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_INT_EN_MASK) >> RDC_INT_EN_INT_EN_SHIFT)
1006 
1007 /*
1008  * ACC_VLD_I_EN (RW)
1009  *
1010  * i_channel accumulate valid interrupt enable for i_channel
1011  */
1012 #define RDC_INT_EN_ACC_VLD_I_EN_MASK (0x8000U)
1013 #define RDC_INT_EN_ACC_VLD_I_EN_SHIFT (15U)
1014 #define RDC_INT_EN_ACC_VLD_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_EN_MASK)
1015 #define RDC_INT_EN_ACC_VLD_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_EN_SHIFT)
1016 
1017 /*
1018  * ACC_VLD_Q_EN (RW)
1019  *
1020  * q_channel accumulate valid interrupt enable for i_channel
1021  */
1022 #define RDC_INT_EN_ACC_VLD_Q_EN_MASK (0x4000U)
1023 #define RDC_INT_EN_ACC_VLD_Q_EN_SHIFT (14U)
1024 #define RDC_INT_EN_ACC_VLD_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_EN_MASK)
1025 #define RDC_INT_EN_ACC_VLD_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_EN_SHIFT)
1026 
1027 /*
1028  * RISING_DELAY_I_EN (RW)
1029  *
1030  * i_channel delayed rectify signal rising edge interrupt enable
1031  */
1032 #define RDC_INT_EN_RISING_DELAY_I_EN_MASK (0x2000U)
1033 #define RDC_INT_EN_RISING_DELAY_I_EN_SHIFT (13U)
1034 #define RDC_INT_EN_RISING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_I_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_I_EN_MASK)
1035 #define RDC_INT_EN_RISING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_I_EN_MASK) >> RDC_INT_EN_RISING_DELAY_I_EN_SHIFT)
1036 
1037 /*
1038  * FALLING_DELAY_I_EN (RW)
1039  *
1040  * i_channel delayed rectify signal falling edge interrupt enable
1041  */
1042 #define RDC_INT_EN_FALLING_DELAY_I_EN_MASK (0x1000U)
1043 #define RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT (12U)
1044 #define RDC_INT_EN_FALLING_DELAY_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK)
1045 #define RDC_INT_EN_FALLING_DELAY_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_I_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_I_EN_SHIFT)
1046 
1047 /*
1048  * RISING_DELAY_Q_EN (RW)
1049  *
1050  * q_channel delayed rectify signal rising edge interrupt enable
1051  */
1052 #define RDC_INT_EN_RISING_DELAY_Q_EN_MASK (0x800U)
1053 #define RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT (11U)
1054 #define RDC_INT_EN_RISING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK)
1055 #define RDC_INT_EN_RISING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_RISING_DELAY_Q_EN_MASK) >> RDC_INT_EN_RISING_DELAY_Q_EN_SHIFT)
1056 
1057 /*
1058  * FALLING_DELAY_Q_EN (RW)
1059  *
1060  * q_channel delayed rectify signal falling edge interrupt enable
1061  */
1062 #define RDC_INT_EN_FALLING_DELAY_Q_EN_MASK (0x400U)
1063 #define RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT (10U)
1064 #define RDC_INT_EN_FALLING_DELAY_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK)
1065 #define RDC_INT_EN_FALLING_DELAY_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_FALLING_DELAY_Q_EN_MASK) >> RDC_INT_EN_FALLING_DELAY_Q_EN_SHIFT)
1066 
1067 /*
1068  * SAMPLE_RISING_I_EN (RW)
1069  *
1070  * i_channel rising edge interrupt enable
1071  */
1072 #define RDC_INT_EN_SAMPLE_RISING_I_EN_MASK (0x200U)
1073 #define RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT (9U)
1074 #define RDC_INT_EN_SAMPLE_RISING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK)
1075 #define RDC_INT_EN_SAMPLE_RISING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_I_EN_SHIFT)
1076 
1077 /*
1078  * SAMPLE_FALLING_I_EN (RW)
1079  *
1080  * i_channel falling edge interrupt enable
1081  */
1082 #define RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK (0x100U)
1083 #define RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT (8U)
1084 #define RDC_INT_EN_SAMPLE_FALLING_I_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK)
1085 #define RDC_INT_EN_SAMPLE_FALLING_I_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_I_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_I_EN_SHIFT)
1086 
1087 /*
1088  * SAMPLE_RISING_Q_EN (RW)
1089  *
1090  * q_channel rising edge interrupt enable
1091  */
1092 #define RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK (0x80U)
1093 #define RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT (7U)
1094 #define RDC_INT_EN_SAMPLE_RISING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK)
1095 #define RDC_INT_EN_SAMPLE_RISING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_RISING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_RISING_Q_EN_SHIFT)
1096 
1097 /*
1098  * SAMPLE_FALLING_Q_EN (RW)
1099  *
1100  * q_channel falling edge interrupt enable
1101  */
1102 #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK (0x40U)
1103 #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT (6U)
1104 #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK)
1105 #define RDC_INT_EN_SAMPLE_FALLING_Q_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_SAMPLE_FALLING_Q_EN_MASK) >> RDC_INT_EN_SAMPLE_FALLING_Q_EN_SHIFT)
1106 
1107 /*
1108  * ACC_VLD_I_OVH_EN (RW)
1109  *
1110  * i_channel accumulate overflow interrupt enable
1111  */
1112 #define RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK (0x20U)
1113 #define RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT (5U)
1114 #define RDC_INT_EN_ACC_VLD_I_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK)
1115 #define RDC_INT_EN_ACC_VLD_I_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVH_EN_SHIFT)
1116 
1117 /*
1118  * ACC_VLD_Q_OVH_EN (RW)
1119  *
1120  * q_channel accumulate overflow interrupt enable
1121  */
1122 #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK (0x10U)
1123 #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT (4U)
1124 #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK)
1125 #define RDC_INT_EN_ACC_VLD_Q_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVH_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVH_EN_SHIFT)
1126 
1127 /*
1128  * ACC_VLD_I_OVL_EN (RW)
1129  *
1130  * i_channel accumulate underflow interrupt enable
1131  */
1132 #define RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK (0x8U)
1133 #define RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT (3U)
1134 #define RDC_INT_EN_ACC_VLD_I_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK)
1135 #define RDC_INT_EN_ACC_VLD_I_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_I_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_I_OVL_EN_SHIFT)
1136 
1137 /*
1138  * ACC_VLD_Q_OVL_EN (RW)
1139  *
1140  * q_channel accumulate underflow interrupt enable
1141  */
1142 #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK (0x4U)
1143 #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT (2U)
1144 #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK)
1145 #define RDC_INT_EN_ACC_VLD_Q_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_VLD_Q_OVL_EN_MASK) >> RDC_INT_EN_ACC_VLD_Q_OVL_EN_SHIFT)
1146 
1147 /*
1148  * ACC_AMP_OVH_EN (RW)
1149  *
1150  * accumulate ample overflow interrupt enable
1151  */
1152 #define RDC_INT_EN_ACC_AMP_OVH_EN_MASK (0x2U)
1153 #define RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT (1U)
1154 #define RDC_INT_EN_ACC_AMP_OVH_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK)
1155 #define RDC_INT_EN_ACC_AMP_OVH_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVH_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVH_EN_SHIFT)
1156 
1157 /*
1158  * ACC_AMP_OVL_EN (RW)
1159  *
1160  * accumulate ample underflow interrupt enable
1161  */
1162 #define RDC_INT_EN_ACC_AMP_OVL_EN_MASK (0x1U)
1163 #define RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT (0U)
1164 #define RDC_INT_EN_ACC_AMP_OVL_EN_SET(x) (((uint32_t)(x) << RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK)
1165 #define RDC_INT_EN_ACC_AMP_OVL_EN_GET(x) (((uint32_t)(x) & RDC_INT_EN_ACC_AMP_OVL_EN_MASK) >> RDC_INT_EN_ACC_AMP_OVL_EN_SHIFT)
1166 
1167 /* Bitfield definition for register: ADC_INT_STATE */
1168 /*
1169  * ACC_VLD_I_STA (W1C)
1170  *
1171  * i_channel accumulate valid interrupt status for i_channel
1172  */
1173 #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK (0x8000U)
1174 #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT (15U)
1175 #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK)
1176 #define RDC_ADC_INT_STATE_ACC_VLD_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_STA_SHIFT)
1177 
1178 /*
1179  * ACC_VLD_Q_STA (W1C)
1180  *
1181  * q_channel accumulate valid interrupt status for i_channel
1182  */
1183 #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK (0x4000U)
1184 #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT (14U)
1185 #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK)
1186 #define RDC_ADC_INT_STATE_ACC_VLD_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_STA_SHIFT)
1187 
1188 /*
1189  * RISING_DELAY_I_STA (W1C)
1190  *
1191  * i_channel delayed rectify signal rising edge interrupt status
1192  */
1193 #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK (0x2000U)
1194 #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT (13U)
1195 #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK)
1196 #define RDC_ADC_INT_STATE_RISING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_I_STA_SHIFT)
1197 
1198 /*
1199  * FALLING_DELAY_I_STA (W1C)
1200  *
1201  * i_channel delayed rectify signal falling edge interrupt status
1202  */
1203 #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK (0x1000U)
1204 #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT (12U)
1205 #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK)
1206 #define RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_I_STA_SHIFT)
1207 
1208 /*
1209  * RISING_DELAY_Q_STA (W1C)
1210  *
1211  * q_channel delayed rectify signal rising edge interrupt status
1212  */
1213 #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK (0x800U)
1214 #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT (11U)
1215 #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK)
1216 #define RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_RISING_DELAY_Q_STA_SHIFT)
1217 
1218 /*
1219  * FALLING_DELAY_Q_STA (W1C)
1220  *
1221  * q_channel delayed rectify signal falling edge interrupt status
1222  */
1223 #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK (0x400U)
1224 #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT (10U)
1225 #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK)
1226 #define RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_MASK) >> RDC_ADC_INT_STATE_FALLING_DELAY_Q_STA_SHIFT)
1227 
1228 /*
1229  * SAMPLE_RISING_I_STA (W1C)
1230  *
1231  * i_channel rising edge interrupt status
1232  */
1233 #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK (0x200U)
1234 #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT (9U)
1235 #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK)
1236 #define RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_I_STA_SHIFT)
1237 
1238 /*
1239  * SAMPLE_FALLING_I_STA (W1C)
1240  *
1241  * i_channel falling edge interrupt status
1242  */
1243 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK (0x100U)
1244 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT (8U)
1245 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK)
1246 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_I_STA_SHIFT)
1247 
1248 /*
1249  * SAMPLE_RISING_Q_STA (W1C)
1250  *
1251  * q_channel rising edge interrupt status
1252  */
1253 #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK (0x80U)
1254 #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT (7U)
1255 #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK)
1256 #define RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_RISING_Q_STA_SHIFT)
1257 
1258 /*
1259  * SAMPLE_FALLING_Q_STA (W1C)
1260  *
1261  * q_channel falling edge interrupt status
1262  */
1263 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK (0x40U)
1264 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT (6U)
1265 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK)
1266 #define RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_MASK) >> RDC_ADC_INT_STATE_SAMPLE_FALLING_Q_STA_SHIFT)
1267 
1268 /*
1269  * ACC_VLD_I_OVH_STA (W1C)
1270  *
1271  * i_channel accumulate overflow interrupt status
1272  */
1273 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK (0x20U)
1274 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT (5U)
1275 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK)
1276 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVH_STA_SHIFT)
1277 
1278 /*
1279  * ACC_VLD_Q_OVH_STA (W1C)
1280  *
1281  * q_channel accumulate overflow interrupt status
1282  */
1283 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK (0x10U)
1284 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT (4U)
1285 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK)
1286 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVH_STA_SHIFT)
1287 
1288 /*
1289  * ACC_VLD_I_OVL_STA (W1C)
1290  *
1291  * i_channel accumulate underflow interrupt status
1292  */
1293 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK (0x8U)
1294 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT (3U)
1295 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK)
1296 #define RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_I_OVL_STA_SHIFT)
1297 
1298 /*
1299  * ACC_VLD_Q_OVL_STA (W1C)
1300  *
1301  * q_channel accumulate underflow interrupt status
1302  */
1303 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK (0x4U)
1304 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT (2U)
1305 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK)
1306 #define RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_VLD_Q_OVL_STA_SHIFT)
1307 
1308 /*
1309  * ACC_AMP_OVH_STA (W1C)
1310  *
1311  * accumulate ample overflow interrupt status
1312  */
1313 #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK (0x2U)
1314 #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT (1U)
1315 #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK)
1316 #define RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVH_STA_SHIFT)
1317 
1318 /*
1319  * ACC_AMP_OVL_STA (W1C)
1320  *
1321  * accumulate ample underflow interrupt status
1322  */
1323 #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK (0x1U)
1324 #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT (0U)
1325 #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SET(x) (((uint32_t)(x) << RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK)
1326 #define RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_GET(x) (((uint32_t)(x) & RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_MASK) >> RDC_ADC_INT_STATE_ACC_AMP_OVL_STA_SHIFT)
1327 
1328 
1329 
1330 
1331 #endif /* HPM_RDC_H */
RDC_Type
Definition: hpm_rdc_regs.h:12