HPM SDK
HPMicro Software Development Kit
hpm_soc_feature.h
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1 /*
2  * Copyright (c) 2021 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef HPM_SOC_FEATURE_H
9 #define HPM_SOC_FEATURE_H
10 
11 #include "hpm_soc.h"
12 #include "hpm_soc_ip_feature.h"
13 
14 /*
15  * UART section
16  */
17 #define UART_SOC_FIFO_SIZE (16U)
18 
19 /*
20  * I2C Section
21  */
22 #define I2C_SOC_FIFO_SIZE (4U)
23 #define I2C_SOC_TRANSFER_COUNT_MAX (256U)
24 
25 /*
26  * PMIC Section
27  */
28 #define PCFG_SOC_LDO1P1_MIN_VOLTAGE_IN_MV (700U)
29 #define PCFG_SOC_LDO1P1_MAX_VOLTAGE_IN_MV (1320U)
30 #define PCFG_SOC_LDO2P5_MIN_VOLTAGE_IN_MV (2125)
31 #define PCFG_SOC_LDO2P5_MAX_VOLTAGE_IN_MV (2900U)
32 #define PCFG_SOC_DCDC_MIN_VOLTAGE_IN_MV (600U)
33 #define PCFG_SOC_DCDC_MAX_VOLTAGE_IN_MV (1375U)
34 
35 /*
36  * PLLCTL Section
37  */
38 #define PLLCTL_SOC_PLL_MAX_COUNT (3U)
39 /* PLL reference clock in hz */
40 #define PLLCTL_SOC_PLL_REFCLK_FREQ (24U * 1000000UL)
41 /* only PLL1 and PLL2 have DIV0, DIV1 */
42 #define PLLCTL_SOC_PLL_HAS_DIV0(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
43 #define PLLCTL_SOC_PLL_HAS_DIV1(x) ((((x) == 1) || ((x) == 2)) ? 1 : 0)
44 
45 
46 /*
47  * PWM Section
48  */
49 #define PWM_SOC_PWM_MAX_COUNT (8U)
50 #define PWM_SOC_CMP_MAX_COUNT (16U)
51 #define PWM_SOC_OUTPUT_TO_PWM_MAX_COUNT (8U)
52 
53 /*
54  * DMA Section
55  */
56 #define DMA_SOC_TRANSFER_WIDTH_MAX(x) (((x) == HPM_XDMA) ? DMA_TRANSFER_WIDTH_DOUBLE_WORD : DMA_TRANSFER_WIDTH_WORD)
57 #define DMA_SOC_TRANSFER_PER_BURST_MAX(x) (((x) == HPM_XDMA) ? DMA_NUM_TRANSFER_PER_BURST_1024T : DMA_NUM_TRANSFER_PER_BURST_128T)
58 #define DMA_SOC_CHANNEL_NUM (8U)
59 #define DMA_SOC_MAX_COUNT (2U)
60 #define DMA_SOC_CHN_TO_DMAMUX_CHN(x, n) (((x) == HPM_XDMA) ? (DMAMUX_MUXCFG_XDMA_MUX0 + n) : (DMAMUX_MUXCFG_HDMA_MUX0 + n))
61 #define DMA_SOC_HAS_IDLE_FLAG (1U)
62 
63 /*
64  * PDMA Section
65  */
66 #define PDMA_SOC_PS_MAX_COUNT (0U)
67 
68 /*
69  * LCDC Section
70  */
71 #define LCDC_SOC_MAX_LAYER_COUNT (0U)
72 #define LCDC_SOC_MAX_CSC_LAYER_COUNT (0U)
73 #define LCDC_SOC_LAYER_SUPPORTS_CSC(x) ((x) < 2)
74 #define LCDC_SOC_LAYER_SUPPORTS_YUV(x) ((x) < 2)
75 
76 /*
77  * USB Section
78  */
79 #define USB_SOC_MAX_COUNT (1U)
80 
81 #define USB_SOC_DCD_QTD_NEXT_INVALID (1U)
82 #define USB_SOC_DCD_QHD_BUFFER_COUNT (5U)
83 #define USB_SOC_DCD_MAX_ENDPOINT_COUNT (8U)
84 #ifndef USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT
85 #define USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT (8U)
86 #endif
87 #define USB_SOC_DCD_MAX_QTD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U * USB_SOC_DCD_QTD_COUNT_EACH_ENDPOINT)
88 #define USB_SOS_DCD_MAX_QHD_COUNT (USB_SOC_DCD_MAX_ENDPOINT_COUNT * 2U)
89 #define USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT (2048U)
90 
91 #define USB_SOC_HCD_FRAMELIST_MAX_ELEMENTS (1024U)
92 
93 /*
94  * ADC Section
95  */
96 #define ADC_SOC_IP_VERSION (1U)
97 #define ADC_SOC_SEQ_MAX_LEN (16U)
98 #define ADC_SOC_MAX_TRIG_CH_LEN (4U)
99 #define ADC_SOC_MAX_TRIG_CH_NUM (11U)
100 #define ADC_SOC_DMA_ADDR_ALIGNMENT (4U)
101 #define ADC_SOC_CONFIG_INTEN_CHAN_BIT_SIZE (8U)
102 #define ADC_SOC_PREEMPT_ENABLE_CTRL_SUPPORT (1U)
103 #define ADC_SOC_SEQ_MAX_DMA_BUFF_LEN_IN_4BYTES (4096U)
104 #define ADC_SOC_PMT_MAX_DMA_BUFF_LEN_IN_4BYTES (48U)
105 
106 #define ADC16_SOC_PARAMS_LEN (34U)
107 #define ADC16_SOC_MAX_CH_NUM (15U)
108 #define ADC16_SOC_MAX_SAMPLE_VALUE (65535U)
109 #define ADC16_SOC_MAX_CONV_CLK_NUM (21U)
110 
111 /*
112  * SYSCTL Section
113  */
114 #define SYSCTL_SOC_CPU_GPR_COUNT (14U)
115 #define SYSCTL_SOC_MONITOR_SLICE_COUNT (4U)
116 
117 /*
118  * PTPC Section
119  */
120 #define PTPC_SOC_TIMER_MAX_COUNT (2U)
121 
122 /*
123  * CAN Section
124  */
125 #define CAN_SOC_MAX_COUNT (2U)
126 #define CAN_SOC_TX_RX_BUFFER_ACCESS_WORKAROUND (1) /* Refer to E00028 in HPM6200 Errata */
127 
128 /*
129  * SDP Section
130  */
131 #define SDP_REGISTER_DESCRIPTOR_COUNT (1U)
132 #define SDP_HAS_SM3_SUPPORT (1U)
133 #define SDP_HAS_SM4_SUPPORT (1U)
134 
135 /*
136  * SOC Privilege mode
137  */
138 #define SOC_HAS_S_MODE (1U)
139 
140 /*
141  * DAC Section
142  */
143 #define DAC_SOC_BUFF_ALIGNED_SIZE (32U)
144 #define DAC_SOC_MAX_DATA (4095U)
145 #define DAC_SOC_MAX_BUFF_COUNT (65536U)
146 #define DAC_SOC_MAX_OUTPUT_FREQ (1000000UL)
147 
148 
149 /*
150  * SDXC Section
151  */
152 #define SDXC_SOC_HAS_MISC_CTRL0 (1)
153 #define SDXC_SOC_HAS_MISC_CTRL1 (1)
154 
155 /*
156  * SPI Section
157  */
158 #define SPI_SOC_TRANSFER_COUNT_MAX (512U)
159 #define SPI_SOC_FIFO_DEPTH (4U)
160 
165 #define PWM_SOC_HRPWM_SUPPORT (1U)
166 #define PWM_SOC_SHADOW_TRIG_SUPPORT (1U)
167 #define PWM_SOC_TIMER_RESET_SUPPORT (1U)
168 
169 #endif /* HPM_SOC_FEATURE_H */
hpm_soc.h
hpm_soc_ip_feature.h