HPM SDK
HPMicro Software Development Kit
hpm_trgmmux_src.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TRGMMUX_SRC_H
10 #define HPM_TRGMMUX_SRC_H
11 
12 /* trgm0_input mux definitions */
13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) /* Low level */
14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) /* High level */
15 #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) /* TRGM0 Input 0 (from IO) */
16 #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) /* TRGM0 Input 1 (from IO) */
17 #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) /* TRGM0 Input 2 (from IO) */
18 #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) /* TRGM0 Input 3 (from IO) */
19 #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) /* TRGM0 Input 4 (from IO) */
20 #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) /* TRGM0 Input 5 (from IO) */
21 #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) /* TRGM0 Input 6 (from IO) */
22 #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) /* TRGM0 Input 7 (from IO) */
23 #define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) /* TRGM0 Input 8 (from IO) */
24 #define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) /* TRGM0 Input 9 (from IO) */
25 #define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) /* TRGM0 Input 10 (from IO) */
26 #define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) /* TRGM0 Input 11 (from IO) */
27 #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) /* TRGM3 Output X0 */
28 #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) /* TRGM3 Output X1 */
29 #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) /* TRGM2 Output X0 */
30 #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) /* TRGM2 Output X1 */
31 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) /* TRGM1 Output X0 */
32 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) /* TRGM1 Output X1 */
33 #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) /* PWM timer 0 channel 8 reference output */
34 #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) /* PWM timer 0 channel 9 reference output */
35 #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) /* PWM timer 0 channel 10 reference output */
36 #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) /* PWM timer 0 channel 11 reference output */
37 #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) /* PWM timer 0 channel 12 reference output */
38 #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) /* PWM timer 0 channel 13 reference output */
39 #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) /* PWM timer 0 channel 14 reference output */
40 #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) /* PWM timer 0 channel 15 reference output */
41 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x1CUL) /* QEI0 triggers output */
42 #define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x1DUL) /* HALL0 triggers output */
43 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x1EUL) /* PTPC output comparison 0 */
44 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x1FUL) /* PTPC output comparison 1 */
45 #define HPM_TRGM0_INPUT_SRC_SYNT_CH0 (0x20UL) /* SYNT0 Channel 0 */
46 #define HPM_TRGM0_INPUT_SRC_SYNT_CH1 (0x21UL) /* SYNT0 Channel 1 */
47 #define HPM_TRGM0_INPUT_SRC_SYNT_CH2 (0x22UL) /* SYNT0 Channel 2 */
48 #define HPM_TRGM0_INPUT_SRC_SYNT_CH3 (0x23UL) /* SYNT0 Channel 3 */
49 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x24UL) /* USB0 frame start */
50 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x25UL) /* the flag bit of debug mode enters */
51 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x26UL) /* GPTMR0 channel 2 */
52 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x27UL) /* GPTMR0 channel 3 */
53 #define HPM_TRGM0_INPUT_SRC_SDM_CMPL0 (0x28UL) /* sdm0 amplitude lower threshold0 */
54 #define HPM_TRGM0_INPUT_SRC_SDM_CMPL1 (0x29UL) /* sdm0 amplitude lower threshold1 */
55 #define HPM_TRGM0_INPUT_SRC_SDM_CMPL2 (0x2AUL) /* sdm0 amplitude lower threshold2 */
56 #define HPM_TRGM0_INPUT_SRC_SDM_CMPL3 (0x2BUL) /* sdm0 amplitude lower threshold3 */
57 #define HPM_TRGM0_INPUT_SRC_SDM_CMPH0 (0x2CUL) /* sdm0 amplitude upper threshold0 */
58 #define HPM_TRGM0_INPUT_SRC_SDM_CMPH1 (0x2DUL) /* sdm0 amplitude upper threshold1 */
59 #define HPM_TRGM0_INPUT_SRC_SDM_CMPH2 (0x2EUL) /* sdm0 amplitude upper threshold2 */
60 #define HPM_TRGM0_INPUT_SRC_SDM_CMPH3 (0x2FUL) /* sdm0 amplitude upper threshold3 */
61 #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ0 (0x30UL) /* SDM0 amplitude zero-crossing threshold0 */
62 #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ1 (0x31UL) /* SDM0 amplitude zero-crossing threshold1 */
63 #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ2 (0x32UL) /* SDM0 amplitude zero-crossing threshold2 */
64 #define HPM_TRGM0_INPUT_SRC_SDM_CMPHZ3 (0x33UL) /* SDM0 amplitude zero-crossing threshold3 */
65 #define HPM_TRGM0_INPUT_SRC_ACMP0_OUT (0x34UL) /* Comparator 0 output */
66 #define HPM_TRGM0_INPUT_SRC_ACMP1_OUT (0x35UL) /* Comparator 1 output */
67 #define HPM_TRGM0_INPUT_SRC_ACMP2_OUT (0x36UL) /* Comparator 2 output */
68 #define HPM_TRGM0_INPUT_SRC_ACMP3_OUT (0x37UL) /* Comparator 3 output */
69 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT0 (0x38UL) /* PLA0 module output 0 */
70 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT1 (0x39UL) /* PLA0 module output 1 */
71 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT2 (0x3AUL) /* PLA0 module output 2 */
72 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT3 (0x3BUL) /* PLA0 module output 3 */
73 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT4 (0x3CUL) /* PLA0 module output 4 */
74 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT5 (0x3DUL) /* PLA0 module output 5 */
75 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT6 (0x3EUL) /* PLA0 module output 6 */
76 #define HPM_TRGM0_INPUT_SRC_PLA0_OUT7 (0x3FUL) /* PLA0 module output 7 */
77 
78 /* trgm1_input mux definitions */
79 #define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) /* Low level */
80 #define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) /* High level */
81 #define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) /* TRGM1 Input 0 (from IO) */
82 #define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) /* TRGM1 Input 1 (from IO) */
83 #define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) /* TRGM1 Input 2 (from IO) */
84 #define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) /* TRGM1 Input 3 (from IO) */
85 #define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) /* TRGM1 Input 4 (from IO) */
86 #define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) /* TRGM1 Input 5 (from IO) */
87 #define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) /* TRGM1 Input 6 (from IO) */
88 #define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) /* TRGM1 Input 7 (from IO) */
89 #define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) /* TRGM1 Input 8 (from IO) */
90 #define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) /* TRGM1 Input 9 (from IO) */
91 #define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) /* TRGM1 Input 10 (from IO) */
92 #define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) /* TRGM1 Input 11 (from IO) */
93 #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) /* TRGM3 Output X0 */
94 #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) /* TRGM3 Output X1 */
95 #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) /* TRGM2 Output X0 */
96 #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) /* TRGM2 Output X1 */
97 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) /* TRGM0 Output X0 */
98 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) /* TRGM0 Output X1 */
99 #define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) /* PWM timer 1 channel 8 reference output */
100 #define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) /* PWM timer 1 channel 9 reference output */
101 #define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) /* PWM timer 1 channel 10 reference output */
102 #define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) /* PWM timer 1 channel 11 reference output */
103 #define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) /* PWM timer 1 channel 12 reference output */
104 #define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) /* PWM timer 1 channel 13 reference output */
105 #define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) /* PWM timer 1 channel 14 reference output */
106 #define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) /* PWM timer 1 channel 15 reference output */
107 #define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x1CUL) /* QEI1 triggers output */
108 #define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x1DUL) /* HALL1 triggers output */
109 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x1EUL) /* PTPC output comparison 0 */
110 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x1FUL) /* PTPC output comparison 1 */
111 #define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x20UL) /* SYNT1 Channel 0 */
112 #define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x21UL) /* SYNT1 Channel 1 */
113 #define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x22UL) /* SYNT1 Channel 2 */
114 #define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x23UL) /* SYNT1 Channel 3 */
115 #define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x24UL) /* USB0 frame start */
116 #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x25UL) /* the flag bit of debug mode enters */
117 #define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT2 (0x26UL) /* GPTMR1 channel 2 */
118 #define HPM_TRGM1_INPUT_SRC_GPTMR1_OUT3 (0x27UL) /* GPTMR1 channel 3 */
119 #define HPM_TRGM1_INPUT_SRC_SDM_CMPL0 (0x28UL) /* sdm amplitude lower threshold0 */
120 #define HPM_TRGM1_INPUT_SRC_SDM_CMPL1 (0x29UL) /* sdm amplitude lower threshold1 */
121 #define HPM_TRGM1_INPUT_SRC_SDM_CMPL2 (0x2AUL) /* sdm amplitude lower threshold2 */
122 #define HPM_TRGM1_INPUT_SRC_SDM_CMPL3 (0x2BUL) /* sdm amplitude lower threshold3 */
123 #define HPM_TRGM1_INPUT_SRC_SDM_CMPH0 (0x2CUL) /* sdm amplitude upper threshold0 */
124 #define HPM_TRGM1_INPUT_SRC_SDM_CMPH1 (0x2DUL) /* sdm amplitude upper threshold1 */
125 #define HPM_TRGM1_INPUT_SRC_SDM_CMPH2 (0x2EUL) /* sdm amplitude upper threshold2 */
126 #define HPM_TRGM1_INPUT_SRC_SDM_CMPH3 (0x2FUL) /* sdm amplitude upper threshold3 */
127 #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ0 (0x30UL) /* SDM amplitude zero-crossing threshold0 */
128 #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ1 (0x31UL) /* SDM amplitude zero-crossing threshold1 */
129 #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ2 (0x32UL) /* SDM amplitude zero-crossing threshold2 */
130 #define HPM_TRGM1_INPUT_SRC_SDM_CMPHZ3 (0x33UL) /* SDM amplitude zero-crossing threshold3 */
131 #define HPM_TRGM1_INPUT_SRC_ACMP0_OUT (0x34UL) /* Comparator 0 output */
132 #define HPM_TRGM1_INPUT_SRC_ACMP1_OUT (0x35UL) /* Comparator 1 output */
133 #define HPM_TRGM1_INPUT_SRC_ACMP2_OUT (0x36UL) /* Comparator 2 output */
134 #define HPM_TRGM1_INPUT_SRC_ACMP3_OUT (0x37UL) /* Comparator 3 output */
135 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT0 (0x38UL) /* PLA1 module output 0 */
136 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT1 (0x39UL) /* PLA1 module output 1 */
137 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT2 (0x3AUL) /* PLA1 module output 2 */
138 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT3 (0x3BUL) /* PLA1 module output 3 */
139 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT4 (0x3CUL) /* PLA1 module output 4 */
140 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT5 (0x3DUL) /* PLA1 module output 5 */
141 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT6 (0x3EUL) /* PLA1 module output 6 */
142 #define HPM_TRGM1_INPUT_SRC_PLA1_OUT7 (0x3FUL) /* PLA1 module output 7 */
143 
144 /* trgm2_input mux definitions */
145 #define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) /* Low level */
146 #define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) /* High level */
147 #define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) /* TRGM2 Input 0 (from IO) */
148 #define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) /* TRGM2 Input 1 (from IO) */
149 #define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) /* TRGM2 Input 2 (from IO) */
150 #define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) /* TRGM2 Input 3 (from IO) */
151 #define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) /* TRGM2 Input 4 (from IO) */
152 #define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) /* TRGM2 Input 5 (from IO) */
153 #define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) /* TRGM2 Input 6 (from IO) */
154 #define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) /* TRGM2 Input 7 (from IO) */
155 #define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) /* TRGM2 Input 8 (from IO) */
156 #define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) /* TRGM2 Input 9 (from IO) */
157 #define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) /* TRGM2 Input 10 (from IO) */
158 #define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) /* TRGM2 Input 11 (from IO) */
159 #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) /* TRGM3 Output X0 */
160 #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) /* TRGM3 Output X1 */
161 #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) /* TRGM1 Output X0 */
162 #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) /* TRGM1 Output X1 */
163 #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) /* TRGM0 Output X0 */
164 #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) /* TRGM0 Output X1 */
165 #define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) /* PWM timer 2 channel 8 reference output */
166 #define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) /* PWM timer 2 channel 9 reference output */
167 #define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) /* PWM timer 2 channel 10 reference output */
168 #define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) /* PWM timer 2 channel 11 reference output */
169 #define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) /* PWM timer 2 channel 12 reference output */
170 #define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) /* PWM timer 2 channel 13 reference output */
171 #define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) /* PWM timer 2 channel 14 reference output */
172 #define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) /* PWM timer 2 channel 15 reference output */
173 #define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x1CUL) /* QEI2 triggers output */
174 #define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x1DUL) /* HALL2 triggers output */
175 #define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x1EUL) /* PTPC output comparison 0 */
176 #define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x1FUL) /* PTPC output comparison 1 */
177 #define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x20UL) /* SYNT2 Channel 0 */
178 #define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x21UL) /* SYNT2 Channel 1 */
179 #define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x22UL) /* SYNT2 Channel 2 */
180 #define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x23UL) /* SYNT2 Channel 3 */
181 #define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x24UL) /* USB0 frame start */
182 #define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x25UL) /* the flag bit of debug mode enters */
183 #define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT2 (0x26UL) /* GPTMR2 channel 2 */
184 #define HPM_TRGM2_INPUT_SRC_GPTMR2_OUT3 (0x27UL) /* GPTMR2 channel 3 */
185 #define HPM_TRGM2_INPUT_SRC_SDM_CMPL0 (0x28UL) /* sdm amplitude lower threshold0 */
186 #define HPM_TRGM2_INPUT_SRC_SDM_CMPL1 (0x29UL) /* sdm amplitude lower threshold1 */
187 #define HPM_TRGM2_INPUT_SRC_SDM_CMPL2 (0x2AUL) /* sdm amplitude lower threshold2 */
188 #define HPM_TRGM2_INPUT_SRC_SDM_CMPL3 (0x2BUL) /* sdm amplitude lower threshold3 */
189 #define HPM_TRGM2_INPUT_SRC_SDM_CMPH0 (0x2CUL) /* sdm amplitude upper threshold0 */
190 #define HPM_TRGM2_INPUT_SRC_SDM_CMPH1 (0x2DUL) /* sdm amplitude upper threshold1 */
191 #define HPM_TRGM2_INPUT_SRC_SDM_CMPH2 (0x2EUL) /* sdm amplitude upper threshold2 */
192 #define HPM_TRGM2_INPUT_SRC_SDM_CMPH3 (0x2FUL) /* sdm amplitude upper threshold3 */
193 #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ0 (0x30UL) /* SDM amplitude zero-crossing threshold0 */
194 #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ1 (0x31UL) /* SDM amplitude zero-crossing threshold1 */
195 #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ2 (0x32UL) /* SDM amplitude zero-crossing threshold2 */
196 #define HPM_TRGM2_INPUT_SRC_SDM_CMPHZ3 (0x33UL) /* SDM amplitude zero-crossing threshold3 */
197 #define HPM_TRGM2_INPUT_SRC_ACMP0_OUT (0x34UL) /* Comparator 0 output */
198 #define HPM_TRGM2_INPUT_SRC_ACMP1_OUT (0x35UL) /* Comparator 1 output */
199 #define HPM_TRGM2_INPUT_SRC_ACMP2_OUT (0x36UL) /* Comparator 2 output */
200 #define HPM_TRGM2_INPUT_SRC_ACMP3_OUT (0x37UL) /* Comparator 3 output */
201 
202 /* trgm3_input mux definitions */
203 #define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) /* Low level */
204 #define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) /* High level */
205 #define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) /* TRGM3 Input 0 (from IO) */
206 #define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) /* TRGM3 Input 1 (from IO) */
207 #define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) /* TRGM3 Input 2 (from IO) */
208 #define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) /* TRGM3 Input 3 (from IO) */
209 #define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) /* TRGM3 Input 4 (from IO) */
210 #define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) /* TRGM3 Input 5 (from IO) */
211 #define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) /* TRGM3 Input 6 (from IO) */
212 #define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) /* TRGM3 Input 7 (from IO) */
213 #define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) /* TRGM3 Input 8 (from IO) */
214 #define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) /* TRGM3 Input 9 (from IO) */
215 #define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) /* TRGM3 Input 10 (from IO) */
216 #define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) /* TRGM3 Input 11 (from IO) */
217 #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) /* TRGM2 Output X0 */
218 #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) /* TRGM2 Output X1 */
219 #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) /* TRGM1 Output X0 */
220 #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) /* TRGM1 Output X1 */
221 #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) /* TRGM0 Output X0 */
222 #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) /* TRGM0 Output X1 */
223 #define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) /* PWM timer 3 channel 8 reference output */
224 #define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) /* PWM timer 3 channel 9 reference output */
225 #define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) /* PWM timer 3 channel 10 reference output */
226 #define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) /* PWM timer 3 channel 11 reference output */
227 #define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) /* PWM timer 3 channel 12 reference output */
228 #define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) /* PWM timer 3 channel 13 reference output */
229 #define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) /* PWM timer 3 channel 14 reference output */
230 #define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) /* PWM timer 3 channel 15 reference output */
231 #define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x1CUL) /* QEI3 triggers output */
232 #define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x1DUL) /* HALL3 triggers output */
233 #define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x1EUL) /* PTPC output comparison 0 */
234 #define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x1FUL) /* PTPC output comparison 1 */
235 #define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x20UL) /* SYNT3 Channel 0 */
236 #define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x21UL) /* SYNT3 Channel 1 */
237 #define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x22UL) /* SYNT3 Channel 2 */
238 #define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x23UL) /* SYNT3 Channel 3 */
239 #define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x24UL) /* USB0 frame start */
240 #define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x25UL) /* the flag bit of debug mode enters */
241 #define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT2 (0x26UL) /* GPTMR3 channel 2 */
242 #define HPM_TRGM3_INPUT_SRC_GPTMR3_OUT3 (0x27UL) /* GPTMR3 channel 3 */
243 #define HPM_TRGM3_INPUT_SRC_SDM_CMPL0 (0x28UL) /* sdm amplitude lower threshold0 */
244 #define HPM_TRGM3_INPUT_SRC_SDM_CMPL1 (0x29UL) /* sdm amplitude lower threshold1 */
245 #define HPM_TRGM3_INPUT_SRC_SDM_CMPL2 (0x2AUL) /* sdm amplitude lower threshold2 */
246 #define HPM_TRGM3_INPUT_SRC_SDM_CMPL3 (0x2BUL) /* sdm amplitude lower threshold3 */
247 #define HPM_TRGM3_INPUT_SRC_SDM_CMPH0 (0x2CUL) /* sdm amplitude upper threshold0 */
248 #define HPM_TRGM3_INPUT_SRC_SDM_CMPH1 (0x2DUL) /* sdm amplitude upper threshold1 */
249 #define HPM_TRGM3_INPUT_SRC_SDM_CMPH2 (0x2EUL) /* sdm amplitude upper threshold2 */
250 #define HPM_TRGM3_INPUT_SRC_SDM_CMPH3 (0x2FUL) /* sdm amplitude upper threshold3 */
251 #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ0 (0x30UL) /* SDM amplitude zero-crossing threshold0 */
252 #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ1 (0x31UL) /* SDM amplitude zero-crossing threshold1 */
253 #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ2 (0x32UL) /* SDM amplitude zero-crossing threshold2 */
254 #define HPM_TRGM3_INPUT_SRC_SDM_CMPHZ3 (0x33UL) /* SDM amplitude zero-crossing threshold3 */
255 #define HPM_TRGM3_INPUT_SRC_ACMP0_OUT (0x34UL) /* Comparator 0 output */
256 #define HPM_TRGM3_INPUT_SRC_ACMP1_OUT (0x35UL) /* Comparator 1 output */
257 #define HPM_TRGM3_INPUT_SRC_ACMP2_OUT (0x36UL) /* Comparator 2 output */
258 #define HPM_TRGM3_INPUT_SRC_ACMP3_OUT (0x37UL) /* Comparator 3 output */
259 
260 /* trgm0_output mux definitions */
261 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) /* TRGM0 Output 0 (to IO) */
262 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) /* TRGM0 Output 1 (to IO) */
263 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) /* TRGM0 Output 2 (to IO) */
264 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) /* TRGM0 Output 3 (to IO) */
265 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) /* TRGM0 Output 4 (to IO) */
266 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) /* TRGM0 Output 5 (to IO) */
267 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) /* TRGM0 Output 6 (to IO) */
268 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) /* TRGM0 Output 7 (to IO) */
269 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) /* TRGM0 Output 8 (to IO) */
270 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) /* TRGM0 Output 9 (to IO) */
271 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) /* TRGM0 Output 10 (to IO) */
272 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) /* TRGM0 Output 11 (to IO) */
273 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) /* TRGM0 Output X0 (to another TRGM) */
274 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) /* TRGM0 Output X1 (to another TRGM) */
275 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) /* PWM timer 0 counter synchronously triggers input */
276 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) /* the input value for PWM timer 0 forces control */
277 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) /* the synchronous input for PWM timer 0 forces control */
278 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) /* PWM timer 0 Shadow register to activate trigger input */
279 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) /* PWM timer 0 Fault protection input 0 */
280 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) /* PWM timer 0 Fault protection input 1 */
281 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) /* PWM timer 0 Fault protection input 2 */
282 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) /* PWM timer 0 Fault protection input 3 */
283 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) /* PWM timer 0 capture input 8 */
284 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) /* PWM timer 0 capture input 9 */
285 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) /* PWM timer 0 capture input 10 */
286 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) /* PWM timer 0 capture input 11 */
287 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) /* PWM timer 0 capture input 12 */
288 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) /* PWM timer 0 capture input 13 */
289 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) /* PWM timer 0 capture input 14 */
290 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) /* PWM timer 0 capture input 15 */
291 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN0 (0x1EUL) /* PLA0 module input 0 */
292 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN1 (0x1FUL) /* PLA0 module input 1 */
293 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN2 (0x20UL) /* PLA0 module input 2 */
294 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN3 (0x21UL) /* PLA0 module input 3 */
295 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN4 (0x22UL) /* PLA0 module input 4 */
296 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN5 (0x23UL) /* PLA0 module input 5 */
297 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN6 (0x24UL) /* PLA0 module input 6 */
298 #define HPM_TRGM0_OUTPUT_SRC_PLA0_IN7 (0x25UL) /* PLA0 module input 7 */
299 #define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) /* QEI0 input of phase A */
300 #define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) /* QEI0 input of phase B */
301 #define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) /* QEI0 input of phase Z */
302 #define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) /* QEI0 input of phase H */
303 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) /* QEI0 Pause input */
304 #define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) /* QEI0 Snap input */
305 #define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) /* HALL0 input of phase U */
306 #define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) /* HALL0 input of phase V */
307 #define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) /* HALL0 input of phase W */
308 #define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) /* HALL0 Snap input */
309 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* The sequence conversion of ADC0 triggers input */
310 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* The sequence conversion of ADC1 triggers input */
311 #define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* The sequence conversion of ADC2 triggers input */
312 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 0A */
313 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 0B */
314 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 0C */
315 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) /* GPTMR0 counter synchronous input */
316 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) /* GPTMR0 channel 2 input */
317 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) /* GPTMR0 channel 3 input */
318 #define HPM_TRGM0_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) /* DAC0 buffer mode starts to trigger */
319 #define HPM_TRGM0_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) /* DAC0 step mode starts to trigger */
320 #define HPM_TRGM0_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) /* DAC1 step mode starts to trigger */
321 #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) /* Comparator 0 window mode input */
322 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC input capture 0 */
323 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC input capture 1 */
324 #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG0 (0x40UL) /* SDM triggers input 0 */
325 #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG1 (0x41UL) /* SDM triggers input 1 */
326 #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG2 (0x42UL) /* SDM triggers input 2 */
327 #define HPM_TRGM0_OUTPUT_SRC_SDM_TRG3 (0x43UL) /* SDM triggers input 3 */
328 
329 /* trgm1_output mux definitions */
330 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) /* TRGM1 Output 0 (to IO) */
331 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) /* TRGM1 Output 1 (to IO) */
332 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) /* TRGM1 Output 2 (to IO) */
333 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) /* TRGM1 Output 3 (to IO) */
334 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) /* TRGM1 Output 4 (to IO) */
335 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) /* TRGM1 Output 5 (to IO) */
336 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) /* TRGM1 Output 6 (to IO) */
337 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) /* TRGM1 Output 7 (to IO) */
338 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) /* TRGM1 Output 8 (to IO) */
339 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) /* TRGM1 Output 9 (to IO) */
340 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) /* TRGM1 Output 10 (to IO) */
341 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) /* TRGM1 Output 11 (to IO) */
342 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) /* TRGM1 Output X0 (to another TRGM) */
343 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) /* TRGM1 Output X1 (to another TRGM) */
344 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) /* PWM timer 1 counter synchronously triggers input */
345 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) /* the input value for PWM timer 1 forces control */
346 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) /* the synchronous input for PWM timer 1 forces control */
347 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) /* PWM timer 1 Shadow register to activate trigger input */
348 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) /* PWM timer 1 Fault protection input 0 */
349 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) /* PWM timer 1 Fault protection input 1 */
350 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) /* PWM timer 1 Fault protection input 2 */
351 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) /* PWM timer 1 Fault protection input 3 */
352 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) /* PWM timer 1 capture input 8 */
353 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) /* PWM timer 1 capture input 9 */
354 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) /* PWM timer 1 capture input 10 */
355 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) /* PWM timer 1 capture input 11 */
356 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) /* PWM timer 1 capture input 12 */
357 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) /* PWM timer 1 capture input 13 */
358 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) /* PWM timer 1 capture input 14 */
359 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) /* PWM timer 1 capture input 15 */
360 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN0 (0x1EUL) /* PLA1 module input 0 */
361 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN1 (0x1FUL) /* PLA1 module input 1 */
362 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN2 (0x20UL) /* PLA1 module input 2 */
363 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN3 (0x21UL) /* PLA1 module input 3 */
364 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN4 (0x22UL) /* PLA1 module input 4 */
365 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN5 (0x23UL) /* PLA1 module input 5 */
366 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN6 (0x24UL) /* PLA1 module input 6 */
367 #define HPM_TRGM1_OUTPUT_SRC_PLA1_IN7 (0x25UL) /* PLA1 module input 7 */
368 #define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) /* QEI1 input of phase A */
369 #define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) /* QEI1 input of phase B */
370 #define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) /* QEI1 input of phase Z */
371 #define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) /* QEI1 input of phase H */
372 #define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) /* QEI1 Pause input */
373 #define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) /* QEI1 Snap input */
374 #define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) /* HALL1 input of phase U */
375 #define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) /* HALL1 input of phase V */
376 #define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) /* HALL1 input of phase W */
377 #define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) /* HALL1 Snap input */
378 #define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* The sequence conversion of ADC0 triggers input */
379 #define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* The sequence conversion of ADC1 triggers input */
380 #define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* The sequence conversion of ADC2 triggers input */
381 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 1A */
382 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 1B */
383 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 1C */
384 #define HPM_TRGM1_OUTPUT_SRC_GPTMR1_SYNCI (0x37UL) /* GPTMR1 counter synchronous input */
385 #define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN2 (0x38UL) /* GPTMR1 channel 2 input */
386 #define HPM_TRGM1_OUTPUT_SRC_GPTMR1_IN3 (0x39UL) /* GPTMR1 channel 3 input */
387 #define HPM_TRGM1_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) /* DAC1 buffer mode starts to trigger */
388 #define HPM_TRGM1_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) /* DAC0 step mode starts to trigger */
389 #define HPM_TRGM1_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) /* DAC1 step mode starts to trigger */
390 #define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) /* Comparator 1 window mode input */
391 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC input capture 0 */
392 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC input capture 1 */
393 #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG4 (0x40UL) /* SDM triggers input 4 */
394 #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG5 (0x41UL) /* SDM triggers input 5 */
395 #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG6 (0x42UL) /* SDM triggers input 6 */
396 #define HPM_TRGM1_OUTPUT_SRC_SDM_TRG7 (0x43UL) /* SDM triggers input 7 */
397 
398 /* trgm2_output mux definitions */
399 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) /* TRGM2 Output 0 (to IO) */
400 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) /* TRGM2 Output 1 (to IO) */
401 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) /* TRGM2 Output 2 (to IO) */
402 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) /* TRGM2 Output 3 (to IO) */
403 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) /* TRGM2 Output 4 (to IO) */
404 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) /* TRGM2 Output 5 (to IO) */
405 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) /* TRGM2 Output 6 (to IO) */
406 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) /* TRGM2 Output 7 (to IO) */
407 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) /* TRGM2 Output 8 (to IO) */
408 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) /* TRGM2 Output 9 (to IO) */
409 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) /* TRGM2 Output 10 (to IO) */
410 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) /* TRGM2 Output 11 (to IO) */
411 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) /* TRGM2 Output X0 (to another TRGM) */
412 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) /* TRGM2 Output X1 (to another TRGM) */
413 #define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) /* PWM timer 2 counter synchronously triggers input */
414 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) /* the input value for PWM timer 2 forces control */
415 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) /* the synchronous input for PWM timer 2 forces control */
416 #define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) /* PWM timer 2 Shadow register to activate trigger input */
417 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) /* PWM timer 2 Fault protection input 0 */
418 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) /* PWM timer 2 Fault protection input 1 */
419 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) /* PWM timer 2 Fault protection input 2 */
420 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) /* PWM timer 2 Fault protection input 3 */
421 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) /* PWM timer 2 capture input 8 */
422 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) /* PWM timer 2 capture input 9 */
423 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) /* PWM timer 2 capture input 10 */
424 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) /* PWM timer 2 capture input 11 */
425 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) /* PWM timer 2 capture input 12 */
426 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) /* PWM timer 2 capture input 13 */
427 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) /* PWM timer 2 capture input 14 */
428 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) /* PWM timer 2 capture input 15 */
429 #define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) /* QEI2 input of phase A */
430 #define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) /* QEI2 input of phase B */
431 #define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) /* QEI2 input of phase Z */
432 #define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) /* QEI2 input of phase H */
433 #define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) /* QEI2 Pause input */
434 #define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) /* QEI2 Snap input */
435 #define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) /* HALL2 input of phase U */
436 #define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) /* HALL2 input of phase V */
437 #define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) /* HALL2 input of phase W */
438 #define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) /* HALL2 Snap input */
439 #define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* The sequence conversion of ADC0 triggers input */
440 #define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* The sequence conversion of ADC1 triggers input */
441 #define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* The sequence conversion of ADC2 triggers input */
442 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 2A */
443 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 2B */
444 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 2C */
445 #define HPM_TRGM2_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) /* GPTMR2 counter synchronous input */
446 #define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) /* GPTMR2 channel 2 input */
447 #define HPM_TRGM2_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) /* GPTMR2 channel 3 input */
448 #define HPM_TRGM2_OUTPUT_SRC_DAC0_BUF_TRG (0x3AUL) /* DAC0 buffer mode starts to trigger */
449 #define HPM_TRGM2_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) /* DAC0 step mode starts to trigger */
450 #define HPM_TRGM2_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) /* DAC1 step mode starts to trigger */
451 #define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) /* Comparator 2 window mode input */
452 #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC input capture 0 */
453 #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC input capture 1 */
454 #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG8 (0x40UL) /* SDM triggers input 8 */
455 #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG9 (0x41UL) /* SDM triggers input 9 */
456 #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG10 (0x42UL) /* SDM triggers input 10 */
457 #define HPM_TRGM2_OUTPUT_SRC_SDM_TRG11 (0x43UL) /* SDM triggers input 11 */
458 
459 /* trgm3_output mux definitions */
460 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) /* TRGM3 Output 0 (to IO) */
461 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) /* TRGM3 Output 1 (to IO) */
462 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) /* TRGM3 Output 2 (to IO) */
463 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) /* TRGM3 Output 3 (to IO) */
464 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) /* TRGM3 Output 4 (to IO) */
465 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) /* TRGM3 Output 5 (to IO) */
466 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) /* TRGM3 Output 6 (to IO) */
467 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) /* TRGM3 Output 7 (to IO) */
468 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) /* TRGM3 Output 8 (to IO) */
469 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) /* TRGM3 Output 9 (to IO) */
470 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) /* TRGM3 Output 10 (to IO) */
471 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) /* TRGM3 Output 11 (to IO) */
472 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) /* TRGM3 Output X0 (to another TRGM) */
473 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) /* TRGM3 Output X1 (to another TRGM) */
474 #define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) /* PWM timer 3 counter synchronously triggers input */
475 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) /* the input value for PWM timer 3 forces control */
476 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) /* the synchronous input for PWM timer 3 forces control */
477 #define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) /* PWM timer 3 Shadow register to activate trigger input */
478 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) /* PWM timer 3 Fault protection input 0 */
479 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) /* PWM timer 3 Fault protection input 1 */
480 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) /* PWM timer 3 Fault protection input 2 */
481 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) /* PWM timer 3 Fault protection input 3 */
482 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) /* PWM timer 3 capture input 8 */
483 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) /* PWM timer 3 capture input 9 */
484 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) /* PWM timer 3 capture input 10 */
485 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) /* PWM timer 3 capture input 11 */
486 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) /* PWM timer 3 capture input 12 */
487 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) /* PWM timer 3 capture input 13 */
488 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) /* PWM timer 3 capture input 14 */
489 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) /* PWM timer 3 capture input 15 */
490 #define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) /* QEI3 input of phase A */
491 #define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) /* QEI3 input of phase B */
492 #define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) /* QEI3 input of phase Z */
493 #define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) /* QEI3 input of phase H */
494 #define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) /* QEI3 Pause input */
495 #define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) /* QEI3 Snap input */
496 #define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) /* HALL3 input of phase U */
497 #define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) /* HALL3 input of phase V */
498 #define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) /* HALL3 input of phase W */
499 #define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) /* HALL3 Snap input */
500 #define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* The sequence conversion of ADC0 triggers input */
501 #define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* The sequence conversion of ADC1 triggers input */
502 #define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* The sequence conversion of ADC2 triggers input */
503 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 3A */
504 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 3B */
505 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 3C */
506 #define HPM_TRGM3_OUTPUT_SRC_GPTMR3_SYNCI (0x37UL) /* GPTMR3 counter synchronous input */
507 #define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN2 (0x38UL) /* GPTMR3 channel 2 input */
508 #define HPM_TRGM3_OUTPUT_SRC_GPTMR3_IN3 (0x39UL) /* GPTMR3 channel 3 input */
509 #define HPM_TRGM3_OUTPUT_SRC_DAC1_BUF_TRG (0x3AUL) /* DAC1 buffer mode starts to trigger */
510 #define HPM_TRGM3_OUTPUT_SRC_DAC0_STP_TRG (0x3BUL) /* DAC0 step mode starts to trigger */
511 #define HPM_TRGM3_OUTPUT_SRC_DAC1_STP_TRG (0x3CUL) /* DAC1 step mode starts to trigger */
512 #define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) /* Comparator 3 window mode input */
513 #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC input capture 0 */
514 #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC input capture 1 */
515 #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG12 (0x40UL) /* SDM triggers input 12 */
516 #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG13 (0x41UL) /* SDM triggers input 13 */
517 #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG14 (0x42UL) /* SDM triggers input 14 */
518 #define HPM_TRGM3_OUTPUT_SRC_SDFM_TRG15 (0x43UL) /* SDM triggers input 15 */
519 
520 /* trgm0_filter mux definitions */
521 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) /* PWM timer 0 capture Input 0 */
522 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) /* PWM timer 0 capture Input 1 */
523 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) /* PWM timer 0 capture Input 2 */
524 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) /* PWM timer 0 capture Input 3 */
525 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) /* PWM timer 0 capture Input 4 */
526 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) /* PWM timer 0 capture Input 5 */
527 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) /* PWM timer 0 capture Input 6 */
528 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) /* PWM timer 0 capture Input 7 */
529 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) /* TRGM0 iutput 0 */
530 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) /* TRGM0 iutput 1 */
531 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) /* TRGM0 iutput 2 */
532 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) /* TRGM0 iutput 3 */
533 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) /* TRGM0 iutput 4 */
534 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) /* TRGM0 iutput 5 */
535 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) /* TRGM0 iutput 6 */
536 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) /* TRGM0 iutput 7 */
537 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) /* TRGM0 iutput 8 */
538 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) /* TRGM0 iutput 9 */
539 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) /* TRGM0 iutput 10 */
540 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) /* TRGM0 iutput 11 */
541 
542 /* trgm1_filter mux definitions */
543 #define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) /* PWM timer 1 capture Input 0 */
544 #define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) /* PWM timer 1 capture Input 1 */
545 #define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) /* PWM timer 1 capture Input 2 */
546 #define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) /* PWM timer 1 capture Input 3 */
547 #define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) /* PWM timer 1 capture Input 4 */
548 #define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) /* PWM timer 1 capture Input 5 */
549 #define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) /* PWM timer 1 capture Input 6 */
550 #define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) /* PWM timer 1 capture Input 7 */
551 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) /* TRGM1 iutput 0 */
552 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) /* TRGM1 iutput 1 */
553 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) /* TRGM1 iutput 2 */
554 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) /* TRGM1 iutput 3 */
555 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) /* TRGM1 iutput 4 */
556 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) /* TRGM1 iutput 5 */
557 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) /* TRGM1 iutput 6 */
558 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) /* TRGM1 iutput 7 */
559 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) /* TRGM1 iutput 8 */
560 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) /* TRGM1 iutput 9 */
561 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) /* TRGM1 iutput 10 */
562 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) /* TRGM1 iutput 11 */
563 
564 /* trgm2_filter mux definitions */
565 #define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) /* PWM timer 2 capture Input 0 */
566 #define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) /* PWM timer 2 capture Input 1 */
567 #define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) /* PWM timer 2 capture Input 2 */
568 #define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) /* PWM timer 2 capture Input 3 */
569 #define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) /* PWM timer 2 capture Input 4 */
570 #define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) /* PWM timer 2 capture Input 5 */
571 #define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) /* PWM timer 2 capture Input 6 */
572 #define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) /* PWM timer 2 capture Input 7 */
573 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) /* TRGM2 iutput 0 */
574 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) /* TRGM2 iutput 1 */
575 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) /* TRGM2 iutput 2 */
576 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) /* TRGM2 iutput 3 */
577 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) /* TRGM2 iutput 4 */
578 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) /* TRGM2 iutput 5 */
579 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) /* TRGM2 iutput 6 */
580 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) /* TRGM2 iutput 7 */
581 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) /* TRGM2 iutput 8 */
582 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) /* TRGM2 iutput 9 */
583 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) /* TRGM2 iutput 10 */
584 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) /* TRGM2 iutput 11 */
585 
586 /* trgm3_filter mux definitions */
587 #define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) /* PWM timer 3 capture Input 0 */
588 #define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) /* PWM timer 3 capture Input 1 */
589 #define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) /* PWM timer 3 capture Input 2 */
590 #define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) /* PWM timer 3 capture Input 3 */
591 #define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) /* PWM timer 3 capture Input 4 */
592 #define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) /* PWM timer 3 capture Input 5 */
593 #define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) /* PWM timer 3 capture Input 6 */
594 #define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) /* PWM timer 3 capture Input 7 */
595 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) /* TRGM3 iutput 0 */
596 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) /* TRGM3 iutput 1 */
597 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) /* TRGM3 iutput 2 */
598 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) /* TRGM3 iutput 3 */
599 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) /* TRGM3 iutput 4 */
600 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) /* TRGM3 iutput 5 */
601 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) /* TRGM3 iutput 6 */
602 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) /* TRGM3 iutput 7 */
603 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) /* TRGM3 iutput 8 */
604 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) /* TRGM3 iutput 9 */
605 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) /* TRGM3 iutput 10 */
606 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) /* TRGM3 iutput 11 */
607 
608 /* trgm0_dma mux definitions */
609 #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) /* The capture input or matches output of PWM timer 0 comparator 0 */
610 #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) /* The capture input or matches output of PWM timer 0 comparator 1 */
611 #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) /* The capture input or matches output of PWM timer 0 comparator 2 */
612 #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) /* The capture input or matches output of PWM timer 0 comparator 3 */
613 #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) /* The capture input or matches output of PWM timer 0 comparator 4 */
614 #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) /* The capture input or matches output of PWM timer 0 comparator 5 */
615 #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) /* The capture input or matches output of PWM timer 0 comparator 6 */
616 #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) /* The capture input or matches output of PWM timer 0 comparator 7 */
617 #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) /* The capture input or matches output of PWM timer 0 comparator 8 */
618 #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) /* The capture input or matches output of PWM timer 0 comparator 9 */
619 #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) /* The capture input or matches output of PWM timer 0 comparator 10 */
620 #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) /* The capture input or matches output of PWM timer 0 comparator 11 */
621 #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) /* The capture input or matches output of PWM timer 0 comparator 12 */
622 #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) /* The capture input or matches output of PWM timer 0 comparator 13 */
623 #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) /* The capture input or matches output of PWM timer 0 comparator 14 */
624 #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) /* The capture input or matches output of PWM timer 0 comparator 15 */
625 #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) /* The capture input or matches output of PWM timer 0 comparator 16 */
626 #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) /* The capture input or matches output of PWM timer 0 comparator 17 */
627 #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) /* The capture input or matches output of PWM timer 0 comparator 18 */
628 #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) /* The capture input or matches output of PWM timer 0 comparator 19 */
629 #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) /* The capture input or matches output of PWM timer 0 comparator 20 */
630 #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) /* The capture input or matches output of PWM timer 0 comparator 21 */
631 #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) /* The capture input or matches output of PWM timer 0 comparator 22 */
632 #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) /* The capture input or matches output of PWM timer 0 comparator 23 */
633 #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) /* PWM timer 0 counter reload */
634 #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) /* PWM timer 0 half cycle reload */
635 #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) /* PWM timer 0 extended counter reload */
636 #define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) /* DMA request for QEI0 */
637 #define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) /* DMA request for HALL0 */
638 
639 /* trgm1_dma mux definitions */
640 #define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) /* The capture input or matches output of PWM timer 1 comparator 0 */
641 #define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) /* The capture input or matches output of PWM timer 1 comparator 1 */
642 #define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) /* The capture input or matches output of PWM timer 1 comparator 2 */
643 #define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) /* The capture input or matches output of PWM timer 1 comparator 3 */
644 #define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) /* The capture input or matches output of PWM timer 1 comparator 4 */
645 #define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) /* The capture input or matches output of PWM timer 1 comparator 5 */
646 #define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) /* The capture input or matches output of PWM timer 1 comparator 6 */
647 #define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) /* The capture input or matches output of PWM timer 1 comparator 7 */
648 #define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) /* The capture input or matches output of PWM timer 1 comparator 8 */
649 #define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) /* The capture input or matches output of PWM timer 1 comparator 9 */
650 #define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) /* The capture input or matches output of PWM timer 1 comparator 10 */
651 #define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) /* The capture input or matches output of PWM timer 1 comparator 11 */
652 #define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) /* The capture input or matches output of PWM timer 1 comparator 12 */
653 #define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) /* The capture input or matches output of PWM timer 1 comparator 13 */
654 #define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) /* The capture input or matches output of PWM timer 1 comparator 14 */
655 #define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) /* The capture input or matches output of PWM timer 1 comparator 15 */
656 #define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) /* The capture input or matches output of PWM timer 1 comparator 16 */
657 #define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) /* The capture input or matches output of PWM timer 1 comparator 17 */
658 #define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) /* The capture input or matches output of PWM timer 1 comparator 18 */
659 #define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) /* The capture input or matches output of PWM timer 1 comparator 19 */
660 #define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) /* The capture input or matches output of PWM timer 1 comparator 20 */
661 #define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) /* The capture input or matches output of PWM timer 1 comparator 21 */
662 #define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) /* The capture input or matches output of PWM timer 1 comparator 22 */
663 #define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) /* The capture input or matches output of PWM timer 1 comparator 23 */
664 #define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) /* PWM timer 1 counter reload */
665 #define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) /* PWM timer 1 half cycle reload */
666 #define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) /* PWM timer 1 extended counter reload */
667 #define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) /* DMA request for QEI1 */
668 #define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) /* DMA request for HALL1 */
669 
670 /* trgm2_dma mux definitions */
671 #define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) /* The capture input or matches output of PWM timer 2 comparator 0 */
672 #define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) /* The capture input or matches output of PWM timer 2 comparator 1 */
673 #define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) /* The capture input or matches output of PWM timer 2 comparator 2 */
674 #define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) /* The capture input or matches output of PWM timer 2 comparator 3 */
675 #define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) /* The capture input or matches output of PWM timer 2 comparator 4 */
676 #define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) /* The capture input or matches output of PWM timer 2 comparator 5 */
677 #define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) /* The capture input or matches output of PWM timer 2 comparator 6 */
678 #define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) /* The capture input or matches output of PWM timer 2 comparator 7 */
679 #define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) /* The capture input or matches output of PWM timer 2 comparator 8 */
680 #define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) /* The capture input or matches output of PWM timer 2 comparator 9 */
681 #define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) /* The capture input or matches output of PWM timer 2 comparator 10 */
682 #define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) /* The capture input or matches output of PWM timer 2 comparator 11 */
683 #define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) /* The capture input or matches output of PWM timer 2 comparator 12 */
684 #define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) /* The capture input or matches output of PWM timer 2 comparator 13 */
685 #define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) /* The capture input or matches output of PWM timer 2 comparator 14 */
686 #define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) /* The capture input or matches output of PWM timer 2 comparator 15 */
687 #define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) /* The capture input or matches output of PWM timer 2 comparator 16 */
688 #define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) /* The capture input or matches output of PWM timer 2 comparator 17 */
689 #define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) /* The capture input or matches output of PWM timer 2 comparator 18 */
690 #define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) /* The capture input or matches output of PWM timer 2 comparator 19 */
691 #define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) /* The capture input or matches output of PWM timer 2 comparator 20 */
692 #define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) /* The capture input or matches output of PWM timer 2 comparator 21 */
693 #define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) /* The capture input or matches output of PWM timer 2 comparator 22 */
694 #define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) /* The capture input or matches output of PWM timer 2 comparator 23 */
695 #define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) /* PWM timer 2 counter reload */
696 #define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) /* PWM timer 2 half cycle reload */
697 #define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) /* PWM timer 2 extended counter reload */
698 #define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) /* DMA request for QEI2 */
699 #define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) /* DMA request for HALL2 */
700 
701 /* trgm3_dma mux definitions */
702 #define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) /* The capture input or matches output of PWM timer 3 comparator 0 */
703 #define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) /* The capture input or matches output of PWM timer 3 comparator 1 */
704 #define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) /* The capture input or matches output of PWM timer 3 comparator 2 */
705 #define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) /* The capture input or matches output of PWM timer 3 comparator 3 */
706 #define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) /* The capture input or matches output of PWM timer 3 comparator 4 */
707 #define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) /* The capture input or matches output of PWM timer 3 comparator 5 */
708 #define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) /* The capture input or matches output of PWM timer 3 comparator 6 */
709 #define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) /* The capture input or matches output of PWM timer 3 comparator 7 */
710 #define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) /* The capture input or matches output of PWM timer 3 comparator 8 */
711 #define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) /* The capture input or matches output of PWM timer 3 comparator 9 */
712 #define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) /* The capture input or matches output of PWM timer 3 comparator 10 */
713 #define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) /* The capture input or matches output of PWM timer 3 comparator 11 */
714 #define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) /* The capture input or matches output of PWM timer 3 comparator 12 */
715 #define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) /* The capture input or matches output of PWM timer 3 comparator 13 */
716 #define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) /* The capture input or matches output of PWM timer 3 comparator 14 */
717 #define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) /* The capture input or matches output of PWM timer 3 comparator 15 */
718 #define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) /* The capture input or matches output of PWM timer 3 comparator 16 */
719 #define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) /* The capture input or matches output of PWM timer 3 comparator 17 */
720 #define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) /* The capture input or matches output of PWM timer 3 comparator 18 */
721 #define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) /* The capture input or matches output of PWM timer 3 comparator 19 */
722 #define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) /* The capture input or matches output of PWM timer 3 comparator 20 */
723 #define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) /* The capture input or matches output of PWM timer 3 comparator 21 */
724 #define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) /* The capture input or matches output of PWM timer 3 comparator 22 */
725 #define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) /* The capture input or matches output of PWM timer 3 comparator 23 */
726 #define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) /* PWM timer 3 counter reload */
727 #define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) /* PWM timer 3 half cycle reload */
728 #define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) /* PWM timer 3 extended counter reload */
729 #define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) /* DMA request for QEI3 */
730 #define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) /* DMA request for HALL3 */
731 
732 
733 
734 #endif /* HPM_TRGMMUX_SRC_H */