HPM SDK
HPMicro Software Development Kit
hpm_sysctl_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYSCTL_H
10 #define HPM_SYSCTL_H
11 
12 typedef struct {
13  __RW uint32_t RESOURCE[322]; /* 0x0 - 0x504: Resource control register for cpu0_core */
14  __R uint8_t RESERVED0[760]; /* 0x508 - 0x7FF: Reserved */
15  struct {
16  __RW uint32_t VALUE; /* 0x800: Group setting */
17  __RW uint32_t SET; /* 0x804: Group setting */
18  __RW uint32_t CLEAR; /* 0x808: Group setting */
19  __RW uint32_t TOGGLE; /* 0x80C: Group setting */
20  } GROUP0[3];
21  __R uint8_t RESERVED1[16]; /* 0x830 - 0x83F: Reserved */
22  struct {
23  __RW uint32_t VALUE; /* 0x840: Group setting */
24  __RW uint32_t SET; /* 0x844: Group setting */
25  __RW uint32_t CLEAR; /* 0x848: Group setting */
26  __RW uint32_t TOGGLE; /* 0x84C: Group setting */
27  } GROUP1[3];
28  __R uint8_t RESERVED2[144]; /* 0x870 - 0x8FF: Reserved */
29  struct {
30  __RW uint32_t VALUE; /* 0x900: Affiliate of Group */
31  __RW uint32_t SET; /* 0x904: Affiliate of Group */
32  __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */
33  __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */
34  } AFFILIATE[2];
35  struct {
36  __RW uint32_t VALUE; /* 0x920: Retention Control */
37  __RW uint32_t SET; /* 0x924: Retention Control */
38  __RW uint32_t CLEAR; /* 0x928: Retention Control */
39  __RW uint32_t TOGGLE; /* 0x92C: Retention Control */
40  } RETENTION[2];
41  __R uint8_t RESERVED3[1728]; /* 0x940 - 0xFFF: Reserved */
42  struct {
43  __RW uint32_t STATUS; /* 0x1000: Power Setting */
44  __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */
45  __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */
46  __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */
47  } POWER[2];
48  __R uint8_t RESERVED4[992]; /* 0x1020 - 0x13FF: Reserved */
49  struct {
50  __RW uint32_t CONTROL; /* 0x1400: Reset Setting */
51  __RW uint32_t CONFIG; /* 0x1404: Reset Setting */
52  __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */
53  __RW uint32_t COUNTER; /* 0x140C: Reset Setting */
54  } RESET[3];
55  __R uint8_t RESERVED5[976]; /* 0x1430 - 0x17FF: Reserved */
56  __RW uint32_t CLOCK_CPU[1]; /* 0x1800: Clock setting */
57  __RW uint32_t CLOCK[39]; /* 0x1804 - 0x189C: Clock setting */
58  __R uint8_t RESERVED6[864]; /* 0x18A0 - 0x1BFF: Reserved */
59  __RW uint32_t ADCCLK[3]; /* 0x1C00 - 0x1C08: Clock setting */
60  __RW uint32_t DACCLK[2]; /* 0x1C0C - 0x1C10: Clock setting */
61  __R uint8_t RESERVED7[1004]; /* 0x1C14 - 0x1FFF: Reserved */
62  __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */
63  __R uint8_t RESERVED8[1020]; /* 0x2004 - 0x23FF: Reserved */
64  struct {
65  __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */
66  __R uint32_t CURRENT; /* 0x2404: Clock measure result */
67  __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */
68  __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */
69  __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */
70  } MONITOR[4];
71  __R uint8_t RESERVED9[896]; /* 0x2480 - 0x27FF: Reserved */
72  struct {
73  __RW uint32_t LP; /* 0x2800: CPU0 LP control */
74  __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */
75  __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */
76  __R uint32_t WAKEUP_STATUS[4]; /* 0x2840 - 0x284C: CPU0 wakeup IRQ status */
77  __R uint8_t RESERVED0[48]; /* 0x2850 - 0x287F: Reserved */
78  __RW uint32_t WAKEUP_ENABLE[4]; /* 0x2880 - 0x288C: CPU0 wakeup IRQ enable */
79  __R uint8_t RESERVED1[880]; /* 0x2890 - 0x2BFF: Reserved */
80  } CPU[2];
81 } SYSCTL_Type;
82 
83 
84 /* Bitfield definition for register array: RESOURCE */
85 /*
86  * GLB_BUSY (RO)
87  *
88  * global busy
89  * 0: no changes pending to any nodes
90  * 1: any of nodes is changing status
91  */
92 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL)
93 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U)
94 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT)
95 
96 /*
97  * LOC_BUSY (RO)
98  *
99  * local busy
100  * 0: no change is pending for current node
101  * 1: current node is changing status
102  */
103 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL)
104 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U)
105 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT)
106 
107 /*
108  * MODE (RW)
109  *
110  * resource work mode
111  * 0:auto turn on and off as system required(recommended)
112  * 1:always on
113  * 2:always off
114  * 3:reserved
115  */
116 #define SYSCTL_RESOURCE_MODE_MASK (0x3U)
117 #define SYSCTL_RESOURCE_MODE_SHIFT (0U)
118 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK)
119 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT)
120 
121 /* Bitfield definition for register of struct array GROUP0: VALUE */
122 /*
123  * LINK (RW)
124  *
125  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
126  * 0: peripheral is not needed
127  * 1: periphera is needed
128  */
129 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL)
130 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U)
131 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK)
132 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT)
133 
134 /* Bitfield definition for register of struct array GROUP0: SET */
135 /*
136  * LINK (RW)
137  *
138  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
139  * 0: no effect
140  * 1: add periphera into this group，periphera is needed
141  */
142 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL)
143 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U)
144 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK)
145 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT)
146 
147 /* Bitfield definition for register of struct array GROUP0: CLEAR */
148 /*
149  * LINK (RW)
150  *
151  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
152  * 0: no effect
153  * 1: delete periphera in this group，periphera is not needed
154  */
155 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL)
156 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U)
157 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK)
158 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT)
159 
160 /* Bitfield definition for register of struct array GROUP0: TOGGLE */
161 /*
162  * LINK (RW)
163  *
164  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
165  * 0: no effect
166  * 1: toggle the result that whether periphera is needed before
167  */
168 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
169 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U)
170 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK)
171 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT)
172 
173 /* Bitfield definition for register of struct array GROUP1: VALUE */
174 /*
175  * LINK (RW)
176  *
177  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
178  * 0: peripheral is not needed
179  * 1: periphera is needed
180  */
181 #define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL)
182 #define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U)
183 #define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK)
184 #define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT)
185 
186 /* Bitfield definition for register of struct array GROUP1: SET */
187 /*
188  * LINK (RW)
189  *
190  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
191  * 0: no effect
192  * 1: add periphera into this group，periphera is needed
193  */
194 #define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL)
195 #define SYSCTL_GROUP1_SET_LINK_SHIFT (0U)
196 #define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK)
197 #define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT)
198 
199 /* Bitfield definition for register of struct array GROUP1: CLEAR */
200 /*
201  * LINK (RW)
202  *
203  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
204  * 0: no effect
205  * 1: delete periphera in this group，periphera is not needed
206  */
207 #define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL)
208 #define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U)
209 #define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK)
210 #define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT)
211 
212 /* Bitfield definition for register of struct array GROUP1: TOGGLE */
213 /*
214  * LINK (RW)
215  *
216  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
217  * 0: no effect
218  * 1: toggle the result that whether periphera is needed before
219  */
220 #define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
221 #define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U)
222 #define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK)
223 #define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT)
224 
225 /* Bitfield definition for register of struct array AFFILIATE: VALUE */
226 /*
227  * LINK (RW)
228  *
229  * Affiliate groups of cpu0, each bit represents a group
230  * bit0: cpu0 depends on group0
231  * bit1: cpu0 depends on group1
232  * bit2: cpu0 depends on group2
233  * bit3: cpu0 depends on group3
234  */
235 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU)
236 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U)
237 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK)
238 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT)
239 
240 /* Bitfield definition for register of struct array AFFILIATE: SET */
241 /*
242  * LINK (RW)
243  *
244  * Affiliate groups of cpu0，each bit represents a group
245  * 0: no effect
246  * 1: the group is assigned to CPU0
247  */
248 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU)
249 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U)
250 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK)
251 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT)
252 
253 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */
254 /*
255  * LINK (RW)
256  *
257  * Affiliate groups of cpu0, each bit represents a group
258  * 0: no effect
259  * 1: the group is not assigned to CPU0
260  */
261 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU)
262 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U)
263 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK)
264 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT)
265 
266 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */
267 /*
268  * LINK (RW)
269  *
270  * Affiliate groups of cpu0, each bit represents a group
271  * 0: no effect
272  * 1: toggle the result that whether the group is assigned to CPU0 before
273  */
274 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU)
275 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U)
276 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK)
277 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT)
278 
279 /* Bitfield definition for register of struct array RETENTION: VALUE */
280 /*
281  * LINK (RW)
282  *
283  * retention setting while CPU0 enter stop mode, each bit represents a resource
284  * bit00: soc_mem is kept on while cpu0 stop
285  * bit01: soc_ctx is kept on while cpu0 stop
286  * bit02: cpu0_mem is kept on while cpu0 stop
287  * bit03: cpu0_ctx is kept on while cpu0 stop
288  * bit04: cpu1_mem is kept on while cpu0 stop
289  * bit05: cpu1_ctx is kept on while cpu0 stop
290  * bit06: xtal_hold is kept on while cpu0 stop
291  * bit07: pll0_hold is kept on while cpu0 stop
292  * bit08: pll1_hold is kept on while cpu0 stop
293  * bit09: pll2_hold is kept on while cpu0 stop
294  */
295 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x3FFU)
296 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U)
297 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK)
298 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT)
299 
300 /* Bitfield definition for register of struct array RETENTION: SET */
301 /*
302  * LINK (RW)
303  *
304  * retention setting while CPU0 enter stop mode, each bit represents a resource
305  * 0: no effect
306  * 1: keep
307  */
308 #define SYSCTL_RETENTION_SET_LINK_MASK (0x3FFU)
309 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U)
310 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK)
311 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT)
312 
313 /* Bitfield definition for register of struct array RETENTION: CLEAR */
314 /*
315  * LINK (RW)
316  *
317  * retention setting while CPU0 enter stop mode, each bit represents a resource
318  * 0: no effect
319  * 1: no keep
320  */
321 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x3FFU)
322 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U)
323 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK)
324 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT)
325 
326 /* Bitfield definition for register of struct array RETENTION: TOGGLE */
327 /*
328  * LINK (RW)
329  *
330  * retention setting while CPU0 enter stop mode, each bit represents a resource
331  * 0: no effect
332  * 1: toggle the result that whether the resource is kept on while CPU0 stop before
333  */
334 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x3FFU)
335 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U)
336 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK)
337 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT)
338 
339 /* Bitfield definition for register of struct array POWER: STATUS */
340 /*
341  * FLAG (RW)
342  *
343  * flag represents power cycle happened from last clear of this bit
344  * 0: power domain did not edurance power cycle since last clear of this bit
345  * 1: power domain enduranced power cycle since last clear of this bit
346  */
347 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL)
348 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U)
349 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK)
350 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT)
351 
352 /*
353  * FLAG_WAKE (RW)
354  *
355  * flag represents wakeup power cycle happened from last clear of this bit
356  * 0: power domain did not edurance wakeup power cycle since last clear of this bit
357  * 1: power domain enduranced wakeup power cycle since last clear of this bit
358  */
359 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL)
360 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U)
361 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK)
362 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT)
363 
364 /*
365  * LF_DISABLE (RO)
366  *
367  * low fanout power switch disable
368  * 0: low fanout power switches are turned on
369  * 1: low fanout power switches are truned off
370  */
371 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U)
372 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U)
373 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT)
374 
375 /*
376  * LF_ACK (RO)
377  *
378  * low fanout power switch feedback
379  * 0: low fanout power switches are turned on
380  * 1: low fanout power switches are truned off
381  */
382 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U)
383 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U)
384 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT)
385 
386 /* Bitfield definition for register of struct array POWER: LF_WAIT */
387 /*
388  * WAIT (RW)
389  *
390  * wait time for low fan out power switch turn on, default value is 255
391  * 0: 0 clock cycle
392  * 1: 1 clock cycles
393  * . . .
394  * clock cycles count on 24MHz
395  */
396 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL)
397 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U)
398 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK)
399 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
400 
401 /* Bitfield definition for register of struct array POWER: OFF_WAIT */
402 /*
403  * WAIT (RW)
404  *
405  * wait time for power switch turn off, default value is 15
406  * 0: 0 clock cycle
407  * 1: 1 clock cycles
408  * . . .
409  * clock cycles count on 24MHz
410  */
411 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL)
412 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U)
413 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK)
414 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
415 
416 /* Bitfield definition for register of struct array RESET: CONTROL */
417 /*
418  * FLAG (RW)
419  *
420  * flag represents reset happened from last clear of this bit
421  * 0: domain did not edurance reset cycle since last clear of this bit
422  * 1: domain enduranced reset cycle since last clear of this bit
423  */
424 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL)
425 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U)
426 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK)
427 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT)
428 
429 /*
430  * FLAG_WAKE (RW)
431  *
432  * flag represents wakeup reset happened from last clear of this bit
433  * 0: domain did not edurance wakeup reset cycle since last clear of this bit
434  * 1: domain enduranced wakeup reset cycle since last clear of this bit
435  */
436 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL)
437 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U)
438 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK)
439 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT)
440 
441 /*
442  * HOLD (RW)
443  *
444  * perform reset and hold in reset, until ths bit cleared by software
445  * 0: reset is released for function
446  * 1: reset is assert and hold
447  */
448 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U)
449 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U)
450 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK)
451 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT)
452 
453 /*
454  * RESET (RW)
455  *
456  * perform reset and release imediately
457  * 0: reset is released
458  * 1 reset is asserted and will release automatically
459  */
460 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U)
461 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U)
462 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK)
463 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT)
464 
465 /* Bitfield definition for register of struct array RESET: CONFIG */
466 /*
467  * PRE_WAIT (RW)
468  *
469  * wait cycle numbers before assert reset
470  * 0: wait 0 cycle
471  * 1: wait 1 cycles
472  * . . .
473  * Note, clock cycle is base on 24M
474  */
475 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL)
476 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U)
477 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK)
478 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
479 
480 /*
481  * RSTCLK_NUM (RW)
482  *
483  * reset clock number(must be even number)
484  * 0: 0 cycle
485  * 1: 0 cycles
486  * 2: 2 cycles
487  * 3: 2 cycles
488  * . . .
489  * Note, clock cycle is base on 24M
490  */
491 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U)
492 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U)
493 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK)
494 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
495 
496 /*
497  * POST_WAIT (RW)
498  *
499  * time guard band for reset release
500  * 0: wait 0 cycle
501  * 1: wait 1 cycles
502  * . . .
503  * Note, clock cycle is base on 24M
504  */
505 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU)
506 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U)
507 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK)
508 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
509 
510 /* Bitfield definition for register of struct array RESET: COUNTER */
511 /*
512  * COUNTER (RW)
513  *
514  * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset
515  * 0: wait 0 cycle
516  * 1: wait 1 cycles
517  * . . .
518  * Note, clock cycle is base on 24M
519  */
520 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL)
521 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U)
522 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK)
523 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
524 
525 /* Bitfield definition for register array: CLOCK_CPU */
526 /*
527  * GLB_BUSY (RO)
528  *
529  * global busy
530  * 0: no changes pending to any clock
531  * 1: any of nodes is changing status
532  */
533 #define SYSCTL_CLOCK_CPU_GLB_BUSY_MASK (0x80000000UL)
534 #define SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT (31U)
535 #define SYSCTL_CLOCK_CPU_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_GLB_BUSY_MASK) >> SYSCTL_CLOCK_CPU_GLB_BUSY_SHIFT)
536 
537 /*
538  * LOC_BUSY (RO)
539  *
540  * local busy
541  * 0: a change is pending for current node
542  * 1: current node is changing status
543  */
544 #define SYSCTL_CLOCK_CPU_LOC_BUSY_MASK (0x40000000UL)
545 #define SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT (30U)
546 #define SYSCTL_CLOCK_CPU_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_LOC_BUSY_MASK) >> SYSCTL_CLOCK_CPU_LOC_BUSY_SHIFT)
547 
548 /*
549  * PRESERVE (RW)
550  *
551  * preserve function against global select
552  * 0: select global clock setting
553  * 1: not select global clock setting
554  */
555 #define SYSCTL_CLOCK_CPU_PRESERVE_MASK (0x10000000UL)
556 #define SYSCTL_CLOCK_CPU_PRESERVE_SHIFT (28U)
557 #define SYSCTL_CLOCK_CPU_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_PRESERVE_SHIFT) & SYSCTL_CLOCK_CPU_PRESERVE_MASK)
558 #define SYSCTL_CLOCK_CPU_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_PRESERVE_MASK) >> SYSCTL_CLOCK_CPU_PRESERVE_SHIFT)
559 
560 /*
561  * SUB1_DIV (RW)
562  *
563  * ahb bus divider, the bus clock is generated by cpu_clock/div
564  * 0: divider by 1
565  * 1: divider by 2
566  * …
567  */
568 #define SYSCTL_CLOCK_CPU_SUB1_DIV_MASK (0xF00000UL)
569 #define SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT (20U)
570 #define SYSCTL_CLOCK_CPU_SUB1_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK)
571 #define SYSCTL_CLOCK_CPU_SUB1_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB1_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB1_DIV_SHIFT)
572 
573 /*
574  * SUB0_DIV (RW)
575  *
576  * axi bus divider, the bus clock is generated by cpu_clock/div
577  * 0: divider by 1
578  * 1: divider by 2
579  * …
580  */
581 #define SYSCTL_CLOCK_CPU_SUB0_DIV_MASK (0xF0000UL)
582 #define SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT (16U)
583 #define SYSCTL_CLOCK_CPU_SUB0_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK)
584 #define SYSCTL_CLOCK_CPU_SUB0_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_SUB0_DIV_MASK) >> SYSCTL_CLOCK_CPU_SUB0_DIV_SHIFT)
585 
586 /*
587  * MUX (RW)
588  *
589  * current mux in clock component
590  * 0:osc0_clk0
591  * 1:pll0_clk0
592  * 2:pll0_clk1
593  * 3:pll0_clk2
594  * 4:pll1_clk0
595  * 5:pll1_clk1
596  * 6:pll2_clk0
597  * 7:pll2_clk1
598  */
599 #define SYSCTL_CLOCK_CPU_MUX_MASK (0x700U)
600 #define SYSCTL_CLOCK_CPU_MUX_SHIFT (8U)
601 #define SYSCTL_CLOCK_CPU_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_MUX_SHIFT) & SYSCTL_CLOCK_CPU_MUX_MASK)
602 #define SYSCTL_CLOCK_CPU_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_MUX_MASK) >> SYSCTL_CLOCK_CPU_MUX_SHIFT)
603 
604 /*
605  * DIV (RW)
606  *
607  * clock divider
608  * 0: divider by 1
609  * 1: divider by 2
610  * 2: divider by 3
611  * . . .
612  * 255: divider by 256
613  */
614 #define SYSCTL_CLOCK_CPU_DIV_MASK (0xFFU)
615 #define SYSCTL_CLOCK_CPU_DIV_SHIFT (0U)
616 #define SYSCTL_CLOCK_CPU_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_CPU_DIV_SHIFT) & SYSCTL_CLOCK_CPU_DIV_MASK)
617 #define SYSCTL_CLOCK_CPU_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_CPU_DIV_MASK) >> SYSCTL_CLOCK_CPU_DIV_SHIFT)
618 
619 /* Bitfield definition for register array: CLOCK */
620 /*
621  * GLB_BUSY (RO)
622  *
623  * global busy
624  * 0: no changes pending to any clock
625  * 1: any of nodes is changing status
626  */
627 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL)
628 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U)
629 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT)
630 
631 /*
632  * LOC_BUSY (RO)
633  *
634  * local busy
635  * 0: a change is pending for current node
636  * 1: current node is changing status
637  */
638 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL)
639 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U)
640 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT)
641 
642 /*
643  * PRESERVE (RW)
644  *
645  * preserve function against global select
646  * 0: select global clock setting
647  * 1: not select global clock setting
648  */
649 #define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL)
650 #define SYSCTL_CLOCK_PRESERVE_SHIFT (28U)
651 #define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK)
652 #define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT)
653 
654 /*
655  * MUX (RW)
656  *
657  * current mux in clock component
658  * 0:osc0_clk0
659  * 1:pll0_clk0
660  * 2:pll0_clk1
661  * 3:pll0_clk2
662  * 4:pll1_clk0
663  * 5:pll1_clk1
664  * 6:pll2_clk0
665  * 7:pll2_clk1
666  */
667 #define SYSCTL_CLOCK_MUX_MASK (0x700U)
668 #define SYSCTL_CLOCK_MUX_SHIFT (8U)
669 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK)
670 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT)
671 
672 /*
673  * DIV (RW)
674  *
675  * clock divider
676  * 0: divider by 1
677  * 1: divider by 2
678  * 2: divider by 3
679  * . . .
680  * 255: divider by 256
681  */
682 #define SYSCTL_CLOCK_DIV_MASK (0xFFU)
683 #define SYSCTL_CLOCK_DIV_SHIFT (0U)
684 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK)
685 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT)
686 
687 /* Bitfield definition for register array: ADCCLK */
688 /*
689  * GLB_BUSY (RO)
690  *
691  * global busy
692  * 0: no changes pending to any clock
693  * 1: any of nodes is changing status
694  */
695 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL)
696 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U)
697 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT)
698 
699 /*
700  * LOC_BUSY (RO)
701  *
702  * local busy
703  * 0: a change is pending for current node
704  * 1: current node is changing status
705  */
706 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL)
707 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U)
708 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT)
709 
710 /*
711  * PRESERVE (RW)
712  *
713  * preserve function against global select
714  * 0: select global clock setting
715  * 1: not select global clock setting
716  */
717 #define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL)
718 #define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U)
719 #define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK)
720 #define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT)
721 
722 /*
723  * MUX (RW)
724  *
725  * current mux
726  * 0: ana clock N
727  * 1: ahb clock
728  */
729 #define SYSCTL_ADCCLK_MUX_MASK (0x100U)
730 #define SYSCTL_ADCCLK_MUX_SHIFT (8U)
731 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK)
732 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT)
733 
734 /* Bitfield definition for register array: DACCLK */
735 /*
736  * GLB_BUSY (RO)
737  *
738  * global busy
739  * 0: no changes pending to any clock
740  * 1: any of nodes is changing status
741  */
742 #define SYSCTL_DACCLK_GLB_BUSY_MASK (0x80000000UL)
743 #define SYSCTL_DACCLK_GLB_BUSY_SHIFT (31U)
744 #define SYSCTL_DACCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_GLB_BUSY_MASK) >> SYSCTL_DACCLK_GLB_BUSY_SHIFT)
745 
746 /*
747  * LOC_BUSY (RO)
748  *
749  * local busy
750  * 0: a change is pending for current node
751  * 1: current node is changing status
752  */
753 #define SYSCTL_DACCLK_LOC_BUSY_MASK (0x40000000UL)
754 #define SYSCTL_DACCLK_LOC_BUSY_SHIFT (30U)
755 #define SYSCTL_DACCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_LOC_BUSY_MASK) >> SYSCTL_DACCLK_LOC_BUSY_SHIFT)
756 
757 /*
758  * PRESERVE (RW)
759  *
760  * preserve function against global select
761  * 0: select global clock setting
762  * 1: not select global clock setting
763  */
764 #define SYSCTL_DACCLK_PRESERVE_MASK (0x10000000UL)
765 #define SYSCTL_DACCLK_PRESERVE_SHIFT (28U)
766 #define SYSCTL_DACCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_PRESERVE_SHIFT) & SYSCTL_DACCLK_PRESERVE_MASK)
767 #define SYSCTL_DACCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_PRESERVE_MASK) >> SYSCTL_DACCLK_PRESERVE_SHIFT)
768 
769 /*
770  * MUX (RW)
771  *
772  * current mux
773  * 0: ana clock N
774  * 1: ahb clock
775  */
776 #define SYSCTL_DACCLK_MUX_MASK (0x100U)
777 #define SYSCTL_DACCLK_MUX_SHIFT (8U)
778 #define SYSCTL_DACCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_DACCLK_MUX_SHIFT) & SYSCTL_DACCLK_MUX_MASK)
779 #define SYSCTL_DACCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_DACCLK_MUX_MASK) >> SYSCTL_DACCLK_MUX_SHIFT)
780 
781 /* Bitfield definition for register: GLOBAL00 */
782 /*
783  * MUX (RW)
784  *
785  * global clock override request
786  * bit0: override to preset0
787  * bit1: override to preset1
788  * bit2: override to preset2
789  * bit3: override to preset3
790  */
791 #define SYSCTL_GLOBAL00_MUX_MASK (0xFU)
792 #define SYSCTL_GLOBAL00_MUX_SHIFT (0U)
793 #define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK)
794 #define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT)
795 
796 /* Bitfield definition for register of struct array MONITOR: CONTROL */
797 /*
798  * VALID (RW)
799  *
800  * result is ready for read
801  * 0: not ready
802  * 1: result is ready
803  */
804 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL)
805 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U)
806 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK)
807 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT)
808 
809 /*
810  * DIV_BUSY (RO)
811  *
812  * divider is applying new setting
813  */
814 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL)
815 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U)
816 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT)
817 
818 /*
819  * OUTEN (RW)
820  *
821  * enable clock output
822  */
823 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL)
824 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U)
825 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK)
826 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT)
827 
828 /*
829  * DIV (RW)
830  *
831  * output divider
832  */
833 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL)
834 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U)
835 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK)
836 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
837 
838 /*
839  * HIGH (RW)
840  *
841  * clock frequency higher than upper limit
842  */
843 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U)
844 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U)
845 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK)
846 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT)
847 
848 /*
849  * LOW (RW)
850  *
851  * clock frequency lower than lower limit
852  */
853 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U)
854 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U)
855 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK)
856 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT)
857 
858 /*
859  * START (RW)
860  *
861  * start measurement
862  */
863 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U)
864 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U)
865 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK)
866 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT)
867 
868 /*
869  * MODE (RW)
870  *
871  * work mode,
872  * 0: register value will be compared to measurement
873  * 1: upper and lower value will be recordered in register
874  */
875 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U)
876 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U)
877 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK)
878 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT)
879 
880 /*
881  * ACCURACY (RW)
882  *
883  * measurement accuracy,
884  * 0: resolution is 1kHz
885  * 1: resolution is 1Hz
886  */
887 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U)
888 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U)
889 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK)
890 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT)
891 
892 /*
893  * REFERENCE (RW)
894  *
895  * reference clock selection,
896  * 0: 32k
897  * 1: 24M
898  */
899 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U)
900 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U)
901 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK)
902 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT)
903 
904 /*
905  * SELECTION (RW)
906  *
907  * clock measurement selection
908  * 0: clk_32k
909  * 1: clk_irc24m
910  * 2: clk_xtal_24m
911  * 3: clk_usb0_phy
912  * 8: clk0_osc0
913  * 9: clk0_pll0
914  * 10: clk1_pll0
915  * 11: clk2_pll0
916  * 12: clk0_pll1
917  * 13: clk1_pll1
918  * 14: clk0_pll2
919  * 15: clk1_pll2
920  * 128: clk_top_cpu0
921  * 129: clk_top_mct0
922  * 130: clk_top_mct1
923  * 131: clk_top_xpi0
924  * 132: clk_top_tmr0
925  * 133: clk_top_tmr1
926  * 134: clk_top_tmr2
927  * 135: clk_top_tmr3
928  * 136: clk_top_urt0
929  * 137: clk_top_urt1
930  * 138: clk_top_urt2
931  * 139: clk_top_urt3
932  * 140: clk_top_urt4
933  * 141: clk_top_urt5
934  * 142: clk_top_urt6
935  * 143: clk_top_urt7
936  * 144: clk_top_i2c0
937  * 145: clk_top_i2c1
938  * 146: clk_top_i2c2
939  * 147: clk_top_i2c3
940  * 148: clk_top_spi0
941  * 149: clk_top_spi1
942  * 150: clk_top_spi2
943  * 151: clk_top_spi3
944  * 152: clk_top_can0
945  * 153: clk_top_can1
946  * 154: clk_top_can2
947  * 155: clk_top_can3
948  * 156: clk_top_ptpc
949  * 157: clk_top_ana0
950  * 158: clk_top_ana1
951  * 159: clk_top_ana2
952  * 160: clk_top_ana3
953  * 161: clk_top_ana4
954  * 162: clk_top_ref0
955  * 163: clk_top_ref1
956  * 164: clk_top_lin0
957  * 165: clk_top_lin1
958  * 166: clk_top_lin2
959  * 167: clk_top_lin3
960  */
961 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU)
962 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U)
963 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK)
964 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
965 
966 /* Bitfield definition for register of struct array MONITOR: CURRENT */
967 /*
968  * FREQUENCY (RO)
969  *
970  * self updating measure result
971  */
972 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL)
973 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U)
974 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT)
975 
976 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */
977 /*
978  * FREQUENCY (RW)
979  *
980  * lower frequency
981  */
982 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
983 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U)
984 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK)
985 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT)
986 
987 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */
988 /*
989  * FREQUENCY (RW)
990  *
991  * upper frequency
992  */
993 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
994 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U)
995 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK)
996 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT)
997 
998 /* Bitfield definition for register of struct array CPU: LP */
999 /*
1000  * WAKE_CNT (RW)
1001  *
1002  * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear
1003  */
1004 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL)
1005 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U)
1006 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK)
1007 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
1008 
1009 /*
1010  * HALT (RW)
1011  *
1012  * halt request for CPU0,
1013  * 0: CPU0 will start to execute after reset or receive wakeup request
1014  * 1: CPU0 will not start after reset, or wakeup after WFI
1015  */
1016 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL)
1017 #define SYSCTL_CPU_LP_HALT_SHIFT (16U)
1018 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK)
1019 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT)
1020 
1021 /*
1022  * WAKE (RO)
1023  *
1024  * CPU0 is waking up
1025  * 0: CPU0 wake up not asserted
1026  * 1: CPU0 wake up asserted
1027  */
1028 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U)
1029 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U)
1030 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT)
1031 
1032 /*
1033  * EXEC (RO)
1034  *
1035  * CPU0 is executing
1036  * 0: CPU0 is not executing
1037  * 1: CPU0 is executing
1038  */
1039 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U)
1040 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U)
1041 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT)
1042 
1043 /*
1044  * WAKE_FLAG (RW)
1045  *
1046  * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit
1047  * 0: CPU0 wakeup not happened
1048  * 1: CPU0 wake up happened
1049  */
1050 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U)
1051 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U)
1052 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK)
1053 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT)
1054 
1055 /*
1056  * SLEEP_FLAG (RW)
1057  *
1058  * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit
1059  * 0: CPU0 sleep not happened
1060  * 1: CPU0 sleep happened
1061  */
1062 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U)
1063 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U)
1064 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK)
1065 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT)
1066 
1067 /*
1068  * RESET_FLAG (RW)
1069  *
1070  * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit
1071  * 0: CPU0 reset not happened
1072  * 1: CPU0 reset happened
1073  */
1074 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U)
1075 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U)
1076 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK)
1077 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT)
1078 
1079 /*
1080  * MODE (RW)
1081  *
1082  * Low power mode, system behavior after WFI
1083  * 00: CPU clock stop after WFI
1084  * 01: System enter low power mode after WFI
1085  * 10: Keep running after WFI
1086  * 11: reserved
1087  */
1088 #define SYSCTL_CPU_LP_MODE_MASK (0x3U)
1089 #define SYSCTL_CPU_LP_MODE_SHIFT (0U)
1090 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK)
1091 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT)
1092 
1093 /* Bitfield definition for register of struct array CPU: LOCK */
1094 /*
1095  * GPR (RW)
1096  *
1097  * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset
1098  */
1099 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU)
1100 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U)
1101 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK)
1102 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT)
1103 
1104 /*
1105  * LOCK (RW)
1106  *
1107  * Lock bit for CPU_LOCK
1108  */
1109 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U)
1110 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U)
1111 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK)
1112 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT)
1113 
1114 /* Bitfield definition for register of struct array CPU: GPR0 */
1115 /*
1116  * GPR (RW)
1117  *
1118  * register for software to handle resume, can save resume address or status
1119  */
1120 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL)
1121 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U)
1122 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK)
1123 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT)
1124 
1125 /* Bitfield definition for register of struct array CPU: STATUS0 */
1126 /*
1127  * STATUS (RO)
1128  *
1129  * IRQ values
1130  */
1131 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL)
1132 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U)
1133 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT)
1134 
1135 /* Bitfield definition for register of struct array CPU: ENABLE0 */
1136 /*
1137  * ENABLE (RW)
1138  *
1139  * IRQ wakeup enable
1140  */
1141 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
1142 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U)
1143 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK)
1144 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT)
1145 
1146 
1147 
1148 /* RESOURCE register group index macro definition */
1149 #define SYSCTL_RESOURCE_CPU0 (0UL)
1150 #define SYSCTL_RESOURCE_CPX0 (1UL)
1151 #define SYSCTL_RESOURCE_CPU1 (8UL)
1152 #define SYSCTL_RESOURCE_CPX1 (9UL)
1153 #define SYSCTL_RESOURCE_POW_CPU0 (21UL)
1154 #define SYSCTL_RESOURCE_POW_CPU1 (22UL)
1155 #define SYSCTL_RESOURCE_RST_SOC (23UL)
1156 #define SYSCTL_RESOURCE_RST_CPU0 (24UL)
1157 #define SYSCTL_RESOURCE_RST_CPU1 (25UL)
1158 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL)
1159 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL)
1160 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL)
1161 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL)
1162 #define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL0 (36UL)
1163 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (37UL)
1164 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (38UL)
1165 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (39UL)
1166 #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL)
1167 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL)
1168 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL)
1169 #define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL)
1170 #define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL)
1171 #define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL)
1172 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL)
1173 #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL)
1174 #define SYSCTL_RESOURCE_CLK_TOP_MCT1 (66UL)
1175 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (67UL)
1176 #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (68UL)
1177 #define SYSCTL_RESOURCE_CLK_TOP_TMR1 (69UL)
1178 #define SYSCTL_RESOURCE_CLK_TOP_TMR2 (70UL)
1179 #define SYSCTL_RESOURCE_CLK_TOP_TMR3 (71UL)
1180 #define SYSCTL_RESOURCE_CLK_TOP_URT0 (72UL)
1181 #define SYSCTL_RESOURCE_CLK_TOP_URT1 (73UL)
1182 #define SYSCTL_RESOURCE_CLK_TOP_URT2 (74UL)
1183 #define SYSCTL_RESOURCE_CLK_TOP_URT3 (75UL)
1184 #define SYSCTL_RESOURCE_CLK_TOP_URT4 (76UL)
1185 #define SYSCTL_RESOURCE_CLK_TOP_URT5 (77UL)
1186 #define SYSCTL_RESOURCE_CLK_TOP_URT6 (78UL)
1187 #define SYSCTL_RESOURCE_CLK_TOP_URT7 (79UL)
1188 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (80UL)
1189 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (81UL)
1190 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (82UL)
1191 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (83UL)
1192 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (84UL)
1193 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (85UL)
1194 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (86UL)
1195 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (87UL)
1196 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (88UL)
1197 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (89UL)
1198 #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (90UL)
1199 #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (91UL)
1200 #define SYSCTL_RESOURCE_CLK_TOP_PTPC (92UL)
1201 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (93UL)
1202 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (94UL)
1203 #define SYSCTL_RESOURCE_CLK_TOP_ANA2 (95UL)
1204 #define SYSCTL_RESOURCE_CLK_TOP_ANA3 (96UL)
1205 #define SYSCTL_RESOURCE_CLK_TOP_ANA4 (97UL)
1206 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (98UL)
1207 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (99UL)
1208 #define SYSCTL_RESOURCE_CLK_TOP_LIN0 (100UL)
1209 #define SYSCTL_RESOURCE_CLK_TOP_LIN1 (101UL)
1210 #define SYSCTL_RESOURCE_CLK_TOP_LIN2 (102UL)
1211 #define SYSCTL_RESOURCE_CLK_TOP_LIN3 (103UL)
1212 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (128UL)
1213 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (129UL)
1214 #define SYSCTL_RESOURCE_CLK_TOP_ADC2 (130UL)
1215 #define SYSCTL_RESOURCE_CLK_TOP_DAC0 (131UL)
1216 #define SYSCTL_RESOURCE_CLK_TOP_DAC1 (132UL)
1217 #define SYSCTL_RESOURCE_AHBP (256UL)
1218 #define SYSCTL_RESOURCE_AXIS (257UL)
1219 #define SYSCTL_RESOURCE_AXIC (258UL)
1220 #define SYSCTL_RESOURCE_LMM0 (259UL)
1221 #define SYSCTL_RESOURCE_MCT0 (260UL)
1222 #define SYSCTL_RESOURCE_LMM1 (261UL)
1223 #define SYSCTL_RESOURCE_MCT1 (262UL)
1224 #define SYSCTL_RESOURCE_ROM0 (263UL)
1225 #define SYSCTL_RESOURCE_RAM0 (264UL)
1226 #define SYSCTL_RESOURCE_I2C0 (265UL)
1227 #define SYSCTL_RESOURCE_I2C1 (266UL)
1228 #define SYSCTL_RESOURCE_I2C2 (267UL)
1229 #define SYSCTL_RESOURCE_I2C3 (268UL)
1230 #define SYSCTL_RESOURCE_TMR0 (269UL)
1231 #define SYSCTL_RESOURCE_TMR1 (270UL)
1232 #define SYSCTL_RESOURCE_TMR2 (271UL)
1233 #define SYSCTL_RESOURCE_TMR3 (272UL)
1234 #define SYSCTL_RESOURCE_GPIO (273UL)
1235 #define SYSCTL_RESOURCE_ADC0 (274UL)
1236 #define SYSCTL_RESOURCE_ADC1 (275UL)
1237 #define SYSCTL_RESOURCE_ADC2 (276UL)
1238 #define SYSCTL_RESOURCE_DAC0 (277UL)
1239 #define SYSCTL_RESOURCE_DAC1 (278UL)
1240 #define SYSCTL_RESOURCE_ACMP (279UL)
1241 #define SYSCTL_RESOURCE_SPI0 (280UL)
1242 #define SYSCTL_RESOURCE_SPI1 (281UL)
1243 #define SYSCTL_RESOURCE_SPI2 (282UL)
1244 #define SYSCTL_RESOURCE_SPI3 (283UL)
1245 #define SYSCTL_RESOURCE_SDM0 (284UL)
1246 #define SYSCTL_RESOURCE_URT0 (285UL)
1247 #define SYSCTL_RESOURCE_URT1 (286UL)
1248 #define SYSCTL_RESOURCE_URT2 (287UL)
1249 #define SYSCTL_RESOURCE_URT3 (288UL)
1250 #define SYSCTL_RESOURCE_URT4 (289UL)
1251 #define SYSCTL_RESOURCE_URT5 (290UL)
1252 #define SYSCTL_RESOURCE_URT6 (291UL)
1253 #define SYSCTL_RESOURCE_URT7 (292UL)
1254 #define SYSCTL_RESOURCE_LIN0 (293UL)
1255 #define SYSCTL_RESOURCE_LIN1 (294UL)
1256 #define SYSCTL_RESOURCE_LIN2 (295UL)
1257 #define SYSCTL_RESOURCE_LIN3 (296UL)
1258 #define SYSCTL_RESOURCE_PTPC (297UL)
1259 #define SYSCTL_RESOURCE_CAN0 (298UL)
1260 #define SYSCTL_RESOURCE_CAN1 (299UL)
1261 #define SYSCTL_RESOURCE_CAN2 (300UL)
1262 #define SYSCTL_RESOURCE_CAN3 (301UL)
1263 #define SYSCTL_RESOURCE_WDG0 (302UL)
1264 #define SYSCTL_RESOURCE_WDG1 (303UL)
1265 #define SYSCTL_RESOURCE_MBX0 (304UL)
1266 #define SYSCTL_RESOURCE_MBX1 (305UL)
1267 #define SYSCTL_RESOURCE_CRC0 (306UL)
1268 #define SYSCTL_RESOURCE_MOT0 (307UL)
1269 #define SYSCTL_RESOURCE_MOT1 (308UL)
1270 #define SYSCTL_RESOURCE_MOT2 (309UL)
1271 #define SYSCTL_RESOURCE_MOT3 (310UL)
1272 #define SYSCTL_RESOURCE_SYNT (311UL)
1273 #define SYSCTL_RESOURCE_XPI0 (312UL)
1274 #define SYSCTL_RESOURCE_HDMA (313UL)
1275 #define SYSCTL_RESOURCE_XDMA (314UL)
1276 #define SYSCTL_RESOURCE_KMAN (315UL)
1277 #define SYSCTL_RESOURCE_SDP0 (316UL)
1278 #define SYSCTL_RESOURCE_RNG0 (317UL)
1279 #define SYSCTL_RESOURCE_TSNS (318UL)
1280 #define SYSCTL_RESOURCE_USB0 (319UL)
1281 #define SYSCTL_RESOURCE_REF0 (320UL)
1282 #define SYSCTL_RESOURCE_REF1 (321UL)
1283 
1284 /* GROUP0 register group index macro definition */
1285 #define SYSCTL_GROUP0_LINK0 (0UL)
1286 #define SYSCTL_GROUP0_LINK1 (1UL)
1287 #define SYSCTL_GROUP0_LINK2 (2UL)
1288 
1289 /* GROUP1 register group index macro definition */
1290 #define SYSCTL_GROUP1_LINK0 (0UL)
1291 #define SYSCTL_GROUP1_LINK1 (1UL)
1292 #define SYSCTL_GROUP1_LINK2 (2UL)
1293 
1294 /* AFFILIATE register group index macro definition */
1295 #define SYSCTL_AFFILIATE_CPU0 (0UL)
1296 #define SYSCTL_AFFILIATE_CPU1 (1UL)
1297 
1298 /* RETENTION register group index macro definition */
1299 #define SYSCTL_RETENTION_CPU0 (0UL)
1300 #define SYSCTL_RETENTION_CPU1 (1UL)
1301 
1302 /* POWER register group index macro definition */
1303 #define SYSCTL_POWER_CPU0 (0UL)
1304 #define SYSCTL_POWER_CPU1 (1UL)
1305 
1306 /* RESET register group index macro definition */
1307 #define SYSCTL_RESET_SOC (0UL)
1308 #define SYSCTL_RESET_CPU0 (1UL)
1309 #define SYSCTL_RESET_CPU1 (2UL)
1310 
1311 /* CLOCK_CPU register group index macro definition */
1312 #define SYSCTL_CLOCK_CPU_CLK_TOP_CPU0 (0UL)
1313 
1314 /* CLOCK register group index macro definition */
1315 #define SYSCTL_CLOCK_CLK_TOP_MCT0 (0UL)
1316 #define SYSCTL_CLOCK_CLK_TOP_MCT1 (1UL)
1317 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (2UL)
1318 #define SYSCTL_CLOCK_CLK_TOP_TMR0 (3UL)
1319 #define SYSCTL_CLOCK_CLK_TOP_TMR1 (4UL)
1320 #define SYSCTL_CLOCK_CLK_TOP_TMR2 (5UL)
1321 #define SYSCTL_CLOCK_CLK_TOP_TMR3 (6UL)
1322 #define SYSCTL_CLOCK_CLK_TOP_URT0 (7UL)
1323 #define SYSCTL_CLOCK_CLK_TOP_URT1 (8UL)
1324 #define SYSCTL_CLOCK_CLK_TOP_URT2 (9UL)
1325 #define SYSCTL_CLOCK_CLK_TOP_URT3 (10UL)
1326 #define SYSCTL_CLOCK_CLK_TOP_URT4 (11UL)
1327 #define SYSCTL_CLOCK_CLK_TOP_URT5 (12UL)
1328 #define SYSCTL_CLOCK_CLK_TOP_URT6 (13UL)
1329 #define SYSCTL_CLOCK_CLK_TOP_URT7 (14UL)
1330 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (15UL)
1331 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (16UL)
1332 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (17UL)
1333 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (18UL)
1334 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (19UL)
1335 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (20UL)
1336 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (21UL)
1337 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (22UL)
1338 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (23UL)
1339 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (24UL)
1340 #define SYSCTL_CLOCK_CLK_TOP_CAN2 (25UL)
1341 #define SYSCTL_CLOCK_CLK_TOP_CAN3 (26UL)
1342 #define SYSCTL_CLOCK_CLK_TOP_PTPC (27UL)
1343 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (28UL)
1344 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (29UL)
1345 #define SYSCTL_CLOCK_CLK_TOP_ANA2 (30UL)
1346 #define SYSCTL_CLOCK_CLK_TOP_ANA3 (31UL)
1347 #define SYSCTL_CLOCK_CLK_TOP_ANA4 (32UL)
1348 #define SYSCTL_CLOCK_CLK_TOP_REF0 (33UL)
1349 #define SYSCTL_CLOCK_CLK_TOP_REF1 (34UL)
1350 #define SYSCTL_CLOCK_CLK_TOP_LIN0 (35UL)
1351 #define SYSCTL_CLOCK_CLK_TOP_LIN1 (36UL)
1352 #define SYSCTL_CLOCK_CLK_TOP_LIN2 (37UL)
1353 #define SYSCTL_CLOCK_CLK_TOP_LIN3 (38UL)
1354 
1355 /* ADCCLK register group index macro definition */
1356 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL)
1357 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL)
1358 #define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL)
1359 
1360 /* DACCLK register group index macro definition */
1361 #define SYSCTL_DACCLK_CLK_TOP_DAC0 (0UL)
1362 #define SYSCTL_DACCLK_CLK_TOP_DAC1 (1UL)
1363 
1364 /* MONITOR register group index macro definition */
1365 #define SYSCTL_MONITOR_SLICE0 (0UL)
1366 #define SYSCTL_MONITOR_SLICE1 (1UL)
1367 #define SYSCTL_MONITOR_SLICE2 (2UL)
1368 #define SYSCTL_MONITOR_SLICE3 (3UL)
1369 
1370 /* GPR register group index macro definition */
1371 #define SYSCTL_CPU_GPR_GPR0 (0UL)
1372 #define SYSCTL_CPU_GPR_GPR1 (1UL)
1373 #define SYSCTL_CPU_GPR_GPR2 (2UL)
1374 #define SYSCTL_CPU_GPR_GPR3 (3UL)
1375 #define SYSCTL_CPU_GPR_GPR4 (4UL)
1376 #define SYSCTL_CPU_GPR_GPR5 (5UL)
1377 #define SYSCTL_CPU_GPR_GPR6 (6UL)
1378 #define SYSCTL_CPU_GPR_GPR7 (7UL)
1379 #define SYSCTL_CPU_GPR_GPR8 (8UL)
1380 #define SYSCTL_CPU_GPR_GPR9 (9UL)
1381 #define SYSCTL_CPU_GPR_GPR10 (10UL)
1382 #define SYSCTL_CPU_GPR_GPR11 (11UL)
1383 #define SYSCTL_CPU_GPR_GPR12 (12UL)
1384 #define SYSCTL_CPU_GPR_GPR13 (13UL)
1385 
1386 /* WAKEUP_STATUS register group index macro definition */
1387 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL)
1388 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL)
1389 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL)
1390 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL)
1391 
1392 /* WAKEUP_ENABLE register group index macro definition */
1393 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL)
1394 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL)
1395 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL)
1396 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL)
1397 
1398 /* CPU register group index macro definition */
1399 #define SYSCTL_CPU_CPU0 (0UL)
1400 #define SYSCTL_CPU_CPU1 (1UL)
1401 
1402 
1403 #endif /* HPM_SYSCTL_H */
SYSCTL_Type
Definition: hpm_sysctl_regs.h:12