HPM SDK
HPMicro Software Development Kit
hpm_trgmmux_src.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TRGMMUX_SRC_H
10 #define HPM_TRGMMUX_SRC_H
11 
12 /* trgm0_input mux definitions */
13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) /* Low level */
14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) /* High level */
15 #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) /* TRGM0 Input 0 (from IO) */
16 #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) /* TRGM0 Input 1 (from IO) */
17 #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) /* TRGM0 Input 2 (from IO) */
18 #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) /* TRGM0 Input 3 (from IO) */
19 #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) /* TRGM0 Input 4 (from IO) */
20 #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) /* TRGM0 Input 5 (from IO) */
21 #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) /* TRGM0 Input 6 (from IO) */
22 #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) /* TRGM0 Input 7 (from IO) */
23 #define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) /* TRGM0 Input 8 (from IO) */
24 #define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) /* TRGM0 Input 9 (from IO) */
25 #define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) /* TRGM0 Input 10 (from IO) */
26 #define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) /* TRGM0 Input 11 (from IO) */
27 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) /* TRGM1 Output X0 */
28 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) /* TRGM1 Output X1 */
29 #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) /* PWM timer 0 channel 8 reference output */
30 #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) /* PWM timer 0 channel 9 reference output */
31 #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) /* PWM timer 0 channel 10 reference output */
32 #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) /* PWM timer 0 channel 11 reference output */
33 #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) /* PWM timer 0 channel 12 reference output */
34 #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) /* PWM timer 0 channel 13 reference output */
35 #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) /* PWM timer 0 channel 14 reference output */
36 #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) /* PWM timer 0 channel 15 reference output */
37 #define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) /* PWM timer 0 channel 16 reference output */
38 #define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) /* PWM timer 0 channel 17 reference output */
39 #define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) /* PWM timer 0 channel 18 reference output */
40 #define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) /* PWM timer 0 channel 19 reference output */
41 #define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) /* PWM timer 0 channel 20 reference output */
42 #define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) /* PWM timer 0 channel 21 reference output */
43 #define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) /* PWM timer 0 channel 22 reference output */
44 #define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) /* PWM timer 0 channel 23 reference output */
45 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) /* QEI0 triggers output */
46 #define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) /* HALL0 triggers output */
47 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) /* USB0 frame start */
48 #define HPM_TRGM0_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) /* NTMR channel 1 comparison output */
49 #define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) /* PTP output bit 3 of ENET0 */
50 #define HPM_TRGM0_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) /* NTMR channel 0 comparison output */
51 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) /* PTPC output comparison 0 */
52 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) /* PTPC output comparison 1 */
53 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) /* SYNT0 Channel 0 */
54 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) /* SYNT0 Channel 1 */
55 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) /* SYNT0 Channel 2 */
56 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) /* SYNT0 Channel 3 */
57 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) /* GPTMR0 channel 2 */
58 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) /* GPTMR0 channel 3 */
59 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) /* GPTMR1 channel 2 */
60 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) /* GPTMR1 channel 3 */
61 #define HPM_TRGM0_INPUT_SRC_ACMP0_OUT (0x34UL) /* Comparator 0 output */
62 #define HPM_TRGM0_INPUT_SRC_ACMP1_OUT (0x35UL) /* Comparator 1 output */
63 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) /* the flag bit of debug mode enters */
64 
65 /* trgm1_input mux definitions */
66 #define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) /* Low level */
67 #define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) /* High level */
68 #define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) /* TRGM1 Input 0 (from IO) */
69 #define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) /* TRGM1 Input 1 (from IO) */
70 #define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) /* TRGM1 Input 2 (from IO) */
71 #define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) /* TRGM1 Input 3 (from IO) */
72 #define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) /* TRGM1 Input 4 (from IO) */
73 #define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) /* TRGM1 Input 5 (from IO) */
74 #define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) /* TRGM1 Input 6 (from IO) */
75 #define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) /* TRGM1 Input 7 (from IO) */
76 #define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) /* TRGM1 Input 8 (from IO) */
77 #define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) /* TRGM1 Input 9 (from IO) */
78 #define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) /* TRGM1 Input 10 (from IO) */
79 #define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) /* TRGM1 Input 11 (from IO) */
80 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) /* TRGM0 Output X0 */
81 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) /* TRGM0 Output X1 */
82 #define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) /* PWM timer 1 channel 8 reference output */
83 #define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) /* PWM timer 1 channel 9 reference output */
84 #define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) /* PWM timer 1 channel 10 reference output */
85 #define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) /* PWM timer 1 channel 11 reference output */
86 #define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) /* PWM timer 1 channel 12 reference output */
87 #define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) /* PWM timer 1 channel 13 reference output */
88 #define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) /* PWM timer 1 channel 14 reference output */
89 #define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) /* PWM timer 1 channel 15 reference output */
90 #define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) /* PWM timer 1 channel 16 reference output */
91 #define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) /* PWM timer 1 channel 17 reference output */
92 #define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) /* PWM timer 1 channel 18 reference output */
93 #define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) /* PWM timer 1 channel 19 reference output */
94 #define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) /* PWM timer 1 channel 20 reference output */
95 #define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) /* PWM timer 1 channel 21 reference output */
96 #define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) /* PWM timer 1 channel 22 reference output */
97 #define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) /* PWM timer 1 channel 23 reference output */
98 #define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) /* QEI1 triggers output */
99 #define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) /* HALL1 triggers output */
100 #define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) /* USB0 frame start */
101 #define HPM_TRGM1_INPUT_SRC_NTMR0_CH1_OUT (0x27UL) /* NTMR channel 1 comparison output */
102 #define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) /* PTP output bit 3 of ENET0 */
103 #define HPM_TRGM1_INPUT_SRC_NTMR0_CH0_OUT (0x29UL) /* NTMR channel 0 comparison output */
104 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) /* PTPC output comparison 0 */
105 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) /* PTPC output comparison 1 */
106 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH0 (0x2CUL) /* SYNT0 Channel 0 */
107 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH1 (0x2DUL) /* SYNT0 Channel 1 */
108 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH2 (0x2EUL) /* SYNT0 Channel 2 */
109 #define HPM_TRGM1_INPUT_SRC_SYNT0_CH3 (0x2FUL) /* SYNT0 Channel 3 */
110 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) /* GPTMR2 channel 2 */
111 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) /* GPTMR2 channel 3 */
112 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) /* GPTMR3 channel 2 */
113 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) /* GPTMR3 channel 3 */
114 #define HPM_TRGM1_INPUT_SRC_ACMP0_OUT (0x34UL) /* Comparator 0 output */
115 #define HPM_TRGM1_INPUT_SRC_ACMP1_OUT (0x35UL) /* Comparator 1 output */
116 #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) /* the flag bit of debug mode enters */
117 
118 /* trgm0_output mux definitions */
119 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) /* TRGM0 Output 0 (to IO) */
120 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) /* TRGM0 Output 1 (to IO) */
121 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) /* TRGM0 Output 2 (to IO) */
122 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) /* TRGM0 Output 3 (to IO) */
123 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) /* TRGM0 Output 4 (to IO) */
124 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) /* TRGM0 Output 5 (to IO) */
125 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) /* TRGM0 Output 6 (to IO) */
126 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) /* TRGM0 Output 7 (to IO) */
127 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) /* TRGM0 Output 8 (to IO) */
128 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) /* TRGM0 Output 9 (to IO) */
129 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) /* TRGM0 Output 10 (to IO) */
130 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) /* TRGM0 Output 11 (to IO) */
131 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) /* TRGM0 Output X0 (to another TRGM) */
132 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) /* TRGM0 Output X1 (to another TRGM) */
133 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) /* PWM timer 0 counter synchronously triggers input */
134 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) /* the input value for PWM timer 0 forces control */
135 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) /* the synchronous input for PWM timer 0 forces control */
136 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) /* PWM timer 0 Shadow register to activate trigger input */
137 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) /* PWM timer 0 Fault protection input 0 */
138 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) /* PWM timer 0 Fault protection input 1 */
139 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) /* PWM timer 0 Fault protection input 2 */
140 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) /* PWM timer 0 Fault protection input 3 */
141 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) /* PWM timer 0 capture input 8 */
142 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) /* PWM timer 0 capture input 9 */
143 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) /* PWM timer 0 capture input 10 */
144 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) /* PWM timer 0 capture input 11 */
145 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) /* PWM timer 0 capture input 12 */
146 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) /* PWM timer 0 capture input 13 */
147 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) /* PWM timer 0 capture input 14 */
148 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) /* PWM timer 0 capture input 15 */
149 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) /* PWM timer 0 capture input 16 */
150 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) /* PWM timer 0 capture input 17 */
151 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) /* PWM timer 0 capture input 18 */
152 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) /* PWM timer 0 capture input 19 */
153 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) /* PWM timer 0 capture input 20 */
154 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) /* PWM timer 0 capture input 21 */
155 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) /* PWM timer 0 capture input 22 */
156 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) /* PWM timer 0 capture input 23 */
157 #define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) /* QEI0 input of phase A */
158 #define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) /* QEI0 input of phase B */
159 #define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) /* QEI0 input of phase Z */
160 #define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) /* QEI0 input of phase H */
161 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) /* QEI0 Pause input */
162 #define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) /* QEI0 Snap input */
163 #define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) /* HALL0 input of phase U */
164 #define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) /* HALL0 input of phase V */
165 #define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) /* HALL0 input of phase W */
166 #define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) /* HALL0 Snap input */
167 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI2A (0x30UL) /* The sequence conversion of ADC0 triggers input;This bit is also activated as the preemption conversion of ADC0, 1 , 2 triggers input 2A */
168 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI2B (0x31UL) /* The sequence conversion of ADC1 triggers input;This bit is also activated as the preemption conversion of ADC0, 1 , 2 triggers input 2B */
169 #define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI2C (0x32UL) /* The sequence conversion of ADC2 triggers input;This bit is also activated as the preemption conversion of ADC0, 1 , 2 triggers input 2C */
170 #define HPM_TRGM0_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) /* DAC0 buffer mode starts to trigger */
171 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 0A */
172 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 0B */
173 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 0C */
174 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) /* GPTMR0 counter synchronous input */
175 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) /* GPTMR0 channel 2 input */
176 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) /* GPTMR0 channel 3 input */
177 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) /* GPTMR1 counter synchronous input */
178 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) /* GPTMR1 channel 2 input */
179 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) /* GPTMR1 channel 3 input */
180 #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) /* Comparator 0 window mode input */
181 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC input capture 0 */
182 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC input capture 1 */
183 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) /* DAC STEP mode triggers input 0 */
184 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) /* DAC STEP mode triggers input 1 */
185 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) /* DAC STEP mode triggers input 2 */
186 #define HPM_TRGM0_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) /* DAC STEP mode triggers input 3 */
187 
188 /* trgm1_output mux definitions */
189 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) /* TRGM1 Output 0 (to IO) */
190 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) /* TRGM1 Output 1 (to IO) */
191 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) /* TRGM1 Output 2 (to IO) */
192 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) /* TRGM1 Output 3 (to IO) */
193 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) /* TRGM1 Output 4 (to IO) */
194 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) /* TRGM1 Output 5 (to IO) */
195 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) /* TRGM1 Output 6 (to IO) */
196 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) /* TRGM1 Output 7 (to IO) */
197 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) /* TRGM1 Output 8 (to IO) */
198 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) /* TRGM1 Output 9 (to IO) */
199 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) /* TRGM1 Output 10 (to IO) */
200 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) /* TRGM1 Output 11 (to IO) */
201 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) /* TRGM1 Output X0 (to another TRGM) */
202 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) /* TRGM1 Output X1 (to another TRGM) */
203 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) /* PWM timer 1 counter synchronously triggers input */
204 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) /* the input value for PWM timer 1 forces control */
205 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) /* the synchronous input for PWM timer 1 forces control */
206 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) /* PWM timer 1 Shadow register to activate trigger input */
207 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) /* PWM timer 1 Fault protection input 0 */
208 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) /* PWM timer 1 Fault protection input 1 */
209 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) /* PWM timer 1 Fault protection input 2 */
210 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) /* PWM timer 1 Fault protection input 3 */
211 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) /* PWM timer 1 capture input 8 */
212 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) /* PWM timer 1 capture input 9 */
213 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) /* PWM timer 1 capture input 10 */
214 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) /* PWM timer 1 capture input 11 */
215 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) /* PWM timer 1 capture input 12 */
216 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) /* PWM timer 1 capture input 13 */
217 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) /* PWM timer 1 capture input 14 */
218 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) /* PWM timer 1 capture input 15 */
219 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) /* PWM timer 1 capture input 16 */
220 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) /* PWM timer 1 capture input 17 */
221 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) /* PWM timer 1 capture input 18 */
222 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) /* PWM timer 1 capture input 19 */
223 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) /* PWM timer 1 capture input 20 */
224 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) /* PWM timer 1 capture input 21 */
225 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) /* PWM timer 1 capture input 22 */
226 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) /* PWM timer 1 capture input 23 */
227 #define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) /* QEI1 input of phase A */
228 #define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) /* QEI1 input of phase B */
229 #define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) /* QEI1 input of phase Z */
230 #define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) /* QEI1 input of phase H */
231 #define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) /* QEI1 Pause input */
232 #define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) /* QEI1 Snap input */
233 #define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) /* HALL1 input of phase U */
234 #define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) /* HALL1 input of phase V */
235 #define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) /* HALL1 input of phase W */
236 #define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) /* HALL1 Snap input */
237 #define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI_ADCX_PTRGI3A (0x30UL) /* The sequence conversion of ADC0 triggers input;This bit is also activated as the preemption conversion of ADC0, 1 , 2 triggers input 3A */
238 #define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI_ADCX_PTRGI3B (0x31UL) /* The sequence conversion of ADC1 triggers input;This bit is also activated as the preemption conversion of ADC0, 1 , 2 triggers input 3B */
239 #define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI_ADCX_PTRGI3C (0x32UL) /* The sequence conversion of ADC2 triggers input;This bit is also activated as the preemption conversion of ADC0, 1 , 2 triggers input 3C */
240 #define HPM_TRGM1_OUTPUT_SRC_DAC_BUFF_TRIGGER (0x33UL) /* DAC buffer mode starts to trigger */
241 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 1A */
242 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 1B */
243 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) /* The preemption conversion of ADC0, 1 , 2 triggers input 1C */
244 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) /* GPTMR2 counter synchronous input */
245 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) /* GPTMR2 channel 2 input */
246 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) /* GPTMR2 channel 3 input */
247 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) /* GPTMR3 counter synchronous input */
248 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) /* GPTMR3 channel 2 input */
249 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) /* GPTMR3 channel 3 input */
250 #define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) /* Comparator 1 window mode input */
251 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC input capture 0 */
252 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC input capture 1 */
253 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN0 (0x40UL) /* DAC STEP mode triggers input 0 */
254 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN1 (0x41UL) /* DAC STEP mode triggers input 1 */
255 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN2 (0x42UL) /* DAC STEP mode triggers input 2 */
256 #define HPM_TRGM1_OUTPUT_SRC_DAC_STEP_TRIGGER_IN3 (0x43UL) /* DAC STEP mode triggers input 3 */
257 
258 /* trgm0_filter mux definitions */
259 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) /* PWM timer 0 capture Input 0 */
260 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) /* PWM timer 0 capture Input 1 */
261 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) /* PWM timer 0 capture Input 2 */
262 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) /* PWM timer 0 capture Input 3 */
263 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) /* PWM timer 0 capture Input 4 */
264 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) /* PWM timer 0 capture Input 5 */
265 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) /* PWM timer 0 capture Input 6 */
266 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) /* PWM timer 0 capture Input 7 */
267 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) /* TRGM0 iutput 0 */
268 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) /* TRGM0 iutput 1 */
269 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) /* TRGM0 iutput 2 */
270 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) /* TRGM0 iutput 3 */
271 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) /* TRGM0 iutput 4 */
272 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) /* TRGM0 iutput 5 */
273 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) /* TRGM0 iutput 6 */
274 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) /* TRGM0 iutput 7 */
275 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) /* TRGM0 iutput 8 */
276 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) /* TRGM0 iutput 9 */
277 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) /* TRGM0 iutput 10 */
278 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) /* TRGM0 iutput 11 */
279 
280 /* trgm1_filter mux definitions */
281 #define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) /* PWM timer 1 capture input 0 */
282 #define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) /* PWM timer 1 capture input 1 */
283 #define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) /* PWM timer 1 capture input 2 */
284 #define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) /* PWM timer 1 capture input 3 */
285 #define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) /* PWM timer 1 capture input 4 */
286 #define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) /* PWM timer 1 capture input 5 */
287 #define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) /* PWM timer 1 capture input 6 */
288 #define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) /* PWM timer 1 capture input 7 */
289 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) /* TRGM1 iutput 0 */
290 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) /* TRGM1 iutput 1 */
291 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) /* TRGM1 iutput 2 */
292 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) /* TRGM1 iutput 3 */
293 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) /* TRGM1 iutput 4 */
294 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) /* TRGM1 iutput 5 */
295 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) /* TRGM1 iutput 6 */
296 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) /* TRGM1 iutput 7 */
297 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) /* TRGM1 iutput 8 */
298 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) /* TRGM1 iutput 9 */
299 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) /* TRGM1 iutput 10 */
300 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) /* TRGM1 iutput 11 */
301 
302 /* trgm0_dma mux definitions */
303 #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) /* The capture input or matches output of PWM timer 0 comparator 0 */
304 #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) /* The capture input or matches output of PWM timer 0 comparator 1 */
305 #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) /* The capture input or matches output of PWM timer 0 comparator 2 */
306 #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) /* The capture input or matches output of PWM timer 0 comparator 3 */
307 #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) /* The capture input or matches output of PWM timer 0 comparator 4 */
308 #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) /* The capture input or matches output of PWM timer 0 comparator 5 */
309 #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) /* The capture input or matches output of PWM timer 0 comparator 6 */
310 #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) /* The capture input or matches output of PWM timer 0 comparator 7 */
311 #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) /* The capture input or matches output of PWM timer 0 comparator 8 */
312 #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) /* The capture input or matches output of PWM timer 0 comparator 9 */
313 #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) /* The capture input or matches output of PWM timer 0 comparator 10 */
314 #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) /* The capture input or matches output of PWM timer 0 comparator 11 */
315 #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) /* The capture input or matches output of PWM timer 0 comparator 12 */
316 #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) /* The capture input or matches output of PWM timer 0 comparator 13 */
317 #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) /* The capture input or matches output of PWM timer 0 comparator 14 */
318 #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) /* The capture input or matches output of PWM timer 0 comparator 15 */
319 #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) /* The capture input or matches output of PWM timer 0 comparator 16 */
320 #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) /* The capture input or matches output of PWM timer 0 comparator 17 */
321 #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) /* The capture input or matches output of PWM timer 0 comparator 18 */
322 #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) /* The capture input or matches output of PWM timer 0 comparator 19 */
323 #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) /* The capture input or matches output of PWM timer 0 comparator 20 */
324 #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) /* The capture input or matches output of PWM timer 0 comparator 21 */
325 #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) /* The capture input or matches output of PWM timer 0 comparator 22 */
326 #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) /* The capture input or matches output of PWM timer 0 comparator 23 */
327 #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) /* PWM timer 0 counter reload */
328 #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) /* PWM timer 0 half cycle reload */
329 #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) /* PWM timer 0 extended counter reload */
330 #define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) /* DMA request for QEI0 */
331 #define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) /* DMA request for HALL0 */
332 
333 /* trgm1_dma mux definitions */
334 #define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) /* The capture input or matches output of PWM timer 1 comparator 0 */
335 #define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) /* The capture input or matches output of PWM timer 1 comparator 1 */
336 #define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) /* The capture input or matches output of PWM timer 1 comparator 2 */
337 #define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) /* The capture input or matches output of PWM timer 1 comparator 3 */
338 #define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) /* The capture input or matches output of PWM timer 1 comparator 4 */
339 #define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) /* The capture input or matches output of PWM timer 1 comparator 5 */
340 #define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) /* The capture input or matches output of PWM timer 1 comparator 6 */
341 #define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) /* The capture input or matches output of PWM timer 1 comparator 7 */
342 #define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) /* The capture input or matches output of PWM timer 1 comparator 8 */
343 #define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) /* The capture input or matches output of PWM timer 1 comparator 9 */
344 #define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) /* The capture input or matches output of PWM timer 1 comparator 10 */
345 #define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) /* The capture input or matches output of PWM timer 1 comparator 11 */
346 #define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) /* The capture input or matches output of PWM timer 1 comparator 12 */
347 #define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) /* The capture input or matches output of PWM timer 1 comparator 13 */
348 #define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) /* The capture input or matches output of PWM timer 1 comparator 14 */
349 #define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) /* The capture input or matches output of PWM timer 1 comparator 15 */
350 #define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) /* The capture input or matches output of PWM timer 1 comparator 16 */
351 #define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) /* The capture input or matches output of PWM timer 1 comparator 17 */
352 #define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) /* The capture input or matches output of PWM timer 1 comparator 18 */
353 #define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) /* The capture input or matches output of PWM timer 1 comparator 19 */
354 #define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) /* The capture input or matches output of PWM timer 1 comparator 20 */
355 #define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) /* The capture input or matches output of PWM timer 1 comparator 21 */
356 #define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) /* The capture input or matches output of PWM timer 1 comparator 22 */
357 #define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) /* The capture input or matches output of PWM timer 1 comparator 23 */
358 #define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) /* PWM timer 1 counter reload */
359 #define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) /* PWM timer 1 half cycle reload */
360 #define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) /* PWM timer 1 extended counter reload */
361 #define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) /* DMA request for QEI1 */
362 #define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) /* DMA request for HALL1 */
363 
364 
365 
366 #endif /* HPM_TRGMMUX_SRC_H */