HPM SDK
HPMicro Software Development Kit
hpm_bcfg_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_BCFG_H
10 #define HPM_BCFG_H
11 
12 typedef struct {
13  __RW uint32_t VBG_CFG; /* 0x0: Bandgap config */
14  __R uint8_t RESERVED0[4]; /* 0x4 - 0x7: Reserved */
15  __RW uint32_t IRC32K_CFG; /* 0x8: On-chip 32k oscillator config */
16  __RW uint32_t XTAL32K_CFG; /* 0xC: XTAL 32K config */
17  __RW uint32_t CLK_CFG; /* 0x10: Clock config */
18 } BCFG_Type;
19 
20 
21 /* Bitfield definition for register: VBG_CFG */
22 /*
23  * VBG_TRIMMED (RW)
24  *
25  * Bandgap trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value
26  * 0: bandgap is not trimmed
27  * 1: bandgap is trimmed
28  */
29 #define BCFG_VBG_CFG_VBG_TRIMMED_MASK (0x80000000UL)
30 #define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT (31U)
31 #define BCFG_VBG_CFG_VBG_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK)
32 #define BCFG_VBG_CFG_VBG_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT)
33 
34 /*
35  * LP_MODE (RW)
36  *
37  * Bandgap works in low power mode
38  * 0: not in low power mode
39  * 1: bandgap work in low power mode
40  */
41 #define BCFG_VBG_CFG_LP_MODE_MASK (0x2000000UL)
42 #define BCFG_VBG_CFG_LP_MODE_SHIFT (25U)
43 #define BCFG_VBG_CFG_LP_MODE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK)
44 #define BCFG_VBG_CFG_LP_MODE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT)
45 
46 /*
47  * POWER_SAVE (RW)
48  *
49  * Bandgap works in power save mode
50  * 0: not in power save mode
51  * 1: bandgap work in power save mode
52  */
53 #define BCFG_VBG_CFG_POWER_SAVE_MASK (0x1000000UL)
54 #define BCFG_VBG_CFG_POWER_SAVE_SHIFT (24U)
55 #define BCFG_VBG_CFG_POWER_SAVE_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK)
56 #define BCFG_VBG_CFG_POWER_SAVE_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT)
57 
58 /*
59  * VBG_1P0 (RW)
60  *
61  * Bandgap 1.0V output trim
62  */
63 #define BCFG_VBG_CFG_VBG_1P0_MASK (0x1F0000UL)
64 #define BCFG_VBG_CFG_VBG_1P0_SHIFT (16U)
65 #define BCFG_VBG_CFG_VBG_1P0_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK)
66 #define BCFG_VBG_CFG_VBG_1P0_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT)
67 
68 /*
69  * VBG_P65 (RW)
70  *
71  * Bandgap 0.65V output trim
72  */
73 #define BCFG_VBG_CFG_VBG_P65_MASK (0x1F00U)
74 #define BCFG_VBG_CFG_VBG_P65_SHIFT (8U)
75 #define BCFG_VBG_CFG_VBG_P65_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK)
76 #define BCFG_VBG_CFG_VBG_P65_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT)
77 
78 /*
79  * VBG_P50 (RW)
80  *
81  * Bandgap 0.50V output trim
82  */
83 #define BCFG_VBG_CFG_VBG_P50_MASK (0x1FU)
84 #define BCFG_VBG_CFG_VBG_P50_SHIFT (0U)
85 #define BCFG_VBG_CFG_VBG_P50_SET(x) (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK)
86 #define BCFG_VBG_CFG_VBG_P50_GET(x) (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT)
87 
88 /* Bitfield definition for register: IRC32K_CFG */
89 /*
90  * IRC_TRIMMED (RW)
91  *
92  * IRC32K trim happened, this bit set by hardware after trim value loaded, and stop load, write 0 will clear this bit and reload trim value
93  * 0: irc is not trimmed
94  * 1: irc is trimmed
95  */
96 #define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK (0x80000000UL)
97 #define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT (31U)
98 #define BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK)
99 #define BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT)
100 
101 /*
102  * CAPEX7_TRIM (RW)
103  *
104  * IRC32K bit 7
105  */
106 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK (0x800000UL)
107 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT (23U)
108 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK)
109 #define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT)
110 
111 /*
112  * CAPEX6_TRIM (RW)
113  *
114  * IRC32K bit 6
115  */
116 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK (0x400000UL)
117 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT (22U)
118 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK)
119 #define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT)
120 
121 /*
122  * CAP_TRIM (RW)
123  *
124  * capacitor trim bits
125  */
126 #define BCFG_IRC32K_CFG_CAP_TRIM_MASK (0x1FFU)
127 #define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT (0U)
128 #define BCFG_IRC32K_CFG_CAP_TRIM_SET(x) (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK)
129 #define BCFG_IRC32K_CFG_CAP_TRIM_GET(x) (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT)
130 
131 /* Bitfield definition for register: XTAL32K_CFG */
132 /*
133  * HYST_EN (RW)
134  *
135  * crystal 32k hysteres enable
136  */
137 #define BCFG_XTAL32K_CFG_HYST_EN_MASK (0x1000U)
138 #define BCFG_XTAL32K_CFG_HYST_EN_SHIFT (12U)
139 #define BCFG_XTAL32K_CFG_HYST_EN_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK)
140 #define BCFG_XTAL32K_CFG_HYST_EN_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT)
141 
142 /*
143  * GMSEL (RW)
144  *
145  * crystal 32k gm selection
146  */
147 #define BCFG_XTAL32K_CFG_GMSEL_MASK (0x300U)
148 #define BCFG_XTAL32K_CFG_GMSEL_SHIFT (8U)
149 #define BCFG_XTAL32K_CFG_GMSEL_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK)
150 #define BCFG_XTAL32K_CFG_GMSEL_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT)
151 
152 /*
153  * CFG (RW)
154  *
155  * crystal 32k config
156  */
157 #define BCFG_XTAL32K_CFG_CFG_MASK (0x10U)
158 #define BCFG_XTAL32K_CFG_CFG_SHIFT (4U)
159 #define BCFG_XTAL32K_CFG_CFG_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK)
160 #define BCFG_XTAL32K_CFG_CFG_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT)
161 
162 /*
163  * AMP (RW)
164  *
165  * crystal 32k amplifier
166  */
167 #define BCFG_XTAL32K_CFG_AMP_MASK (0x3U)
168 #define BCFG_XTAL32K_CFG_AMP_SHIFT (0U)
169 #define BCFG_XTAL32K_CFG_AMP_SET(x) (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK)
170 #define BCFG_XTAL32K_CFG_AMP_GET(x) (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT)
171 
172 /* Bitfield definition for register: CLK_CFG */
173 /*
174  * XTAL_SEL (RO)
175  *
176  * crystal selected
177  */
178 #define BCFG_CLK_CFG_XTAL_SEL_MASK (0x10000000UL)
179 #define BCFG_CLK_CFG_XTAL_SEL_SHIFT (28U)
180 #define BCFG_CLK_CFG_XTAL_SEL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT)
181 
182 /*
183  * KEEP_IRC (RW)
184  *
185  * force irc32k run
186  */
187 #define BCFG_CLK_CFG_KEEP_IRC_MASK (0x10000UL)
188 #define BCFG_CLK_CFG_KEEP_IRC_SHIFT (16U)
189 #define BCFG_CLK_CFG_KEEP_IRC_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK)
190 #define BCFG_CLK_CFG_KEEP_IRC_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT)
191 
192 /*
193  * FORCE_XTAL (RW)
194  *
195  * force switch to crystal
196  */
197 #define BCFG_CLK_CFG_FORCE_XTAL_MASK (0x10U)
198 #define BCFG_CLK_CFG_FORCE_XTAL_SHIFT (4U)
199 #define BCFG_CLK_CFG_FORCE_XTAL_SET(x) (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK)
200 #define BCFG_CLK_CFG_FORCE_XTAL_GET(x) (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT)
201 
202 
203 
204 
205 #endif /* HPM_BCFG_H */
BCFG_Type
Definition: hpm_bcfg_regs.h:12