HPM SDK
HPMicro Software Development Kit
hpm_trgmmux_src.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TRGMMUX_SRC_H
10 #define HPM_TRGMMUX_SRC_H
11 
12 /* trgm0_input mux definitions */
13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) /* low level voltage */
14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) /* high level voltage */
15 #define HPM_TRGM0_INPUT_SRC_TRGM0_P0 (0x2UL) /* TRGM0 input data0(from IO) */
16 #define HPM_TRGM0_INPUT_SRC_TRGM0_P1 (0x3UL) /* TRGM0 input data1(from IO) */
17 #define HPM_TRGM0_INPUT_SRC_TRGM0_P2 (0x4UL) /* TRGM0 input data2(from IO) */
18 #define HPM_TRGM0_INPUT_SRC_TRGM0_P3 (0x5UL) /* TRGM0 input data3(from IO) */
19 #define HPM_TRGM0_INPUT_SRC_TRGM0_P4 (0x6UL) /* TRGM0 input data4(from IO) */
20 #define HPM_TRGM0_INPUT_SRC_TRGM0_P5 (0x7UL) /* TRGM0 input data5(from IO) */
21 #define HPM_TRGM0_INPUT_SRC_TRGM0_P6 (0x8UL) /* TRGM0 input data6(from IO) */
22 #define HPM_TRGM0_INPUT_SRC_TRGM0_P7 (0x9UL) /* TRGM0 input data7(from IO) */
23 #define HPM_TRGM0_INPUT_SRC_TRGM0_P8 (0xAUL) /* TRGM0 input data8(from IO) */
24 #define HPM_TRGM0_INPUT_SRC_TRGM0_P9 (0xBUL) /* TRGM0 input data9(from IO) */
25 #define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0xCUL) /* TRGM0 input data10(from IO) */
26 #define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0xDUL) /* TRGM0 input data11(from IO) */
27 #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX0 (0xEUL) /* TRGM3 output0(from other TRGM to TRGM0) */
28 #define HPM_TRGM0_INPUT_SRC_TRGM3_OUTX1 (0xFUL) /* TRGM3 output1(from other TRGM to TRGM0) */
29 #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX0 (0x10UL) /* TRGM2 output0(from other TRGM to TRGM0) */
30 #define HPM_TRGM0_INPUT_SRC_TRGM2_OUTX1 (0x11UL) /* TRGM2 output1(from other TRGM to TRGM0) */
31 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX0 (0x12UL) /* TRGM1 output0(from other TRGM to TRGM0) */
32 #define HPM_TRGM0_INPUT_SRC_TRGM1_OUTX1 (0x13UL) /* TRGM1 output1(from other TRGM to TRGM0) */
33 #define HPM_TRGM0_INPUT_SRC_PWM0_CH8REF (0x14UL) /* PWM0 channel8 trigger out */
34 #define HPM_TRGM0_INPUT_SRC_PWM0_CH9REF (0x15UL) /* PWM0 channel9 trigger out */
35 #define HPM_TRGM0_INPUT_SRC_PWM0_CH10REF (0x16UL) /* PWM0 channel10 trigger out */
36 #define HPM_TRGM0_INPUT_SRC_PWM0_CH11REF (0x17UL) /* PWM0 channel11 trigger out */
37 #define HPM_TRGM0_INPUT_SRC_PWM0_CH12REF (0x18UL) /* PWM0 channel12 trigger out */
38 #define HPM_TRGM0_INPUT_SRC_PWM0_CH13REF (0x19UL) /* PWM0 channel13 trigger out */
39 #define HPM_TRGM0_INPUT_SRC_PWM0_CH14REF (0x1AUL) /* PWM0 channel14 trigger out */
40 #define HPM_TRGM0_INPUT_SRC_PWM0_CH15REF (0x1BUL) /* PWM0 channel15 trigger out */
41 #define HPM_TRGM0_INPUT_SRC_PWM0_CH16REF (0x1CUL) /* PWM0 channel16 trigger out */
42 #define HPM_TRGM0_INPUT_SRC_PWM0_CH17REF (0x1DUL) /* PWM0 channel17 trigger out */
43 #define HPM_TRGM0_INPUT_SRC_PWM0_CH18REF (0x1EUL) /* PWM0 channel18 trigger out */
44 #define HPM_TRGM0_INPUT_SRC_PWM0_CH19REF (0x1FUL) /* PWM0 channel19 trigger out */
45 #define HPM_TRGM0_INPUT_SRC_PWM0_CH20REF (0x20UL) /* PWM0 channel20 trigger out */
46 #define HPM_TRGM0_INPUT_SRC_PWM0_CH21REF (0x21UL) /* PWM0 channel21 trigger out */
47 #define HPM_TRGM0_INPUT_SRC_PWM0_CH22REF (0x22UL) /* PWM0 channel22 trigger out */
48 #define HPM_TRGM0_INPUT_SRC_PWM0_CH23REF (0x23UL) /* PWM0 channel23 trigger out */
49 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0x24UL) /* QEI0 trigger out */
50 #define HPM_TRGM0_INPUT_SRC_HALL0_TRGO (0x25UL) /* HALL0 trigger out */
51 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x26UL) /* USB0 start of frame marker */
52 #define HPM_TRGM0_INPUT_SRC_USB1_SOF (0x27UL) /* USB1 start of frame marker */
53 #define HPM_TRGM0_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) /* ENET0 PTP output bit3 */
54 #define HPM_TRGM0_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) /* ENET1 PTP output bit3 */
55 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x2AUL) /* PTPC compare output0 */
56 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x2BUL) /* PTPC compare output1 */
57 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH0 (0x2CUL) /* SYNT channel0 pulse output */
58 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH1 (0x2DUL) /* SYNT channel1 pulse output */
59 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH2 (0x2EUL) /* SYNT channel2 pulse output */
60 #define HPM_TRGM0_INPUT_SRC_SYNT0_CH3 (0x2FUL) /* SYNT channel3 pulse output */
61 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x30UL) /* GPTMR0 channel2 compare output */
62 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x31UL) /* GPTMR0 channel3 compare output */
63 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x32UL) /* GPTMR1 channel2 compare output */
64 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x33UL) /* GPTMR1 channel3 compare output */
65 #define HPM_TRGM0_INPUT_SRC_ACMP0_OUT (0x34UL) /* CMP0 compare output */
66 #define HPM_TRGM0_INPUT_SRC_ACMP1_OUT (0x35UL) /* CMP1 compare output */
67 #define HPM_TRGM0_INPUT_SRC_ACMP2_OUT (0x36UL) /* CMP2 compare output */
68 #define HPM_TRGM0_INPUT_SRC_ACMP3_OUT (0x37UL) /* CMP3 compare output */
69 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0x38UL) /* debug mode flag */
70 
71 /* trgm1_input mux definitions */
72 #define HPM_TRGM1_INPUT_SRC_VSS (0x0UL) /* low level voltage */
73 #define HPM_TRGM1_INPUT_SRC_VDD (0x1UL) /* high level voltage */
74 #define HPM_TRGM1_INPUT_SRC_TRGM1_P0 (0x2UL) /* TRGM1 input data0(from IO) */
75 #define HPM_TRGM1_INPUT_SRC_TRGM1_P1 (0x3UL) /* TRGM1 input data1(from IO) */
76 #define HPM_TRGM1_INPUT_SRC_TRGM1_P2 (0x4UL) /* TRGM1 input data2(from IO) */
77 #define HPM_TRGM1_INPUT_SRC_TRGM1_P3 (0x5UL) /* TRGM1 input data3(from IO) */
78 #define HPM_TRGM1_INPUT_SRC_TRGM1_P4 (0x6UL) /* TRGM1 input data4(from IO) */
79 #define HPM_TRGM1_INPUT_SRC_TRGM1_P5 (0x7UL) /* TRGM1 input data5(from IO) */
80 #define HPM_TRGM1_INPUT_SRC_TRGM1_P6 (0x8UL) /* TRGM1 input data6(from IO) */
81 #define HPM_TRGM1_INPUT_SRC_TRGM1_P7 (0x9UL) /* TRGM1 input data7(from IO) */
82 #define HPM_TRGM1_INPUT_SRC_TRGM1_P8 (0xAUL) /* TRGM1 input data8(from IO) */
83 #define HPM_TRGM1_INPUT_SRC_TRGM1_P9 (0xBUL) /* TRGM1 input data9(from IO) */
84 #define HPM_TRGM1_INPUT_SRC_TRGM1_P10 (0xCUL) /* TRGM1 input data10(from IO) */
85 #define HPM_TRGM1_INPUT_SRC_TRGM1_P11 (0xDUL) /* TRGM1 input data11(from IO) */
86 #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX0 (0xEUL) /* TRGM3 output0(from other TRGM to TRGM1) */
87 #define HPM_TRGM1_INPUT_SRC_TRGM3_OUTX1 (0xFUL) /* TRGM3 output1(from other TRGM to TRGM1) */
88 #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX0 (0x10UL) /* TRGM2 output0(from other TRGM to TRGM1) */
89 #define HPM_TRGM1_INPUT_SRC_TRGM2_OUTX1 (0x11UL) /* TRGM2 output1(from other TRGM to TRGM1) */
90 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX0 (0x12UL) /* TRGM0 output0(from other TRGM to TRGM1) */
91 #define HPM_TRGM1_INPUT_SRC_TRGM0_OUTX1 (0x13UL) /* TRGM0 output1(from other TRGM to TRGM1) */
92 #define HPM_TRGM1_INPUT_SRC_PWM1_CH8REF (0x14UL) /* PWM1 channel8 trigger out */
93 #define HPM_TRGM1_INPUT_SRC_PWM1_CH9REF (0x15UL) /* PWM1 channel9 trigger out */
94 #define HPM_TRGM1_INPUT_SRC_PWM1_CH10REF (0x16UL) /* PWM1 channel10 trigger out */
95 #define HPM_TRGM1_INPUT_SRC_PWM1_CH11REF (0x17UL) /* PWM1 channel11 trigger out */
96 #define HPM_TRGM1_INPUT_SRC_PWM1_CH12REF (0x18UL) /* PWM1 channel12 trigger out */
97 #define HPM_TRGM1_INPUT_SRC_PWM1_CH13REF (0x19UL) /* PWM1 channel13 trigger out */
98 #define HPM_TRGM1_INPUT_SRC_PWM1_CH14REF (0x1AUL) /* PWM1 channel14 trigger out */
99 #define HPM_TRGM1_INPUT_SRC_PWM1_CH15REF (0x1BUL) /* PWM1 channel15 trigger out */
100 #define HPM_TRGM1_INPUT_SRC_PWM1_CH16REF (0x1CUL) /* PWM1 channel16 trigger out */
101 #define HPM_TRGM1_INPUT_SRC_PWM1_CH17REF (0x1DUL) /* PWM1 channel17 trigger out */
102 #define HPM_TRGM1_INPUT_SRC_PWM1_CH18REF (0x1EUL) /* PWM1 channel18 trigger out */
103 #define HPM_TRGM1_INPUT_SRC_PWM1_CH19REF (0x1FUL) /* PWM1 channel19 trigger out */
104 #define HPM_TRGM1_INPUT_SRC_PWM1_CH20REF (0x20UL) /* PWM1 channel20 trigger out */
105 #define HPM_TRGM1_INPUT_SRC_PWM1_CH21REF (0x21UL) /* PWM1 channel21 trigger out */
106 #define HPM_TRGM1_INPUT_SRC_PWM1_CH22REF (0x22UL) /* PWM1 channel22 trigger out */
107 #define HPM_TRGM1_INPUT_SRC_PWM1_CH23REF (0x23UL) /* PWM1 channel23 trigger out */
108 #define HPM_TRGM1_INPUT_SRC_QEI1_TRGO (0x24UL) /* QEI1 trigger out */
109 #define HPM_TRGM1_INPUT_SRC_HALL1_TRGO (0x25UL) /* HALL1 trigger out */
110 #define HPM_TRGM1_INPUT_SRC_USB0_SOF (0x26UL) /* USB0 start of frame marker */
111 #define HPM_TRGM1_INPUT_SRC_USB1_SOF (0x27UL) /* USB1 start of frame marker */
112 #define HPM_TRGM1_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) /* ENET0 PTP output bit3 */
113 #define HPM_TRGM1_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) /* ENET1 PTP output bit3 */
114 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP0 (0x2AUL) /* PTPC compare output0 */
115 #define HPM_TRGM1_INPUT_SRC_PTPC_CMP1 (0x2BUL) /* PTPC compare output1 */
116 #define HPM_TRGM1_INPUT_SRC_SYNT_CH0 (0x2CUL) /* SYNT channel0 pulse output */
117 #define HPM_TRGM1_INPUT_SRC_SYNT_CH1 (0x2DUL) /* SYNT channel1 pulse output */
118 #define HPM_TRGM1_INPUT_SRC_SYNT_CH2 (0x2EUL) /* SYNT channel2 pulse output */
119 #define HPM_TRGM1_INPUT_SRC_SYNT_CH3 (0x2FUL) /* SYNT channel3 pulse output */
120 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT2 (0x30UL) /* GPTMR2 channel2 compare output */
121 #define HPM_TRGM1_INPUT_SRC_GPTMR2_OUT3 (0x31UL) /* GPTMR2 channel3 compare output */
122 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT2 (0x32UL) /* GPTMR3 channel2 compare output */
123 #define HPM_TRGM1_INPUT_SRC_GPTMR3_OUT3 (0x33UL) /* GPTMR3 channel3 compare output */
124 #define HPM_TRGM1_INPUT_SRC_ACMP0_OUT (0x34UL) /* CMP0 compare output */
125 #define HPM_TRGM1_INPUT_SRC_ACMP1_OUT (0x35UL) /* CMP1 compare output */
126 #define HPM_TRGM1_INPUT_SRC_ACMP2_OUT (0x36UL) /* CMP2 compare output */
127 #define HPM_TRGM1_INPUT_SRC_ACMP3_OUT (0x37UL) /* CMP3 compare output */
128 #define HPM_TRGM1_INPUT_SRC_DEBUG_FLAG (0x38UL) /* debug mode flag */
129 
130 /* trgm2_input mux definitions */
131 #define HPM_TRGM2_INPUT_SRC_VSS (0x0UL) /* low level voltage */
132 #define HPM_TRGM2_INPUT_SRC_VDD (0x1UL) /* high level voltage */
133 #define HPM_TRGM2_INPUT_SRC_TRGM2_P0 (0x2UL) /* TRGM2 input data0(from IO) */
134 #define HPM_TRGM2_INPUT_SRC_TRGM2_P1 (0x3UL) /* TRGM2 input data1(from IO) */
135 #define HPM_TRGM2_INPUT_SRC_TRGM2_P2 (0x4UL) /* TRGM2 input data2(from IO) */
136 #define HPM_TRGM2_INPUT_SRC_TRGM2_P3 (0x5UL) /* TRGM2 input data3(from IO) */
137 #define HPM_TRGM2_INPUT_SRC_TRGM2_P4 (0x6UL) /* TRGM2 input data4(from IO) */
138 #define HPM_TRGM2_INPUT_SRC_TRGM2_P5 (0x7UL) /* TRGM2 input data5(from IO) */
139 #define HPM_TRGM2_INPUT_SRC_TRGM2_P6 (0x8UL) /* TRGM2 input data6(from IO) */
140 #define HPM_TRGM2_INPUT_SRC_TRGM2_P7 (0x9UL) /* TRGM2 input data7(from IO) */
141 #define HPM_TRGM2_INPUT_SRC_TRGM2_P8 (0xAUL) /* TRGM0 input data8(from IO) */
142 #define HPM_TRGM2_INPUT_SRC_TRGM2_P9 (0xBUL) /* TRGM0 input data9(from IO) */
143 #define HPM_TRGM2_INPUT_SRC_TRGM2_P10 (0xCUL) /* TRGM0 input data10(from IO) */
144 #define HPM_TRGM2_INPUT_SRC_TRGM2_P11 (0xDUL) /* TRGM0 input data11(from IO) */
145 #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX0 (0xEUL) /* TRGM3 output0(from other TRGM to TRGM2) */
146 #define HPM_TRGM2_INPUT_SRC_TRGM3_OUTX1 (0xFUL) /* TRGM3 output1(from other TRGM to TRGM2) */
147 #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX0 (0x10UL) /* TRGM1 output0(from other TRGM to TRGM2) */
148 #define HPM_TRGM2_INPUT_SRC_TRGM1_OUTX1 (0x11UL) /* TRGM1 output1(from other TRGM to TRGM2) */
149 #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX0 (0x12UL) /* TRGM0 output0(from other TRGM to TRGM2) */
150 #define HPM_TRGM2_INPUT_SRC_TRGM0_OUTX1 (0x13UL) /* TRGM0 output1(from other TRGM to TRGM2) */
151 #define HPM_TRGM2_INPUT_SRC_PWM2_CH8REF (0x14UL) /* PWM2 channel8 trigger out */
152 #define HPM_TRGM2_INPUT_SRC_PWM2_CH9REF (0x15UL) /* PWM2 channel9 trigger out */
153 #define HPM_TRGM2_INPUT_SRC_PWM2_CH10REF (0x16UL) /* PWM2 channel10 trigger out */
154 #define HPM_TRGM2_INPUT_SRC_PWM2_CH11REF (0x17UL) /* PWM2 channel11 trigger out */
155 #define HPM_TRGM2_INPUT_SRC_PWM2_CH12REF (0x18UL) /* PWM2 channel12 trigger out */
156 #define HPM_TRGM2_INPUT_SRC_PWM2_CH13REF (0x19UL) /* PWM2 channel13 trigger out */
157 #define HPM_TRGM2_INPUT_SRC_PWM2_CH14REF (0x1AUL) /* PWM2 channel14 trigger out */
158 #define HPM_TRGM2_INPUT_SRC_PWM2_CH15REF (0x1BUL) /* PWM2 channel15 trigger out */
159 #define HPM_TRGM2_INPUT_SRC_PWM2_CH16REF (0x1CUL) /* PWM2 channel16 trigger out */
160 #define HPM_TRGM2_INPUT_SRC_PWM2_CH17REF (0x1DUL) /* PWM2 channel17 trigger out */
161 #define HPM_TRGM2_INPUT_SRC_PWM2_CH18REF (0x1EUL) /* PWM2 channel18 trigger out */
162 #define HPM_TRGM2_INPUT_SRC_PWM2_CH19REF (0x1FUL) /* PWM2 channel19 trigger out */
163 #define HPM_TRGM2_INPUT_SRC_PWM2_CH20REF (0x20UL) /* PWM2 channel20 trigger out */
164 #define HPM_TRGM2_INPUT_SRC_PWM2_CH21REF (0x21UL) /* PWM2 channel21 trigger out */
165 #define HPM_TRGM2_INPUT_SRC_PWM2_CH22REF (0x22UL) /* PWM2 channel22 trigger out */
166 #define HPM_TRGM2_INPUT_SRC_PWM2_CH23REF (0x23UL) /* PWM2 channel23 trigger out */
167 #define HPM_TRGM2_INPUT_SRC_QEI2_TRGO (0x24UL) /* QEI2 trigger out */
168 #define HPM_TRGM2_INPUT_SRC_HALL2_TRGO (0x25UL) /* HALL2 trigger out */
169 #define HPM_TRGM2_INPUT_SRC_USB0_SOF (0x26UL) /* USB0 start of frame marker */
170 #define HPM_TRGM2_INPUT_SRC_USB1_SOF (0x27UL) /* USB1 start of frame marker */
171 #define HPM_TRGM2_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) /* ENET0 PTP output bit3 */
172 #define HPM_TRGM2_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) /* ENET1 PTP output bit3 */
173 #define HPM_TRGM2_INPUT_SRC_PTPC_CMP0 (0x2AUL) /* PTPC compare output0 */
174 #define HPM_TRGM2_INPUT_SRC_PTPC_CMP1 (0x2BUL) /* PTPC compare output1 */
175 #define HPM_TRGM2_INPUT_SRC_SYNT_CH0 (0x2CUL) /* SYNT channel0 pulse output */
176 #define HPM_TRGM2_INPUT_SRC_SYNT_CH1 (0x2DUL) /* SYNT channel1 pulse output */
177 #define HPM_TRGM2_INPUT_SRC_SYNT_CH2 (0x2EUL) /* SYNT channel2 pulse output */
178 #define HPM_TRGM2_INPUT_SRC_SYNT_CH3 (0x2FUL) /* SYNT channel3 pulse output */
179 #define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT2 (0x30UL) /* GPTMR4 channel2 compare output */
180 #define HPM_TRGM2_INPUT_SRC_GPTMR4_OUT3 (0x31UL) /* GPTMR4 channel3 compare output */
181 #define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT2 (0x32UL) /* GPTMR5 channel2 compare output */
182 #define HPM_TRGM2_INPUT_SRC_GPTMR5_OUT3 (0x33UL) /* GPTMR5 channel3 compare output */
183 #define HPM_TRGM2_INPUT_SRC_ACMP0_OUT (0x34UL) /* CMP0 compare output */
184 #define HPM_TRGM2_INPUT_SRC_ACMP1_OUT (0x35UL) /* CMP1 compare output */
185 #define HPM_TRGM2_INPUT_SRC_ACMP2_OUT (0x36UL) /* CMP2 compare output */
186 #define HPM_TRGM2_INPUT_SRC_ACMP3_OUT (0x37UL) /* CMP3 compare output */
187 #define HPM_TRGM2_INPUT_SRC_DEBUG_FLAG (0x38UL) /* debug mode flag */
188 
189 /* trgm3_input mux definitions */
190 #define HPM_TRGM3_INPUT_SRC_VSS (0x0UL) /* low level voltage */
191 #define HPM_TRGM3_INPUT_SRC_VDD (0x1UL) /* high level voltage */
192 #define HPM_TRGM3_INPUT_SRC_TRGM3_P0 (0x2UL) /* TRGM3 input data0(from IO) */
193 #define HPM_TRGM3_INPUT_SRC_TRGM3_P1 (0x3UL) /* TRGM3 input data1(from IO) */
194 #define HPM_TRGM3_INPUT_SRC_TRGM3_P2 (0x4UL) /* TRGM3 input data2(from IO) */
195 #define HPM_TRGM3_INPUT_SRC_TRGM3_P3 (0x5UL) /* TRGM3 input data3(from IO) */
196 #define HPM_TRGM3_INPUT_SRC_TRGM3_P4 (0x6UL) /* TRGM3 input data4(from IO) */
197 #define HPM_TRGM3_INPUT_SRC_TRGM3_P5 (0x7UL) /* TRGM3 input data5(from IO) */
198 #define HPM_TRGM3_INPUT_SRC_TRGM3_P6 (0x8UL) /* TRGM3 input data6(from IO) */
199 #define HPM_TRGM3_INPUT_SRC_TRGM3_P7 (0x9UL) /* TRGM3 input data7(from IO) */
200 #define HPM_TRGM3_INPUT_SRC_TRGM3_P8 (0xAUL) /* TRGM3 input data8(from IO) */
201 #define HPM_TRGM3_INPUT_SRC_TRGM3_P9 (0xBUL) /* TRGM3 input data9(from IO) */
202 #define HPM_TRGM3_INPUT_SRC_TRGM3_P10 (0xCUL) /* TGM3 input data10(from IO) */
203 #define HPM_TRGM3_INPUT_SRC_TRGM3_P11 (0xDUL) /* TGM3 input data11(from IO) */
204 #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX0 (0xEUL) /* TRGM2 output0(from other TRGM to TRGM3) */
205 #define HPM_TRGM3_INPUT_SRC_TRGM2_OUTX1 (0xFUL) /* TRGM2 output1(from other TRGM to TRGM3) */
206 #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX0 (0x10UL) /* TRGM1 output0(from other TRGM to TRGM3) */
207 #define HPM_TRGM3_INPUT_SRC_TRGM1_OUTX1 (0x11UL) /* TRGM1 output1(from other TRGM to TRGM3) */
208 #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX0 (0x12UL) /* TRGM0 output0(from other TRGM to TRGM3) */
209 #define HPM_TRGM3_INPUT_SRC_TRGM0_OUTX1 (0x13UL) /* TRGM0 output1(from other TRGM to TRGM3) */
210 #define HPM_TRGM3_INPUT_SRC_PWM3_CH8REF (0x14UL) /* PWM3 channel8 trigger out */
211 #define HPM_TRGM3_INPUT_SRC_PWM3_CH9REF (0x15UL) /* PWM3 channel9 trigger out */
212 #define HPM_TRGM3_INPUT_SRC_PWM3_CH10REF (0x16UL) /* PWM3 channel10 trigger out */
213 #define HPM_TRGM3_INPUT_SRC_PWM3_CH11REF (0x17UL) /* PWM3 channel11 trigger out */
214 #define HPM_TRGM3_INPUT_SRC_PWM3_CH12REF (0x18UL) /* PWM3 channel12 trigger out */
215 #define HPM_TRGM3_INPUT_SRC_PWM3_CH13REF (0x19UL) /* PWM3 channel13 trigger out */
216 #define HPM_TRGM3_INPUT_SRC_PWM3_CH14REF (0x1AUL) /* PWM3 channel14 trigger out */
217 #define HPM_TRGM3_INPUT_SRC_PWM3_CH15REF (0x1BUL) /* PWM3 channel15 trigger out */
218 #define HPM_TRGM3_INPUT_SRC_PWM3_CH16REF (0x1CUL) /* PWM3 channel16 trigger out */
219 #define HPM_TRGM3_INPUT_SRC_PWM3_CH17REF (0x1DUL) /* PWM3 channel17 trigger out */
220 #define HPM_TRGM3_INPUT_SRC_PWM3_CH18REF (0x1EUL) /* PWM3 channel18 trigger out */
221 #define HPM_TRGM3_INPUT_SRC_PWM3_CH19REF (0x1FUL) /* PWM3 channel19 trigger out */
222 #define HPM_TRGM3_INPUT_SRC_PWM3_CH20REF (0x20UL) /* PWM3 channel20 trigger out */
223 #define HPM_TRGM3_INPUT_SRC_PWM3_CH21REF (0x21UL) /* PWM3 channel21 trigger out */
224 #define HPM_TRGM3_INPUT_SRC_PWM3_CH22REF (0x22UL) /* PWM3 channel22 trigger out */
225 #define HPM_TRGM3_INPUT_SRC_PWM3_CH23REF (0x23UL) /* PWM3 channel23 trigger out */
226 #define HPM_TRGM3_INPUT_SRC_QEI3_TRGO (0x24UL) /* QEI3 trigger out */
227 #define HPM_TRGM3_INPUT_SRC_HALL3_TRGO (0x25UL) /* HALL3 trigger out */
228 #define HPM_TRGM3_INPUT_SRC_USB0_SOF (0x26UL) /* USB0 start of frame */
229 #define HPM_TRGM3_INPUT_SRC_USB1_SOF (0x27UL) /* USB1 start of frame */
230 #define HPM_TRGM3_INPUT_SRC_ENET0_PTP_OUT3 (0x28UL) /* ENET0 PTP output bit3 */
231 #define HPM_TRGM3_INPUT_SRC_ENET1_PTP_OUT3 (0x29UL) /* ENET1 PTP output bit3 */
232 #define HPM_TRGM3_INPUT_SRC_PTPC_CMP0 (0x2AUL) /* PTPC compare output0 */
233 #define HPM_TRGM3_INPUT_SRC_PTPC_CMP1 (0x2BUL) /* PTPC compare output1 */
234 #define HPM_TRGM3_INPUT_SRC_SYNT_CH0 (0x2CUL) /* SYNT channel0 pulse output */
235 #define HPM_TRGM3_INPUT_SRC_SYNT_CH1 (0x2DUL) /* SYNT channel1 pulse output */
236 #define HPM_TRGM3_INPUT_SRC_SYNT_CH2 (0x2EUL) /* SYNT channel2 pulse output */
237 #define HPM_TRGM3_INPUT_SRC_SYNT_CH3 (0x2FUL) /* SYNT channel3 pulse output */
238 #define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT2 (0x30UL) /* GPTMR6 channel2 compare output */
239 #define HPM_TRGM3_INPUT_SRC_GPTMR6_OUT3 (0x31UL) /* GPTMR6 channel3 compare output */
240 #define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT2 (0x32UL) /* GPTMR7 channel2 compare output */
241 #define HPM_TRGM3_INPUT_SRC_GPTMR7_OUT3 (0x33UL) /* GPTMR7 channel3 compare output */
242 #define HPM_TRGM3_INPUT_SRC_ACMP0_OUT (0x34UL) /* CMP0 compare output */
243 #define HPM_TRGM3_INPUT_SRC_ACMP1_OUT (0x35UL) /* CMP1 compare output */
244 #define HPM_TRGM3_INPUT_SRC_ACMP2_OUT (0x36UL) /* CMP2 compare output */
245 #define HPM_TRGM3_INPUT_SRC_ACMP3_OUT (0x37UL) /* CMP3 compare output */
246 #define HPM_TRGM3_INPUT_SRC_DEBUG_FLAG (0x38UL) /* debug mode flag */
247 
248 /* trgm0_output mux definitions */
249 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P0 (0x0UL) /* TRGM0 output data0(to IO) */
250 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P1 (0x1UL) /* TRGM0 output data1(to IO) */
251 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P2 (0x2UL) /* TRGM0 output data2(to IO) */
252 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P3 (0x3UL) /* TRGM0 output data3(to IO) */
253 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P4 (0x4UL) /* TRGM0 output data4(to IO) */
254 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P5 (0x5UL) /* TRGM0 output data5(to IO) */
255 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P6 (0x6UL) /* TRGM0 output data6(to IO) */
256 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P7 (0x7UL) /* TRGM0 output data7(to IO) */
257 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P8 (0x8UL) /* TRGM0 output data8(to IO) */
258 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P9 (0x9UL) /* TRGM0 output data9(to IO) */
259 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P10 (0xAUL) /* TRGM0 output data10(to IO) */
260 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_P11 (0xBUL) /* TRGM0 output data11(to IO) */
261 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX0 (0xCUL) /* TRGM0 output data0(to other TRGM) */
262 #define HPM_TRGM0_OUTPUT_SRC_TRGM0_OUTX1 (0xDUL) /* TRGM0 output data1(to other TRGM) */
263 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SYNCI (0xEUL) /* PWM0 counter sync input */
264 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCI (0xFUL) /* PWM0 force output control */
265 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FRCSYNCI (0x10UL) /* PWM0 force output sync control */
266 #define HPM_TRGM0_OUTPUT_SRC_PWM0_SHRLDSYNCI (0x11UL) /* PWM0 shadow register valid signal */
267 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI0 (0x12UL) /* PWM0 fault0 */
268 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI1 (0x13UL) /* PWM0 fault1 */
269 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI2 (0x14UL) /* PWM0 fault2 */
270 #define HPM_TRGM0_OUTPUT_SRC_PWM0_FAULTI3 (0x15UL) /* PWM0 fault3 */
271 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN8 (0x16UL) /* PWM0 capture in8 */
272 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN9 (0x17UL) /* PWM0 capture in9 */
273 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN10 (0x18UL) /* PWM0 capture in10 */
274 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN11 (0x19UL) /* PWM0 capture in11 */
275 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN12 (0x1AUL) /* PWM0 capture in12 */
276 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN13 (0x1BUL) /* PWM0 capture in13 */
277 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN14 (0x1CUL) /* PWM0 capture in14 */
278 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN15 (0x1DUL) /* PWM0 capture in15 */
279 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN16 (0x1EUL) /* PWM0 capture in16 */
280 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN17 (0x1FUL) /* PWM0 capture in17 */
281 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN18 (0x20UL) /* PWM0 capture in18 */
282 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN19 (0x21UL) /* PWM0 capture in19 */
283 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN20 (0x22UL) /* PWM0 capture in20 */
284 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN21 (0x23UL) /* PWM0 capture in21 */
285 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN22 (0x24UL) /* PWM0 capture in22 */
286 #define HPM_TRGM0_OUTPUT_SRC_PWM0_IN23 (0x25UL) /* PWM0 capture in23 */
287 #define HPM_TRGM0_OUTPUT_SRC_QEI0_A (0x26UL) /* QEI0 phase A input */
288 #define HPM_TRGM0_OUTPUT_SRC_QEI0_B (0x27UL) /* QEI0 phase B input */
289 #define HPM_TRGM0_OUTPUT_SRC_QEI0_Z (0x28UL) /* QEI0 phase Z input */
290 #define HPM_TRGM0_OUTPUT_SRC_QEI0_H (0x29UL) /* QEI0 phase H input */
291 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x2AUL) /* QEI0 counter pause */
292 #define HPM_TRGM0_OUTPUT_SRC_QEI0_SNAPI (0x2BUL) /* QEI0 snap pulse input */
293 #define HPM_TRGM0_OUTPUT_SRC_HALL0_U (0x2CUL) /* HALL0 phase U input */
294 #define HPM_TRGM0_OUTPUT_SRC_HALL0_V (0x2DUL) /* HALL0 phase V input */
295 #define HPM_TRGM0_OUTPUT_SRC_HALL0_W (0x2EUL) /* HALL0 phase W input */
296 #define HPM_TRGM0_OUTPUT_SRC_HALL0_SNAPI (0x2FUL) /* HALL0 snap pulse input */
297 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* ADC0 sequence queue trigger */
298 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* ADC1 sequence queue trigger */
299 #define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* ADC2 sequence queue trigger */
300 #define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI (0x33UL) /* ADC3 sequence queue trigger */
301 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) /* "ADC0, 1, 2, 3" preemption trigger0A */
302 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) /* "ADC0, 1, 2, 3" preemption trigger0B */
303 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) /* "ADC0, 1, 2, 3" preemption trigger0C */
304 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x37UL) /* GPTMR0 counter sync input */
305 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x38UL) /* GPTMR0 channel2 capture in */
306 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x39UL) /* GPTMR0 channel3 capture in */
307 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x3AUL) /* GPTMR1 counter sync input */
308 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x3BUL) /* GPTMR1 channel2 capture in */
309 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x3CUL) /* GPTMR1 channel3 capture in */
310 #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x3DUL) /* CMP0 window */
311 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC capture in0 */
312 #define HPM_TRGM0_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC capture in1 */
313 
314 /* trgm1_output mux definitions */
315 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P0 (0x0UL) /* TRGM1 output data0(to IO) */
316 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P1 (0x1UL) /* TRGM1 output data1(to IO) */
317 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P2 (0x2UL) /* TRGM1 output data2(to IO) */
318 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P3 (0x3UL) /* TRGM1 output data3(to IO) */
319 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P4 (0x4UL) /* TRGM1 output data4(to IO) */
320 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P5 (0x5UL) /* TRGM1 output data5(to IO) */
321 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P6 (0x6UL) /* TRGM1 output data6(to IO) */
322 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P7 (0x7UL) /* TRGM1 output data7(to IO) */
323 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P8 (0x8UL) /* TRGM1 output data8(to IO) */
324 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P9 (0x9UL) /* TRGM1 output data9(to IO) */
325 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P10 (0xAUL) /* TRGM1 output data10(to IO) */
326 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_P11 (0xBUL) /* TRGM1 output data11(to IO) */
327 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX0 (0xCUL) /* TRGM1 output data0(to other TRGM) */
328 #define HPM_TRGM1_OUTPUT_SRC_TRGM1_OUTX1 (0xDUL) /* TRGM1 output data1(to other TRGM) */
329 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SYNCI (0xEUL) /* PWM1 counter sync input */
330 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCI (0xFUL) /* PWM1 force output control */
331 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FRCSYNCI (0x10UL) /* PWM1 force output sync control */
332 #define HPM_TRGM1_OUTPUT_SRC_PWM1_SHRLDSYNCI (0x11UL) /* PWM1 shadow register valid signal */
333 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI0 (0x12UL) /* PWM1 fault0 */
334 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI1 (0x13UL) /* PWM1 fault1 */
335 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI2 (0x14UL) /* PWM1 fault2 */
336 #define HPM_TRGM1_OUTPUT_SRC_PWM1_FAULTI3 (0x15UL) /* PWM1 fault3 */
337 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN8 (0x16UL) /* PWM1 capture in8 */
338 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN9 (0x17UL) /* PWM1 capture in9 */
339 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN10 (0x18UL) /* PWM1 capture in10 */
340 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN11 (0x19UL) /* PWM1 capture in11 */
341 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN12 (0x1AUL) /* PWM1 capture in12 */
342 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN13 (0x1BUL) /* PWM1 capture in13 */
343 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN14 (0x1CUL) /* PWM1 capture in14 */
344 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN15 (0x1DUL) /* PWM1 capture in15 */
345 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN16 (0x1EUL) /* PWM1 capture in16 */
346 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN17 (0x1FUL) /* PWM1 capture in17 */
347 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN18 (0x20UL) /* PWM1 capture in18 */
348 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN19 (0x21UL) /* PWM1 capture in19 */
349 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN20 (0x22UL) /* PWM1 capture in20 */
350 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN21 (0x23UL) /* PWM1 capture in21 */
351 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN22 (0x24UL) /* PWM1 capture in22 */
352 #define HPM_TRGM1_OUTPUT_SRC_PWM1_IN23 (0x25UL) /* PWM1 capture in23 */
353 #define HPM_TRGM1_OUTPUT_SRC_QEI1_A (0x26UL) /* QEI1 phase A input */
354 #define HPM_TRGM1_OUTPUT_SRC_QEI1_B (0x27UL) /* QEI1 phase B input */
355 #define HPM_TRGM1_OUTPUT_SRC_QEI1_Z (0x28UL) /* QEI1 phase Z input */
356 #define HPM_TRGM1_OUTPUT_SRC_QEI1_H (0x29UL) /* QEI1 phase H input */
357 #define HPM_TRGM1_OUTPUT_SRC_QEI1_PAUSE (0x2AUL) /* QEI1 counter pause */
358 #define HPM_TRGM1_OUTPUT_SRC_QEI1_SNAPI (0x2BUL) /* QEI1 snap pulse input */
359 #define HPM_TRGM1_OUTPUT_SRC_HALL1_U (0x2CUL) /* HALL1 phase U input */
360 #define HPM_TRGM1_OUTPUT_SRC_HALL1_V (0x2DUL) /* HALL1 phase V input */
361 #define HPM_TRGM1_OUTPUT_SRC_HALL1_W (0x2EUL) /* HALL1 phase W input */
362 #define HPM_TRGM1_OUTPUT_SRC_HALL1_SNAPI (0x2FUL) /* HALL1 snap pulse input */
363 #define HPM_TRGM1_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* ADC0 sequence queue trigger */
364 #define HPM_TRGM1_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* ADC1 sequence queue trigger */
365 #define HPM_TRGM1_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* ADC2 sequence queue trigger */
366 #define HPM_TRGM1_OUTPUT_SRC_ADC3_STRGI (0x33UL) /* ADC3 sequence queue trigger */
367 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1A (0x34UL) /* "ADC0, 1, 2, 3" preemption trigger1A */
368 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1B (0x35UL) /* "ADC0, 1, 2, 3" preemption trigger1B */
369 #define HPM_TRGM1_OUTPUT_SRC_ADCX_PTRGI1C (0x36UL) /* "ADC0, 1, 2, 3" preemption trigger1C */
370 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_SYNCI (0x37UL) /* GPTMR2 counter sync input */
371 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN2 (0x38UL) /* GPTMR2 channel2 capture in */
372 #define HPM_TRGM1_OUTPUT_SRC_GPTMR2_IN3 (0x39UL) /* GPTMR2 channel3 capture in */
373 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_SYNCI (0x3AUL) /* GPTMR3 counter sync input */
374 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN2 (0x3BUL) /* GPTMR3 channel2 capture in */
375 #define HPM_TRGM1_OUTPUT_SRC_GPTMR3_IN3 (0x3CUL) /* GPTMR3 channel3 capture in */
376 #define HPM_TRGM1_OUTPUT_SRC_ACMP1_WIN (0x3DUL) /* CMP1 window */
377 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC capture in0 */
378 #define HPM_TRGM1_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC capture in1 */
379 
380 /* trgm2_output mux definitions */
381 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P0 (0x0UL) /* TRGM2 output data0(to IO) */
382 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P1 (0x1UL) /* TRGM2 output data1(to IO) */
383 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P2 (0x2UL) /* TRGM2 output data2(to IO) */
384 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P3 (0x3UL) /* TRGM2 output data3(to IO) */
385 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P4 (0x4UL) /* TRGM2 output data4(to IO) */
386 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P5 (0x5UL) /* TRGM2 output data5(to IO) */
387 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P6 (0x6UL) /* TRGM2 output data6(to IO) */
388 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P7 (0x7UL) /* TRGM2 output data7(to IO) */
389 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P8 (0x8UL) /* TRGM2 output data8(to IO) */
390 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P9 (0x9UL) /* TRGM2 output data9(to IO) */
391 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P10 (0xAUL) /* TRGM2 output data10(to IO) */
392 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_P11 (0xBUL) /* TRGM2 output data11(to IO) */
393 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX0 (0xCUL) /* TRGM2 output data0(to other TRGM) */
394 #define HPM_TRGM2_OUTPUT_SRC_TRGM2_OUTX1 (0xDUL) /* TRGM2 output data1(to other TRGM) */
395 #define HPM_TRGM2_OUTPUT_SRC_PWM2_SYNCI (0xEUL) /* PWM2 counter sync input */
396 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCI (0xFUL) /* PWM2 force output control */
397 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FRCSYNCI (0x10UL) /* PWM2 force output sync control */
398 #define HPM_TRGM2_OUTPUT_SRC_PWM2_SHRLDSYNCI (0x11UL) /* PWM2 shadow register valid signal */
399 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI0 (0x12UL) /* PWM2 fault0 */
400 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI1 (0x13UL) /* PWM2 fault1 */
401 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI2 (0x14UL) /* PWM2 fault2 */
402 #define HPM_TRGM2_OUTPUT_SRC_PWM2_FAULTI3 (0x15UL) /* PWM2 fault3 */
403 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN8 (0x16UL) /* PWM2 capture in8 */
404 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN9 (0x17UL) /* PWM2 capture in9 */
405 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN10 (0x18UL) /* PWM2 capture in10 */
406 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN11 (0x19UL) /* PWM2 capture in11 */
407 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN12 (0x1AUL) /* PWM2 capture in12 */
408 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN13 (0x1BUL) /* PWM2 capture in13 */
409 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN14 (0x1CUL) /* PWM2 capture in14 */
410 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN15 (0x1DUL) /* PWM2 capture in15 */
411 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN16 (0x1EUL) /* PWM2 capture in16 */
412 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN17 (0x1FUL) /* PWM2 capture in17 */
413 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN18 (0x20UL) /* PWM2 capture in18 */
414 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN19 (0x21UL) /* PWM2 capture in19 */
415 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN20 (0x22UL) /* PWM2 capture in20 */
416 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN21 (0x23UL) /* PWM2 capture in21 */
417 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN22 (0x24UL) /* PWM2 capture in22 */
418 #define HPM_TRGM2_OUTPUT_SRC_PWM2_IN23 (0x25UL) /* PWM2 capture in23 */
419 #define HPM_TRGM2_OUTPUT_SRC_QEI2_A (0x26UL) /* QEI2 phase A input */
420 #define HPM_TRGM2_OUTPUT_SRC_QEI2_B (0x27UL) /* QEI2 phase B input */
421 #define HPM_TRGM2_OUTPUT_SRC_QEI2_Z (0x28UL) /* QEI2 phase Z input */
422 #define HPM_TRGM2_OUTPUT_SRC_QEI2_H (0x29UL) /* QEI2 phase H input */
423 #define HPM_TRGM2_OUTPUT_SRC_QEI2_PAUSE (0x2AUL) /* QEI2 counter pause */
424 #define HPM_TRGM2_OUTPUT_SRC_QEI2_SNAPI (0x2BUL) /* QEI2 snap pulse input */
425 #define HPM_TRGM2_OUTPUT_SRC_HALL2_U (0x2CUL) /* HALL2 phase U input */
426 #define HPM_TRGM2_OUTPUT_SRC_HALL2_V (0x2DUL) /* HALL2 phase V input */
427 #define HPM_TRGM2_OUTPUT_SRC_HALL2_W (0x2EUL) /* HALL2 phase W input */
428 #define HPM_TRGM2_OUTPUT_SRC_HALL2_SNAPI (0x2FUL) /* HALL2 snap pulse input */
429 #define HPM_TRGM2_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* ADC0 sequence queue trigger */
430 #define HPM_TRGM2_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* ADC1 sequence queue trigger */
431 #define HPM_TRGM2_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* ADC2 sequence queue trigger */
432 #define HPM_TRGM2_OUTPUT_SRC_ADC3_STRGI (0x33UL) /* ADC3 sequence queue trigger */
433 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2A (0x34UL) /* "ADC0, 1, 2, 3" preemption triggerA */
434 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2B (0x35UL) /* "ADC0, 1, 2, 3" preemption triggerB */
435 #define HPM_TRGM2_OUTPUT_SRC_ADCX_PTRGI2C (0x36UL) /* "ADC0, 1, 2, 3" preemption triggerC */
436 #define HPM_TRGM2_OUTPUT_SRC_GPTMR4_SYNCI (0x37UL) /* GPTMR4 counter sync input */
437 #define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN2 (0x38UL) /* GPTMR4 channel2 capture in */
438 #define HPM_TRGM2_OUTPUT_SRC_GPTMR4_IN3 (0x39UL) /* GPTMR4 channel3 capture in */
439 #define HPM_TRGM2_OUTPUT_SRC_GPTMR5_SYNCI (0x3AUL) /* GPTMR5 counter sync input */
440 #define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN2 (0x3BUL) /* GPTMR5 channel2 capture in */
441 #define HPM_TRGM2_OUTPUT_SRC_GPTMR5_IN3 (0x3CUL) /* GPTMR5 channel3 capture in */
442 #define HPM_TRGM2_OUTPUT_SRC_ACMP2_WIN (0x3DUL) /* CMP2 window */
443 #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC capture in0 */
444 #define HPM_TRGM2_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC capture in1 */
445 
446 /* trgm3_output mux definitions */
447 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P0 (0x0UL) /* TRGM3 output data0(to IO) */
448 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P1 (0x1UL) /* TRGM3 output data1(to IO) */
449 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P2 (0x2UL) /* TRGM3 output data2(to IO) */
450 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P3 (0x3UL) /* TRGM3 output data3(to IO) */
451 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P4 (0x4UL) /* TRGM3 output data4(to IO) */
452 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P5 (0x5UL) /* TRGM3 output data5(to IO) */
453 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P6 (0x6UL) /* TRGM3 output data6(to IO) */
454 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P7 (0x7UL) /* TRGM3 output data7(to IO) */
455 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P8 (0x8UL) /* TRGM3 output data8(to IO) */
456 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P9 (0x9UL) /* TRGM3 output data9(to IO) */
457 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P10 (0xAUL) /* TRGM3 output data10(to IO) */
458 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_P11 (0xBUL) /* TRGM3 output data11(to IO) */
459 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX0 (0xCUL) /* TRGM3 output data0(to other TRGM) */
460 #define HPM_TRGM3_OUTPUT_SRC_TRGM3_OUTX1 (0xDUL) /* TRGM3 output data1(to other TRGM) */
461 #define HPM_TRGM3_OUTPUT_SRC_PWM3_SYNCI (0xEUL) /* PWM3 counter sync input */
462 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCI (0xFUL) /* PWM3 force output control */
463 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FRCSYNCI (0x10UL) /* PWM3 force output sync control */
464 #define HPM_TRGM3_OUTPUT_SRC_PWM3_SHRLDSYNCI (0x11UL) /* PWM3 shadow register valid signal */
465 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI0 (0x12UL) /* PWM3 fault0 */
466 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI1 (0x13UL) /* PWM3 fault1 */
467 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI2 (0x14UL) /* PWM3 fault2 */
468 #define HPM_TRGM3_OUTPUT_SRC_PWM3_FAULTI3 (0x15UL) /* PWM3 fault3 */
469 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN8 (0x16UL) /* PWM3 capture in8 */
470 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN9 (0x17UL) /* PWM3 capture in9 */
471 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN10 (0x18UL) /* PWM3 capture in10 */
472 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN11 (0x19UL) /* PWM3 capture in11 */
473 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN12 (0x1AUL) /* PWM3 capture in12 */
474 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN13 (0x1BUL) /* PWM3 capture in13 */
475 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN14 (0x1CUL) /* PWM3 capture in14 */
476 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN15 (0x1DUL) /* PWM3 capture in15 */
477 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN16 (0x1EUL) /* PWM3 capture in16 */
478 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN17 (0x1FUL) /* PWM3 capture in17 */
479 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN18 (0x20UL) /* PWM3 capture in18 */
480 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN19 (0x21UL) /* PWM3 capture in19 */
481 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN20 (0x22UL) /* PWM3 capture in20 */
482 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN21 (0x23UL) /* PWM3 capture in21 */
483 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN22 (0x24UL) /* PWM3 capture in22 */
484 #define HPM_TRGM3_OUTPUT_SRC_PWM3_IN23 (0x25UL) /* PWM3 capture in23 */
485 #define HPM_TRGM3_OUTPUT_SRC_QEI3_A (0x26UL) /* QEI3 phase A input */
486 #define HPM_TRGM3_OUTPUT_SRC_QEI3_B (0x27UL) /* QEI3 phase B input */
487 #define HPM_TRGM3_OUTPUT_SRC_QEI3_Z (0x28UL) /* QEI3 phase Z input */
488 #define HPM_TRGM3_OUTPUT_SRC_QEI3_H (0x29UL) /* QEI3 phase H input */
489 #define HPM_TRGM3_OUTPUT_SRC_QEI3_PAUSE (0x2AUL) /* QEI3 pause */
490 #define HPM_TRGM3_OUTPUT_SRC_QEI3_SNAPI (0x2BUL) /* QEI3 snap pulse input */
491 #define HPM_TRGM3_OUTPUT_SRC_HALL3_U (0x2CUL) /* HALL3 phase U input */
492 #define HPM_TRGM3_OUTPUT_SRC_HALL3_V (0x2DUL) /* HALL3 phase V input */
493 #define HPM_TRGM3_OUTPUT_SRC_HALL3_W (0x2EUL) /* HALL3 phase W input */
494 #define HPM_TRGM3_OUTPUT_SRC_HALL3_SNAPI (0x2FUL) /* HALL3 snap pulse input */
495 #define HPM_TRGM3_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* ADC0 sequence queue trigger */
496 #define HPM_TRGM3_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* ADC1 sequence queue trigger */
497 #define HPM_TRGM3_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* ADC2 sequence queue trigger */
498 #define HPM_TRGM3_OUTPUT_SRC_ADC3_STRGI (0x33UL) /* ADC3 sequence queue trigger */
499 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3A (0x34UL) /* "ADC0, 1, 2, 3" preemption triggerA */
500 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3B (0x35UL) /* "ADC0, 1, 2, 3" preemption triggerB */
501 #define HPM_TRGM3_OUTPUT_SRC_ADCX_PTRGI3C (0x36UL) /* "ADC0, 1, 2, 3" preemption triggerC */
502 #define HPM_TRGM3_OUTPUT_SRC_GPTMR6_SYNCI (0x37UL) /* GPTMR6 counter sync input */
503 #define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN2 (0x38UL) /* GPTMR6 channel2 capture in */
504 #define HPM_TRGM3_OUTPUT_SRC_GPTMR6_IN3 (0x39UL) /* GPTMR6 channel3 capture in */
505 #define HPM_TRGM3_OUTPUT_SRC_GPTMR7_SYNCI (0x3AUL) /* GPTMR7 counter sync input */
506 #define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN2 (0x3BUL) /* GPTMR7 channel2 capture in */
507 #define HPM_TRGM3_OUTPUT_SRC_GPTMR7_IN3 (0x3CUL) /* GPTMR7 channel3 capture in */
508 #define HPM_TRGM3_OUTPUT_SRC_ACMP3_WIN (0x3DUL) /* CMP3 window */
509 #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP0 (0x3EUL) /* PTPC capture in0 */
510 #define HPM_TRGM3_OUTPUT_SRC_PTPC_CAP1 (0x3FUL) /* PTPC capture in1 */
511 
512 /* trgm0_filter mux definitions */
513 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) /* PWM0 capture in0 */
514 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) /* PWM0 capture in1 */
515 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) /* PWM0 capture in2 */
516 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) /* PWM0 capture in3 */
517 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) /* PWM0 capture in4 */
518 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) /* PWM0 capture in5 */
519 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) /* PWM0 capture in6 */
520 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) /* PWM0 capture in7 */
521 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN0 (0x8UL) /* TRGM0 input0 */
522 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN1 (0x9UL) /* TRGM0 input1 */
523 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN2 (0xAUL) /* TRGM0 input2 */
524 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN3 (0xBUL) /* TRGM0 input3 */
525 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN4 (0xCUL) /* TRGM0 input4 */
526 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN5 (0xDUL) /* TRGM0 input5 */
527 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN6 (0xEUL) /* TRGM0 input6 */
528 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN7 (0xFUL) /* TRGM0 input7 */
529 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN8 (0x10UL) /* TRGM0 input8 */
530 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN9 (0x11UL) /* TRGM0 input9 */
531 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN10 (0x12UL) /* TRGM0 input10 */
532 #define HPM_TRGM0_FILTER_SRC_TRGM0_IN11 (0x13UL) /* TRGM0 input11 */
533 
534 /* trgm1_filter mux definitions */
535 #define HPM_TRGM1_FILTER_SRC_PWM1_IN0 (0x0UL) /* PWM1 capture in0 */
536 #define HPM_TRGM1_FILTER_SRC_PWM1_IN1 (0x1UL) /* PWM1 capture in1 */
537 #define HPM_TRGM1_FILTER_SRC_PWM1_IN2 (0x2UL) /* PWM1 capture in2 */
538 #define HPM_TRGM1_FILTER_SRC_PWM1_IN3 (0x3UL) /* PWM1 capture in3 */
539 #define HPM_TRGM1_FILTER_SRC_PWM1_IN4 (0x4UL) /* PWM1 capture in4 */
540 #define HPM_TRGM1_FILTER_SRC_PWM1_IN5 (0x5UL) /* PWM1 capture in5 */
541 #define HPM_TRGM1_FILTER_SRC_PWM1_IN6 (0x6UL) /* PWM1 capture in6 */
542 #define HPM_TRGM1_FILTER_SRC_PWM1_IN7 (0x7UL) /* PWM1 capture in7 */
543 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN0 (0x8UL) /* TRGM1 input0 */
544 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN1 (0x9UL) /* TRGM1 input1 */
545 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN2 (0xAUL) /* TRGM1 input2 */
546 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN3 (0xBUL) /* TRGM1 input3 */
547 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN4 (0xCUL) /* TRGM1 input4 */
548 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN5 (0xDUL) /* TRGM1 input5 */
549 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN6 (0xEUL) /* TRGM1 input6 */
550 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN7 (0xFUL) /* TRGM1 input7 */
551 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN8 (0x10UL) /* TRGM1 input8 */
552 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN9 (0x11UL) /* TRGM1 input9 */
553 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN10 (0x12UL) /* TRGM1 input10 */
554 #define HPM_TRGM1_FILTER_SRC_TRGM1_IN11 (0x13UL) /* TRGM1 input11 */
555 
556 /* trgm2_filter mux definitions */
557 #define HPM_TRGM2_FILTER_SRC_PWM2_IN0 (0x0UL) /* PWM0 capture in0 */
558 #define HPM_TRGM2_FILTER_SRC_PWM2_IN1 (0x1UL) /* PWM0 capture in1 */
559 #define HPM_TRGM2_FILTER_SRC_PWM2_IN2 (0x2UL) /* PWM0 capture in2 */
560 #define HPM_TRGM2_FILTER_SRC_PWM2_IN3 (0x3UL) /* PWM0 capture in3 */
561 #define HPM_TRGM2_FILTER_SRC_PWM2_IN4 (0x4UL) /* PWM0 capture in4 */
562 #define HPM_TRGM2_FILTER_SRC_PWM2_IN5 (0x5UL) /* PWM0 capture in5 */
563 #define HPM_TRGM2_FILTER_SRC_PWM2_IN6 (0x6UL) /* PWM0 capture in6 */
564 #define HPM_TRGM2_FILTER_SRC_PWM2_IN7 (0x7UL) /* PWM0 capture in7 */
565 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN0 (0x8UL) /* TRGM2 input0 */
566 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN1 (0x9UL) /* TRGM2 input1 */
567 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN2 (0xAUL) /* TRGM2 input2 */
568 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN3 (0xBUL) /* TRGM2 input3 */
569 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN4 (0xCUL) /* TRGM2 input4 */
570 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN5 (0xDUL) /* TRGM2 input5 */
571 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN6 (0xEUL) /* TRGM2 input6 */
572 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN7 (0xFUL) /* TRGM2 input7 */
573 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN8 (0x10UL) /* TRGM2 input8 */
574 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN9 (0x11UL) /* TRGM2 input9 */
575 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN10 (0x12UL) /* TRGM2 input10 */
576 #define HPM_TRGM2_FILTER_SRC_TRGM2_IN11 (0x13UL) /* TRGM2 input11 */
577 
578 /* trgm3_filter mux definitions */
579 #define HPM_TRGM3_FILTER_SRC_PWM3_IN0 (0x0UL) /* PWM3 capture in0 */
580 #define HPM_TRGM3_FILTER_SRC_PWM3_IN1 (0x1UL) /* PWM3 capture in1 */
581 #define HPM_TRGM3_FILTER_SRC_PWM3_IN2 (0x2UL) /* PWM3 capture in2 */
582 #define HPM_TRGM3_FILTER_SRC_PWM3_IN3 (0x3UL) /* PWM3 capture in3 */
583 #define HPM_TRGM3_FILTER_SRC_PWM3_IN4 (0x4UL) /* PWM3 capture in4 */
584 #define HPM_TRGM3_FILTER_SRC_PWM3_IN5 (0x5UL) /* PWM3 capture in5 */
585 #define HPM_TRGM3_FILTER_SRC_PWM3_IN6 (0x6UL) /* PWM3 capture in6 */
586 #define HPM_TRGM3_FILTER_SRC_PWM3_IN7 (0x7UL) /* PWM3 capture in7 */
587 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN0 (0x8UL) /* TRGM3 input0 */
588 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN1 (0x9UL) /* TRGM3 input1 */
589 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN2 (0xAUL) /* TRGM3 input2 */
590 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN3 (0xBUL) /* TRGM3 input3 */
591 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN4 (0xCUL) /* TRGM3 input4 */
592 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN5 (0xDUL) /* TRGM3 input5 */
593 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN6 (0xEUL) /* TRGM3 input6 */
594 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN7 (0xFUL) /* TRGM3 input7 */
595 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN8 (0x10UL) /* TRGM3 input8 */
596 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN9 (0x11UL) /* TRGM3 input9 */
597 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN10 (0x12UL) /* TRGM3 input10 */
598 #define HPM_TRGM3_FILTER_SRC_TRGM3_IN11 (0x13UL) /* TRGM3 input11 */
599 
600 /* trgm0_dma mux definitions */
601 #define HPM_TRGM0_DMA_SRC_PWM0_CMP0 (0x0UL) /* PWM0 CMP0 capture in or CMP0 comparison result of compare value and timer value */
602 #define HPM_TRGM0_DMA_SRC_PWM0_CMP1 (0x1UL) /* PWM0 CMP1 capture in or CMP1 comparison result of compare value and timer value */
603 #define HPM_TRGM0_DMA_SRC_PWM0_CMP2 (0x2UL) /* PWM0 CMP2 capture in or CMP2 comparison result of compare value and timer value */
604 #define HPM_TRGM0_DMA_SRC_PWM0_CMP3 (0x3UL) /* PWM0 CMP3 capture in or CMP3 comparison result of compare value and timer value */
605 #define HPM_TRGM0_DMA_SRC_PWM0_CMP4 (0x4UL) /* PWM0 CMP4 capture in or CMP4 comparison result of compare value and timer value */
606 #define HPM_TRGM0_DMA_SRC_PWM0_CMP5 (0x5UL) /* PWM0 CMP5 capture in or CMP5 comparison result of compare value and timer value */
607 #define HPM_TRGM0_DMA_SRC_PWM0_CMP6 (0x6UL) /* PWM0 CMP6 capture in or CMP6 comparison result of compare value and timer value */
608 #define HPM_TRGM0_DMA_SRC_PWM0_CMP7 (0x7UL) /* PWM0 CMP7 capture in or CMP7 comparison result of compare value and timer value */
609 #define HPM_TRGM0_DMA_SRC_PWM0_CMP8 (0x8UL) /* PWM0 CMP8 capture in or CMP8 comparison result of compare value and timer value */
610 #define HPM_TRGM0_DMA_SRC_PWM0_CMP9 (0x9UL) /* PWM0 CMP9 capture in or CMP9 comparison result of compare value and timer value */
611 #define HPM_TRGM0_DMA_SRC_PWM0_CMP10 (0xAUL) /* PWM0 CMP10 capture in or CMP10 comparison result of compare value and timer value */
612 #define HPM_TRGM0_DMA_SRC_PWM0_CMP11 (0xBUL) /* PWM0 CMP11 capture in or CMP11 comparison result of compare value and timer value */
613 #define HPM_TRGM0_DMA_SRC_PWM0_CMP12 (0xCUL) /* PWM0 CMP12 capture in or CMP12 comparison result of compare value and timer value */
614 #define HPM_TRGM0_DMA_SRC_PWM0_CMP13 (0xDUL) /* PWM0 CMP13 capture in or CMP13 comparison result of compare value and timer value */
615 #define HPM_TRGM0_DMA_SRC_PWM0_CMP14 (0xEUL) /* PWM0 CMP14 capture in or CMP14 comparison result of compare value and timer value */
616 #define HPM_TRGM0_DMA_SRC_PWM0_CMP15 (0xFUL) /* PWM0 CMP15 capture in or CMP15 comparison result of compare value and timer value */
617 #define HPM_TRGM0_DMA_SRC_PWM0_CMP16 (0x10UL) /* PWM0 CMP16 capture in or CMP16 comparison result of compare value and timer value */
618 #define HPM_TRGM0_DMA_SRC_PWM0_CMP17 (0x11UL) /* PWM0 CMP17 capture in or CMP17 comparison result of compare value and timer value */
619 #define HPM_TRGM0_DMA_SRC_PWM0_CMP18 (0x12UL) /* PWM0 CMP18 capture in or CMP18 comparison result of compare value and timer value */
620 #define HPM_TRGM0_DMA_SRC_PWM0_CMP19 (0x13UL) /* PWM0 CMP19 capture in or CMP19 comparison result of compare value and timer value */
621 #define HPM_TRGM0_DMA_SRC_PWM0_CMP20 (0x14UL) /* PWM0 CMP20 capture in or CMP20 comparison result of compare value and timer value */
622 #define HPM_TRGM0_DMA_SRC_PWM0_CMP21 (0x15UL) /* PWM0 CMP21 capture in or CMP21 comparison result of compare value and timer value */
623 #define HPM_TRGM0_DMA_SRC_PWM0_CMP22 (0x16UL) /* PWM0 CMP22 capture in or CMP22 comparison result of compare value and timer value */
624 #define HPM_TRGM0_DMA_SRC_PWM0_CMP23 (0x17UL) /* PWM0 CMP23 capture in or CMP23 comparison result of compare value and timer value */
625 #define HPM_TRGM0_DMA_SRC_PWM0_RLD (0x18UL) /* PWM0 main count reload */
626 #define HPM_TRGM0_DMA_SRC_PWM0_HALFRLD (0x19UL) /* PWM0 count half reload */
627 #define HPM_TRGM0_DMA_SRC_PWM0_XRLD (0x1AUL) /* PWM0 main count xreload */
628 #define HPM_TRGM0_DMA_SRC_QEI0 (0x1BUL) /* QEI0 dma request */
629 #define HPM_TRGM0_DMA_SRC_HALL0 (0x1CUL) /* HALL0 dma request */
630 
631 /* trgm1_dma mux definitions */
632 #define HPM_TRGM1_DMA_SRC_PWM1_CMP0 (0x0UL) /* PWM1 CMP0 capture in or CMP0 comparison result of compare value and timer value */
633 #define HPM_TRGM1_DMA_SRC_PWM1_CMP1 (0x1UL) /* PWM1 CMP1 capture in or CMP1 comparison result of compare value and timer value */
634 #define HPM_TRGM1_DMA_SRC_PWM1_CMP2 (0x2UL) /* PWM1 CMP2 capture in or CMP2 comparison result of compare value and timer value */
635 #define HPM_TRGM1_DMA_SRC_PWM1_CMP3 (0x3UL) /* PWM1 CMP3 capture in or CMP3 comparison result of compare value and timer value */
636 #define HPM_TRGM1_DMA_SRC_PWM1_CMP4 (0x4UL) /* PWM1 CMP4 capture in or CMP4 comparison result of compare value and timer value */
637 #define HPM_TRGM1_DMA_SRC_PWM1_CMP5 (0x5UL) /* PWM1 CMP5 capture in or CMP5 comparison result of compare value and timer value */
638 #define HPM_TRGM1_DMA_SRC_PWM1_CMP6 (0x6UL) /* PWM1 CMP6 capture in or CMP6 comparison result of compare value and timer value */
639 #define HPM_TRGM1_DMA_SRC_PWM1_CMP7 (0x7UL) /* PWM1 CMP7 capture in or CMP7 comparison result of compare value and timer value */
640 #define HPM_TRGM1_DMA_SRC_PWM1_CMP8 (0x8UL) /* PWM1 CMP8 capture in or CMP8 comparison result of compare value and timer value */
641 #define HPM_TRGM1_DMA_SRC_PWM1_CMP9 (0x9UL) /* PWM1 CMP9 capture in or CMP9 comparison result of compare value and timer value */
642 #define HPM_TRGM1_DMA_SRC_PWM1_CMP10 (0xAUL) /* PWM1 CMP10 capture in or CMP10 comparison result of compare value and timer value */
643 #define HPM_TRGM1_DMA_SRC_PWM1_CMP11 (0xBUL) /* PWM1 CMP11 capture in or CMP11 comparison result of compare value and timer value */
644 #define HPM_TRGM1_DMA_SRC_PWM1_CMP12 (0xCUL) /* PWM1 CMP12 capture in or CMP12 comparison result of compare value and timer value */
645 #define HPM_TRGM1_DMA_SRC_PWM1_CMP13 (0xDUL) /* PWM1 CMP13 capture in or CMP13 comparison result of compare value and timer value */
646 #define HPM_TRGM1_DMA_SRC_PWM1_CMP14 (0xEUL) /* PWM1 CMP14 capture in or CMP14 comparison result of compare value and timer value */
647 #define HPM_TRGM1_DMA_SRC_PWM1_CMP15 (0xFUL) /* PWM1 CMP15 capture in or CMP15 comparison result of compare value and timer value */
648 #define HPM_TRGM1_DMA_SRC_PWM1_CMP16 (0x10UL) /* PWM1 CMP16 capture in or CMP16 comparison result of compare value and timer value */
649 #define HPM_TRGM1_DMA_SRC_PWM1_CMP17 (0x11UL) /* PWM1 CMP17 capture in or CMP17 comparison result of compare value and timer value */
650 #define HPM_TRGM1_DMA_SRC_PWM1_CMP18 (0x12UL) /* PWM1 CMP18 capture in or CMP18 comparison result of compare value and timer value */
651 #define HPM_TRGM1_DMA_SRC_PWM1_CMP19 (0x13UL) /* PWM1 CMP19 capture in or CMP19 comparison result of compare value and timer value */
652 #define HPM_TRGM1_DMA_SRC_PWM1_CMP20 (0x14UL) /* PWM1 CMP20 capture in or CMP20 comparison result of compare value and timer value */
653 #define HPM_TRGM1_DMA_SRC_PWM1_CMP21 (0x15UL) /* PWM1 CMP21 capture in or CMP21 comparison result of compare value and timer value */
654 #define HPM_TRGM1_DMA_SRC_PWM1_CMP22 (0x16UL) /* PWM1 CMP22 capture in or CMP22 comparison result of compare value and timer value */
655 #define HPM_TRGM1_DMA_SRC_PWM1_CMP23 (0x17UL) /* PWM1 CMP23 capture in or CMP23 comparison result of compare value and timer value */
656 #define HPM_TRGM1_DMA_SRC_PWM1_RLD (0x18UL) /* PWM1 main count reload */
657 #define HPM_TRGM1_DMA_SRC_PWM1_HALFRLD (0x19UL) /* PWM1 count half reload */
658 #define HPM_TRGM1_DMA_SRC_PWM1_XRLD (0x1AUL) /* PWM1 main count xreload */
659 #define HPM_TRGM1_DMA_SRC_QEI1 (0x1BUL) /* QEI1 dma request */
660 #define HPM_TRGM1_DMA_SRC_HALL1 (0x1CUL) /* HALL1 dma request */
661 
662 /* trgm2_dma mux definitions */
663 #define HPM_TRGM2_DMA_SRC_PWM2_CMP0 (0x0UL) /* PWM2 CMP0 capture in or CMP0 comparison result of compare value and timer value */
664 #define HPM_TRGM2_DMA_SRC_PWM2_CMP1 (0x1UL) /* PWM2 CMP1 capture in or CMP1 comparison result of compare value and timer value */
665 #define HPM_TRGM2_DMA_SRC_PWM2_CMP2 (0x2UL) /* PWM2 CMP2 capture in or CMP2 comparison result of compare value and timer value */
666 #define HPM_TRGM2_DMA_SRC_PWM2_CMP3 (0x3UL) /* PWM2 CMP3 capture in or CMP3 comparison result of compare value and timer value */
667 #define HPM_TRGM2_DMA_SRC_PWM2_CMP4 (0x4UL) /* PWM2 CMP4 capture in or CMP4 comparison result of compare value and timer value */
668 #define HPM_TRGM2_DMA_SRC_PWM2_CMP5 (0x5UL) /* PWM2 CMP5 capture in or CMP5 comparison result of compare value and timer value */
669 #define HPM_TRGM2_DMA_SRC_PWM2_CMP6 (0x6UL) /* PWM2 CMP6 capture in or CMP6 comparison result of compare value and timer value */
670 #define HPM_TRGM2_DMA_SRC_PWM2_CMP7 (0x7UL) /* PWM2 CMP7 capture in or CMP7 comparison result of compare value and timer value */
671 #define HPM_TRGM2_DMA_SRC_PWM2_CMP8 (0x8UL) /* PWM2 CMP8 capture in or CMP8 comparison result of compare value and timer value */
672 #define HPM_TRGM2_DMA_SRC_PWM2_CMP9 (0x9UL) /* PWM2 CMP9 capture in or CMP9 comparison result of compare value and timer value */
673 #define HPM_TRGM2_DMA_SRC_PWM2_CMP10 (0xAUL) /* PWM2 CMP10 capture in or CMP10 comparison result of compare value and timer value */
674 #define HPM_TRGM2_DMA_SRC_PWM2_CMP11 (0xBUL) /* PWM2 CMP11 capture in or CMP11 comparison result of compare value and timer value */
675 #define HPM_TRGM2_DMA_SRC_PWM2_CMP12 (0xCUL) /* PWM2 CMP12 capture in or CMP12 comparison result of compare value and timer value */
676 #define HPM_TRGM2_DMA_SRC_PWM2_CMP13 (0xDUL) /* PWM2 CMP13 capture in or CMP13 comparison result of compare value and timer value */
677 #define HPM_TRGM2_DMA_SRC_PWM2_CMP14 (0xEUL) /* PWM2 CMP14 capture in or CMP14 comparison result of compare value and timer value */
678 #define HPM_TRGM2_DMA_SRC_PWM2_CMP15 (0xFUL) /* PWM2 CMP15 capture in or CMP15 comparison result of compare value and timer value */
679 #define HPM_TRGM2_DMA_SRC_PWM2_CMP16 (0x10UL) /* PWM2 CMP16 capture in or CMP16 comparison result of compare value and timer value */
680 #define HPM_TRGM2_DMA_SRC_PWM2_CMP17 (0x11UL) /* PWM2 CMP17 capture in or CMP17 comparison result of compare value and timer value */
681 #define HPM_TRGM2_DMA_SRC_PWM2_CMP18 (0x12UL) /* PWM2 CMP18 capture in or CMP18 comparison result of compare value and timer value */
682 #define HPM_TRGM2_DMA_SRC_PWM2_CMP19 (0x13UL) /* PWM2 CMP19 capture in or CMP19 comparison result of compare value and timer value */
683 #define HPM_TRGM2_DMA_SRC_PWM2_CMP20 (0x14UL) /* PWM2 CMP20 capture in or CMP20 comparison result of compare value and timer value */
684 #define HPM_TRGM2_DMA_SRC_PWM2_CMP21 (0x15UL) /* PWM2 CMP21 capture in or CMP21 comparison result of compare value and timer value */
685 #define HPM_TRGM2_DMA_SRC_PWM2_CMP22 (0x16UL) /* PWM2 CMP22 capture in or CMP22 comparison result of compare value and timer value */
686 #define HPM_TRGM2_DMA_SRC_PWM2_CMP23 (0x17UL) /* PWM2 CMP23 capture in or CMP23 comparison result of compare value and timer value */
687 #define HPM_TRGM2_DMA_SRC_PWM2_RLD (0x18UL) /* PWM2 main count reload */
688 #define HPM_TRGM2_DMA_SRC_PWM2_HALFRLD (0x19UL) /* PWM2 count half reload */
689 #define HPM_TRGM2_DMA_SRC_PWM2_XRLD (0x1AUL) /* PWM2 main count xreload */
690 #define HPM_TRGM2_DMA_SRC_QEI2 (0x1BUL) /* QEI2 dma request */
691 #define HPM_TRGM2_DMA_SRC_HALL2 (0x1CUL) /* HALL2 dma request */
692 
693 /* trgm3_dma mux definitions */
694 #define HPM_TRGM3_DMA_SRC_PWM3_CMP0 (0x0UL) /* PWM3 CMP0 capture in or CMP0 comparison result of compare value and timer value */
695 #define HPM_TRGM3_DMA_SRC_PWM3_CMP1 (0x1UL) /* PWM3 CMP1 capture in or CMP1 comparison result of compare value and timer value */
696 #define HPM_TRGM3_DMA_SRC_PWM3_CMP2 (0x2UL) /* PWM3 CMP2 capture in or CMP2 comparison result of compare value and timer value */
697 #define HPM_TRGM3_DMA_SRC_PWM3_CMP3 (0x3UL) /* PWM3 CMP3 capture in or CMP3 comparison result of compare value and timer value */
698 #define HPM_TRGM3_DMA_SRC_PWM3_CMP4 (0x4UL) /* PWM3 CMP4 capture in or CMP4 comparison result of compare value and timer value */
699 #define HPM_TRGM3_DMA_SRC_PWM3_CMP5 (0x5UL) /* PWM3 CMP5 capture in or CMP5 comparison result of compare value and timer value */
700 #define HPM_TRGM3_DMA_SRC_PWM3_CMP6 (0x6UL) /* PWM3 CMP6 capture in or CMP6 comparison result of compare value and timer value */
701 #define HPM_TRGM3_DMA_SRC_PWM3_CMP7 (0x7UL) /* PWM3 CMP7 capture in or CMP7 comparison result of compare value and timer value */
702 #define HPM_TRGM3_DMA_SRC_PWM3_CMP8 (0x8UL) /* PWM3 CMP8 capture in or CMP8 comparison result of compare value and timer value */
703 #define HPM_TRGM3_DMA_SRC_PWM3_CMP9 (0x9UL) /* PWM3 CMP9 capture in or CMP9 comparison result of compare value and timer value */
704 #define HPM_TRGM3_DMA_SRC_PWM3_CMP10 (0xAUL) /* PWM3 CMP10 capture in or CMP10 comparison result of compare value and timer value */
705 #define HPM_TRGM3_DMA_SRC_PWM3_CMP11 (0xBUL) /* PWM3 CMP11 capture in or CMP11 comparison result of compare value and timer value */
706 #define HPM_TRGM3_DMA_SRC_PWM3_CMP12 (0xCUL) /* PWM3 CMP12 capture in or CMP12 comparison result of compare value and timer value */
707 #define HPM_TRGM3_DMA_SRC_PWM3_CMP13 (0xDUL) /* PWM3 CMP13 capture in or CMP13 comparison result of compare value and timer value */
708 #define HPM_TRGM3_DMA_SRC_PWM3_CMP14 (0xEUL) /* PWM3 CMP14 capture in or CMP14 comparison result of compare value and timer value */
709 #define HPM_TRGM3_DMA_SRC_PWM3_CMP15 (0xFUL) /* PWM3 CMP15 capture in or CMP15 comparison result of compare value and timer value */
710 #define HPM_TRGM3_DMA_SRC_PWM3_CMP16 (0x10UL) /* PWM3 CMP16 capture in or CMP16 comparison result of compare value and timer value */
711 #define HPM_TRGM3_DMA_SRC_PWM3_CMP17 (0x11UL) /* PWM3 CMP17 capture in or CMP17 comparison result of compare value and timer value */
712 #define HPM_TRGM3_DMA_SRC_PWM3_CMP18 (0x12UL) /* PWM3 CMP18 capture in or CMP18 comparison result of compare value and timer value */
713 #define HPM_TRGM3_DMA_SRC_PWM3_CMP19 (0x13UL) /* PWM3 CMP19 capture in or CMP19 comparison result of compare value and timer value */
714 #define HPM_TRGM3_DMA_SRC_PWM3_CMP20 (0x14UL) /* PWM3 CMP20 capture in or CMP20 comparison result of compare value and timer value */
715 #define HPM_TRGM3_DMA_SRC_PWM3_CMP21 (0x15UL) /* PWM3 CMP21 capture in or CMP21 comparison result of compare value and timer value */
716 #define HPM_TRGM3_DMA_SRC_PWM3_CMP22 (0x16UL) /* PWM3 CMP22 capture in or CMP22 comparison result of compare value and timer value */
717 #define HPM_TRGM3_DMA_SRC_PWM3_CMP23 (0x17UL) /* PWM3 CMP23 capture in or CMP23 comparison result of compare value and timer value */
718 #define HPM_TRGM3_DMA_SRC_PWM3_RLD (0x18UL) /* PWM3 main count reload */
719 #define HPM_TRGM3_DMA_SRC_PWM3_HALFRLD (0x19UL) /* PWM3 count half reload */
720 #define HPM_TRGM3_DMA_SRC_PWM3_XRLD (0x1AUL) /* PWM3 main count xreload */
721 #define HPM_TRGM3_DMA_SRC_QEI3 (0x1BUL) /* QEI3 dma request */
722 #define HPM_TRGM3_DMA_SRC_HALL3 (0x1CUL) /* HALL3 dma request */
723 
724 
725 
726 #endif /* HPM_TRGMMUX_SRC_H */