hpm_pcfg_drv.h

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/*
 * Copyright (c) 2021 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_PCFG_DRV_H
#define HPM_PCFG_DRV_H
 
#include "hpm_common.h"
#include "hpm_pcfg_regs.h"
 
#define PCFG_CLOCK_GATE_MODE_ALWAYS_ON          (0x3UL)
#define PCFG_CLOCK_GATE_MODE_ALWAYS_OFF         (0x2UL)
 
#define PCFG_PERIPH_KEEP_CLOCK_ON(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_ON << (p))
#define PCFG_PERIPH_KEEP_CLOCK_OFF(p) (PCFG_CLOCK_GATE_MODE_ALWAYS_OFF << (p))
 
/* @brief PCFG irc24m reference */
typedef enum {
    pcfg_irc24m_reference_32k = 0,
    pcfg_irc24m_reference_24m_xtal = 1
} pcfg_irc24m_reference_t;
 
/* @brief PCFG dcdc current limit */
typedef enum {
    pcfg_dcdc_lp_current_limit_250ma = 0,
    pcfg_dcdc_lp_current_limit_200ma = 1,
} pcfg_dcdc_lp_current_limit_t;
 
typedef enum {
    pcfg_dcdc_oc_limit_2000ma = 0,
    pcfg_dcdc_oc_limit_1300ma = 1,
} pcfg_dcdc_oc_limit_t;
 
/* @brief PCFG dcdc current hys */
typedef enum {
    pcfg_dcdc_current_hys_12_5mv = 0,
    pcfg_dcdc_current_hys_25mv = 1,
} pcfg_dcdc_current_hys_t;
 
/* @brief PCFG dcdc mode */
typedef enum {
    pcfg_dcdc_mode_off = 0,
    pcfg_dcdc_mode_basic = 1,
    pcfg_dcdc_mode_general = 3,
    pcfg_dcdc_mode_expert = 7,
} pcfg_dcdc_mode_t;
 
/* @brief PCFG pmc domain peripherals */
typedef enum {
    pcfg_pmc_periph_gpio = 6,
    pcfg_pmc_periph_ioc = 8,
    pcfg_pmc_periph_timer = 10,
    pcfg_pmc_periph_wdog = 12,
    pcfg_pmc_periph_uart = 14,
    pcfg_pmc_periph_vad = 16,
    pcfg_pmc_periph_pmic_mem = 18,
} pcfg_pmc_periph_t;
 
/* @brief PCFG wakeup source */
typedef enum {
    pcfg_wakeup_src_puart = (1 << 7),
    pcfg_wakeup_src_ptimer = (1 << 8),
    pcfg_wakeup_src_pwdg = (1 << 9),
    pcfg_wakeup_src_pgpio = (1 << 10),
} pcfg_wakeup_src_t;
 
/* @brief PCFG status */
enum {
    status_pcfg_ldo_out_of_range = MAKE_STATUS(status_group_pcfg, 1),
};
 
/* @brief PCFG irc24m config */
typedef struct {
    uint32_t freq_in_hz;
    pcfg_irc24m_reference_t reference;
    bool return_to_default_on_xtal_loss;
    bool free_run;
} pcfg_irc24m_config_t;
 
 
#define PCFG_CLOCK_GATE_CONTROL_MASK(module, mode) \
    ((uint32_t) (mode) << ((module) << 1))
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void pcfg_bandgap_disable_power_save_mode(PCFG_Type *ptr)
{
    ptr->BANDGAP &= ~PCFG_BANDGAP_POWER_SAVE_MASK;
}
 
static inline void pcfg_bandgap_enable_power_save_mode(PCFG_Type *ptr)
{
    ptr->BANDGAP |= PCFG_BANDGAP_POWER_SAVE_MASK;
}
 
static inline void pcfg_bandgap_disable_lowpower_mode(PCFG_Type *ptr)
{
    ptr->BANDGAP &= ~PCFG_BANDGAP_LOWPOWER_MODE_MASK;
}
 
static inline void pcfg_bandgap_enable_lowpower_mode(PCFG_Type *ptr)
{
    ptr->BANDGAP |= PCFG_BANDGAP_LOWPOWER_MODE_MASK;
}
 
static inline bool pcfg_bandgap_is_trimmed(PCFG_Type *ptr)
{
    return ptr->BANDGAP & PCFG_BANDGAP_VBG_TRIMMED_MASK;
}
 
static inline void pcfg_bandgap_reload_trim(PCFG_Type *ptr)
{
    ptr->BANDGAP &= ~PCFG_BANDGAP_VBG_TRIMMED_MASK;
}
 
static inline void pcfg_ldo2p5_turn_off(PCFG_Type *ptr)
{
    ptr->LDO2P5 &= ~PCFG_LDO2P5_ENABLE_MASK;
}
 
static inline void pcfg_ldo2p5_turn_on(PCFG_Type *ptr)
{
    ptr->LDO2P5 |= PCFG_LDO2P5_ENABLE_MASK;
}
 
static inline bool pcfg_ldo2p5_is_stable(PCFG_Type *ptr)
{
    return PCFG_LDO2P5_READY_GET(ptr->LDO2P5);
}
 
/*
 * @brief check if DCDC is stable or not
 * @param[in] ptr base address
 * @retval true if DCDC is stable
 */
static inline bool pcfg_dcdc_is_stable(PCFG_Type *ptr)
{
    return PCFG_DCDC_MODE_READY_GET(ptr->DCDC_MODE);
}
 
/*
 * @brief set DCDC work mode
 * @param[in] ptr base address
 */
static inline void pcfg_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode)
{
    ptr->DCDC_MODE = (ptr->DCDC_MODE & ~PCFG_DCDC_MODE_MODE_MASK) | PCFG_DCDC_MODE_MODE_SET(mode);
}
 
static inline void pcfg_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit, bool over_limit)
{
    (void) over_limit;
    ptr->DCDC_PROT = (ptr->DCDC_PROT & ~(PCFG_DCDC_PROT_ILIMIT_LP_MASK))
        | PCFG_DCDC_PROT_ILIMIT_LP_SET(limit);
}
 
static inline void pcfg_dcdc_disable_power_loss_prot(PCFG_Type *ptr)
{
    ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK;
}
 
static inline void pcfg_dcdc_enable_power_loss_prot(PCFG_Type *ptr)
{
    ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_POWER_LOSS_MASK;
}
 
static inline bool pcfg_dcdc_is_power_loss(PCFG_Type *ptr)
{
    return PCFG_DCDC_PROT_POWER_LOSS_FLAG_GET(ptr->DCDC_PROT);
}
 
static inline void pcfg_dcdc_disable_over_voltage_prot(PCFG_Type *ptr)
{
    ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK;
}
 
static inline void pcfg_dcdc_enable_over_voltage_prot(PCFG_Type *ptr)
{
    ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_OVERVOLTAGE_MASK;
}
 
static inline bool pcfg_dcdc_is_over_voltage(PCFG_Type *ptr)
{
    return PCFG_DCDC_PROT_OVERVOLT_FLAG_GET(ptr->DCDC_PROT);
}
 
static inline void pcfg_dcdc_disable_over_current_prot(PCFG_Type *ptr)
{
    ptr->DCDC_PROT |= PCFG_DCDC_PROT_DISABLE_SHORT_MASK;
}
 
static inline void pcfg_dcdc_enable_over_current_prot(PCFG_Type *ptr)
{
    ptr->DCDC_PROT &= ~PCFG_DCDC_PROT_DISABLE_SHORT_MASK;
}
 
static inline void pcfg_dcdc_set_over_current_limit(PCFG_Type *ptr, pcfg_dcdc_oc_limit_t limit)
{
    ptr->DCDC_PROT = (ptr->DCDC_PROT & ~PCFG_DCDC_PROT_SHORT_CURRENT_MASK) | PCFG_DCDC_PROT_SHORT_CURRENT_SET(limit);
}
 
static inline bool pcfg_dcdc_is_over_current(PCFG_Type *ptr)
{
    return PCFG_DCDC_PROT_SHORT_FLAG_GET(ptr->DCDC_PROT);
}
 
static inline void pcfg_dcdc_disable_measure_current(PCFG_Type *ptr)
{
    ptr->DCDC_CURRENT &= ~PCFG_DCDC_CURRENT_ESTI_EN_MASK;
}
 
static inline void pcfg_dcdc_enable_measure_current(PCFG_Type *ptr)
{
    ptr->DCDC_CURRENT |= PCFG_DCDC_CURRENT_ESTI_EN_MASK;
}
 
static inline bool pcfg_dcdc_is_measure_current_valid(PCFG_Type *ptr)
{
    return ptr->DCDC_CURRENT & PCFG_DCDC_CURRENT_VALID_MASK;
}
 
static inline bool pcfg_dcdc_get_measured_current_level(PCFG_Type *ptr)
{
    return PCFG_DCDC_CURRENT_LEVEL_GET(ptr->DCDC_CURRENT);
}
 
static inline uint32_t pcfg_dcdc_get_start_time_in_cycle(PCFG_Type *ptr)
{
    return PCFG_DCDC_START_TIME_START_TIME_GET(ptr->DCDC_START_TIME);
}
 
static inline uint32_t pcfg_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr)
{
    return PCFG_DCDC_RESUME_TIME_RESUME_TIME_GET(ptr->DCDC_RESUME_TIME);
}
 
static inline void pcfg_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles)
{
    ptr->DCDC_START_TIME = PCFG_DCDC_START_TIME_START_TIME_SET(cycles);
}
 
static inline void pcfg_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles)
{
    ptr->DCDC_RESUME_TIME = PCFG_DCDC_RESUME_TIME_RESUME_TIME_SET(cycles);
}
 
static inline void pcfg_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range)
{
    ptr->DCDC_MISC = (ptr->DCDC_MISC & (~PCFG_DCDC_MISC_OL_HYST_MASK)) | PCFG_DCDC_MISC_OL_HYST_SET(range);
}
 
static inline void pcfg_disable_power_trap(PCFG_Type *ptr)
{
    ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_TRAP_MASK;
}
 
static inline void pcfg_enable_power_trap(PCFG_Type *ptr)
{
    ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRAP_MASK;
}
 
static inline bool pcfg_is_power_trap_triggered(PCFG_Type *ptr)
{
    return ptr->POWER_TRAP & PCFG_POWER_TRAP_TRIGGERED_MASK;
}
 
static inline void pcfg_clear_power_trap_trigger_flag(PCFG_Type *ptr)
{
    ptr->POWER_TRAP |= PCFG_POWER_TRAP_TRIGGERED_MASK;
}
 
static inline void pcfg_disable_dcdc_retention(PCFG_Type *ptr)
{
    ptr->POWER_TRAP &= ~PCFG_POWER_TRAP_RETENTION_MASK;
}
 
static inline void pcfg_enable_dcdc_retention(PCFG_Type *ptr)
{
    ptr->POWER_TRAP |= PCFG_POWER_TRAP_RETENTION_MASK;
}
 
static inline void pcfg_clear_wakeup_cause(PCFG_Type *ptr, uint32_t mask)
{
    ptr->WAKE_CAUSE |= mask;
}
 
static inline uint32_t pcfg_get_wakeup_cause(PCFG_Type *ptr)
{
    return ptr->WAKE_CAUSE;
}
 
static inline void pcfg_enable_wakeup_source(PCFG_Type *ptr, uint32_t mask)
{
    ptr->WAKE_MASK &= ~mask;
}
 
static inline void pcfg_disable_wakeup_source(PCFG_Type *ptr, uint32_t mask)
{
    ptr->WAKE_MASK |= mask;
}
 
static inline void pcfg_set_periph_clock_mode(PCFG_Type *ptr, uint32_t mode)
{
    ptr->SCG_CTRL = mode;
}
 
static inline void pcfg_update_periph_clock_mode(PCFG_Type *ptr, pcfg_pmc_periph_t periph, bool on)
{
    if (on) {
        ptr->SCG_CTRL = (ptr->SCG_CTRL & ~(0x03 << periph)) | PCFG_PERIPH_KEEP_CLOCK_ON(periph);
    } else {
        ptr->SCG_CTRL = (ptr->SCG_CTRL & ~(0x03 << periph)) | PCFG_PERIPH_KEEP_CLOCK_OFF(periph);
    }
}
 
/*
 * @brief check if DDR DCDC is stable or not
 * @param[in] ptr base address
 * @retval true if DDR DCDC is stable
 */
static inline bool pcfg_ddr_dcdc_is_stable(PCFG_Type *ptr)
{
    return PCFG_DCDCM_MODE_READY_GET(ptr->DCDCM_MODE);
}
 
/*
 * @brief set DDR DCDC work mode
 * @param[in] ptr base address
 */
static inline void pcfg_ddr_dcdc_set_mode(PCFG_Type *ptr, uint8_t mode)
{
    ptr->DCDCM_MODE = (ptr->DCDCM_MODE & ~PCFG_DCDCM_MODE_MODE_MASK) | PCFG_DCDCM_MODE_MODE_SET(mode);
}
 
 
/*
 * @brief set on-chip DDR DCDC enable and voltage
 * @param[in] ptr base address
 * @param[in] voltage unit mv
 */
static inline void pcfg_ddr_dcdc_set_voltage_output(PCFG_Type *ptr, uint8_t voltage)
{
    ptr->DCDCM_MODE = (ptr->DCDCM_MODE & ~(PCFG_DCDCM_MODE_VOLT_MASK | PCFG_DCDCM_MODE_MODE_MASK))
                        | PCFG_DCDCM_MODE_VOLT_SET(voltage) | PCFG_DCDCM_MODE_MODE_SET(pcfg_dcdc_mode_basic);
}
 
static inline void pcfg_ddr_dcdc_set_lp_current_limit(PCFG_Type *ptr, pcfg_dcdc_lp_current_limit_t limit)
{
    ptr->DCDCM_PROT = (ptr->DCDCM_PROT & ~(PCFG_DCDCM_PROT_ILIMIT_LP_MASK))
        | PCFG_DCDCM_PROT_ILIMIT_LP_SET(limit);
}
 
static inline void pcfg_ddr_dcdc_disable_power_loss_prot(PCFG_Type *ptr)
{
    ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK;
}
 
static inline void pcfg_ddr_dcdc_enable_power_loss_prot(PCFG_Type *ptr)
{
    ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_POWER_LOSS_MASK;
}
 
static inline bool pcfg_ddr_dcdc_is_power_loss(PCFG_Type *ptr)
{
    return PCFG_DCDCM_PROT_POWER_LOSS_FLAG_GET(ptr->DCDCM_PROT);
}
 
static inline void pcfg_ddr_dcdc_disable_over_voltage_prot(PCFG_Type *ptr)
{
    ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK;
}
 
static inline void pcfg_ddr_dcdc_enable_over_voltage_prot(PCFG_Type *ptr)
{
    ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_OVERVOLTAGE_MASK;
}
 
static inline bool pcfg_ddr_dcdc_is_over_voltage(PCFG_Type *ptr)
{
    return PCFG_DCDCM_PROT_OVERVOLT_FLAG_GET(ptr->DCDCM_PROT);
}
 
static inline void pcfg_ddr_dcdc_disable_over_current_prot(PCFG_Type *ptr)
{
    ptr->DCDCM_PROT |= PCFG_DCDCM_PROT_DISABLE_SHORT_MASK;
}
 
static inline void pcfg_ddr_dcdc_enable_over_current_prot(PCFG_Type *ptr)
{
    ptr->DCDCM_PROT &= ~PCFG_DCDCM_PROT_DISABLE_SHORT_MASK;
}
 
static inline void pcfg_ddr_dcdc_set_over_current_limit(PCFG_Type *ptr, pcfg_dcdc_oc_limit_t limit)
{
    ptr->DCDCM_PROT = (ptr->DCDCM_PROT & ~PCFG_DCDCM_PROT_SHORT_CURRENT_MASK) | PCFG_DCDCM_PROT_SHORT_CURRENT_SET(limit);
}
 
static inline bool pcfg_ddr_dcdc_is_over_current(PCFG_Type *ptr)
{
    return PCFG_DCDCM_PROT_SHORT_FLAG_GET(ptr->DCDCM_PROT);
}
 
static inline void pcfg_ddr_dcdc_disable_measure_current(PCFG_Type *ptr)
{
    ptr->DCDCM_CURRENT &= ~PCFG_DCDCM_CURRENT_ESTI_EN_MASK;
}
 
static inline void pcfg_ddr_dcdc_enable_measure_current(PCFG_Type *ptr)
{
    ptr->DCDCM_CURRENT |= PCFG_DCDCM_CURRENT_ESTI_EN_MASK;
}
 
static inline bool pcfg_ddr_dcdc_is_measure_current_valid(PCFG_Type *ptr)
{
    return ptr->DCDCM_CURRENT & PCFG_DCDCM_CURRENT_VALID_MASK;
}
 
static inline bool pcfg_ddr_dcdc_get_measured_current_level(PCFG_Type *ptr)
{
    return PCFG_DCDCM_CURRENT_LEVEL_GET(ptr->DCDCM_CURRENT);
}
 
static inline uint32_t pcfg_ddr_dcdc_get_start_time_in_cycle(PCFG_Type *ptr)
{
    return PCFG_DCDCM_START_TIME_START_TIME_GET(ptr->DCDCM_START_TIME);
}
 
static inline uint32_t pcfg_ddr_dcdc_get_resume_time_in_cycle(PCFG_Type *ptr)
{
    return PCFG_DCDCM_RESUME_TIME_RESUME_TIME_GET(ptr->DCDCM_RESUME_TIME);
}
 
static inline void pcfg_ddr_dcdc_set_start_time_in_cycle(PCFG_Type *ptr, uint32_t cycles)
{
    ptr->DCDCM_START_TIME = PCFG_DCDCM_START_TIME_START_TIME_SET(cycles);
}
 
static inline void pcfg_ddr_dcdc_set_resume_time_in_cycle(PCFG_Type *ptr, uint32_t cycles)
{
    ptr->DCDCM_RESUME_TIME = PCFG_DCDCM_RESUME_TIME_RESUME_TIME_SET(cycles);
}
 
static inline void pcfg_ddr_dcdc_set_current_hys_range(PCFG_Type *ptr, pcfg_dcdc_current_hys_t range)
{
    ptr->DCDCM_MISC = (ptr->DCDCM_MISC & (~PCFG_DCDCM_MISC_OL_HYST_MASK)) | PCFG_DCDCM_MISC_OL_HYST_SET(range);
}
 
static inline void pcfg_ddr_dcdc_disable_retention(PCFG_Type *ptr)
{
    ptr->DCDCM_POWER_CONFIG &= ~PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK;
}
 
static inline void pcfg_ddr_dcdc_enable_retention(PCFG_Type *ptr)
{
    ptr->DCDCM_POWER_CONFIG |= PCFG_DCDCM_POWER_CONFIG_RETENTION_MASK;
}
 
static inline bool pcfg_irc24m_is_trimmed(PCFG_Type *ptr)
{
    return ptr->RC24M & PCFG_RC24M_RC_TRIMMED_MASK;
}
 
static inline void pcfg_irc24m_reload_trim(PCFG_Type *ptr)
{
    ptr->RC24M &= ~PCFG_RC24M_RC_TRIMMED_MASK;
}
 
void pcfg_irc24m_config_track(PCFG_Type *ptr, pcfg_irc24m_config_t *config);
 
/*
 * @brief set DCDC voltage at standby mode
 * @param[in] ptr base address
 * @param[in] mv target voltage
 * @retval status_success if successfully configured
 */
hpm_stat_t pcfg_dcdc_set_lpmode_voltage(PCFG_Type *ptr, uint16_t mv);
 
/*
 * @brief set output voltage of LDO 2.5V in mV
 * @param[in] ptr base address
 * @param[in] mv target voltage
 * @retval status_success if successfully configured
 */
hpm_stat_t pcfg_ldo2p5_set_voltage(PCFG_Type *ptr, uint16_t mv);
 
/*
 * @brief set DCDC voltage
 * @param[in] ptr base address
 * @param[in] mv target voltage
 * @retval status_success if successfully configured
 */
hpm_stat_t pcfg_dcdc_set_voltage(PCFG_Type *ptr, uint16_t mv);
 
/*
 * @brief set output voltage of LDO 1V in mV
 * @param[in] ptr base address
 * @param[in] mv target voltage
 * @retval status_success if successfully configured
 */
hpm_stat_t pcfg_ldo1p1_set_voltage(PCFG_Type *ptr, uint16_t mv);
 
/*
 * @brief get current DCDC current level in mA
 *
 * @param[in] ptr base address
 * @retval Current level at mA
 */
uint16_t pcfg_dcdc_get_current_level(PCFG_Type *ptr);
 
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_PCFG_DRV_H */