HPM SDK
HPMicro Software Development Kit
hpm_bsec_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_BSEC_H
10 #define HPM_BSEC_H
11 
12 typedef struct {
13  __RW uint32_t SECURE_STATE; /* 0x0: Secure state */
14  __RW uint32_t SECURE_STATE_CONFIG; /* 0x4: secure state configuration */
15  __RW uint32_t VIOLATION_CONFIG; /* 0x8: Security violation config */
16  __RW uint32_t ESCALATE_CONFIG; /* 0xC: Escalate behavior on security event */
17  __R uint32_t EVENT; /* 0x10: Event and escalate status */
18 } BSEC_Type;
19 
20 
21 /* Bitfield definition for register: SECURE_STATE */
22 /*
23  * ALLOW_NSC (RO)
24  *
25  * Non-secure state allow
26  * 0: system is not healthy to enter non-secure state, request to enter non-secure state will cause a fail state
27  * 1: system is healthy to enter non-secure state
28  */
29 #define BSEC_SECURE_STATE_ALLOW_NSC_MASK (0x20000UL)
30 #define BSEC_SECURE_STATE_ALLOW_NSC_SHIFT (17U)
31 #define BSEC_SECURE_STATE_ALLOW_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_NSC_MASK) >> BSEC_SECURE_STATE_ALLOW_NSC_SHIFT)
32 
33 /*
34  * ALLOW_SEC (RO)
35  *
36  * Secure state allow
37  * 0: system is not healthy to enter secure state, request to enter non-secure state will cause a fail state
38  * 1: system is healthy to enter secure state
39  */
40 #define BSEC_SECURE_STATE_ALLOW_SEC_MASK (0x10000UL)
41 #define BSEC_SECURE_STATE_ALLOW_SEC_SHIFT (16U)
42 #define BSEC_SECURE_STATE_ALLOW_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_ALLOW_SEC_MASK) >> BSEC_SECURE_STATE_ALLOW_SEC_SHIFT)
43 
44 /*
45  * BATT_FAIL (RW)
46  *
47  * BATT secure state one hot indicator
48  * 0: secure state is not in fail state
49  * 1: secure state is in fail state
50  */
51 #define BSEC_SECURE_STATE_BATT_FAIL_MASK (0x8U)
52 #define BSEC_SECURE_STATE_BATT_FAIL_SHIFT (3U)
53 #define BSEC_SECURE_STATE_BATT_FAIL_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_FAIL_SHIFT) & BSEC_SECURE_STATE_BATT_FAIL_MASK)
54 #define BSEC_SECURE_STATE_BATT_FAIL_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_FAIL_MASK) >> BSEC_SECURE_STATE_BATT_FAIL_SHIFT)
55 
56 /*
57  * BATT_NSC (RW)
58  *
59  * BATT secure state one hot indicator
60  * 0: secure state is not in non-secure state
61  * 1: secure state is in non-secure state
62  */
63 #define BSEC_SECURE_STATE_BATT_NSC_MASK (0x4U)
64 #define BSEC_SECURE_STATE_BATT_NSC_SHIFT (2U)
65 #define BSEC_SECURE_STATE_BATT_NSC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_NSC_SHIFT) & BSEC_SECURE_STATE_BATT_NSC_MASK)
66 #define BSEC_SECURE_STATE_BATT_NSC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_NSC_MASK) >> BSEC_SECURE_STATE_BATT_NSC_SHIFT)
67 
68 /*
69  * BATT_SEC (RW)
70  *
71  * BATT secure state one hot indicator
72  * 0: secure state is not in secure state
73  * 1: secure state is in secure state
74  */
75 #define BSEC_SECURE_STATE_BATT_SEC_MASK (0x2U)
76 #define BSEC_SECURE_STATE_BATT_SEC_SHIFT (1U)
77 #define BSEC_SECURE_STATE_BATT_SEC_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_SEC_SHIFT) & BSEC_SECURE_STATE_BATT_SEC_MASK)
78 #define BSEC_SECURE_STATE_BATT_SEC_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_SEC_MASK) >> BSEC_SECURE_STATE_BATT_SEC_SHIFT)
79 
80 /*
81  * BATT_INS (RW)
82  *
83  * BATT secure state one hot indicator
84  * 0: secure state is not in inspect state
85  * 1: secure state is in inspect state
86  */
87 #define BSEC_SECURE_STATE_BATT_INS_MASK (0x1U)
88 #define BSEC_SECURE_STATE_BATT_INS_SHIFT (0U)
89 #define BSEC_SECURE_STATE_BATT_INS_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_BATT_INS_SHIFT) & BSEC_SECURE_STATE_BATT_INS_MASK)
90 #define BSEC_SECURE_STATE_BATT_INS_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_BATT_INS_MASK) >> BSEC_SECURE_STATE_BATT_INS_SHIFT)
91 
92 /* Bitfield definition for register: SECURE_STATE_CONFIG */
93 /*
94  * LOCK (RW)
95  *
96  * Lock bit of allow restart setting, once locked, lock bit itself and configuration register will keep value until next reset
97  * 0: not locked, register can be modified
98  * 1: register locked, write access to the register is ignored
99  */
100 #define BSEC_SECURE_STATE_CONFIG_LOCK_MASK (0x8U)
101 #define BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT (3U)
102 #define BSEC_SECURE_STATE_CONFIG_LOCK_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK)
103 #define BSEC_SECURE_STATE_CONFIG_LOCK_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_LOCK_MASK) >> BSEC_SECURE_STATE_CONFIG_LOCK_SHIFT)
104 
105 /*
106  * ALLOW_RESTART (RW)
107  *
108  * allow secure state restart from fail state
109  * 0: restart is not allowed, only hardware reset can recover secure state
110  * 1: software is allowed to switch to inspect state from fail state
111  */
112 #define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK (0x1U)
113 #define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT (0U)
114 #define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x) (((uint32_t)(x) << BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK)
115 #define BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x) (((uint32_t)(x) & BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> BSEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT)
116 
117 /* Bitfield definition for register: VIOLATION_CONFIG */
118 /*
119  * LOCK_NSC (RW)
120  *
121  * Lock bit non-secure violation setting, once locked, lock bit itself and configuration will keep value until next reset
122  * 0: not locked, configuration can be modified
123  * 1: register locked, write access to the configuration is ignored
124  */
125 #define BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK (0x80000000UL)
126 #define BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT (31U)
127 #define BSEC_VIOLATION_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK)
128 #define BSEC_VIOLATION_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT)
129 
130 /*
131  * NSC_VIO_CFG (RW)
132  *
133  * configuration of non-secure state violations, each bit represents one security event
134  * 0: event is not a security violation
135  * 1: event is a security violation
136  */
137 #define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL)
138 #define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT (16U)
139 #define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK)
140 #define BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT)
141 
142 /*
143  * LOCK_SEC (RW)
144  *
145  * Lock bit secure violation setting, once locked, lock bit itself and configuration will keep value until next reset
146  * 0: not locked, configuration can be modified
147  * 1: register locked, write access to the configuration is ignored
148  */
149 #define BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK (0x8000U)
150 #define BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT (15U)
151 #define BSEC_VIOLATION_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK)
152 #define BSEC_VIOLATION_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> BSEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT)
153 
154 /*
155  * SEC_VIO_CFG (RW)
156  *
157  * configuration of secure state violations, each bit represents one security event
158  * 0: event is not a security violation
159  * 1: event is a security violation
160  */
161 #define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU)
162 #define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT (0U)
163 #define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK)
164 #define BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT)
165 
166 /* Bitfield definition for register: ESCALATE_CONFIG */
167 /*
168  * LOCK_NSC (RW)
169  *
170  * Lock bit non-secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset
171  * 0: not locked, configuration can be modified
172  * 1: register locked, write access to the configuration is ignored
173  */
174 #define BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK (0x80000000UL)
175 #define BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT (31U)
176 #define BSEC_ESCALATE_CONFIG_LOCK_NSC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK)
177 #define BSEC_ESCALATE_CONFIG_LOCK_NSC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT)
178 
179 /*
180  * NSC_VIO_CFG (RW)
181  *
182  * configuration of non-secure state escalates, each bit represents one security event
183  * 0: event is not a security escalate
184  * 1: event is a security escalate
185  */
186 #define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK (0x7FFF0000UL)
187 #define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT (16U)
188 #define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK)
189 #define BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT)
190 
191 /*
192  * LOCK_SEC (RW)
193  *
194  * Lock bit secure escalate setting, once locked, lock bit itself and configuration will keep value until next reset
195  * 0: not locked, configuration can be modified1: register locked, write access to the configuration is ignored
196  */
197 #define BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK (0x8000U)
198 #define BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT (15U)
199 #define BSEC_ESCALATE_CONFIG_LOCK_SEC_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK)
200 #define BSEC_ESCALATE_CONFIG_LOCK_SEC_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> BSEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT)
201 
202 /*
203  * SEC_VIO_CFG (RW)
204  *
205  * configuration of secure state escalates, each bit represents one security event
206  * 0: event is not a security escalate
207  * 1: event is a security escalate
208  */
209 #define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK (0x7FFFU)
210 #define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT (0U)
211 #define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x) (((uint32_t)(x) << BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK)
212 #define BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x) (((uint32_t)(x) & BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> BSEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT)
213 
214 /* Bitfield definition for register: EVENT */
215 /*
216  * EVENT (RO)
217  *
218  * local event statue, each bit represents one security event
219  */
220 #define BSEC_EVENT_EVENT_MASK (0xFFFF0000UL)
221 #define BSEC_EVENT_EVENT_SHIFT (16U)
222 #define BSEC_EVENT_EVENT_GET(x) (((uint32_t)(x) & BSEC_EVENT_EVENT_MASK) >> BSEC_EVENT_EVENT_SHIFT)
223 
224 /*
225  * BATT_ESC_NSC (RO)
226  *
227  * BATT is escalating non-secure event
228  */
229 #define BSEC_EVENT_BATT_ESC_NSC_MASK (0x2U)
230 #define BSEC_EVENT_BATT_ESC_NSC_SHIFT (1U)
231 #define BSEC_EVENT_BATT_ESC_NSC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_NSC_MASK) >> BSEC_EVENT_BATT_ESC_NSC_SHIFT)
232 
233 /*
234  * BATT_ESC_SEC (RO)
235  *
236  * BATT is escalting ssecure event
237  */
238 #define BSEC_EVENT_BATT_ESC_SEC_MASK (0x1U)
239 #define BSEC_EVENT_BATT_ESC_SEC_SHIFT (0U)
240 #define BSEC_EVENT_BATT_ESC_SEC_GET(x) (((uint32_t)(x) & BSEC_EVENT_BATT_ESC_SEC_MASK) >> BSEC_EVENT_BATT_ESC_SEC_SHIFT)
241 
242 
243 
244 
245 #endif /* HPM_BSEC_H */
BSEC_Type
Definition: hpm_bsec_regs.h:12