HPM SDK
HPMicro Software Development Kit
hpm_trgmmux_src.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TRGMMUX_SRC_H
10 #define HPM_TRGMMUX_SRC_H
11 
12 /* trgm0_input mux definitions */
13 #define HPM_TRGM0_INPUT_SRC_VSS (0x0UL) /* low level voltage */
14 #define HPM_TRGM0_INPUT_SRC_VDD (0x1UL) /* high level voltage */
15 #define HPM_TRGM0_INPUT_SRC_USB0_SOF (0x2UL) /* USB0 start of frame marker */
16 #define HPM_TRGM0_INPUT_SRC_ENET0_PTP3 (0x3UL) /* ENET0 PTP output bit3 */
17 #define HPM_TRGM0_INPUT_SRC_ESC_SYNC0 (0x4UL) /* ethercat sync0 event */
18 #define HPM_TRGM0_INPUT_SRC_TSN_PTP3 (0x5UL) /* TSW PTP output bit 3 */
19 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP0 (0x6UL) /* PTPC compare output0 */
20 #define HPM_TRGM0_INPUT_SRC_PTPC_CMP1 (0x7UL) /* PTPC compare output1 */
21 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN0 (0x8UL) /* PWM0 input bit0(from IO) */
22 #define HPM_TRGM0_INPUT_SRC_PWM0_CAPIN1 (0x9UL) /* PWM0 input bit1(from IO) */
23 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN0 (0xAUL) /* PWM1 input bit0(from IO) */
24 #define HPM_TRGM0_INPUT_SRC_PWM1_CAPIN1 (0xBUL) /* PWM1 input bit1(from IO) */
25 #define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN0 (0xCUL) /* PWM2 input bit0(from IO) */
26 #define HPM_TRGM0_INPUT_SRC_PWM2_CAPIN1 (0xDUL) /* PWM2 input bit1(from IO) */
27 #define HPM_TRGM0_INPUT_SRC_PWM3_CAPIN0 (0xEUL) /* PWM3 input bit0(from IO) */
28 #define HPM_TRGM0_INPUT_SRC_ESC_SYNC1 (0xFUL) /* ethercat sync1 event */
29 #define HPM_TRGM0_INPUT_SRC_SYNT_CH00 (0x10UL) /* SYNT channel0 pulse output */
30 #define HPM_TRGM0_INPUT_SRC_SYNT_CH01 (0x11UL) /* SYNT channel1 pulse output */
31 #define HPM_TRGM0_INPUT_SRC_SYNT_CH02 (0x12UL) /* SYNT channel2 pulse output */
32 #define HPM_TRGM0_INPUT_SRC_SYNT_CH03 (0x13UL) /* SYNT channel3 pulse output */
33 #define HPM_TRGM0_INPUT_SRC_SYNT_CH04 (0x14UL) /* SYNT channel4 pulse output */
34 #define HPM_TRGM0_INPUT_SRC_SYNT_CH05 (0x15UL) /* SYNT channel5 pulse output */
35 #define HPM_TRGM0_INPUT_SRC_SYNT_CH06 (0x16UL) /* SYNT channel6 pulse output */
36 #define HPM_TRGM0_INPUT_SRC_SYNT_CH07 (0x17UL) /* SYNT channel7 pulse output */
37 #define HPM_TRGM0_INPUT_SRC_SYNT_CH08 (0x18UL) /* SYNT channel8 pulse output */
38 #define HPM_TRGM0_INPUT_SRC_SYNT_CH09 (0x19UL) /* SYNT channel9 pulse output */
39 #define HPM_TRGM0_INPUT_SRC_SYNT_CH10 (0x1AUL) /* SYNT channel10 pulse output */
40 #define HPM_TRGM0_INPUT_SRC_SYNT_CH11 (0x1BUL) /* SYNT channel11 pulse output */
41 #define HPM_TRGM0_INPUT_SRC_SYNT_CH12 (0x1CUL) /* SYNT channel12 pulse output */
42 #define HPM_TRGM0_INPUT_SRC_SYNT_CH13 (0x1DUL) /* SYNT channel13 pulse output */
43 #define HPM_TRGM0_INPUT_SRC_SYNT_CH14 (0x1EUL) /* SYNT channel14 pulse output */
44 #define HPM_TRGM0_INPUT_SRC_SYNT_CH15 (0x1FUL) /* SYNT channel15 pulse output */
45 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT2 (0x20UL) /* GPTMR0 channel2 compare output */
46 #define HPM_TRGM0_INPUT_SRC_GPTMR0_OUT3 (0x21UL) /* GPTMR0 channel3 compare output */
47 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT2 (0x22UL) /* GPTMR0 channel2 compare output */
48 #define HPM_TRGM0_INPUT_SRC_GPTMR1_OUT3 (0x23UL) /* GPTMR0 channel3 compare output */
49 #define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT2 (0x24UL) /* GPTMR0 channel2 compare output */
50 #define HPM_TRGM0_INPUT_SRC_GPTMR2_OUT3 (0x25UL) /* GPTMR0 channel3 compare output */
51 #define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT2 (0x26UL) /* GPTMR0 channel2 compare output */
52 #define HPM_TRGM0_INPUT_SRC_GPTMR3_OUT3 (0x27UL) /* GPTMR0 channel3 compare output */
53 #define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT2 (0x28UL) /* GPTMR0 channel2 compare output */
54 #define HPM_TRGM0_INPUT_SRC_GPTMR4_OUT3 (0x29UL) /* GPTMR0 channel3 compare output */
55 #define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT2 (0x2AUL) /* GPTMR0 channel2 compare output */
56 #define HPM_TRGM0_INPUT_SRC_GPTMR5_OUT3 (0x2BUL) /* GPTMR0 channel3 compare output */
57 #define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT2 (0x2CUL) /* GPTMR0 channel2 compare output */
58 #define HPM_TRGM0_INPUT_SRC_GPTMR6_OUT3 (0x2DUL) /* GPTMR0 channel3 compare output */
59 #define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT2 (0x2EUL) /* GPTMR0 channel2 compare output */
60 #define HPM_TRGM0_INPUT_SRC_GPTMR7_OUT3 (0x2FUL) /* GPTMR0 channel3 compare output */
61 #define HPM_TRGM0_INPUT_SRC_ACMP0_OUT (0x30UL) /* CMP0 compare output */
62 #define HPM_TRGM0_INPUT_SRC_ACMP1_OUT (0x31UL) /* CMP1 compare output */
63 #define HPM_TRGM0_INPUT_SRC_ACMP2_OUT (0x32UL) /* CMP2 compare output */
64 #define HPM_TRGM0_INPUT_SRC_ACMP3_OUT (0x33UL) /* CMP3 compare output */
65 #define HPM_TRGM0_INPUT_SRC_ACMP4_OUT (0x34UL) /* CMP4 compare output */
66 #define HPM_TRGM0_INPUT_SRC_ACMP5_OUT (0x35UL) /* CMP5 compare output */
67 #define HPM_TRGM0_INPUT_SRC_ACMP6_OUT (0x36UL) /* CMP6 compare output */
68 #define HPM_TRGM0_INPUT_SRC_ACMP7_OUT (0x37UL) /* CMP7 compare output */
69 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_0 (0x38UL) /* SEI trigger out0 */
70 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_1 (0x39UL) /* SEI trigger out1 */
71 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_2 (0x3AUL) /* SEI trigger out2 */
72 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_3 (0x3BUL) /* SEI trigger out3 */
73 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_4 (0x3CUL) /* SEI trigger out4 */
74 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_5 (0x3DUL) /* SEI trigger out5 */
75 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_6 (0x3EUL) /* SEI trigger out6 */
76 #define HPM_TRGM0_INPUT_SRC_SEI_TRGO_7 (0x3FUL) /* SEI trigger out7 */
77 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_0 (0x40UL) /* PWM0 trigger out0 */
78 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_1 (0x41UL) /* PWM0 trigger out1 */
79 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_2 (0x42UL) /* PWM0 trigger out2 */
80 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_3 (0x43UL) /* PWM0 trigger out3 */
81 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_4 (0x44UL) /* PWM0 trigger out4 */
82 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_5 (0x45UL) /* PWM0 trigger out5 */
83 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_6 (0x46UL) /* PWM0 trigger out6 */
84 #define HPM_TRGM0_INPUT_SRC_PWM0_TRGO_7 (0x47UL) /* PWM0 trigger out7 */
85 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_0 (0x48UL) /* PWM1 trigger out0 */
86 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_1 (0x49UL) /* PWM1 trigger out1 */
87 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_2 (0x4AUL) /* PWM1 trigger out2 */
88 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_3 (0x4BUL) /* PWM1 trigger out3 */
89 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_4 (0x4CUL) /* PWM1 trigger out4 */
90 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_5 (0x4DUL) /* PWM1 trigger out5 */
91 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_6 (0x4EUL) /* PWM1 trigger out6 */
92 #define HPM_TRGM0_INPUT_SRC_PWM1_TRGO_7 (0x46UL) /* PWM1 trigger out7 */
93 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_0 (0x50UL) /* PWM2 trigger out0 */
94 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_1 (0x51UL) /* PWM2 trigger out1 */
95 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_2 (0x52UL) /* PWM2 trigger out2 */
96 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_3 (0x53UL) /* PWM2 trigger out3 */
97 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_4 (0x54UL) /* PWM2 trigger out4 */
98 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_5 (0x55UL) /* PWM2 trigger out5 */
99 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_6 (0x56UL) /* PWM2 trigger out6 */
100 #define HPM_TRGM0_INPUT_SRC_PWM2_TRGO_7 (0x57UL) /* PWM2 trigger out7 */
101 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_0 (0x58UL) /* PWM3 trigger out0 */
102 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_1 (0x59UL) /* PWM3 trigger out1 */
103 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_2 (0x5AUL) /* PWM3 trigger out2 */
104 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_3 (0x5BUL) /* PWM3 trigger out3 */
105 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_4 (0x5CUL) /* PWM3 trigger out4 */
106 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_5 (0x5DUL) /* PWM3 trigger out5 */
107 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_6 (0x5EUL) /* PWM3 trigger out6 */
108 #define HPM_TRGM0_INPUT_SRC_PWM3_TRGO_7 (0x5FUL) /* PWM3 trigger out7 */
109 #define HPM_TRGM0_INPUT_SRC_TRGM0_P00 (0x60UL) /* TRGM input data0(from IO) */
110 #define HPM_TRGM0_INPUT_SRC_TRGM0_P01 (0x61UL) /* TRGM input data1(from IO) */
111 #define HPM_TRGM0_INPUT_SRC_TRGM0_P02 (0x62UL) /* TRGM input data2(from IO) */
112 #define HPM_TRGM0_INPUT_SRC_TRGM0_P03 (0x63UL) /* TRGM input data3(from IO) */
113 #define HPM_TRGM0_INPUT_SRC_TRGM0_P04 (0x64UL) /* TRGM input data4(from IO) */
114 #define HPM_TRGM0_INPUT_SRC_TRGM0_P05 (0x65UL) /* TRGM input data5(from IO) */
115 #define HPM_TRGM0_INPUT_SRC_TRGM0_P06 (0x66UL) /* TRGM input data6(from IO) */
116 #define HPM_TRGM0_INPUT_SRC_TRGM0_P07 (0x67UL) /* TRGM input data7(from IO) */
117 #define HPM_TRGM0_INPUT_SRC_TRGM0_P08 (0x68UL) /* TRGM input data8(from IO) */
118 #define HPM_TRGM0_INPUT_SRC_TRGM0_P09 (0x69UL) /* TRGM input data9(from IO) */
119 #define HPM_TRGM0_INPUT_SRC_TRGM0_P10 (0x6AUL) /* TRGM input data10(from IO) */
120 #define HPM_TRGM0_INPUT_SRC_TRGM0_P11 (0x6BUL) /* TRGM input data11(from IO) */
121 #define HPM_TRGM0_INPUT_SRC_TRGM0_P12 (0x6CUL) /* TRGM input data12(from IO) */
122 #define HPM_TRGM0_INPUT_SRC_TRGM0_P13 (0x6DUL) /* TRGM input data13(from IO) */
123 #define HPM_TRGM0_INPUT_SRC_TRGM0_P14 (0x6EUL) /* TRGM input data14(from IO) */
124 #define HPM_TRGM0_INPUT_SRC_TRGM0_P15 (0x6FUL) /* TRGM input data15(from IO) */
125 #define HPM_TRGM0_INPUT_SRC_TRGM0_P16 (0x70UL) /* TRGM input data16(from IO) */
126 #define HPM_TRGM0_INPUT_SRC_TRGM0_P17 (0x71UL) /* TRGM input data17(from IO) */
127 #define HPM_TRGM0_INPUT_SRC_TRGM0_P18 (0x72UL) /* TRGM input data18(from IO) */
128 #define HPM_TRGM0_INPUT_SRC_TRGM0_P19 (0x73UL) /* TRGM input data19(from IO) */
129 #define HPM_TRGM0_INPUT_SRC_TRGM0_P20 (0x74UL) /* TRGM input data20(from IO) */
130 #define HPM_TRGM0_INPUT_SRC_TRGM0_P21 (0x75UL) /* TRGM input data21(from IO) */
131 #define HPM_TRGM0_INPUT_SRC_TRGM0_P22 (0x76UL) /* TRGM input data22(from IO) */
132 #define HPM_TRGM0_INPUT_SRC_TRGM0_P23 (0x77UL) /* TRGM input data23(from IO) */
133 #define HPM_TRGM0_INPUT_SRC_TRGM0_P24 (0x78UL) /* TRGM input data24(from IO) */
134 #define HPM_TRGM0_INPUT_SRC_TRGM0_P25 (0x79UL) /* TRGM input data25(from IO) */
135 #define HPM_TRGM0_INPUT_SRC_TRGM0_P26 (0x7AUL) /* TRGM input data26(from IO) */
136 #define HPM_TRGM0_INPUT_SRC_TRGM0_P27 (0x7BUL) /* TRGM input data27(from IO) */
137 #define HPM_TRGM0_INPUT_SRC_TRGM0_P28 (0x7CUL) /* TRGM input data28(from IO) */
138 #define HPM_TRGM0_INPUT_SRC_TRGM0_P29 (0x7DUL) /* TRGM input data29(from IO) */
139 #define HPM_TRGM0_INPUT_SRC_TRGM0_P30 (0x7EUL) /* TRGM input data30(from IO) */
140 #define HPM_TRGM0_INPUT_SRC_TRGM0_P31 (0x7FUL) /* TRGM input data31(from IO) */
141 #define HPM_TRGM0_INPUT_SRC_PLB_OUT00 (0x80UL) /* PLB trigger out0 */
142 #define HPM_TRGM0_INPUT_SRC_PLB_OUT01 (0x81UL) /* PLB trigger out1 */
143 #define HPM_TRGM0_INPUT_SRC_PLB_OUT02 (0x82UL) /* PLB trigger out2 */
144 #define HPM_TRGM0_INPUT_SRC_PLB_OUT03 (0x83UL) /* PLB trigger out3 */
145 #define HPM_TRGM0_INPUT_SRC_PLB_OUT04 (0x84UL) /* PLB trigger out4 */
146 #define HPM_TRGM0_INPUT_SRC_PLB_OUT05 (0x85UL) /* PLB trigger out5 */
147 #define HPM_TRGM0_INPUT_SRC_PLB_OUT06 (0x86UL) /* PLB trigger out6 */
148 #define HPM_TRGM0_INPUT_SRC_PLB_OUT07 (0x87UL) /* PLB trigger out7 */
149 #define HPM_TRGM0_INPUT_SRC_PLB_OUT08 (0x88UL) /* PLB trigger out8 */
150 #define HPM_TRGM0_INPUT_SRC_PLB_OUT09 (0x89UL) /* PLB trigger out9 */
151 #define HPM_TRGM0_INPUT_SRC_PLB_OUT10 (0x8AUL) /* PLB trigger out10 */
152 #define HPM_TRGM0_INPUT_SRC_PLB_OUT11 (0x8BUL) /* PLB trigger out11 */
153 #define HPM_TRGM0_INPUT_SRC_PLB_OUT12 (0x8CUL) /* PLB trigger out12 */
154 #define HPM_TRGM0_INPUT_SRC_PLB_OUT13 (0x8DUL) /* PLB trigger out13 */
155 #define HPM_TRGM0_INPUT_SRC_PLB_OUT14 (0x8EUL) /* PLB trigger out14 */
156 #define HPM_TRGM0_INPUT_SRC_PLB_OUT15 (0x8FUL) /* PLB trigger out15 */
157 #define HPM_TRGM0_INPUT_SRC_PLB_OUT16 (0x90UL) /* PLB trigger out16 */
158 #define HPM_TRGM0_INPUT_SRC_PLB_OUT17 (0x91UL) /* PLB trigger out17 */
159 #define HPM_TRGM0_INPUT_SRC_PLB_OUT18 (0x92UL) /* PLB trigger out18 */
160 #define HPM_TRGM0_INPUT_SRC_PLB_OUT19 (0x93UL) /* PLB trigger out19 */
161 #define HPM_TRGM0_INPUT_SRC_PLB_OUT20 (0x94UL) /* PLB trigger out20 */
162 #define HPM_TRGM0_INPUT_SRC_PLB_OUT21 (0x95UL) /* PLB trigger out21 */
163 #define HPM_TRGM0_INPUT_SRC_PLB_OUT22 (0x96UL) /* PLB trigger out22 */
164 #define HPM_TRGM0_INPUT_SRC_PLB_OUT23 (0x97UL) /* PLB trigger out23 */
165 #define HPM_TRGM0_INPUT_SRC_PLB_OUT24 (0x98UL) /* PLB trigger out24 */
166 #define HPM_TRGM0_INPUT_SRC_PLB_OUT25 (0x99UL) /* PLB trigger out25 */
167 #define HPM_TRGM0_INPUT_SRC_PLB_OUT26 (0x9AUL) /* PLB trigger out26 */
168 #define HPM_TRGM0_INPUT_SRC_PLB_OUT27 (0x9BUL) /* PLB trigger out27 */
169 #define HPM_TRGM0_INPUT_SRC_PLB_OUT28 (0x9CUL) /* PLB trigger out28 */
170 #define HPM_TRGM0_INPUT_SRC_PLB_OUT29 (0x9DUL) /* PLB trigger out29 */
171 #define HPM_TRGM0_INPUT_SRC_PLB_OUT30 (0x9EUL) /* PLB trigger out30 */
172 #define HPM_TRGM0_INPUT_SRC_PLB_OUT31 (0x9FUL) /* PLB trigger out31 */
173 #define HPM_TRGM0_INPUT_SRC_PLB_OUT32 (0xA0UL) /* PLB trigger out32 */
174 #define HPM_TRGM0_INPUT_SRC_PLB_OUT33 (0xA1UL) /* PLB trigger out33 */
175 #define HPM_TRGM0_INPUT_SRC_PLB_OUT34 (0xA2UL) /* PLB trigger out34 */
176 #define HPM_TRGM0_INPUT_SRC_PLB_OUT35 (0xA3UL) /* PLB trigger out35 */
177 #define HPM_TRGM0_INPUT_SRC_PLB_OUT36 (0xA4UL) /* PLB trigger out36 */
178 #define HPM_TRGM0_INPUT_SRC_PLB_OUT37 (0xA5UL) /* PLB trigger out37 */
179 #define HPM_TRGM0_INPUT_SRC_PLB_OUT38 (0xA6UL) /* PLB trigger out38 */
180 #define HPM_TRGM0_INPUT_SRC_PLB_OUT39 (0xA7UL) /* PLB trigger out39 */
181 #define HPM_TRGM0_INPUT_SRC_PLB_OUT40 (0xA8UL) /* PLB trigger out40 */
182 #define HPM_TRGM0_INPUT_SRC_PLB_OUT41 (0xA9UL) /* PLB trigger out41 */
183 #define HPM_TRGM0_INPUT_SRC_PLB_OUT42 (0xAAUL) /* PLB trigger out42 */
184 #define HPM_TRGM0_INPUT_SRC_PLB_OUT43 (0xABUL) /* PLB trigger out43 */
185 #define HPM_TRGM0_INPUT_SRC_PLB_OUT44 (0xACUL) /* PLB trigger out44 */
186 #define HPM_TRGM0_INPUT_SRC_PLB_OUT45 (0xADUL) /* PLB trigger out45 */
187 #define HPM_TRGM0_INPUT_SRC_PLB_OUT46 (0xAEUL) /* PLB trigger out46 */
188 #define HPM_TRGM0_INPUT_SRC_PLB_OUT47 (0xAFUL) /* PLB trigger out47 */
189 #define HPM_TRGM0_INPUT_SRC_PLB_OUT48 (0xB0UL) /* PLB trigger out48 */
190 #define HPM_TRGM0_INPUT_SRC_PLB_OUT49 (0xB1UL) /* PLB trigger out49 */
191 #define HPM_TRGM0_INPUT_SRC_PLB_OUT50 (0xB2UL) /* PLB trigger out50 */
192 #define HPM_TRGM0_INPUT_SRC_PLB_OUT51 (0xAAUL) /* PLB trigger out51 */
193 #define HPM_TRGM0_INPUT_SRC_PLB_OUT52 (0xB4UL) /* PLB trigger out52 */
194 #define HPM_TRGM0_INPUT_SRC_PLB_OUT53 (0xB5UL) /* PLB trigger out53 */
195 #define HPM_TRGM0_INPUT_SRC_PLB_OUT54 (0xB6UL) /* PLB trigger out54 */
196 #define HPM_TRGM0_INPUT_SRC_PLB_OUT55 (0xB7UL) /* PLB trigger out55 */
197 #define HPM_TRGM0_INPUT_SRC_PLB_OUT56 (0xB8UL) /* PLB trigger out56 */
198 #define HPM_TRGM0_INPUT_SRC_PLB_OUT57 (0xB9UL) /* PLB trigger out57 */
199 #define HPM_TRGM0_INPUT_SRC_PLB_OUT58 (0xBAUL) /* PLB trigger out58 */
200 #define HPM_TRGM0_INPUT_SRC_PLB_OUT59 (0xBBUL) /* PLB trigger out59 */
201 #define HPM_TRGM0_INPUT_SRC_PLB_OUT60 (0xBCUL) /* PLB trigger out60 */
202 #define HPM_TRGM0_INPUT_SRC_PLB_OUT61 (0xBDUL) /* PLB trigger out61 */
203 #define HPM_TRGM0_INPUT_SRC_PLB_OUT62 (0xBEUL) /* PLB trigger out62 */
204 #define HPM_TRGM0_INPUT_SRC_PLB_OUT63 (0xBFUL) /* PLB trigger out63 */
205 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ0 (0xC0UL) /* inform of sdm1 channel0 value through zero */
206 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ1 (0xC1UL) /* inform of sdm1 channel1 value through zero */
207 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ2 (0xC2UL) /* inform of sdm1 channel2 value through zero */
208 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHZ3 (0xC3UL) /* inform of sdm1 channel3 value through zero */
209 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA0 (0xC4UL) /* inform of sdm1 channel0 value over upper limit */
210 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA1 (0xC5UL) /* inform of sdm1 channel1 value over upper limit */
211 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA2 (0xC6UL) /* inform of sdm1 channel2 value over upper limit */
212 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPHA3 (0xC7UL) /* inform of sdm1 channel3 value over upper limit */
213 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPL0 (0xC8UL) /* inform of sdm1 channel value beyond lower limit */
214 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPL1 (0xC9UL) /* inform of sdm1 channel value beyond lower limit */
215 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPL2 (0xCAUL) /* inform of sdm1 channel value beyond lower limit */
216 #define HPM_TRGM0_INPUT_SRC_SDM1_COMPL3 (0xCBUL) /* inform of sdm1 channel value beyond lower limit */
217 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ0 (0xCCUL) /* inform of sdm0 channel0 value through zero */
218 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ1 (0xCDUL) /* inform of sdm0 channel1 value through zero */
219 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ2 (0xCEUL) /* inform of sdm0 channel2 value through zero */
220 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHZ3 (0xCFUL) /* inform of sdm0 channel3 value through zero */
221 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPL0 (0xD0UL) /* inform of sdm0 channel0 value over upper limit */
222 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPL1 (0xD1UL) /* inform of sdm0 channel1 value over upper limit */
223 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPL2 (0xD2UL) /* inform of sdm0 channel2 value over upper limit */
224 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPL3 (0xD3UL) /* inform of sdm0 channel3 value over upper limit */
225 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA0 (0xD4UL) /* inform of sdm0 channel value beyond lower limit */
226 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA1 (0xD5UL) /* inform of sdm0 channel value beyond lower limit */
227 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA2 (0xD6UL) /* inform of sdm0 channel value beyond lower limit */
228 #define HPM_TRGM0_INPUT_SRC_SDM0_COMPHA3 (0xD7UL) /* inform of sdm0 channel value beyond lower limit */
229 #define HPM_TRGM0_INPUT_SRC_ADC0_TRGO (0xD8UL) /* ADC0 trigger out */
230 #define HPM_TRGM0_INPUT_SRC_ADC1_TRGO (0xD9UL) /* ADC1 trigger out */
231 #define HPM_TRGM0_INPUT_SRC_ADC2_TRGO (0xDAUL) /* ADC2 trigger out */
232 #define HPM_TRGM0_INPUT_SRC_ADC3_TRGO (0xDBUL) /* ADC3 trigger out */
233 #define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_0 (0xDCUL) /* RDC0 trigger out0 */
234 #define HPM_TRGM0_INPUT_SRC_RDC0_TRGO_1 (0xDDUL) /* RDC0 trigger out1 */
235 #define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_0 (0xDEUL) /* RDC1 trigger out0 */
236 #define HPM_TRGM0_INPUT_SRC_RDC1_TRGO_1 (0xDFUL) /* RDC1 trigger out1 */
237 #define HPM_TRGM0_INPUT_SRC_DEBUG_FLAG (0xE0UL) /* debug mode flag */
238 #define HPM_TRGM0_INPUT_SRC_QEI0_TRGO (0xE1UL) /* QEI0 trigger out */
239 #define HPM_TRGM0_INPUT_SRC_QEI1_TRGO (0xE2UL) /* QEI1 trigger out */
240 #define HPM_TRGM0_INPUT_SRC_QEI2_TRGO (0xE3UL) /* QEI2 trigger out */
241 #define HPM_TRGM0_INPUT_SRC_QEI3_TRGO (0xE4UL) /* QEI3 trigger out */
242 
243 /* trgm0_output mux definitions */
244 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO0 (0x0UL) /* TRGM output data0(to IO) */
245 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO1 (0x1UL) /* TRGM output data1(to IO) */
246 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO2 (0x2UL) /* TRGM output data2(to IO) */
247 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO3 (0x3UL) /* TRGM output data3(to IO) */
248 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO4 (0x4UL) /* TRGM output data4(to IO) */
249 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO5 (0x5UL) /* TRGM output data5(to IO) */
250 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO6 (0x6UL) /* TRGM output data6(to IO) */
251 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO7 (0x7UL) /* TRGM output data7(to IO) */
252 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO8 (0x8UL) /* TRGM output data8(to IO) */
253 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO9 (0x9UL) /* TRGM output data9(to IO) */
254 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO10 (0xAUL) /* TRGM output data10(to IO) */
255 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO11 (0xBUL) /* TRGM output data11(to IO) */
256 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO12 (0xCUL) /* TRGM output data12(to IO) */
257 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO13 (0xDUL) /* TRGM output data13(to IO) */
258 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO14 (0xEUL) /* TRGM output data14(to IO) */
259 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO15 (0xFUL) /* TRGM output data15(to IO) */
260 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO16 (0x10UL) /* TRGM output data16(to IO) */
261 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO17 (0x11UL) /* TRGM output data17(to IO) */
262 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO18 (0x12UL) /* TRGM output data18(to IO) */
263 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO19 (0x13UL) /* TRGM output data19(to IO) */
264 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO20 (0x14UL) /* TRGM output data20(to IO) */
265 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO21 (0x15UL) /* TRGM output data21(to IO) */
266 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO22 (0x16UL) /* TRGM output data22(to IO) */
267 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO23 (0x17UL) /* TRGM output data23(to IO) */
268 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO24 (0x18UL) /* TRGM output data24(to IO) */
269 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO25 (0x19UL) /* TRGM output data25(to IO) */
270 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO26 (0x1AUL) /* TRGM output data26(to IO) */
271 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO27 (0x1BUL) /* TRGM output data27(to IO) */
272 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO28 (0x1CUL) /* TRGM output data28(to IO) */
273 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO29 (0x1DUL) /* TRGM output data29(to IO) */
274 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO30 (0x1EUL) /* TRGM output data30(to IO) */
275 #define HPM_TRGM0_OUTPUT_SRC_MOT_GPIO31 (0x1FUL) /* TRGM output data31(to IO) */
276 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC0 (0x20UL) /* SDM sync event input0 */
277 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC1 (0x21UL) /* SDM sync event input1 */
278 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC2 (0x22UL) /* SDM sync event input2 */
279 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC3 (0x23UL) /* SDM sync event input3 */
280 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC4 (0x24UL) /* SDM sync event input4 */
281 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC5 (0x25UL) /* SDM sync event input5 */
282 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC6 (0x26UL) /* SDM sync event input6 */
283 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC7 (0x27UL) /* SDM sync event input7 */
284 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC8 (0x28UL) /* SDM sync event input8 */
285 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC9 (0x29UL) /* SDM sync event input9 */
286 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC10 (0x2AUL) /* SDM sync event input10 */
287 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC11 (0x2BUL) /* SDM sync event input11 */
288 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC12 (0x2CUL) /* SDM sync event input12 */
289 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC13 (0x2DUL) /* SDM sync event input13 */
290 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC14 (0x2EUL) /* SDM sync event input14 */
291 #define HPM_TRGM0_OUTPUT_SRC_SDM_PWM_SOC15 (0x2FUL) /* SDM sync event input15 */
292 #define HPM_TRGM0_OUTPUT_SRC_ADC0_STRGI (0x30UL) /* ADC0 sequence queue trigger */
293 #define HPM_TRGM0_OUTPUT_SRC_ADC1_STRGI (0x31UL) /* ADC1 sequence queue trigger */
294 #define HPM_TRGM0_OUTPUT_SRC_ADC2_STRGI (0x32UL) /* ADC2 sequence queue trigger */
295 #define HPM_TRGM0_OUTPUT_SRC_ADC3_STRGI (0x33UL) /* ADC3 sequence queue trigger */
296 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0A (0x34UL) /* ADC preemption trigger0A */
297 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0B (0x35UL) /* ADC preemption trigger0B */
298 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI0C (0x36UL) /* ADC preemption trigger0C */
299 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1A (0x37UL) /* ADC preemption trigger1A */
300 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1B (0x38UL) /* ADC preemption trigger1B */
301 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI1C (0x39UL) /* ADC preemption trigger1C */
302 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2A (0x3AUL) /* ADC preemption trigger2A */
303 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2B (0x3BUL) /* ADC preemption trigger2B */
304 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI2C (0x3CUL) /* ADC preemption trigger2C */
305 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3A (0x3DUL) /* ADC preemption trigger3A */
306 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3B (0x3EUL) /* ADC preemption trigger3B */
307 #define HPM_TRGM0_OUTPUT_SRC_ADCX_PTRGI3C (0x3FUL) /* ADC preemption trigger3C */
308 #define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN0 (0x40UL) /* VSC0 trigger in0 */
309 #define HPM_TRGM0_OUTPUT_SRC_VSC0_TRIG_IN1 (0x41UL) /* VSC0 trigger in1 */
310 #define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN0 (0x42UL) /* VSC1 trigger in0 */
311 #define HPM_TRGM0_OUTPUT_SRC_VSC1_TRIG_IN1 (0x43UL) /* VSC1 trigger in1 */
312 #define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN0 (0x44UL) /* RDC0 trigger in0 */
313 #define HPM_TRGM0_OUTPUT_SRC_RDC0_TRIG_IN1 (0x45UL) /* RDC0 trigger in1 */
314 #define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN0 (0x46UL) /* RDC1 trigger in0 */
315 #define HPM_TRGM0_OUTPUT_SRC_RDC1_TRIG_IN1 (0x47UL) /* RDC1 trigger in1 */
316 #define HPM_TRGM0_OUTPUT_SRC_QEI0_TRIG_IN (0x48UL) /* QEI0 trigger in */
317 #define HPM_TRGM0_OUTPUT_SRC_QEI1_TRIG_IN (0x49UL) /* QEI1 trigger in */
318 #define HPM_TRGM0_OUTPUT_SRC_QEI2_TRIG_IN (0x4AUL) /* QEI2 trigger in */
319 #define HPM_TRGM0_OUTPUT_SRC_QEI3_TRIG_IN (0x4BUL) /* QEI3 trigger in */
320 #define HPM_TRGM0_OUTPUT_SRC_QEI0_PAUSE (0x4CUL) /* QEI0 pause */
321 #define HPM_TRGM0_OUTPUT_SRC_QEI1_PAUSE (0x4DUL) /* QEI1 pause */
322 #define HPM_TRGM0_OUTPUT_SRC_QEI2_PAUSE (0x4EUL) /* QEI2 pause */
323 #define HPM_TRGM0_OUTPUT_SRC_QEI3_PAUSE (0x4FUL) /* QEI3 pause */
324 #define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN0 (0x50UL) /* QEO0 trigger in0 */
325 #define HPM_TRGM0_OUTPUT_SRC_QEO0_TRIG_IN1 (0x51UL) /* QEO0 trigger in1 */
326 #define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN0 (0x52UL) /* QEO1 trigger in0 */
327 #define HPM_TRGM0_OUTPUT_SRC_QEO1_TRIG_IN1 (0x53UL) /* QEO1 trigger in1 */
328 #define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN0 (0x54UL) /* QEO2 trigger in0 */
329 #define HPM_TRGM0_OUTPUT_SRC_QEO2_TRIG_IN1 (0x55UL) /* QEO2 trigger in1 */
330 #define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN0 (0x56UL) /* QEO3 trigger in0 */
331 #define HPM_TRGM0_OUTPUT_SRC_QEO3_TRIG_IN1 (0x57UL) /* QEO3 trigger in1 */
332 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN0 (0x58UL) /* SEI trigger in0 */
333 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN1 (0x59UL) /* SEI trigger in1 */
334 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN2 (0x5AUL) /* SEI trigger in2 */
335 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN3 (0x5BUL) /* SEI trigger in3 */
336 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN4 (0x5CUL) /* SEI trigger in4 */
337 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN5 (0x5DUL) /* SEI trigger in5 */
338 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN6 (0x5EUL) /* SEI trigger in6 */
339 #define HPM_TRGM0_OUTPUT_SRC_SEI_TRIG_IN7 (0x5FUL) /* SEI trigger in7 */
340 #define HPM_TRGM0_OUTPUT_SRC_ACMP0_WIN (0x60UL) /* CMP0 window */
341 #define HPM_TRGM0_OUTPUT_SRC_ACMP1_WIN (0x61UL) /* CMP1 window */
342 #define HPM_TRGM0_OUTPUT_SRC_ACMP2_WIN (0x62UL) /* CMP2 window */
343 #define HPM_TRGM0_OUTPUT_SRC_ACMP3_WIN (0x63UL) /* CMP3 window */
344 #define HPM_TRGM0_OUTPUT_SRC_ACMP4_WIN (0x64UL) /* CMP4 window */
345 #define HPM_TRGM0_OUTPUT_SRC_ACMP5_WIN (0x65UL) /* CMP5 window */
346 #define HPM_TRGM0_OUTPUT_SRC_ACMP6_WIN (0x66UL) /* CMP6 window */
347 #define HPM_TRGM0_OUTPUT_SRC_ACMP7_WIN (0x67UL) /* CMP7 window */
348 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN2 (0x68UL) /* GPTMR0 channe2 capture in */
349 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_IN3 (0x69UL) /* GPTMR0 channe3 capture in */
350 #define HPM_TRGM0_OUTPUT_SRC_GPTMR0_SYNCI (0x6AUL) /* GPTMR0 hardware sync in */
351 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN2 (0x6BUL) /* GPTMR1 channe2 capture in */
352 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_IN3 (0x6CUL) /* GPTMR1 channe3 capture in */
353 #define HPM_TRGM0_OUTPUT_SRC_GPTMR1_SYNCI (0x6DUL) /* GPTMR1 hardware sync in */
354 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN2 (0x6EUL) /* GPTMR2 channe2 capture in */
355 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_IN3 (0x6FUL) /* GPTMR2 channe3 capture in */
356 #define HPM_TRGM0_OUTPUT_SRC_GPTMR2_SYNCI (0x70UL) /* GPTMR2 hardware sync in */
357 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN2 (0x71UL) /* GPTMR3 channe2 capture in */
358 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_IN3 (0x72UL) /* GPTMR3 channe3 capture in */
359 #define HPM_TRGM0_OUTPUT_SRC_GPTMR3_SYNCI (0x73UL) /* GPTMR3 hardware sync in */
360 #define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN2 (0x74UL) /* GPTMR4 channe2 capture in */
361 #define HPM_TRGM0_OUTPUT_SRC_GPTMR4_IN3 (0x75UL) /* GPTMR4 channe3 capture in */
362 #define HPM_TRGM0_OUTPUT_SRC_GPTMR4_SYNCI (0x76UL) /* GPTMR4 hardware sync in */
363 #define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN2 (0x77UL) /* GPTMR5 channe2 capture in */
364 #define HPM_TRGM0_OUTPUT_SRC_GPTMR5_IN3 (0x78UL) /* GPTMR5 channe3 capture in */
365 #define HPM_TRGM0_OUTPUT_SRC_GPTMR5_SYNCI (0x79UL) /* GPTMR5 hardware sync in */
366 #define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN2 (0x7AUL) /* GPTMR6 channe2 capture in */
367 #define HPM_TRGM0_OUTPUT_SRC_GPTMR6_IN3 (0x7BUL) /* GPTMR6 channe3 capture in */
368 #define HPM_TRGM0_OUTPUT_SRC_GPTMR6_SYNCI (0x7CUL) /* GPTMR6 hardware sync in */
369 #define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN2 (0x7DUL) /* GPTMR7 channe2 capture in */
370 #define HPM_TRGM0_OUTPUT_SRC_GPTMR7_IN3 (0x7EUL) /* GPTMR7 channe3 capture in */
371 #define HPM_TRGM0_OUTPUT_SRC_GPTMR7_SYNCI (0x7FUL) /* GPTMR7 hardware sync in */
372 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_00 (0x80UL) /* PLB trigger in0 */
373 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_01 (0x81UL) /* PLB trigger in1 */
374 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_02 (0x82UL) /* PLB trigger in2 */
375 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_03 (0x83UL) /* PLB trigger in3 */
376 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_04 (0x84UL) /* PLB trigger in4 */
377 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_05 (0x85UL) /* PLB trigger in5 */
378 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_06 (0x86UL) /* PLB trigger in6 */
379 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_07 (0x87UL) /* PLB trigger in7 */
380 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_08 (0x88UL) /* PLB trigger in8 */
381 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_09 (0x89UL) /* PLB trigger in9 */
382 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_10 (0x8AUL) /* PLB trigger in10 */
383 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_11 (0x8BUL) /* PLB trigger in11 */
384 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_12 (0x8CUL) /* PLB trigger in12 */
385 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_13 (0x8DUL) /* PLB trigger in13 */
386 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_14 (0x8EUL) /* PLB trigger in14 */
387 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_15 (0x8FUL) /* PLB trigger in15 */
388 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_16 (0x90UL) /* PLB trigger in16 */
389 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_17 (0x91UL) /* PLB trigger in17 */
390 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_18 (0x92UL) /* PLB trigger in18 */
391 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_19 (0x93UL) /* PLB trigger in19 */
392 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_20 (0x94UL) /* PLB trigger in20 */
393 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_21 (0x95UL) /* PLB trigger in21 */
394 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_22 (0x96UL) /* PLB trigger in22 */
395 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_23 (0x97UL) /* PLB trigger in23 */
396 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_24 (0x98UL) /* PLB trigger in24 */
397 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_25 (0x99UL) /* PLB trigger in25 */
398 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_26 (0x9AUL) /* PLB trigger in26 */
399 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_27 (0x9BUL) /* PLB trigger in27 */
400 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_28 (0x9CUL) /* PLB trigger in28 */
401 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_29 (0x9DUL) /* PLB trigger in29 */
402 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_30 (0x9EUL) /* PLB trigger in30 */
403 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_31 (0x9FUL) /* PLB trigger in31 */
404 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_32 (0xA0UL) /* PLB trigger in32 */
405 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_33 (0xA1UL) /* PLB trigger in33 */
406 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_34 (0xA2UL) /* PLB trigger in34 */
407 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_35 (0xA3UL) /* PLB trigger in35 */
408 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_36 (0xA4UL) /* PLB trigger in36 */
409 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_37 (0xA5UL) /* PLB trigger in37 */
410 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_38 (0xA6UL) /* PLB trigger in38 */
411 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_39 (0xA7UL) /* PLB trigger in39 */
412 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_40 (0xA8UL) /* PLB trigger in40 */
413 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_41 (0xA9UL) /* PLB trigger in41 */
414 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_42 (0xAAUL) /* PLB trigger in42 */
415 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_43 (0xABUL) /* PLB trigger in43 */
416 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_44 (0xACUL) /* PLB trigger in44 */
417 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_45 (0xADUL) /* PLB trigger in45 */
418 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_46 (0xAEUL) /* PLB trigger in46 */
419 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_47 (0xAFUL) /* PLB trigger in47 */
420 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_48 (0xB0UL) /* PLB trigger in48 */
421 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_49 (0xB1UL) /* PLB trigger in49 */
422 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_50 (0xB2UL) /* PLB trigger in50 */
423 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_51 (0xB3UL) /* PLB trigger in51 */
424 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_52 (0xB4UL) /* PLB trigger in52 */
425 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_53 (0xB5UL) /* PLB trigger in53 */
426 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_54 (0xB6UL) /* PLB trigger in54 */
427 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_55 (0xB7UL) /* PLB trigger in55 */
428 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_56 (0xB8UL) /* PLB trigger in56 */
429 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_57 (0xB9UL) /* PLB trigger in57 */
430 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_58 (0xBAUL) /* PLB trigger in58 */
431 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_59 (0xBBUL) /* PLB trigger in59 */
432 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_60 (0xBCUL) /* PLB trigger in60 */
433 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_61 (0xBDUL) /* PLB trigger in61 */
434 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_62 (0xBEUL) /* PLB trigger in62 */
435 #define HPM_TRGM0_OUTPUT_SRC_PLB_IN_63 (0xBFUL) /* PLB trigger in63 */
436 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN0 (0xC0UL) /* PWM0 trigger in0 */
437 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN1 (0xC1UL) /* PWM0 trigger in1 */
438 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN2 (0xC2UL) /* PWM0 trigger in2 */
439 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN3 (0xC3UL) /* PWM0 trigger in3 */
440 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN4 (0xC4UL) /* PWM0 trigger in4 */
441 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN5 (0xC5UL) /* PWM0 trigger in5 */
442 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN6 (0xC6UL) /* PWM0 trigger in6 */
443 #define HPM_TRGM0_OUTPUT_SRC_PWM0_TRIG_IN7 (0xC7UL) /* PWM0 trigger in7 */
444 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN0 (0xC8UL) /* PWM1 trigger in0 */
445 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN1 (0xC9UL) /* PWM1 trigger in1 */
446 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN2 (0xCAUL) /* PWM1 trigger in2 */
447 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN3 (0xCBUL) /* PWM1 trigger in3 */
448 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN4 (0xCCUL) /* PWM1 trigger in4 */
449 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN5 (0xCDUL) /* PWM1 trigger in5 */
450 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN6 (0xCEUL) /* PWM1 trigger in6 */
451 #define HPM_TRGM0_OUTPUT_SRC_PWM1_TRIG_IN7 (0xCFUL) /* PWM1 trigger in7 */
452 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN0 (0xD0UL) /* PWM2 trigger in0 */
453 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN1 (0xD1UL) /* PWM2 trigger in1 */
454 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN2 (0xD2UL) /* PWM2 trigger in2 */
455 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN3 (0xD3UL) /* PWM2 trigger in3 */
456 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN4 (0xD4UL) /* PWM2 trigger in4 */
457 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN5 (0xD5UL) /* PWM2 trigger in5 */
458 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN6 (0xD6UL) /* PWM2 trigger in6 */
459 #define HPM_TRGM0_OUTPUT_SRC_PWM2_TRIG_IN7 (0xD7UL) /* PWM2 trigger in7 */
460 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN0 (0xD8UL) /* PWM3 trigger in0 */
461 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN1 (0xD9UL) /* PWM3 trigger in1 */
462 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN2 (0xDAUL) /* PWM3 trigger in2 */
463 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN3 (0xDBUL) /* PWM3 trigger in3 */
464 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN4 (0xDCUL) /* PWM3 trigger in4 */
465 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN5 (0xDDUL) /* PWM3 trigger in5 */
466 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN6 (0xDEUL) /* PWM3 trigger in6 */
467 #define HPM_TRGM0_OUTPUT_SRC_PWM3_TRIG_IN7 (0xDFUL) /* PWM3 trigger in7 */
468 #define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC0_CAP (0xE0UL) /* PTPC capture in0 */
469 #define HPM_TRGM0_OUTPUT_SRC_MCAN_PTPC1_CAP (0xE1UL) /* PTPC capture in1 */
470 #define HPM_TRGM0_OUTPUT_SRC_UART_TRIG0 (0xE2UL) /* UART0 ~ UART3 trigger event */
471 #define HPM_TRGM0_OUTPUT_SRC_UART_TRIG1 (0xE3UL) /* UART4 ~ UART7 trigger event */
472 #define HPM_TRGM0_OUTPUT_SRC_SYNCTIMER_TRIG (0xE4UL) /* SYNT sync trigger */
473 #define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ0 (0xE5UL) /* TRGM interrupt0 */
474 #define HPM_TRGM0_OUTPUT_SRC_TRGM_IRQ1 (0xE6UL) /* TRGM interrupt1 */
475 #define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA0 (0xE7UL) /* TRGM DMA request0 */
476 #define HPM_TRGM0_OUTPUT_SRC_TRGM_DMA1 (0xE8UL) /* TRGM DMA request1 */
477 #define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN0 (0xE9UL) /* MTG0 trigger in0 */
478 #define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN1 (0xEAUL) /* MTG0 trigger in1 */
479 #define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN2 (0xEBUL) /* MTG0 trigger in2 */
480 #define HPM_TRGM0_OUTPUT_SRC_MTG0_TRIG_IN3 (0xECUL) /* MTG0 trigger in3 */
481 #define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN0 (0xEDUL) /* MTG1 trigger in0 */
482 #define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN1 (0xEEUL) /* MTG1 trigger in1 */
483 #define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN2 (0xEFUL) /* MTG1 trigger in2 */
484 #define HPM_TRGM0_OUTPUT_SRC_MTG1_TRIG_IN3 (0xF0UL) /* MTG1 trigger in3 */
485 #define HPM_TRGM0_OUTPUT_SRC_ESC_TRIG_IN (0xF1UL) /* ESC latch0 */
486 
487 /* trgm0_filter mux definitions */
488 #define HPM_TRGM0_FILTER_SRC_PWM0_IN0 (0x0UL) /* PWM0 capture in0 */
489 #define HPM_TRGM0_FILTER_SRC_PWM0_IN1 (0x1UL) /* PWM0 capture in1 */
490 #define HPM_TRGM0_FILTER_SRC_PWM0_IN2 (0x2UL) /* PWM0 capture in2 */
491 #define HPM_TRGM0_FILTER_SRC_PWM0_IN3 (0x3UL) /* PWM0 capture in3 */
492 #define HPM_TRGM0_FILTER_SRC_PWM0_IN4 (0x4UL) /* PWM0 capture in4 */
493 #define HPM_TRGM0_FILTER_SRC_PWM0_IN5 (0x5UL) /* PWM0 capture in5 */
494 #define HPM_TRGM0_FILTER_SRC_PWM0_IN6 (0x6UL) /* PWM0 capture in6 */
495 #define HPM_TRGM0_FILTER_SRC_PWM0_IN7 (0x7UL) /* PWM0 capture in7 */
496 #define HPM_TRGM0_FILTER_SRC_PWM1_IN0 (0x8UL) /* PWM1 capture in0 */
497 #define HPM_TRGM0_FILTER_SRC_PWM1_IN1 (0x9UL) /* PWM1 capture in1 */
498 #define HPM_TRGM0_FILTER_SRC_PWM1_IN2 (0xAUL) /* PWM1 capture in2 */
499 #define HPM_TRGM0_FILTER_SRC_PWM1_IN3 (0xBUL) /* PWM1 capture in3 */
500 #define HPM_TRGM0_FILTER_SRC_PWM1_IN4 (0xCUL) /* PWM1 capture in4 */
501 #define HPM_TRGM0_FILTER_SRC_PWM1_IN5 (0xDUL) /* PWM1 capture in5 */
502 #define HPM_TRGM0_FILTER_SRC_PWM1_IN6 (0xEUL) /* PWM1 capture in6 */
503 #define HPM_TRGM0_FILTER_SRC_PWM1_IN7 (0xFUL) /* PWM1 capture in7 */
504 #define HPM_TRGM0_FILTER_SRC_PWM2_IN0 (0x10UL) /* PWM2 capture in0 */
505 #define HPM_TRGM0_FILTER_SRC_PWM2_IN1 (0x11UL) /* PWM2 capture in1 */
506 #define HPM_TRGM0_FILTER_SRC_PWM2_IN2 (0x12UL) /* PWM2 capture in2 */
507 #define HPM_TRGM0_FILTER_SRC_PWM2_IN3 (0x13UL) /* PWM2 capture in3 */
508 #define HPM_TRGM0_FILTER_SRC_PWM2_IN4 (0x14UL) /* PWM2 capture in4 */
509 #define HPM_TRGM0_FILTER_SRC_PWM2_IN5 (0x15UL) /* PWM2 capture in5 */
510 #define HPM_TRGM0_FILTER_SRC_PWM2_IN6 (0x16UL) /* PWM2 capture in6 */
511 #define HPM_TRGM0_FILTER_SRC_PWM2_IN7 (0x17UL) /* PWM2 capture in7 */
512 #define HPM_TRGM0_FILTER_SRC_PWM3_IN0 (0x18UL) /* PWM3 capture in0 */
513 #define HPM_TRGM0_FILTER_SRC_PWM3_IN1 (0x19UL) /* PWM3 capture in1 */
514 #define HPM_TRGM0_FILTER_SRC_PWM3_IN2 (0x1AUL) /* PWM3 capture in2 */
515 #define HPM_TRGM0_FILTER_SRC_PWM3_IN3 (0x1BUL) /* PWM3 capture in3 */
516 #define HPM_TRGM0_FILTER_SRC_PWM3_IN4 (0x1CUL) /* PWM3 capture in4 */
517 #define HPM_TRGM0_FILTER_SRC_PWM3_IN5 (0x1DUL) /* PWM3 capture in5 */
518 #define HPM_TRGM0_FILTER_SRC_PWM3_IN6 (0x1EUL) /* PWM3 capture in6 */
519 #define HPM_TRGM0_FILTER_SRC_PWM3_IN7 (0x1FUL) /* PWM3 capture in7 */
520 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN0 (0x20UL) /* TRGM input0 */
521 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN1 (0x21UL) /* TRGM input1 */
522 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN2 (0x22UL) /* TRGM input2 */
523 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN3 (0x23UL) /* TRGM input3 */
524 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN4 (0x24UL) /* TRGM input4 */
525 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN5 (0x25UL) /* TRGM input5 */
526 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN6 (0x26UL) /* TRGM input6 */
527 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN7 (0x27UL) /* TRGM input7 */
528 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN8 (0x28UL) /* TRGM input8 */
529 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN9 (0x29UL) /* TRGM input9 */
530 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN10 (0x2AUL) /* TRGM input10 */
531 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN11 (0x2BUL) /* TRGM input11 */
532 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN12 (0x2CUL) /* TRGM input12 */
533 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN13 (0x2DUL) /* TRGM input13 */
534 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN14 (0x2EUL) /* TRGM input14 */
535 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN15 (0x2FUL) /* TRGM input15 */
536 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN16 (0x30UL) /* TRGM input16 */
537 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN17 (0x31UL) /* TRGM input17 */
538 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN18 (0x32UL) /* TRGM input18 */
539 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN19 (0x33UL) /* TRGM input19 */
540 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN20 (0x34UL) /* TRGM input20 */
541 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN21 (0x35UL) /* TRGM input21 */
542 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN22 (0x36UL) /* TRGM input22 */
543 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN23 (0x37UL) /* TRGM input23 */
544 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN24 (0x38UL) /* TRGM input24 */
545 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN25 (0x39UL) /* TRGM input25 */
546 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN26 (0x3AUL) /* TRGM input26 */
547 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN27 (0x3BUL) /* TRGM input27 */
548 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN28 (0x3CUL) /* TRGM input28 */
549 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN29 (0x3DUL) /* TRGM input29 */
550 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN30 (0x3EUL) /* TRGM input30 */
551 #define HPM_TRGM0_FILTER_SRC_MOTO_GPIO_IN31 (0x3FUL) /* TRGM input31 */
552 
553 /* trgm0_dma mux definitions */
554 #define HPM_TRGM0_DMA_SRC_PWM0_REQ0 (0x0UL) /* PWM0 DMA request0 */
555 #define HPM_TRGM0_DMA_SRC_PWM0_REQ1 (0x1UL) /* PWM0 DMA request1 */
556 #define HPM_TRGM0_DMA_SRC_PWM0_REQ2 (0x2UL) /* PWM0 DMA request2 */
557 #define HPM_TRGM0_DMA_SRC_PWM0_REQ3 (0x3UL) /* PWM0 DMA request3 */
558 #define HPM_TRGM0_DMA_SRC_PWM1_REQ0 (0x4UL) /* PWM1 DMA request0 */
559 #define HPM_TRGM0_DMA_SRC_PWM1_REQ1 (0x5UL) /* PWM1 DMA request1 */
560 #define HPM_TRGM0_DMA_SRC_PWM1_REQ2 (0x6UL) /* PWM1 DMA request2 */
561 #define HPM_TRGM0_DMA_SRC_PWM1_REQ3 (0x7UL) /* PWM1 DMA request3 */
562 #define HPM_TRGM0_DMA_SRC_PWM2_REQ0 (0x8UL) /* PWM2 DMA request0 */
563 #define HPM_TRGM0_DMA_SRC_PWM2_REQ1 (0x9UL) /* PWM2 DMA request1 */
564 #define HPM_TRGM0_DMA_SRC_PWM2_REQ2 (0xAUL) /* PWM2 DMA request2 */
565 #define HPM_TRGM0_DMA_SRC_PWM2_REQ3 (0xBUL) /* PWM2 DMA request3 */
566 #define HPM_TRGM0_DMA_SRC_PWM3_REQ0 (0xCUL) /* PWM3 DMA request0 */
567 #define HPM_TRGM0_DMA_SRC_PWM3_REQ1 (0xDUL) /* PWM3 DMA request1 */
568 #define HPM_TRGM0_DMA_SRC_PWM3_REQ2 (0xEUL) /* PWM3 DMA request2 */
569 #define HPM_TRGM0_DMA_SRC_PWM3_REQ3 (0xFUL) /* PWM3 DMA request3 */
570 #define HPM_TRGM0_DMA_SRC_QEI0_REQ (0x10UL) /* QEI0 DMA request */
571 #define HPM_TRGM0_DMA_SRC_QEI1_REQ (0x11UL) /* QEI1 DMA request */
572 #define HPM_TRGM0_DMA_SRC_QEI2_REQ (0x12UL) /* QEI2 DMA request */
573 #define HPM_TRGM0_DMA_SRC_QEI3_REQ (0x13UL) /* QEI3 DMA request */
574 #define HPM_TRGM0_DMA_SRC_SEI_REQ0 (0x14UL) /* SEI DMA request0 */
575 #define HPM_TRGM0_DMA_SRC_SEI_REQ1 (0x15UL) /* SEI DMA request1 */
576 #define HPM_TRGM0_DMA_SRC_SEI_REQ2 (0x16UL) /* SEI DMA request2 */
577 #define HPM_TRGM0_DMA_SRC_SEI_REQ3 (0x17UL) /* SEI DMA request3 */
578 #define HPM_TRGM0_DMA_SRC_TRGM0 (0x18UL) /* TRGM DMA request0 from TRGM output 231 */
579 #define HPM_TRGM0_DMA_SRC_TRGM1 (0x19UL) /* TRGM DMA request1 from TRGM output 232 */
580 
581 
582 
583 #endif /* HPM_TRGMMUX_SRC_H */