HPM SDK
HPMicro Software Development Kit
hpm_sysctl_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SYSCTL_H
10 #define HPM_SYSCTL_H
11 
12 typedef struct {
13  __RW uint32_t RESOURCE[380]; /* 0x0 - 0x5EC: Resource control register for cpu0_core */
14  __R uint8_t RESERVED0[528]; /* 0x5F0 - 0x7FF: Reserved */
15  struct {
16  __RW uint32_t VALUE; /* 0x800: Group setting */
17  __RW uint32_t SET; /* 0x804: Group setting */
18  __RW uint32_t CLEAR; /* 0x808: Group setting */
19  __RW uint32_t TOGGLE; /* 0x80C: Group setting */
20  } GROUP0[4];
21  struct {
22  __RW uint32_t VALUE; /* 0x840: Group setting */
23  __RW uint32_t SET; /* 0x844: Group setting */
24  __RW uint32_t CLEAR; /* 0x848: Group setting */
25  __RW uint32_t TOGGLE; /* 0x84C: Group setting */
26  } GROUP1[4];
27  __R uint8_t RESERVED1[128]; /* 0x880 - 0x8FF: Reserved */
28  struct {
29  __RW uint32_t VALUE; /* 0x900: Affiliate of Group */
30  __RW uint32_t SET; /* 0x904: Affiliate of Group */
31  __RW uint32_t CLEAR; /* 0x908: Affiliate of Group */
32  __RW uint32_t TOGGLE; /* 0x90C: Affiliate of Group */
33  } AFFILIATE[2];
34  struct {
35  __RW uint32_t VALUE; /* 0x920: Retention Contol */
36  __RW uint32_t SET; /* 0x924: Retention Contol */
37  __RW uint32_t CLEAR; /* 0x928: Retention Contol */
38  __RW uint32_t TOGGLE; /* 0x92C: Retention Contol */
39  } RETENTION[2];
40  __R uint8_t RESERVED2[1728]; /* 0x940 - 0xFFF: Reserved */
41  struct {
42  __RW uint32_t STATUS; /* 0x1000: Power Setting */
43  __RW uint32_t LF_WAIT; /* 0x1004: Power Setting */
44  __R uint8_t RESERVED0[4]; /* 0x1008 - 0x100B: Reserved */
45  __RW uint32_t OFF_WAIT; /* 0x100C: Power Setting */
46  } POWER[3];
47  __R uint8_t RESERVED3[976]; /* 0x1030 - 0x13FF: Reserved */
48  struct {
49  __RW uint32_t CONTROL; /* 0x1400: Reset Setting */
50  __RW uint32_t CONFIG; /* 0x1404: Reset Setting */
51  __R uint8_t RESERVED0[4]; /* 0x1408 - 0x140B: Reserved */
52  __RW uint32_t COUNTER; /* 0x140C: Reset Setting */
53  } RESET[4];
54  __R uint8_t RESERVED4[960]; /* 0x1440 - 0x17FF: Reserved */
55  __RW uint32_t CLOCK[73]; /* 0x1800 - 0x1920: Clock setting */
56  __R uint8_t RESERVED5[732]; /* 0x1924 - 0x1BFF: Reserved */
57  __RW uint32_t ADCCLK[4]; /* 0x1C00 - 0x1C0C: Clock setting */
58  __RW uint32_t I2SCLK[2]; /* 0x1C10 - 0x1C14: Clock setting */
59  __R uint8_t RESERVED6[1000]; /* 0x1C18 - 0x1FFF: Reserved */
60  __RW uint32_t GLOBAL00; /* 0x2000: Clock senario */
61  __R uint8_t RESERVED7[1020]; /* 0x2004 - 0x23FF: Reserved */
62  struct {
63  __RW uint32_t CONTROL; /* 0x2400: Clock measure and monitor control */
64  __R uint32_t CURRENT; /* 0x2404: Clock measure result */
65  __RW uint32_t LOW_LIMIT; /* 0x2408: Clock lower limit */
66  __RW uint32_t HIGH_LIMIT; /* 0x240C: Clock upper limit */
67  __R uint8_t RESERVED0[16]; /* 0x2410 - 0x241F: Reserved */
68  } MONITOR[4];
69  __R uint8_t RESERVED8[896]; /* 0x2480 - 0x27FF: Reserved */
70  struct {
71  __RW uint32_t LP; /* 0x2800: CPU0 LP control */
72  __RW uint32_t LOCK; /* 0x2804: CPU0 Lock GPR */
73  __RW uint32_t GPR[14]; /* 0x2808 - 0x283C: CPU0 GPR0 */
74  __R uint32_t WAKEUP_STATUS[6]; /* 0x2840 - 0x2854: CPU0 wakeup IRQ status */
75  __R uint8_t RESERVED0[40]; /* 0x2858 - 0x287F: Reserved */
76  __RW uint32_t WAKEUP_ENABLE[6]; /* 0x2880 - 0x2894: CPU0 wakeup IRQ enable */
77  __R uint8_t RESERVED1[872]; /* 0x2898 - 0x2BFF: Reserved */
78  } CPU[2];
79 } SYSCTL_Type;
80 
81 
82 /* Bitfield definition for register array: RESOURCE */
83 /*
84  * GLB_BUSY (RO)
85  *
86  * global busy
87  * 0: no changes pending to any nodes
88  * 1: any of nodes is changing status
89  */
90 #define SYSCTL_RESOURCE_GLB_BUSY_MASK (0x80000000UL)
91 #define SYSCTL_RESOURCE_GLB_BUSY_SHIFT (31U)
92 #define SYSCTL_RESOURCE_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_GLB_BUSY_MASK) >> SYSCTL_RESOURCE_GLB_BUSY_SHIFT)
93 
94 /*
95  * LOC_BUSY (RO)
96  *
97  * local busy
98  * 0: no change is pending for current node
99  * 1: current node is changing status
100  */
101 #define SYSCTL_RESOURCE_LOC_BUSY_MASK (0x40000000UL)
102 #define SYSCTL_RESOURCE_LOC_BUSY_SHIFT (30U)
103 #define SYSCTL_RESOURCE_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_LOC_BUSY_MASK) >> SYSCTL_RESOURCE_LOC_BUSY_SHIFT)
104 
105 /*
106  * MODE (RW)
107  *
108  * resource work mode
109  * 0:auto turn on and off as system required(recommended)
110  * 1:always on
111  * 2:always off
112  * 3:reserved
113  */
114 #define SYSCTL_RESOURCE_MODE_MASK (0x3U)
115 #define SYSCTL_RESOURCE_MODE_SHIFT (0U)
116 #define SYSCTL_RESOURCE_MODE_SET(x) (((uint32_t)(x) << SYSCTL_RESOURCE_MODE_SHIFT) & SYSCTL_RESOURCE_MODE_MASK)
117 #define SYSCTL_RESOURCE_MODE_GET(x) (((uint32_t)(x) & SYSCTL_RESOURCE_MODE_MASK) >> SYSCTL_RESOURCE_MODE_SHIFT)
118 
119 /* Bitfield definition for register of struct array GROUP0: VALUE */
120 /*
121  * LINK (RW)
122  *
123  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
124  * 0: peripheral is not needed
125  * 1: periphera is needed
126  */
127 #define SYSCTL_GROUP0_VALUE_LINK_MASK (0xFFFFFFFFUL)
128 #define SYSCTL_GROUP0_VALUE_LINK_SHIFT (0U)
129 #define SYSCTL_GROUP0_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_VALUE_LINK_SHIFT) & SYSCTL_GROUP0_VALUE_LINK_MASK)
130 #define SYSCTL_GROUP0_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_VALUE_LINK_MASK) >> SYSCTL_GROUP0_VALUE_LINK_SHIFT)
131 
132 /* Bitfield definition for register of struct array GROUP0: SET */
133 /*
134  * LINK (RW)
135  *
136  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
137  * 0: no effect
138  * 1: add periphera into this group，periphera is needed
139  */
140 #define SYSCTL_GROUP0_SET_LINK_MASK (0xFFFFFFFFUL)
141 #define SYSCTL_GROUP0_SET_LINK_SHIFT (0U)
142 #define SYSCTL_GROUP0_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_SET_LINK_SHIFT) & SYSCTL_GROUP0_SET_LINK_MASK)
143 #define SYSCTL_GROUP0_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_SET_LINK_MASK) >> SYSCTL_GROUP0_SET_LINK_SHIFT)
144 
145 /* Bitfield definition for register of struct array GROUP0: CLEAR */
146 /*
147  * LINK (RW)
148  *
149  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
150  * 0: no effect
151  * 1: delete periphera in this group，periphera is not needed
152  */
153 #define SYSCTL_GROUP0_CLEAR_LINK_MASK (0xFFFFFFFFUL)
154 #define SYSCTL_GROUP0_CLEAR_LINK_SHIFT (0U)
155 #define SYSCTL_GROUP0_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_CLEAR_LINK_SHIFT) & SYSCTL_GROUP0_CLEAR_LINK_MASK)
156 #define SYSCTL_GROUP0_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_CLEAR_LINK_MASK) >> SYSCTL_GROUP0_CLEAR_LINK_SHIFT)
157 
158 /* Bitfield definition for register of struct array GROUP0: TOGGLE */
159 /*
160  * LINK (RW)
161  *
162  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
163  * 0: no effect
164  * 1: toggle the result that whether periphera is needed before
165  */
166 #define SYSCTL_GROUP0_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
167 #define SYSCTL_GROUP0_TOGGLE_LINK_SHIFT (0U)
168 #define SYSCTL_GROUP0_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP0_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP0_TOGGLE_LINK_MASK)
169 #define SYSCTL_GROUP0_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP0_TOGGLE_LINK_MASK) >> SYSCTL_GROUP0_TOGGLE_LINK_SHIFT)
170 
171 /* Bitfield definition for register of struct array GROUP1: VALUE */
172 /*
173  * LINK (RW)
174  *
175  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
176  * 0: peripheral is not needed
177  * 1: periphera is needed
178  */
179 #define SYSCTL_GROUP1_VALUE_LINK_MASK (0xFFFFFFFFUL)
180 #define SYSCTL_GROUP1_VALUE_LINK_SHIFT (0U)
181 #define SYSCTL_GROUP1_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_VALUE_LINK_SHIFT) & SYSCTL_GROUP1_VALUE_LINK_MASK)
182 #define SYSCTL_GROUP1_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_VALUE_LINK_MASK) >> SYSCTL_GROUP1_VALUE_LINK_SHIFT)
183 
184 /* Bitfield definition for register of struct array GROUP1: SET */
185 /*
186  * LINK (RW)
187  *
188  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
189  * 0: no effect
190  * 1: add periphera into this group，periphera is needed
191  */
192 #define SYSCTL_GROUP1_SET_LINK_MASK (0xFFFFFFFFUL)
193 #define SYSCTL_GROUP1_SET_LINK_SHIFT (0U)
194 #define SYSCTL_GROUP1_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_SET_LINK_SHIFT) & SYSCTL_GROUP1_SET_LINK_MASK)
195 #define SYSCTL_GROUP1_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_SET_LINK_MASK) >> SYSCTL_GROUP1_SET_LINK_SHIFT)
196 
197 /* Bitfield definition for register of struct array GROUP1: CLEAR */
198 /*
199  * LINK (RW)
200  *
201  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
202  * 0: no effect
203  * 1: delete periphera in this group，periphera is not needed
204  */
205 #define SYSCTL_GROUP1_CLEAR_LINK_MASK (0xFFFFFFFFUL)
206 #define SYSCTL_GROUP1_CLEAR_LINK_SHIFT (0U)
207 #define SYSCTL_GROUP1_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_CLEAR_LINK_SHIFT) & SYSCTL_GROUP1_CLEAR_LINK_MASK)
208 #define SYSCTL_GROUP1_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_CLEAR_LINK_MASK) >> SYSCTL_GROUP1_CLEAR_LINK_SHIFT)
209 
210 /* Bitfield definition for register of struct array GROUP1: TOGGLE */
211 /*
212  * LINK (RW)
213  *
214  * denpendency on peripherals, index count from resource ahbp(0x400), each bit represents a peripheral
215  * 0: no effect
216  * 1: toggle the result that whether periphera is needed before
217  */
218 #define SYSCTL_GROUP1_TOGGLE_LINK_MASK (0xFFFFFFFFUL)
219 #define SYSCTL_GROUP1_TOGGLE_LINK_SHIFT (0U)
220 #define SYSCTL_GROUP1_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_GROUP1_TOGGLE_LINK_SHIFT) & SYSCTL_GROUP1_TOGGLE_LINK_MASK)
221 #define SYSCTL_GROUP1_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_GROUP1_TOGGLE_LINK_MASK) >> SYSCTL_GROUP1_TOGGLE_LINK_SHIFT)
222 
223 /* Bitfield definition for register of struct array AFFILIATE: VALUE */
224 /*
225  * LINK (RW)
226  *
227  * Affiliate groups of cpu0, each bit represents a group
228  * bit0: cpu0 depends on group0
229  * bit1: cpu0 depends on group1
230  * bit2: cpu0 depends on group2
231  * bit3: cpu0 depends on group3
232  */
233 #define SYSCTL_AFFILIATE_VALUE_LINK_MASK (0xFU)
234 #define SYSCTL_AFFILIATE_VALUE_LINK_SHIFT (0U)
235 #define SYSCTL_AFFILIATE_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_VALUE_LINK_SHIFT) & SYSCTL_AFFILIATE_VALUE_LINK_MASK)
236 #define SYSCTL_AFFILIATE_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_VALUE_LINK_MASK) >> SYSCTL_AFFILIATE_VALUE_LINK_SHIFT)
237 
238 /* Bitfield definition for register of struct array AFFILIATE: SET */
239 /*
240  * LINK (RW)
241  *
242  * Affiliate groups of cpu0，each bit represents a group
243  * 0: no effect
244  * 1: the group is assigned to CPU0
245  */
246 #define SYSCTL_AFFILIATE_SET_LINK_MASK (0xFU)
247 #define SYSCTL_AFFILIATE_SET_LINK_SHIFT (0U)
248 #define SYSCTL_AFFILIATE_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_SET_LINK_SHIFT) & SYSCTL_AFFILIATE_SET_LINK_MASK)
249 #define SYSCTL_AFFILIATE_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_SET_LINK_MASK) >> SYSCTL_AFFILIATE_SET_LINK_SHIFT)
250 
251 /* Bitfield definition for register of struct array AFFILIATE: CLEAR */
252 /*
253  * LINK (RW)
254  *
255  * Affiliate groups of cpu0, each bit represents a group
256  * 0: no effect
257  * 1: the group is not assigned to CPU0
258  */
259 #define SYSCTL_AFFILIATE_CLEAR_LINK_MASK (0xFU)
260 #define SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT (0U)
261 #define SYSCTL_AFFILIATE_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK)
262 #define SYSCTL_AFFILIATE_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_CLEAR_LINK_MASK) >> SYSCTL_AFFILIATE_CLEAR_LINK_SHIFT)
263 
264 /* Bitfield definition for register of struct array AFFILIATE: TOGGLE */
265 /*
266  * LINK (RW)
267  *
268  * Affiliate groups of cpu0, each bit represents a group
269  * 0: no effect
270  * 1: toggle the result that whether the group is assigned to CPU0 before
271  */
272 #define SYSCTL_AFFILIATE_TOGGLE_LINK_MASK (0xFU)
273 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT (0U)
274 #define SYSCTL_AFFILIATE_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK)
275 #define SYSCTL_AFFILIATE_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_AFFILIATE_TOGGLE_LINK_MASK) >> SYSCTL_AFFILIATE_TOGGLE_LINK_SHIFT)
276 
277 /* Bitfield definition for register of struct array RETENTION: VALUE */
278 /*
279  * LINK (RW)
280  *
281  * retention setting while CPU0 enter stop mode, each bit represents a resource
282  * bit00: soc_mem is kept on while cpu0 stop
283  * bit01: soc_ctx is kept on while cpu0 stop
284  * bit02: cpu0_mem is kept on while cpu0 stop
285  * bit03: cpu0_ctx is kept on while cpu0 stop
286  * bit04: cpu1_mem is kept on while cpu0 stop
287  * bit05: cpu1_ctx is kept on while cpu0 stop
288  * bit06: otn_mem is kept on while cpu0 stop
289  * bit07: otn_ctx is kept on while cpu0 stop
290  * bit08: xtal_hold is kept on while cpu0 stop
291  * bit09: pll0_hold is kept on while cpu0 stop
292  * bit10: pll1_hold is kept on while cpu0 stop
293  * bit11: pll2_hold is kept on while cpu0 stop
294  */
295 #define SYSCTL_RETENTION_VALUE_LINK_MASK (0x7FFFU)
296 #define SYSCTL_RETENTION_VALUE_LINK_SHIFT (0U)
297 #define SYSCTL_RETENTION_VALUE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_VALUE_LINK_SHIFT) & SYSCTL_RETENTION_VALUE_LINK_MASK)
298 #define SYSCTL_RETENTION_VALUE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_VALUE_LINK_MASK) >> SYSCTL_RETENTION_VALUE_LINK_SHIFT)
299 
300 /* Bitfield definition for register of struct array RETENTION: SET */
301 /*
302  * LINK (RW)
303  *
304  * retention setting while CPU0 enter stop mode, each bit represents a resource
305  * 0: no effect
306  * 1: keep
307  */
308 #define SYSCTL_RETENTION_SET_LINK_MASK (0x7FFFU)
309 #define SYSCTL_RETENTION_SET_LINK_SHIFT (0U)
310 #define SYSCTL_RETENTION_SET_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_SET_LINK_SHIFT) & SYSCTL_RETENTION_SET_LINK_MASK)
311 #define SYSCTL_RETENTION_SET_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_SET_LINK_MASK) >> SYSCTL_RETENTION_SET_LINK_SHIFT)
312 
313 /* Bitfield definition for register of struct array RETENTION: CLEAR */
314 /*
315  * LINK (RW)
316  *
317  * retention setting while CPU0 enter stop mode, each bit represents a resource
318  * 0: no effect
319  * 1: no keep
320  */
321 #define SYSCTL_RETENTION_CLEAR_LINK_MASK (0x7FFFU)
322 #define SYSCTL_RETENTION_CLEAR_LINK_SHIFT (0U)
323 #define SYSCTL_RETENTION_CLEAR_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_CLEAR_LINK_SHIFT) & SYSCTL_RETENTION_CLEAR_LINK_MASK)
324 #define SYSCTL_RETENTION_CLEAR_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_CLEAR_LINK_MASK) >> SYSCTL_RETENTION_CLEAR_LINK_SHIFT)
325 
326 /* Bitfield definition for register of struct array RETENTION: TOGGLE */
327 /*
328  * LINK (RW)
329  *
330  * retention setting while CPU0 enter stop mode, each bit represents a resource
331  * 0: no effect
332  * 1: toggle the result that whether the resource is kept on while CPU0 stop before
333  */
334 #define SYSCTL_RETENTION_TOGGLE_LINK_MASK (0x7FFFU)
335 #define SYSCTL_RETENTION_TOGGLE_LINK_SHIFT (0U)
336 #define SYSCTL_RETENTION_TOGGLE_LINK_SET(x) (((uint32_t)(x) << SYSCTL_RETENTION_TOGGLE_LINK_SHIFT) & SYSCTL_RETENTION_TOGGLE_LINK_MASK)
337 #define SYSCTL_RETENTION_TOGGLE_LINK_GET(x) (((uint32_t)(x) & SYSCTL_RETENTION_TOGGLE_LINK_MASK) >> SYSCTL_RETENTION_TOGGLE_LINK_SHIFT)
338 
339 /* Bitfield definition for register of struct array POWER: STATUS */
340 /*
341  * FLAG (RW)
342  *
343  * flag represents power cycle happened from last clear of this bit
344  * 0: power domain did not edurance power cycle since last clear of this bit
345  * 1: power domain enduranced power cycle since last clear of this bit
346  */
347 #define SYSCTL_POWER_STATUS_FLAG_MASK (0x80000000UL)
348 #define SYSCTL_POWER_STATUS_FLAG_SHIFT (31U)
349 #define SYSCTL_POWER_STATUS_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_SHIFT) & SYSCTL_POWER_STATUS_FLAG_MASK)
350 #define SYSCTL_POWER_STATUS_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_MASK) >> SYSCTL_POWER_STATUS_FLAG_SHIFT)
351 
352 /*
353  * FLAG_WAKE (RW)
354  *
355  * flag represents wakeup power cycle happened from last clear of this bit
356  * 0: power domain did not edurance wakeup power cycle since last clear of this bit
357  * 1: power domain enduranced wakeup power cycle since last clear of this bit
358  */
359 #define SYSCTL_POWER_STATUS_FLAG_WAKE_MASK (0x40000000UL)
360 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT (30U)
361 #define SYSCTL_POWER_STATUS_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK)
362 #define SYSCTL_POWER_STATUS_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_FLAG_WAKE_MASK) >> SYSCTL_POWER_STATUS_FLAG_WAKE_SHIFT)
363 
364 /*
365  * LF_DISABLE (RO)
366  *
367  * low fanout power switch disable
368  * 0: low fanout power switches are turned on
369  * 1: low fanout power switches are truned off
370  */
371 #define SYSCTL_POWER_STATUS_LF_DISABLE_MASK (0x1000U)
372 #define SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT (12U)
373 #define SYSCTL_POWER_STATUS_LF_DISABLE_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_DISABLE_MASK) >> SYSCTL_POWER_STATUS_LF_DISABLE_SHIFT)
374 
375 /*
376  * LF_ACK (RO)
377  *
378  * low fanout power switch feedback
379  * 0: low fanout power switches are turned on
380  * 1: low fanout power switches are truned off
381  */
382 #define SYSCTL_POWER_STATUS_LF_ACK_MASK (0x100U)
383 #define SYSCTL_POWER_STATUS_LF_ACK_SHIFT (8U)
384 #define SYSCTL_POWER_STATUS_LF_ACK_GET(x) (((uint32_t)(x) & SYSCTL_POWER_STATUS_LF_ACK_MASK) >> SYSCTL_POWER_STATUS_LF_ACK_SHIFT)
385 
386 /* Bitfield definition for register of struct array POWER: LF_WAIT */
387 /*
388  * WAIT (RW)
389  *
390  * wait time for low fan out power switch turn on, default value is 255
391  * 0: 0 clock cycle
392  * 1: 1 clock cycles
393  * . . .
394  * clock cycles count on 24MHz
395  */
396 #define SYSCTL_POWER_LF_WAIT_WAIT_MASK (0xFFFFFUL)
397 #define SYSCTL_POWER_LF_WAIT_WAIT_SHIFT (0U)
398 #define SYSCTL_POWER_LF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_LF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_LF_WAIT_WAIT_MASK)
399 #define SYSCTL_POWER_LF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_LF_WAIT_WAIT_MASK) >> SYSCTL_POWER_LF_WAIT_WAIT_SHIFT)
400 
401 /* Bitfield definition for register of struct array POWER: OFF_WAIT */
402 /*
403  * WAIT (RW)
404  *
405  * wait time for power switch turn off, default value is 15
406  * 0: 0 clock cycle
407  * 1: 1 clock cycles
408  * . . .
409  * clock cycles count on 24MHz
410  */
411 #define SYSCTL_POWER_OFF_WAIT_WAIT_MASK (0xFFFFFUL)
412 #define SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT (0U)
413 #define SYSCTL_POWER_OFF_WAIT_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK)
414 #define SYSCTL_POWER_OFF_WAIT_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_POWER_OFF_WAIT_WAIT_MASK) >> SYSCTL_POWER_OFF_WAIT_WAIT_SHIFT)
415 
416 /* Bitfield definition for register of struct array RESET: CONTROL */
417 /*
418  * FLAG (RW)
419  *
420  * flag represents reset happened from last clear of this bit
421  * 0: domain did not edurance reset cycle since last clear of this bit
422  * 1: domain enduranced reset cycle since last clear of this bit
423  */
424 #define SYSCTL_RESET_CONTROL_FLAG_MASK (0x80000000UL)
425 #define SYSCTL_RESET_CONTROL_FLAG_SHIFT (31U)
426 #define SYSCTL_RESET_CONTROL_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_MASK)
427 #define SYSCTL_RESET_CONTROL_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_MASK) >> SYSCTL_RESET_CONTROL_FLAG_SHIFT)
428 
429 /*
430  * FLAG_WAKE (RW)
431  *
432  * flag represents wakeup reset happened from last clear of this bit
433  * 0: domain did not edurance wakeup reset cycle since last clear of this bit
434  * 1: domain enduranced wakeup reset cycle since last clear of this bit
435  */
436 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK (0x40000000UL)
437 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT (30U)
438 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK)
439 #define SYSCTL_RESET_CONTROL_FLAG_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_FLAG_WAKE_MASK) >> SYSCTL_RESET_CONTROL_FLAG_WAKE_SHIFT)
440 
441 /*
442  * HOLD (RW)
443  *
444  * perform reset and hold in reset, until ths bit cleared by software
445  * 0: reset is released for function
446  * 1: reset is assert and hold
447  */
448 #define SYSCTL_RESET_CONTROL_HOLD_MASK (0x10U)
449 #define SYSCTL_RESET_CONTROL_HOLD_SHIFT (4U)
450 #define SYSCTL_RESET_CONTROL_HOLD_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_HOLD_SHIFT) & SYSCTL_RESET_CONTROL_HOLD_MASK)
451 #define SYSCTL_RESET_CONTROL_HOLD_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_HOLD_MASK) >> SYSCTL_RESET_CONTROL_HOLD_SHIFT)
452 
453 /*
454  * RESET (RW)
455  *
456  * perform reset and release imediately
457  * 0: reset is released
458  * 1 reset is asserted and will release automaticly
459  */
460 #define SYSCTL_RESET_CONTROL_RESET_MASK (0x1U)
461 #define SYSCTL_RESET_CONTROL_RESET_SHIFT (0U)
462 #define SYSCTL_RESET_CONTROL_RESET_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONTROL_RESET_SHIFT) & SYSCTL_RESET_CONTROL_RESET_MASK)
463 #define SYSCTL_RESET_CONTROL_RESET_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONTROL_RESET_MASK) >> SYSCTL_RESET_CONTROL_RESET_SHIFT)
464 
465 /* Bitfield definition for register of struct array RESET: CONFIG */
466 /*
467  * PRE_WAIT (RW)
468  *
469  * wait cycle numbers before assert reset
470  * 0: wait 0 cycle
471  * 1: wait 1 cycles
472  * . . .
473  * Note, clock cycle is base on 24M
474  */
475 #define SYSCTL_RESET_CONFIG_PRE_WAIT_MASK (0xFF0000UL)
476 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT (16U)
477 #define SYSCTL_RESET_CONFIG_PRE_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK)
478 #define SYSCTL_RESET_CONFIG_PRE_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_PRE_WAIT_MASK) >> SYSCTL_RESET_CONFIG_PRE_WAIT_SHIFT)
479 
480 /*
481  * RSTCLK_NUM (RW)
482  *
483  * reset clock number(must be even number)
484  * 0: 0 cycle
485  * 1: 0 cycles
486  * 2: 2 cycles
487  * 3: 2 cycles
488  * . . .
489  * Note, clock cycle is base on 24M
490  */
491 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK (0xFF00U)
492 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT (8U)
493 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK)
494 #define SYSCTL_RESET_CONFIG_RSTCLK_NUM_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_RSTCLK_NUM_MASK) >> SYSCTL_RESET_CONFIG_RSTCLK_NUM_SHIFT)
495 
496 /*
497  * POST_WAIT (RW)
498  *
499  * time guard band for reset release
500  * 0: wait 0 cycle
501  * 1: wait 1 cycles
502  * . . .
503  * Note, clock cycle is base on 24M
504  */
505 #define SYSCTL_RESET_CONFIG_POST_WAIT_MASK (0xFFU)
506 #define SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT (0U)
507 #define SYSCTL_RESET_CONFIG_POST_WAIT_SET(x) (((uint32_t)(x) << SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK)
508 #define SYSCTL_RESET_CONFIG_POST_WAIT_GET(x) (((uint32_t)(x) & SYSCTL_RESET_CONFIG_POST_WAIT_MASK) >> SYSCTL_RESET_CONFIG_POST_WAIT_SHIFT)
509 
510 /* Bitfield definition for register of struct array RESET: COUNTER */
511 /*
512  * COUNTER (RW)
513  *
514  * self clear trigger counter, reset triggered when counter value is 1, write 0 will cancel reset
515  * 0: wait 0 cycle
516  * 1: wait 1 cycles
517  * . . .
518  * Note, clock cycle is base on 24M
519  */
520 #define SYSCTL_RESET_COUNTER_COUNTER_MASK (0xFFFFFUL)
521 #define SYSCTL_RESET_COUNTER_COUNTER_SHIFT (0U)
522 #define SYSCTL_RESET_COUNTER_COUNTER_SET(x) (((uint32_t)(x) << SYSCTL_RESET_COUNTER_COUNTER_SHIFT) & SYSCTL_RESET_COUNTER_COUNTER_MASK)
523 #define SYSCTL_RESET_COUNTER_COUNTER_GET(x) (((uint32_t)(x) & SYSCTL_RESET_COUNTER_COUNTER_MASK) >> SYSCTL_RESET_COUNTER_COUNTER_SHIFT)
524 
525 /* Bitfield definition for register array: CLOCK */
526 /*
527  * GLB_BUSY (RO)
528  *
529  * global busy
530  * 0: no changes pending to any clock
531  * 1: any of nodes is changing status
532  */
533 #define SYSCTL_CLOCK_GLB_BUSY_MASK (0x80000000UL)
534 #define SYSCTL_CLOCK_GLB_BUSY_SHIFT (31U)
535 #define SYSCTL_CLOCK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_GLB_BUSY_MASK) >> SYSCTL_CLOCK_GLB_BUSY_SHIFT)
536 
537 /*
538  * LOC_BUSY (RO)
539  *
540  * local busy
541  * 0: a change is pending for current node
542  * 1: current node is changing status
543  */
544 #define SYSCTL_CLOCK_LOC_BUSY_MASK (0x40000000UL)
545 #define SYSCTL_CLOCK_LOC_BUSY_SHIFT (30U)
546 #define SYSCTL_CLOCK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_LOC_BUSY_MASK) >> SYSCTL_CLOCK_LOC_BUSY_SHIFT)
547 
548 /*
549  * PRESERVE (RW)
550  *
551  * preserve function against global select
552  * 0: select global clock setting
553  * 1: not select global clock setting
554  */
555 #define SYSCTL_CLOCK_PRESERVE_MASK (0x10000000UL)
556 #define SYSCTL_CLOCK_PRESERVE_SHIFT (28U)
557 #define SYSCTL_CLOCK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_PRESERVE_SHIFT) & SYSCTL_CLOCK_PRESERVE_MASK)
558 #define SYSCTL_CLOCK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_PRESERVE_MASK) >> SYSCTL_CLOCK_PRESERVE_SHIFT)
559 
560 /*
561  * MUX (RW)
562  *
563  * current mux in clock component
564  * 0:osc0_clk0
565  * 1:pll0_clk0
566  * 2:pll0_clk1
567  * 3:pll1_clk0
568  * 4:pll1_clk1
569  * 5:pll1_clk2
570  * 6:pll2_clk0
571  * 7:pll2_clk1
572  */
573 #define SYSCTL_CLOCK_MUX_MASK (0x700U)
574 #define SYSCTL_CLOCK_MUX_SHIFT (8U)
575 #define SYSCTL_CLOCK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_MUX_SHIFT) & SYSCTL_CLOCK_MUX_MASK)
576 #define SYSCTL_CLOCK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_MUX_MASK) >> SYSCTL_CLOCK_MUX_SHIFT)
577 
578 /*
579  * DIV (RW)
580  *
581  * clock divider
582  * 0: divider by 1
583  * 1: divider by 2
584  * 2: divider by 3
585  * . . .
586  * 255: divider by 256
587  */
588 #define SYSCTL_CLOCK_DIV_MASK (0xFFU)
589 #define SYSCTL_CLOCK_DIV_SHIFT (0U)
590 #define SYSCTL_CLOCK_DIV_SET(x) (((uint32_t)(x) << SYSCTL_CLOCK_DIV_SHIFT) & SYSCTL_CLOCK_DIV_MASK)
591 #define SYSCTL_CLOCK_DIV_GET(x) (((uint32_t)(x) & SYSCTL_CLOCK_DIV_MASK) >> SYSCTL_CLOCK_DIV_SHIFT)
592 
593 /* Bitfield definition for register array: ADCCLK */
594 /*
595  * GLB_BUSY (RO)
596  *
597  * global busy
598  * 0: no changes pending to any clock
599  * 1: any of nodes is changing status
600  */
601 #define SYSCTL_ADCCLK_GLB_BUSY_MASK (0x80000000UL)
602 #define SYSCTL_ADCCLK_GLB_BUSY_SHIFT (31U)
603 #define SYSCTL_ADCCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_GLB_BUSY_MASK) >> SYSCTL_ADCCLK_GLB_BUSY_SHIFT)
604 
605 /*
606  * LOC_BUSY (RO)
607  *
608  * local busy
609  * 0: a change is pending for current node
610  * 1: current node is changing status
611  */
612 #define SYSCTL_ADCCLK_LOC_BUSY_MASK (0x40000000UL)
613 #define SYSCTL_ADCCLK_LOC_BUSY_SHIFT (30U)
614 #define SYSCTL_ADCCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_LOC_BUSY_MASK) >> SYSCTL_ADCCLK_LOC_BUSY_SHIFT)
615 
616 /*
617  * PRESERVE (RW)
618  *
619  * preserve function against global select
620  * 0: select global clock setting
621  * 1: not select global clock setting
622  */
623 #define SYSCTL_ADCCLK_PRESERVE_MASK (0x10000000UL)
624 #define SYSCTL_ADCCLK_PRESERVE_SHIFT (28U)
625 #define SYSCTL_ADCCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_PRESERVE_SHIFT) & SYSCTL_ADCCLK_PRESERVE_MASK)
626 #define SYSCTL_ADCCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_PRESERVE_MASK) >> SYSCTL_ADCCLK_PRESERVE_SHIFT)
627 
628 /*
629  * MUX (RW)
630  *
631  * current mux
632  * 0: ana clock N
633  * 1: ahb0 clock
634  */
635 #define SYSCTL_ADCCLK_MUX_MASK (0x100U)
636 #define SYSCTL_ADCCLK_MUX_SHIFT (8U)
637 #define SYSCTL_ADCCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_ADCCLK_MUX_SHIFT) & SYSCTL_ADCCLK_MUX_MASK)
638 #define SYSCTL_ADCCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_ADCCLK_MUX_MASK) >> SYSCTL_ADCCLK_MUX_SHIFT)
639 
640 /* Bitfield definition for register array: I2SCLK */
641 /*
642  * GLB_BUSY (RO)
643  *
644  * global busy
645  * 0: no changes pending to any clock
646  * 1: any of nodes is changing status
647  */
648 #define SYSCTL_I2SCLK_GLB_BUSY_MASK (0x80000000UL)
649 #define SYSCTL_I2SCLK_GLB_BUSY_SHIFT (31U)
650 #define SYSCTL_I2SCLK_GLB_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_GLB_BUSY_MASK) >> SYSCTL_I2SCLK_GLB_BUSY_SHIFT)
651 
652 /*
653  * LOC_BUSY (RO)
654  *
655  * local busy
656  * 0: a change is pending for current node
657  * 1: current node is changing status
658  */
659 #define SYSCTL_I2SCLK_LOC_BUSY_MASK (0x40000000UL)
660 #define SYSCTL_I2SCLK_LOC_BUSY_SHIFT (30U)
661 #define SYSCTL_I2SCLK_LOC_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_LOC_BUSY_MASK) >> SYSCTL_I2SCLK_LOC_BUSY_SHIFT)
662 
663 /*
664  * PRESERVE (RW)
665  *
666  * preserve function against global select
667  * 0: select global clock setting
668  * 1: not select global clock setting
669  */
670 #define SYSCTL_I2SCLK_PRESERVE_MASK (0x10000000UL)
671 #define SYSCTL_I2SCLK_PRESERVE_SHIFT (28U)
672 #define SYSCTL_I2SCLK_PRESERVE_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_PRESERVE_SHIFT) & SYSCTL_I2SCLK_PRESERVE_MASK)
673 #define SYSCTL_I2SCLK_PRESERVE_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_PRESERVE_MASK) >> SYSCTL_I2SCLK_PRESERVE_SHIFT)
674 
675 /*
676  * MUX (RW)
677  *
678  * current mux
679  * 0: aud clock N
680  * 1: aud clock 0 for others , aud clock 1 for i2s0
681  */
682 #define SYSCTL_I2SCLK_MUX_MASK (0x100U)
683 #define SYSCTL_I2SCLK_MUX_SHIFT (8U)
684 #define SYSCTL_I2SCLK_MUX_SET(x) (((uint32_t)(x) << SYSCTL_I2SCLK_MUX_SHIFT) & SYSCTL_I2SCLK_MUX_MASK)
685 #define SYSCTL_I2SCLK_MUX_GET(x) (((uint32_t)(x) & SYSCTL_I2SCLK_MUX_MASK) >> SYSCTL_I2SCLK_MUX_SHIFT)
686 
687 /* Bitfield definition for register: GLOBAL00 */
688 /*
689  * MUX (RW)
690  *
691  * global clock override request
692  * bit0: override to preset0
693  * bit1: override to preset1
694  * bit2: override to preset2
695  * bit3: override to preset3
696  * bit4: override to preset4
697  * bit5: override to preset5
698  * bit6: override to preset6
699  * bit7: override to preset7
700  */
701 #define SYSCTL_GLOBAL00_MUX_MASK (0xFFU)
702 #define SYSCTL_GLOBAL00_MUX_SHIFT (0U)
703 #define SYSCTL_GLOBAL00_MUX_SET(x) (((uint32_t)(x) << SYSCTL_GLOBAL00_MUX_SHIFT) & SYSCTL_GLOBAL00_MUX_MASK)
704 #define SYSCTL_GLOBAL00_MUX_GET(x) (((uint32_t)(x) & SYSCTL_GLOBAL00_MUX_MASK) >> SYSCTL_GLOBAL00_MUX_SHIFT)
705 
706 /* Bitfield definition for register of struct array MONITOR: CONTROL */
707 /*
708  * VALID (RW)
709  *
710  * result is ready for read
711  * 0: not ready
712  * 1: result is ready
713  */
714 #define SYSCTL_MONITOR_CONTROL_VALID_MASK (0x80000000UL)
715 #define SYSCTL_MONITOR_CONTROL_VALID_SHIFT (31U)
716 #define SYSCTL_MONITOR_CONTROL_VALID_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_VALID_SHIFT) & SYSCTL_MONITOR_CONTROL_VALID_MASK)
717 #define SYSCTL_MONITOR_CONTROL_VALID_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_VALID_MASK) >> SYSCTL_MONITOR_CONTROL_VALID_SHIFT)
718 
719 /*
720  * DIV_BUSY (RO)
721  *
722  * divider is applying new setting
723  */
724 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK (0x8000000UL)
725 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT (27U)
726 #define SYSCTL_MONITOR_CONTROL_DIV_BUSY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_BUSY_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_BUSY_SHIFT)
727 
728 /*
729  * OUTEN (RW)
730  *
731  * enable clock output
732  */
733 #define SYSCTL_MONITOR_CONTROL_OUTEN_MASK (0x1000000UL)
734 #define SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT (24U)
735 #define SYSCTL_MONITOR_CONTROL_OUTEN_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK)
736 #define SYSCTL_MONITOR_CONTROL_OUTEN_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_OUTEN_MASK) >> SYSCTL_MONITOR_CONTROL_OUTEN_SHIFT)
737 
738 /*
739  * DIV (RW)
740  *
741  * output divider
742  */
743 #define SYSCTL_MONITOR_CONTROL_DIV_MASK (0xFF0000UL)
744 #define SYSCTL_MONITOR_CONTROL_DIV_SHIFT (16U)
745 #define SYSCTL_MONITOR_CONTROL_DIV_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_DIV_SHIFT) & SYSCTL_MONITOR_CONTROL_DIV_MASK)
746 #define SYSCTL_MONITOR_CONTROL_DIV_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_DIV_MASK) >> SYSCTL_MONITOR_CONTROL_DIV_SHIFT)
747 
748 /*
749  * HIGH (RW)
750  *
751  * clock frequency higher than upper limit
752  */
753 #define SYSCTL_MONITOR_CONTROL_HIGH_MASK (0x8000U)
754 #define SYSCTL_MONITOR_CONTROL_HIGH_SHIFT (15U)
755 #define SYSCTL_MONITOR_CONTROL_HIGH_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_HIGH_SHIFT) & SYSCTL_MONITOR_CONTROL_HIGH_MASK)
756 #define SYSCTL_MONITOR_CONTROL_HIGH_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_HIGH_MASK) >> SYSCTL_MONITOR_CONTROL_HIGH_SHIFT)
757 
758 /*
759  * LOW (RW)
760  *
761  * clock frequency lower than lower limit
762  */
763 #define SYSCTL_MONITOR_CONTROL_LOW_MASK (0x4000U)
764 #define SYSCTL_MONITOR_CONTROL_LOW_SHIFT (14U)
765 #define SYSCTL_MONITOR_CONTROL_LOW_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_LOW_SHIFT) & SYSCTL_MONITOR_CONTROL_LOW_MASK)
766 #define SYSCTL_MONITOR_CONTROL_LOW_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_LOW_MASK) >> SYSCTL_MONITOR_CONTROL_LOW_SHIFT)
767 
768 /*
769  * START (RW)
770  *
771  * start measurement
772  */
773 #define SYSCTL_MONITOR_CONTROL_START_MASK (0x1000U)
774 #define SYSCTL_MONITOR_CONTROL_START_SHIFT (12U)
775 #define SYSCTL_MONITOR_CONTROL_START_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_START_SHIFT) & SYSCTL_MONITOR_CONTROL_START_MASK)
776 #define SYSCTL_MONITOR_CONTROL_START_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_START_MASK) >> SYSCTL_MONITOR_CONTROL_START_SHIFT)
777 
778 /*
779  * MODE (RW)
780  *
781  * work mode,
782  * 0: register value will be compared to measurement
783  * 1: upper and lower value will be recordered in register
784  */
785 #define SYSCTL_MONITOR_CONTROL_MODE_MASK (0x400U)
786 #define SYSCTL_MONITOR_CONTROL_MODE_SHIFT (10U)
787 #define SYSCTL_MONITOR_CONTROL_MODE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_MODE_SHIFT) & SYSCTL_MONITOR_CONTROL_MODE_MASK)
788 #define SYSCTL_MONITOR_CONTROL_MODE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_MODE_MASK) >> SYSCTL_MONITOR_CONTROL_MODE_SHIFT)
789 
790 /*
791  * ACCURACY (RW)
792  *
793  * measurement accuracy,
794  * 0: resolution is 1kHz
795  * 1: resolution is 1Hz
796  */
797 #define SYSCTL_MONITOR_CONTROL_ACCURACY_MASK (0x200U)
798 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT (9U)
799 #define SYSCTL_MONITOR_CONTROL_ACCURACY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK)
800 #define SYSCTL_MONITOR_CONTROL_ACCURACY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_ACCURACY_MASK) >> SYSCTL_MONITOR_CONTROL_ACCURACY_SHIFT)
801 
802 /*
803  * REFERENCE (RW)
804  *
805  * refrence clock selection,
806  * 0: 32k
807  * 1: 24M
808  */
809 #define SYSCTL_MONITOR_CONTROL_REFERENCE_MASK (0x100U)
810 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT (8U)
811 #define SYSCTL_MONITOR_CONTROL_REFERENCE_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK)
812 #define SYSCTL_MONITOR_CONTROL_REFERENCE_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_REFERENCE_MASK) >> SYSCTL_MONITOR_CONTROL_REFERENCE_SHIFT)
813 
814 /*
815  * SELECTION (RW)
816  *
817  * clock measurement selection
818  */
819 #define SYSCTL_MONITOR_CONTROL_SELECTION_MASK (0xFFU)
820 #define SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT (0U)
821 #define SYSCTL_MONITOR_CONTROL_SELECTION_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK)
822 #define SYSCTL_MONITOR_CONTROL_SELECTION_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CONTROL_SELECTION_MASK) >> SYSCTL_MONITOR_CONTROL_SELECTION_SHIFT)
823 
824 /* Bitfield definition for register of struct array MONITOR: CURRENT */
825 /*
826  * FREQUENCY (RO)
827  *
828  * self updating measure result
829  */
830 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK (0xFFFFFFFFUL)
831 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT (0U)
832 #define SYSCTL_MONITOR_CURRENT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_CURRENT_FREQUENCY_MASK) >> SYSCTL_MONITOR_CURRENT_FREQUENCY_SHIFT)
833 
834 /* Bitfield definition for register of struct array MONITOR: LOW_LIMIT */
835 /*
836  * FREQUENCY (RW)
837  *
838  * lower frequency
839  */
840 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
841 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT (0U)
842 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK)
843 #define SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_LOW_LIMIT_FREQUENCY_SHIFT)
844 
845 /* Bitfield definition for register of struct array MONITOR: HIGH_LIMIT */
846 /*
847  * FREQUENCY (RW)
848  *
849  * upper frequency
850  */
851 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK (0xFFFFFFFFUL)
852 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT (0U)
853 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SET(x) (((uint32_t)(x) << SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK)
854 #define SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_GET(x) (((uint32_t)(x) & SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_MASK) >> SYSCTL_MONITOR_HIGH_LIMIT_FREQUENCY_SHIFT)
855 
856 /* Bitfield definition for register of struct array CPU: LP */
857 /*
858  * WAKE_CNT (RW)
859  *
860  * CPU0 wake up counter, counter satuated at 255, write 0x00 to clear
861  */
862 #define SYSCTL_CPU_LP_WAKE_CNT_MASK (0xFF000000UL)
863 #define SYSCTL_CPU_LP_WAKE_CNT_SHIFT (24U)
864 #define SYSCTL_CPU_LP_WAKE_CNT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_CNT_SHIFT) & SYSCTL_CPU_LP_WAKE_CNT_MASK)
865 #define SYSCTL_CPU_LP_WAKE_CNT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_CNT_MASK) >> SYSCTL_CPU_LP_WAKE_CNT_SHIFT)
866 
867 /*
868  * HALT (RW)
869  *
870  * halt request for CPU0,
871  * 0: CPU0 will start to execute after reset or receive wakeup request
872  * 1: CPU0 will not start after reset, or wakeup after WFI
873  */
874 #define SYSCTL_CPU_LP_HALT_MASK (0x10000UL)
875 #define SYSCTL_CPU_LP_HALT_SHIFT (16U)
876 #define SYSCTL_CPU_LP_HALT_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_HALT_SHIFT) & SYSCTL_CPU_LP_HALT_MASK)
877 #define SYSCTL_CPU_LP_HALT_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_HALT_MASK) >> SYSCTL_CPU_LP_HALT_SHIFT)
878 
879 /*
880  * WAKE (RO)
881  *
882  * CPU0 is waking up
883  * 0: CPU0 wake up not asserted
884  * 1: CPU0 wake up asserted
885  */
886 #define SYSCTL_CPU_LP_WAKE_MASK (0x2000U)
887 #define SYSCTL_CPU_LP_WAKE_SHIFT (13U)
888 #define SYSCTL_CPU_LP_WAKE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_MASK) >> SYSCTL_CPU_LP_WAKE_SHIFT)
889 
890 /*
891  * EXEC (RO)
892  *
893  * CPU0 is executing
894  * 0: CPU0 is not executing
895  * 1: CPU0 is executing
896  */
897 #define SYSCTL_CPU_LP_EXEC_MASK (0x1000U)
898 #define SYSCTL_CPU_LP_EXEC_SHIFT (12U)
899 #define SYSCTL_CPU_LP_EXEC_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_EXEC_MASK) >> SYSCTL_CPU_LP_EXEC_SHIFT)
900 
901 /*
902  * WAKE_FLAG (RW)
903  *
904  * CPU0 wakeup flag, indicate a wakeup event got active, write 1 to clear this bit
905  * 0: CPU0 wakeup not happened
906  * 1: CPU0 wake up happened
907  */
908 #define SYSCTL_CPU_LP_WAKE_FLAG_MASK (0x400U)
909 #define SYSCTL_CPU_LP_WAKE_FLAG_SHIFT (10U)
910 #define SYSCTL_CPU_LP_WAKE_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_WAKE_FLAG_SHIFT) & SYSCTL_CPU_LP_WAKE_FLAG_MASK)
911 #define SYSCTL_CPU_LP_WAKE_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_WAKE_FLAG_MASK) >> SYSCTL_CPU_LP_WAKE_FLAG_SHIFT)
912 
913 /*
914  * SLEEP_FLAG (RW)
915  *
916  * CPU0 sleep flag, indicate a sleep event got active, write 1 to clear this bit
917  * 0: CPU0 sleep not happened
918  * 1: CPU0 sleep happened
919  */
920 #define SYSCTL_CPU_LP_SLEEP_FLAG_MASK (0x200U)
921 #define SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT (9U)
922 #define SYSCTL_CPU_LP_SLEEP_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK)
923 #define SYSCTL_CPU_LP_SLEEP_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_SLEEP_FLAG_MASK) >> SYSCTL_CPU_LP_SLEEP_FLAG_SHIFT)
924 
925 /*
926  * RESET_FLAG (RW)
927  *
928  * CPU0 reset flag, indicate a reset event got active, write 1 to clear this bit
929  * 0: CPU0 reset not happened
930  * 1: CPU0 reset happened
931  */
932 #define SYSCTL_CPU_LP_RESET_FLAG_MASK (0x100U)
933 #define SYSCTL_CPU_LP_RESET_FLAG_SHIFT (8U)
934 #define SYSCTL_CPU_LP_RESET_FLAG_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_RESET_FLAG_SHIFT) & SYSCTL_CPU_LP_RESET_FLAG_MASK)
935 #define SYSCTL_CPU_LP_RESET_FLAG_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_RESET_FLAG_MASK) >> SYSCTL_CPU_LP_RESET_FLAG_SHIFT)
936 
937 /*
938  * MODE (RW)
939  *
940  * Low power mode, system behavior after WFI
941  * 00: CPU clock stop after WFI
942  * 01: System enter low power mode after WFI
943  * 10: Keep running after WFI
944  * 11: reserved
945  */
946 #define SYSCTL_CPU_LP_MODE_MASK (0x3U)
947 #define SYSCTL_CPU_LP_MODE_SHIFT (0U)
948 #define SYSCTL_CPU_LP_MODE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LP_MODE_SHIFT) & SYSCTL_CPU_LP_MODE_MASK)
949 #define SYSCTL_CPU_LP_MODE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LP_MODE_MASK) >> SYSCTL_CPU_LP_MODE_SHIFT)
950 
951 /* Bitfield definition for register of struct array CPU: LOCK */
952 /*
953  * GPR (RW)
954  *
955  * Lock bit for CPU_DATA0 to CPU_DATA13, once set, this bit will not clear untile next reset
956  */
957 #define SYSCTL_CPU_LOCK_GPR_MASK (0xFFFCU)
958 #define SYSCTL_CPU_LOCK_GPR_SHIFT (2U)
959 #define SYSCTL_CPU_LOCK_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_GPR_SHIFT) & SYSCTL_CPU_LOCK_GPR_MASK)
960 #define SYSCTL_CPU_LOCK_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_GPR_MASK) >> SYSCTL_CPU_LOCK_GPR_SHIFT)
961 
962 /*
963  * LOCK (RW)
964  *
965  * Lock bit for CPU_LOCK
966  */
967 #define SYSCTL_CPU_LOCK_LOCK_MASK (0x2U)
968 #define SYSCTL_CPU_LOCK_LOCK_SHIFT (1U)
969 #define SYSCTL_CPU_LOCK_LOCK_SET(x) (((uint32_t)(x) << SYSCTL_CPU_LOCK_LOCK_SHIFT) & SYSCTL_CPU_LOCK_LOCK_MASK)
970 #define SYSCTL_CPU_LOCK_LOCK_GET(x) (((uint32_t)(x) & SYSCTL_CPU_LOCK_LOCK_MASK) >> SYSCTL_CPU_LOCK_LOCK_SHIFT)
971 
972 /* Bitfield definition for register of struct array CPU: GPR0 */
973 /*
974  * GPR (RW)
975  *
976  * register for software to handle resume, can save resume address or status
977  */
978 #define SYSCTL_CPU_GPR_GPR_MASK (0xFFFFFFFFUL)
979 #define SYSCTL_CPU_GPR_GPR_SHIFT (0U)
980 #define SYSCTL_CPU_GPR_GPR_SET(x) (((uint32_t)(x) << SYSCTL_CPU_GPR_GPR_SHIFT) & SYSCTL_CPU_GPR_GPR_MASK)
981 #define SYSCTL_CPU_GPR_GPR_GET(x) (((uint32_t)(x) & SYSCTL_CPU_GPR_GPR_MASK) >> SYSCTL_CPU_GPR_GPR_SHIFT)
982 
983 /* Bitfield definition for register of struct array CPU: STATUS0 */
984 /*
985  * STATUS (RO)
986  *
987  * IRQ values
988  */
989 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK (0xFFFFFFFFUL)
990 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT (0U)
991 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_STATUS_STATUS_MASK) >> SYSCTL_CPU_WAKEUP_STATUS_STATUS_SHIFT)
992 
993 /* Bitfield definition for register of struct array CPU: ENABLE0 */
994 /*
995  * ENABLE (RW)
996  *
997  * IRQ wakeup enable
998  */
999 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK (0xFFFFFFFFUL)
1000 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT (0U)
1001 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SET(x) (((uint32_t)(x) << SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK)
1002 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_GET(x) (((uint32_t)(x) & SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_MASK) >> SYSCTL_CPU_WAKEUP_ENABLE_ENABLE_SHIFT)
1003 
1004 
1005 
1006 /* RESOURCE register group index macro definition */
1007 #define SYSCTL_RESOURCE_CPU0 (0UL)
1008 #define SYSCTL_RESOURCE_CPX0 (1UL)
1009 #define SYSCTL_RESOURCE_CPU1 (8UL)
1010 #define SYSCTL_RESOURCE_CPX1 (9UL)
1011 #define SYSCTL_RESOURCE_POW_CPU0 (21UL)
1012 #define SYSCTL_RESOURCE_POW_CPU1 (22UL)
1013 #define SYSCTL_RESOURCE_POW_OTN (23UL)
1014 #define SYSCTL_RESOURCE_RST_SOC (24UL)
1015 #define SYSCTL_RESOURCE_RST_CPU0 (25UL)
1016 #define SYSCTL_RESOURCE_RST_CPU1 (26UL)
1017 #define SYSCTL_RESOURCE_RST_OTN (27UL)
1018 #define SYSCTL_RESOURCE_CLK_SRC_XTAL (32UL)
1019 #define SYSCTL_RESOURCE_CLK_SRC_PLL0 (33UL)
1020 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL0 (34UL)
1021 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL0 (35UL)
1022 #define SYSCTL_RESOURCE_CLK_SRC_PLL1 (36UL)
1023 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL1 (37UL)
1024 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL1 (38UL)
1025 #define SYSCTL_RESOURCE_CLK_SRC_CLK2_PLL1 (39UL)
1026 #define SYSCTL_RESOURCE_CLK_SRC_PLL2 (40UL)
1027 #define SYSCTL_RESOURCE_CLK_SRC_CLK0_PLL2 (41UL)
1028 #define SYSCTL_RESOURCE_CLK_SRC_CLK1_PLL2 (42UL)
1029 #define SYSCTL_RESOURCE_CLK_SRC_PLL0_REF (43UL)
1030 #define SYSCTL_RESOURCE_CLK_SRC_PLL1_REF (44UL)
1031 #define SYSCTL_RESOURCE_CLK_SRC_PLL2_REF (45UL)
1032 #define SYSCTL_RESOURCE_CLK_TOP_CPU0 (64UL)
1033 #define SYSCTL_RESOURCE_CLK_TOP_MCT0 (65UL)
1034 #define SYSCTL_RESOURCE_CLK_TOP_CPU1 (66UL)
1035 #define SYSCTL_RESOURCE_CLK_TOP_MCT1 (67UL)
1036 #define SYSCTL_RESOURCE_CLK_TOP_AHB0 (68UL)
1037 #define SYSCTL_RESOURCE_CLK_TOP_AXIF (69UL)
1038 #define SYSCTL_RESOURCE_CLK_TOP_AXIS (70UL)
1039 #define SYSCTL_RESOURCE_CLK_TOP_AXIC (71UL)
1040 #define SYSCTL_RESOURCE_CLK_TOP_AXIN (72UL)
1041 #define SYSCTL_RESOURCE_CLK_TOP_TMR0 (73UL)
1042 #define SYSCTL_RESOURCE_CLK_TOP_TMR1 (74UL)
1043 #define SYSCTL_RESOURCE_CLK_TOP_TMR2 (75UL)
1044 #define SYSCTL_RESOURCE_CLK_TOP_TMR3 (76UL)
1045 #define SYSCTL_RESOURCE_CLK_TOP_TMR4 (77UL)
1046 #define SYSCTL_RESOURCE_CLK_TOP_TMR5 (78UL)
1047 #define SYSCTL_RESOURCE_CLK_TOP_TMR6 (79UL)
1048 #define SYSCTL_RESOURCE_CLK_TOP_TMR7 (80UL)
1049 #define SYSCTL_RESOURCE_CLK_TOP_I2C0 (81UL)
1050 #define SYSCTL_RESOURCE_CLK_TOP_I2C1 (82UL)
1051 #define SYSCTL_RESOURCE_CLK_TOP_I2C2 (83UL)
1052 #define SYSCTL_RESOURCE_CLK_TOP_I2C3 (84UL)
1053 #define SYSCTL_RESOURCE_CLK_TOP_I2C4 (85UL)
1054 #define SYSCTL_RESOURCE_CLK_TOP_I2C5 (86UL)
1055 #define SYSCTL_RESOURCE_CLK_TOP_I2C6 (87UL)
1056 #define SYSCTL_RESOURCE_CLK_TOP_I2C7 (88UL)
1057 #define SYSCTL_RESOURCE_CLK_TOP_SPI0 (89UL)
1058 #define SYSCTL_RESOURCE_CLK_TOP_SPI1 (90UL)
1059 #define SYSCTL_RESOURCE_CLK_TOP_SPI2 (91UL)
1060 #define SYSCTL_RESOURCE_CLK_TOP_SPI3 (92UL)
1061 #define SYSCTL_RESOURCE_CLK_TOP_SPI4 (93UL)
1062 #define SYSCTL_RESOURCE_CLK_TOP_SPI5 (94UL)
1063 #define SYSCTL_RESOURCE_CLK_TOP_SPI6 (95UL)
1064 #define SYSCTL_RESOURCE_CLK_TOP_SPI7 (96UL)
1065 #define SYSCTL_RESOURCE_CLK_TOP_URT0 (97UL)
1066 #define SYSCTL_RESOURCE_CLK_TOP_URT1 (98UL)
1067 #define SYSCTL_RESOURCE_CLK_TOP_URT2 (99UL)
1068 #define SYSCTL_RESOURCE_CLK_TOP_URT3 (100UL)
1069 #define SYSCTL_RESOURCE_CLK_TOP_URT4 (101UL)
1070 #define SYSCTL_RESOURCE_CLK_TOP_URT5 (102UL)
1071 #define SYSCTL_RESOURCE_CLK_TOP_URT6 (103UL)
1072 #define SYSCTL_RESOURCE_CLK_TOP_URT7 (104UL)
1073 #define SYSCTL_RESOURCE_CLK_TOP_URT8 (105UL)
1074 #define SYSCTL_RESOURCE_CLK_TOP_URT9 (106UL)
1075 #define SYSCTL_RESOURCE_CLK_TOP_URT10 (107UL)
1076 #define SYSCTL_RESOURCE_CLK_TOP_URT11 (108UL)
1077 #define SYSCTL_RESOURCE_CLK_TOP_URT12 (109UL)
1078 #define SYSCTL_RESOURCE_CLK_TOP_URT13 (110UL)
1079 #define SYSCTL_RESOURCE_CLK_TOP_URT14 (111UL)
1080 #define SYSCTL_RESOURCE_CLK_TOP_URT15 (112UL)
1081 #define SYSCTL_RESOURCE_CLK_TOP_ANA0 (113UL)
1082 #define SYSCTL_RESOURCE_CLK_TOP_ANA1 (114UL)
1083 #define SYSCTL_RESOURCE_CLK_TOP_ANA2 (115UL)
1084 #define SYSCTL_RESOURCE_CLK_TOP_ANA3 (116UL)
1085 #define SYSCTL_RESOURCE_CLK_TOP_AUD0 (117UL)
1086 #define SYSCTL_RESOURCE_CLK_TOP_AUD1 (118UL)
1087 #define SYSCTL_RESOURCE_CLK_TOP_CAN0 (119UL)
1088 #define SYSCTL_RESOURCE_CLK_TOP_CAN1 (120UL)
1089 #define SYSCTL_RESOURCE_CLK_TOP_CAN2 (121UL)
1090 #define SYSCTL_RESOURCE_CLK_TOP_CAN3 (122UL)
1091 #define SYSCTL_RESOURCE_CLK_TOP_CAN4 (123UL)
1092 #define SYSCTL_RESOURCE_CLK_TOP_CAN5 (124UL)
1093 #define SYSCTL_RESOURCE_CLK_TOP_CAN6 (125UL)
1094 #define SYSCTL_RESOURCE_CLK_TOP_CAN7 (126UL)
1095 #define SYSCTL_RESOURCE_CLK_TOP_XPI0 (127UL)
1096 #define SYSCTL_RESOURCE_CLK_TOP_FEMC (128UL)
1097 #define SYSCTL_RESOURCE_CLK_TOP_ETH0 (129UL)
1098 #define SYSCTL_RESOURCE_CLK_TOP_PTP0 (130UL)
1099 #define SYSCTL_RESOURCE_CLK_TOP_REF0 (131UL)
1100 #define SYSCTL_RESOURCE_CLK_TOP_REF1 (132UL)
1101 #define SYSCTL_RESOURCE_CLK_TOP_NTM0 (133UL)
1102 #define SYSCTL_RESOURCE_CLK_TOP_TSW1 (134UL)
1103 #define SYSCTL_RESOURCE_CLK_TOP_TSW2 (135UL)
1104 #define SYSCTL_RESOURCE_CLK_TOP_TSW3 (136UL)
1105 #define SYSCTL_RESOURCE_CLK_TOP_ADC0 (137UL)
1106 #define SYSCTL_RESOURCE_CLK_TOP_ADC1 (138UL)
1107 #define SYSCTL_RESOURCE_CLK_TOP_ADC2 (139UL)
1108 #define SYSCTL_RESOURCE_CLK_TOP_ADC3 (140UL)
1109 #define SYSCTL_RESOURCE_CLK_TOP_I2S0 (141UL)
1110 #define SYSCTL_RESOURCE_CLK_TOP_I2S1 (142UL)
1111 #define SYSCTL_RESOURCE_AHBP (256UL)
1112 #define SYSCTL_RESOURCE_AXIS (257UL)
1113 #define SYSCTL_RESOURCE_AXIC (258UL)
1114 #define SYSCTL_RESOURCE_AXIN (259UL)
1115 #define SYSCTL_RESOURCE_ROM0 (260UL)
1116 #define SYSCTL_RESOURCE_LMM0 (261UL)
1117 #define SYSCTL_RESOURCE_MCT0 (262UL)
1118 #define SYSCTL_RESOURCE_LMM1 (263UL)
1119 #define SYSCTL_RESOURCE_MCT1 (264UL)
1120 #define SYSCTL_RESOURCE_TMR0 (265UL)
1121 #define SYSCTL_RESOURCE_TMR1 (266UL)
1122 #define SYSCTL_RESOURCE_TMR2 (267UL)
1123 #define SYSCTL_RESOURCE_TMR3 (268UL)
1124 #define SYSCTL_RESOURCE_TMR4 (269UL)
1125 #define SYSCTL_RESOURCE_TMR5 (270UL)
1126 #define SYSCTL_RESOURCE_TMR6 (271UL)
1127 #define SYSCTL_RESOURCE_TMR7 (272UL)
1128 #define SYSCTL_RESOURCE_I2C0 (273UL)
1129 #define SYSCTL_RESOURCE_I2C1 (274UL)
1130 #define SYSCTL_RESOURCE_I2C2 (275UL)
1131 #define SYSCTL_RESOURCE_I2C3 (276UL)
1132 #define SYSCTL_RESOURCE_I2C4 (277UL)
1133 #define SYSCTL_RESOURCE_I2C5 (278UL)
1134 #define SYSCTL_RESOURCE_I2C6 (279UL)
1135 #define SYSCTL_RESOURCE_I2C7 (280UL)
1136 #define SYSCTL_RESOURCE_SPI0 (281UL)
1137 #define SYSCTL_RESOURCE_SPI1 (282UL)
1138 #define SYSCTL_RESOURCE_SPI2 (283UL)
1139 #define SYSCTL_RESOURCE_SPI3 (284UL)
1140 #define SYSCTL_RESOURCE_SPI4 (285UL)
1141 #define SYSCTL_RESOURCE_SPI5 (286UL)
1142 #define SYSCTL_RESOURCE_SPI6 (287UL)
1143 #define SYSCTL_RESOURCE_SPI7 (288UL)
1144 #define SYSCTL_RESOURCE_URT0 (289UL)
1145 #define SYSCTL_RESOURCE_URT1 (290UL)
1146 #define SYSCTL_RESOURCE_URT2 (291UL)
1147 #define SYSCTL_RESOURCE_URT3 (292UL)
1148 #define SYSCTL_RESOURCE_URT4 (293UL)
1149 #define SYSCTL_RESOURCE_URT5 (294UL)
1150 #define SYSCTL_RESOURCE_URT6 (295UL)
1151 #define SYSCTL_RESOURCE_URT7 (296UL)
1152 #define SYSCTL_RESOURCE_URT8 (297UL)
1153 #define SYSCTL_RESOURCE_URT9 (298UL)
1154 #define SYSCTL_RESOURCE_URT10 (299UL)
1155 #define SYSCTL_RESOURCE_URT11 (300UL)
1156 #define SYSCTL_RESOURCE_URT12 (301UL)
1157 #define SYSCTL_RESOURCE_URT13 (302UL)
1158 #define SYSCTL_RESOURCE_URT14 (303UL)
1159 #define SYSCTL_RESOURCE_URT15 (304UL)
1160 #define SYSCTL_RESOURCE_CRC0 (305UL)
1161 #define SYSCTL_RESOURCE_TSNS (306UL)
1162 #define SYSCTL_RESOURCE_WDG0 (307UL)
1163 #define SYSCTL_RESOURCE_WDG1 (308UL)
1164 #define SYSCTL_RESOURCE_WDG2 (309UL)
1165 #define SYSCTL_RESOURCE_WDG3 (310UL)
1166 #define SYSCTL_RESOURCE_MBX0 (311UL)
1167 #define SYSCTL_RESOURCE_MBX1 (312UL)
1168 #define SYSCTL_RESOURCE_GPIO (313UL)
1169 #define SYSCTL_RESOURCE_PPI0 (314UL)
1170 #define SYSCTL_RESOURCE_HDMA (315UL)
1171 #define SYSCTL_RESOURCE_LOBS (316UL)
1172 #define SYSCTL_RESOURCE_ADC0 (317UL)
1173 #define SYSCTL_RESOURCE_ADC1 (318UL)
1174 #define SYSCTL_RESOURCE_ADC2 (319UL)
1175 #define SYSCTL_RESOURCE_ADC3 (320UL)
1176 #define SYSCTL_RESOURCE_CMP0 (321UL)
1177 #define SYSCTL_RESOURCE_CMP1 (322UL)
1178 #define SYSCTL_RESOURCE_CMP2 (323UL)
1179 #define SYSCTL_RESOURCE_CMP3 (324UL)
1180 #define SYSCTL_RESOURCE_I2S0 (325UL)
1181 #define SYSCTL_RESOURCE_I2S1 (326UL)
1182 #define SYSCTL_RESOURCE_PDM0 (327UL)
1183 #define SYSCTL_RESOURCE_CLSD (328UL)
1184 #define SYSCTL_RESOURCE_CAN0 (329UL)
1185 #define SYSCTL_RESOURCE_CAN1 (330UL)
1186 #define SYSCTL_RESOURCE_CAN2 (331UL)
1187 #define SYSCTL_RESOURCE_CAN3 (332UL)
1188 #define SYSCTL_RESOURCE_CAN4 (333UL)
1189 #define SYSCTL_RESOURCE_CAN5 (334UL)
1190 #define SYSCTL_RESOURCE_CAN6 (335UL)
1191 #define SYSCTL_RESOURCE_CAN7 (336UL)
1192 #define SYSCTL_RESOURCE_PTPC (337UL)
1193 #define SYSCTL_RESOURCE_QEI0 (338UL)
1194 #define SYSCTL_RESOURCE_QEI1 (339UL)
1195 #define SYSCTL_RESOURCE_QEI2 (340UL)
1196 #define SYSCTL_RESOURCE_QEI3 (341UL)
1197 #define SYSCTL_RESOURCE_QEO0 (342UL)
1198 #define SYSCTL_RESOURCE_QEO1 (343UL)
1199 #define SYSCTL_RESOURCE_QEO2 (344UL)
1200 #define SYSCTL_RESOURCE_QEO3 (345UL)
1201 #define SYSCTL_RESOURCE_PWM0 (346UL)
1202 #define SYSCTL_RESOURCE_PWM1 (347UL)
1203 #define SYSCTL_RESOURCE_PWM2 (348UL)
1204 #define SYSCTL_RESOURCE_PWM3 (349UL)
1205 #define SYSCTL_RESOURCE_RDC0 (350UL)
1206 #define SYSCTL_RESOURCE_RDC1 (351UL)
1207 #define SYSCTL_RESOURCE_SDM0 (352UL)
1208 #define SYSCTL_RESOURCE_SDM1 (353UL)
1209 #define SYSCTL_RESOURCE_PLB0 (354UL)
1210 #define SYSCTL_RESOURCE_SEI0 (355UL)
1211 #define SYSCTL_RESOURCE_MTG0 (356UL)
1212 #define SYSCTL_RESOURCE_MTG1 (357UL)
1213 #define SYSCTL_RESOURCE_VSC0 (358UL)
1214 #define SYSCTL_RESOURCE_VSC1 (359UL)
1215 #define SYSCTL_RESOURCE_CLC0 (360UL)
1216 #define SYSCTL_RESOURCE_CLC1 (361UL)
1217 #define SYSCTL_RESOURCE_EMDS (362UL)
1218 #define SYSCTL_RESOURCE_RNG0 (363UL)
1219 #define SYSCTL_RESOURCE_SDP0 (364UL)
1220 #define SYSCTL_RESOURCE_PKA0 (365UL)
1221 #define SYSCTL_RESOURCE_KMAN (366UL)
1222 #define SYSCTL_RESOURCE_XPI0 (367UL)
1223 #define SYSCTL_RESOURCE_FEMC (368UL)
1224 #define SYSCTL_RESOURCE_RAM0 (369UL)
1225 #define SYSCTL_RESOURCE_RAM1 (370UL)
1226 #define SYSCTL_RESOURCE_XDMA (371UL)
1227 #define SYSCTL_RESOURCE_FFA0 (372UL)
1228 #define SYSCTL_RESOURCE_ETH0 (373UL)
1229 #define SYSCTL_RESOURCE_USB0 (374UL)
1230 #define SYSCTL_RESOURCE_NTM0 (375UL)
1231 #define SYSCTL_RESOURCE_REF0 (376UL)
1232 #define SYSCTL_RESOURCE_REF1 (377UL)
1233 #define SYSCTL_RESOURCE_TSW0 (378UL)
1234 #define SYSCTL_RESOURCE_ESC0 (379UL)
1235 
1236 /* GROUP0 register group index macro definition */
1237 #define SYSCTL_GROUP0_LINK0 (0UL)
1238 #define SYSCTL_GROUP0_LINK1 (1UL)
1239 #define SYSCTL_GROUP0_LINK2 (2UL)
1240 #define SYSCTL_GROUP0_LINK3 (3UL)
1241 
1242 /* GROUP1 register group index macro definition */
1243 #define SYSCTL_GROUP1_LINK0 (0UL)
1244 #define SYSCTL_GROUP1_LINK1 (1UL)
1245 #define SYSCTL_GROUP1_LINK2 (2UL)
1246 #define SYSCTL_GROUP1_LINK3 (3UL)
1247 
1248 /* AFFILIATE register group index macro definition */
1249 #define SYSCTL_AFFILIATE_CPU0 (0UL)
1250 #define SYSCTL_AFFILIATE_CPU1 (1UL)
1251 
1252 /* RETENTION register group index macro definition */
1253 #define SYSCTL_RETENTION_CPU0 (0UL)
1254 #define SYSCTL_RETENTION_CPU1 (1UL)
1255 
1256 /* POWER register group index macro definition */
1257 #define SYSCTL_POWER_CPU0 (0UL)
1258 #define SYSCTL_POWER_CPU1 (1UL)
1259 #define SYSCTL_POWER_OTN (2UL)
1260 
1261 /* RESET register group index macro definition */
1262 #define SYSCTL_RESET_SOC (0UL)
1263 #define SYSCTL_RESET_CPU0 (1UL)
1264 #define SYSCTL_RESET_CPU1 (2UL)
1265 #define SYSCTL_RESET_OTN (3UL)
1266 
1267 /* CLOCK register group index macro definition */
1268 #define SYSCTL_CLOCK_CLK_TOP_CPU0 (0UL)
1269 #define SYSCTL_CLOCK_CLK_TOP_MCT0 (1UL)
1270 #define SYSCTL_CLOCK_CLK_TOP_CPU1 (2UL)
1271 #define SYSCTL_CLOCK_CLK_TOP_MCT1 (3UL)
1272 #define SYSCTL_CLOCK_CLK_TOP_AHB0 (4UL)
1273 #define SYSCTL_CLOCK_CLK_TOP_AXIF (5UL)
1274 #define SYSCTL_CLOCK_CLK_TOP_AXIS (6UL)
1275 #define SYSCTL_CLOCK_CLK_TOP_AXIC (7UL)
1276 #define SYSCTL_CLOCK_CLK_TOP_AXIN (8UL)
1277 #define SYSCTL_CLOCK_CLK_TOP_TMR0 (9UL)
1278 #define SYSCTL_CLOCK_CLK_TOP_TMR1 (10UL)
1279 #define SYSCTL_CLOCK_CLK_TOP_TMR2 (11UL)
1280 #define SYSCTL_CLOCK_CLK_TOP_TMR3 (12UL)
1281 #define SYSCTL_CLOCK_CLK_TOP_TMR4 (13UL)
1282 #define SYSCTL_CLOCK_CLK_TOP_TMR5 (14UL)
1283 #define SYSCTL_CLOCK_CLK_TOP_TMR6 (15UL)
1284 #define SYSCTL_CLOCK_CLK_TOP_TMR7 (16UL)
1285 #define SYSCTL_CLOCK_CLK_TOP_I2C0 (17UL)
1286 #define SYSCTL_CLOCK_CLK_TOP_I2C1 (18UL)
1287 #define SYSCTL_CLOCK_CLK_TOP_I2C2 (19UL)
1288 #define SYSCTL_CLOCK_CLK_TOP_I2C3 (20UL)
1289 #define SYSCTL_CLOCK_CLK_TOP_I2C4 (21UL)
1290 #define SYSCTL_CLOCK_CLK_TOP_I2C5 (22UL)
1291 #define SYSCTL_CLOCK_CLK_TOP_I2C6 (23UL)
1292 #define SYSCTL_CLOCK_CLK_TOP_I2C7 (24UL)
1293 #define SYSCTL_CLOCK_CLK_TOP_SPI0 (25UL)
1294 #define SYSCTL_CLOCK_CLK_TOP_SPI1 (26UL)
1295 #define SYSCTL_CLOCK_CLK_TOP_SPI2 (27UL)
1296 #define SYSCTL_CLOCK_CLK_TOP_SPI3 (28UL)
1297 #define SYSCTL_CLOCK_CLK_TOP_SPI4 (29UL)
1298 #define SYSCTL_CLOCK_CLK_TOP_SPI5 (30UL)
1299 #define SYSCTL_CLOCK_CLK_TOP_SPI6 (31UL)
1300 #define SYSCTL_CLOCK_CLK_TOP_SPI7 (32UL)
1301 #define SYSCTL_CLOCK_CLK_TOP_URT0 (33UL)
1302 #define SYSCTL_CLOCK_CLK_TOP_URT1 (34UL)
1303 #define SYSCTL_CLOCK_CLK_TOP_URT2 (35UL)
1304 #define SYSCTL_CLOCK_CLK_TOP_URT3 (36UL)
1305 #define SYSCTL_CLOCK_CLK_TOP_URT4 (37UL)
1306 #define SYSCTL_CLOCK_CLK_TOP_URT5 (38UL)
1307 #define SYSCTL_CLOCK_CLK_TOP_URT6 (39UL)
1308 #define SYSCTL_CLOCK_CLK_TOP_URT7 (40UL)
1309 #define SYSCTL_CLOCK_CLK_TOP_URT8 (41UL)
1310 #define SYSCTL_CLOCK_CLK_TOP_URT9 (42UL)
1311 #define SYSCTL_CLOCK_CLK_TOP_URT10 (43UL)
1312 #define SYSCTL_CLOCK_CLK_TOP_URT11 (44UL)
1313 #define SYSCTL_CLOCK_CLK_TOP_URT12 (45UL)
1314 #define SYSCTL_CLOCK_CLK_TOP_URT13 (46UL)
1315 #define SYSCTL_CLOCK_CLK_TOP_URT14 (47UL)
1316 #define SYSCTL_CLOCK_CLK_TOP_URT15 (48UL)
1317 #define SYSCTL_CLOCK_CLK_TOP_ANA0 (49UL)
1318 #define SYSCTL_CLOCK_CLK_TOP_ANA1 (50UL)
1319 #define SYSCTL_CLOCK_CLK_TOP_ANA2 (51UL)
1320 #define SYSCTL_CLOCK_CLK_TOP_ANA3 (52UL)
1321 #define SYSCTL_CLOCK_CLK_TOP_AUD0 (53UL)
1322 #define SYSCTL_CLOCK_CLK_TOP_AUD1 (54UL)
1323 #define SYSCTL_CLOCK_CLK_TOP_CAN0 (55UL)
1324 #define SYSCTL_CLOCK_CLK_TOP_CAN1 (56UL)
1325 #define SYSCTL_CLOCK_CLK_TOP_CAN2 (57UL)
1326 #define SYSCTL_CLOCK_CLK_TOP_CAN3 (58UL)
1327 #define SYSCTL_CLOCK_CLK_TOP_CAN4 (59UL)
1328 #define SYSCTL_CLOCK_CLK_TOP_CAN5 (60UL)
1329 #define SYSCTL_CLOCK_CLK_TOP_CAN6 (61UL)
1330 #define SYSCTL_CLOCK_CLK_TOP_CAN7 (62UL)
1331 #define SYSCTL_CLOCK_CLK_TOP_XPI0 (63UL)
1332 #define SYSCTL_CLOCK_CLK_TOP_FEMC (64UL)
1333 #define SYSCTL_CLOCK_CLK_TOP_ETH0 (65UL)
1334 #define SYSCTL_CLOCK_CLK_TOP_PTP0 (66UL)
1335 #define SYSCTL_CLOCK_CLK_TOP_NTM0 (67UL)
1336 #define SYSCTL_CLOCK_CLK_TOP_REF0 (68UL)
1337 #define SYSCTL_CLOCK_CLK_TOP_REF1 (69UL)
1338 #define SYSCTL_CLOCK_CLK_TOP_TSW1 (70UL)
1339 #define SYSCTL_CLOCK_CLK_TOP_TSW2 (71UL)
1340 #define SYSCTL_CLOCK_CLK_TOP_TSW3 (72UL)
1341 
1342 /* ADCCLK register group index macro definition */
1343 #define SYSCTL_ADCCLK_CLK_TOP_ADC0 (0UL)
1344 #define SYSCTL_ADCCLK_CLK_TOP_ADC1 (1UL)
1345 #define SYSCTL_ADCCLK_CLK_TOP_ADC2 (2UL)
1346 #define SYSCTL_ADCCLK_CLK_TOP_ADC3 (3UL)
1347 
1348 /* I2SCLK register group index macro definition */
1349 #define SYSCTL_I2SCLK_CLK_TOP_I2S0 (0UL)
1350 #define SYSCTL_I2SCLK_CLK_TOP_I2S1 (1UL)
1351 
1352 /* MONITOR register group index macro definition */
1353 #define SYSCTL_MONITOR_SLICE0 (0UL)
1354 #define SYSCTL_MONITOR_SLICE1 (1UL)
1355 #define SYSCTL_MONITOR_SLICE2 (2UL)
1356 #define SYSCTL_MONITOR_SLICE3 (3UL)
1357 
1358 /* GPR register group index macro definition */
1359 #define SYSCTL_CPU_GPR_GPR0 (0UL)
1360 #define SYSCTL_CPU_GPR_GPR1 (1UL)
1361 #define SYSCTL_CPU_GPR_GPR2 (2UL)
1362 #define SYSCTL_CPU_GPR_GPR3 (3UL)
1363 #define SYSCTL_CPU_GPR_GPR4 (4UL)
1364 #define SYSCTL_CPU_GPR_GPR5 (5UL)
1365 #define SYSCTL_CPU_GPR_GPR6 (6UL)
1366 #define SYSCTL_CPU_GPR_GPR7 (7UL)
1367 #define SYSCTL_CPU_GPR_GPR8 (8UL)
1368 #define SYSCTL_CPU_GPR_GPR9 (9UL)
1369 #define SYSCTL_CPU_GPR_GPR10 (10UL)
1370 #define SYSCTL_CPU_GPR_GPR11 (11UL)
1371 #define SYSCTL_CPU_GPR_GPR12 (12UL)
1372 #define SYSCTL_CPU_GPR_GPR13 (13UL)
1373 
1374 /* WAKEUP_STATUS register group index macro definition */
1375 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS0 (0UL)
1376 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS1 (1UL)
1377 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS2 (2UL)
1378 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS3 (3UL)
1379 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS4 (4UL)
1380 #define SYSCTL_CPU_WAKEUP_STATUS_STATUS5 (5UL)
1381 
1382 /* WAKEUP_ENABLE register group index macro definition */
1383 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE0 (0UL)
1384 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE1 (1UL)
1385 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE2 (2UL)
1386 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE3 (3UL)
1387 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE4 (4UL)
1388 #define SYSCTL_CPU_WAKEUP_ENABLE_ENABLE5 (5UL)
1389 
1390 /* CPU register group index macro definition */
1391 #define SYSCTL_CPU_CPU0 (0UL)
1392 #define SYSCTL_CPU_CPU1 (1UL)
1393 
1394 
1395 #endif /* HPM_SYSCTL_H */
SYSCTL_Type
Definition: hpm_sysctl_regs.h:12