hpm_trgm_regs.h

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/*
 * Copyright (c) 2021-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
 
#ifndef HPM_TRGM_H
#define HPM_TRGM_H
 
typedef struct {
    __RW uint32_t FILTCFG[64];                 /* 0x0 - 0xFC: Filter configure register */
    __R  uint8_t  RESERVED0[768];              /* 0x100 - 0x3FF: Reserved */
    __RW uint32_t DMACFG[8];                   /* 0x400 - 0x41C: DMA request configure register */
    __R  uint8_t  RESERVED1[224];              /* 0x420 - 0x4FF: Reserved */
    __RW uint32_t GCR;                         /* 0x500:  */
    __R  uint8_t  RESERVED2[60];               /* 0x504 - 0x53F: Reserved */
    __RW uint32_t ADC_MATRIX_SEL0;             /* 0x540: adc matrix select register0 */
    __RW uint32_t ADC_MATRIX_SEL1;             /* 0x544: adc matrix select register1 */
    __RW uint32_t ADC_MATRIX_SEL2;             /* 0x548: adc matrix select register2 */
    __RW uint32_t ADC_MATRIX_SEL3;             /* 0x54C: adc matrix select register3 */
    __RW uint32_t ADC_MATRIX_SEL4;             /* 0x550: adc matrix select register2 */
    __R  uint8_t  RESERVED3[44];               /* 0x554 - 0x57F: Reserved */
    __RW uint32_t DAC_MATRIX_SEL0;             /* 0x580: dac matrix select register0 */
    __RW uint32_t DAC_MATRIX_SEL1;             /* 0x584: dac matrix select register1 */
    __RW uint32_t DAC_MATRIX_SEL2;             /* 0x588: dac matrix select register2 */
    __RW uint32_t DAC_MATRIX_SEL3;             /* 0x58C: dac matrix select register3 */
    __RW uint32_t DAC_MATRIX_SEL4;             /* 0x590: dac matrix select register4 */
    __RW uint32_t DAC_MATRIX_SEL5;             /* 0x594: dac matrix select register5 */
    __RW uint32_t DAC_MATRIX_SEL6;             /* 0x598: dac matrix select register6 */
    __RW uint32_t DAC_MATRIX_SEL7;             /* 0x59C: dac matrix select register7 */
    __R  uint8_t  RESERVED4[32];               /* 0x5A0 - 0x5BF: Reserved */
    __RW uint32_t POS_MATRIX_SEL0;             /* 0x5C0: position matrix select register0 */
    __RW uint32_t POS_MATRIX_SEL1;             /* 0x5C4: position matrix select register0 */
    __RW uint32_t POS_MATRIX_SEL2;             /* 0x5C8: position matrix select register2 */
    __R  uint8_t  RESERVED5[52];               /* 0x5CC - 0x5FF: Reserved */
    __R  uint32_t TRGM_IN[8];                  /* 0x600 - 0x61C: trigmux input read register0 */
    __R  uint8_t  RESERVED6[96];               /* 0x620 - 0x67F: Reserved */
    __R  uint32_t TRGM_OUT[8];                 /* 0x680 - 0x69C: trigmux output read register0 */
    __R  uint8_t  RESERVED7[352];              /* 0x6A0 - 0x7FF: Reserved */
    __RW uint32_t PWM_DELAY_CFG;               /* 0x800: pwm delay chain config register */
    __RW uint32_t PWM_CALIB_CFG;               /* 0x804: pwm delay chain calibration control register */
    __R  uint8_t  RESERVED8[8];                /* 0x808 - 0x80F: Reserved */
    __R  uint32_t PWM_CALIB_STATUS0;           /* 0x810:  */
    __R  uint8_t  RESERVED9[2028];             /* 0x814 - 0xFFF: Reserved */
    __RW uint32_t TRGOCFG[242];                /* 0x1000 - 0x13C4: Trigger manager output configure register */
} TRGM_Type;
 
 
/* Bitfield definition for register array: FILTCFG */
/*
 * OUTINV (RW)
 *
 * 1- Filter will invert the output
 * 0- Filter will not invert the output
 */
#define TRGM_FILTCFG_OUTINV_MASK (0x10000UL)
#define TRGM_FILTCFG_OUTINV_SHIFT (16U)
#define TRGM_FILTCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_OUTINV_SHIFT) & TRGM_FILTCFG_OUTINV_MASK)
#define TRGM_FILTCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_OUTINV_MASK) >> TRGM_FILTCFG_OUTINV_SHIFT)
 
/*
 * MODE (RW)
 *
 * This bitfields defines the filter mode
 * 000-bypass;
 * 100-rapid change mode;
 * 101-delay filter mode;
 * 110-stalbe low mode;
 * 111-stable high mode
 */
#define TRGM_FILTCFG_MODE_MASK (0xE000U)
#define TRGM_FILTCFG_MODE_SHIFT (13U)
#define TRGM_FILTCFG_MODE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_MODE_SHIFT) & TRGM_FILTCFG_MODE_MASK)
#define TRGM_FILTCFG_MODE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_MODE_MASK) >> TRGM_FILTCFG_MODE_SHIFT)
 
/*
 * SYNCEN (RW)
 *
 * set to enable sychronization input signal with TRGM clock
 */
#define TRGM_FILTCFG_SYNCEN_MASK (0x1000U)
#define TRGM_FILTCFG_SYNCEN_SHIFT (12U)
#define TRGM_FILTCFG_SYNCEN_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_SYNCEN_SHIFT) & TRGM_FILTCFG_SYNCEN_MASK)
#define TRGM_FILTCFG_SYNCEN_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_SYNCEN_MASK) >> TRGM_FILTCFG_SYNCEN_SHIFT)
 
/*
 * FILTLEN_SHIFT (RW)
 *
 */
#define TRGM_FILTCFG_FILTLEN_SHIFT_MASK (0xE00U)
#define TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT (9U)
#define TRGM_FILTCFG_FILTLEN_SHIFT_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK)
#define TRGM_FILTCFG_FILTLEN_SHIFT_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_SHIFT_MASK) >> TRGM_FILTCFG_FILTLEN_SHIFT_SHIFT)
 
/*
 * FILTLEN_BASE (RW)
 *
 * This bitfields defines the filter counter length.
 */
#define TRGM_FILTCFG_FILTLEN_BASE_MASK (0x1FFU)
#define TRGM_FILTCFG_FILTLEN_BASE_SHIFT (0U)
#define TRGM_FILTCFG_FILTLEN_BASE_SET(x) (((uint32_t)(x) << TRGM_FILTCFG_FILTLEN_BASE_SHIFT) & TRGM_FILTCFG_FILTLEN_BASE_MASK)
#define TRGM_FILTCFG_FILTLEN_BASE_GET(x) (((uint32_t)(x) & TRGM_FILTCFG_FILTLEN_BASE_MASK) >> TRGM_FILTCFG_FILTLEN_BASE_SHIFT)
 
/* Bitfield definition for register array: DMACFG */
/*
 * DMAMUX_EN (RW)
 *
 */
#define TRGM_DMACFG_DMAMUX_EN_MASK (0x80000000UL)
#define TRGM_DMACFG_DMAMUX_EN_SHIFT (31U)
#define TRGM_DMACFG_DMAMUX_EN_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMAMUX_EN_SHIFT) & TRGM_DMACFG_DMAMUX_EN_MASK)
#define TRGM_DMACFG_DMAMUX_EN_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMAMUX_EN_MASK) >> TRGM_DMACFG_DMAMUX_EN_SHIFT)
 
/*
 * DMASRCSEL (RW)
 *
 */
#define TRGM_DMACFG_DMASRCSEL_MASK (0x3FU)
#define TRGM_DMACFG_DMASRCSEL_SHIFT (0U)
#define TRGM_DMACFG_DMASRCSEL_SET(x) (((uint32_t)(x) << TRGM_DMACFG_DMASRCSEL_SHIFT) & TRGM_DMACFG_DMASRCSEL_MASK)
#define TRGM_DMACFG_DMASRCSEL_GET(x) (((uint32_t)(x) & TRGM_DMACFG_DMASRCSEL_MASK) >> TRGM_DMACFG_DMASRCSEL_SHIFT)
 
/* Bitfield definition for register: GCR */
/*
 * TRGOPEN (RW)
 *
 */
#define TRGM_GCR_TRGOPEN_MASK (0xFFFFFFFFUL)
#define TRGM_GCR_TRGOPEN_SHIFT (0U)
#define TRGM_GCR_TRGOPEN_SET(x) (((uint32_t)(x) << TRGM_GCR_TRGOPEN_SHIFT) & TRGM_GCR_TRGOPEN_MASK)
#define TRGM_GCR_TRGOPEN_GET(x) (((uint32_t)(x) & TRGM_GCR_TRGOPEN_MASK) >> TRGM_GCR_TRGOPEN_SHIFT)
 
/* Bitfield definition for register: ADC_MATRIX_SEL0 */
/*
 * RDC1_ADC1_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_MASK (0xFF000000UL)
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SHIFT (24U)
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC1_ADC1_SEL_SHIFT)
 
/*
 * RDC1_ADC0_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_MASK (0xFF0000UL)
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SHIFT (16U)
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC1_ADC0_SEL_SHIFT)
 
/*
 * RDC0_ADC1_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK (0xFF00U)
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT (8U)
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC1_SEL_SHIFT)
 
/*
 * RDC0_ADC0_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK (0xFFU)
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT (0U)
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL0_RDC0_ADC0_SEL_SHIFT)
 
/* Bitfield definition for register: ADC_MATRIX_SEL1 */
/*
 * QEI3_ADC1_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_MASK (0xFF000000UL)
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SHIFT (24U)
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI3_ADC1_SEL_SHIFT)
 
/*
 * QEI3_ADC0_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_MASK (0xFF0000UL)
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SHIFT (16U)
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI3_ADC0_SEL_SHIFT)
 
/*
 * QEI2_ADC1_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_MASK (0xFF00U)
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SHIFT (8U)
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI2_ADC1_SEL_SHIFT)
 
/*
 * QEI2_ADC0_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_MASK (0xFFU)
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SHIFT (0U)
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL1_QEI2_ADC0_SEL_SHIFT)
 
/* Bitfield definition for register: ADC_MATRIX_SEL2 */
/*
 * VSC1_ADC0_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_MASK (0xFF000000UL)
#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SHIFT (24U)
#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC1_ADC0_SEL_SHIFT)
 
/*
 * VSC0_ADC2_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_MASK (0xFF0000UL)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SHIFT (16U)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC0_ADC2_SEL_SHIFT)
 
/*
 * VSC0_ADC1_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_MASK (0xFF00U)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SHIFT (8U)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC0_ADC1_SEL_SHIFT)
 
/*
 * VSC0_ADC0_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_MASK (0xFFU)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SHIFT (0U)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_MASK) >> TRGM_ADC_MATRIX_SEL2_VSC0_ADC0_SEL_SHIFT)
 
/* Bitfield definition for register: ADC_MATRIX_SEL3 */
/*
 * CLC0_IQ_ADC_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_MASK (0xFF000000UL)
#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SHIFT (24U)
#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_CLC0_IQ_ADC_SEL_SHIFT)
 
/*
 * CLC0_ID_ADC_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_MASK (0xFF0000UL)
#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SHIFT (16U)
#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_CLC0_ID_ADC_SEL_SHIFT)
 
/*
 * VSC1_ADC2_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_MASK (0xFF00U)
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SHIFT (8U)
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_VSC1_ADC2_SEL_SHIFT)
 
/*
 * VSC1_ADC1_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_MASK (0xFFU)
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SHIFT (0U)
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_MASK) >> TRGM_ADC_MATRIX_SEL3_VSC1_ADC1_SEL_SHIFT)
 
/* Bitfield definition for register: ADC_MATRIX_SEL4 */
/*
 * CLC1_VB_ADC_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_MASK (0xFF000000UL)
#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SHIFT (24U)
#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC1_VB_ADC_SEL_SHIFT)
 
/*
 * CLC1_IQ_ADC_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_MASK (0xFF0000UL)
#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SHIFT (16U)
#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC1_IQ_ADC_SEL_SHIFT)
 
/*
 * CLC1_ID_ADC_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_MASK (0xFF00U)
#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SHIFT (8U)
#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC1_ID_ADC_SEL_SHIFT)
 
/*
 * CLC0_VB_ADC_SEL (RW)
 *
 */
#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_MASK (0xFFU)
#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SHIFT (0U)
#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SET(x) (((uint32_t)(x) << TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SHIFT) & TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_MASK)
#define TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_GET(x) (((uint32_t)(x) & TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_MASK) >> TRGM_ADC_MATRIX_SEL4_CLC0_VB_ADC_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL0 */
/*
 * ACMP3_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP3_DAC_SEL_SHIFT)
 
/*
 * ACMP2_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP2_DAC_SEL_SHIFT)
 
/*
 * ACMP1_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP1_DAC_SEL_SHIFT)
 
/*
 * ACMP0_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL0_ACMP0_DAC_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL1 */
/*
 * ACMP7_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP7_DAC_SEL_SHIFT)
 
/*
 * ACMP6_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP6_DAC_SEL_SHIFT)
 
/*
 * ACMP5_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP5_DAC_SEL_SHIFT)
 
/*
 * ACMP4_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL1_ACMP4_DAC_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL2 */
/*
 * PWM0_DAC3_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC3_SEL_SHIFT)
 
/*
 * PWM0_DAC2_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC2_SEL_SHIFT)
 
/*
 * PWM0_DAC1_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC1_SEL_SHIFT)
 
/*
 * PWM0_DAC0_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL2_PWM0_DAC0_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL3 */
/*
 * PWM1_DAC3_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC3_SEL_SHIFT)
 
/*
 * PWM1_DAC2_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC2_SEL_SHIFT)
 
/*
 * PWM1_DAC1_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC1_SEL_SHIFT)
 
/*
 * PWM1_DAC0_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL3_PWM1_DAC0_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL4 */
/*
 * PWM2_DAC3_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC3_SEL_SHIFT)
 
/*
 * PWM2_DAC2_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC2_SEL_SHIFT)
 
/*
 * PWM2_DAC1_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC1_SEL_SHIFT)
 
/*
 * PWM2_DAC0_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL4_PWM2_DAC0_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL5 */
/*
 * PWM3_DAC3_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC3_SEL_SHIFT)
 
/*
 * PWM3_DAC2_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC2_SEL_SHIFT)
 
/*
 * PWM3_DAC1_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC1_SEL_SHIFT)
 
/*
 * PWM3_DAC0_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_MASK) >> TRGM_DAC_MATRIX_SEL5_PWM3_DAC0_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL6 */
/*
 * QEO1_VQ_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VQ_DAC_SEL_SHIFT)
 
/*
 * QEO1_VD_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO1_VD_DAC_SEL_SHIFT)
 
/*
 * QEO0_VQ_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VQ_DAC_SEL_SHIFT)
 
/*
 * QEO0_VD_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL6_QEO0_VD_DAC_SEL_SHIFT)
 
/* Bitfield definition for register: DAC_MATRIX_SEL7 */
/*
 * QEO3_VQ_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_MASK (0xFF000000UL)
#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SHIFT (24U)
#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO3_VQ_DAC_SEL_SHIFT)
 
/*
 * QEO3_VD_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_MASK (0xFF0000UL)
#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SHIFT (16U)
#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO3_VD_DAC_SEL_SHIFT)
 
/*
 * QEO2_VQ_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_MASK (0xFF00U)
#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SHIFT (8U)
#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO2_VQ_DAC_SEL_SHIFT)
 
/*
 * QEO2_VD_DAC_SEL (RW)
 *
 */
#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_MASK (0xFFU)
#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SHIFT (0U)
#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SET(x) (((uint32_t)(x) << TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SHIFT) & TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_MASK)
#define TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_GET(x) (((uint32_t)(x) & TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_MASK) >> TRGM_DAC_MATRIX_SEL7_QEO2_VD_DAC_SEL_SHIFT)
 
/* Bitfield definition for register: POS_MATRIX_SEL0 */
/*
 * SEI_POSIN3_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_MASK (0xFF000000UL)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SHIFT (24U)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_MASK)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN3_SEL_SHIFT)
 
/*
 * SEI_POSIN2_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_MASK (0xFF0000UL)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SHIFT (16U)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_MASK)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN2_SEL_SHIFT)
 
/*
 * SEI_POSIN1_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK (0xFF00U)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT (8U)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN1_SEL_SHIFT)
 
/*
 * SEI_POSIN0_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK (0xFFU)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT (0U)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK)
#define TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_MASK) >> TRGM_POS_MATRIX_SEL0_SEI_POSIN0_SEL_SHIFT)
 
/* Bitfield definition for register: POS_MATRIX_SEL1 */
/*
 * QEO1_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK (0xFF000000UL)
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT (24U)
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO1_POS_SEL_SHIFT)
 
/*
 * QEO0_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK (0xFF0000UL)
#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT (16U)
#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_QEO0_POS_SEL_SHIFT)
 
/*
 * MTG1_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_MASK (0xFF00U)
#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SHIFT (8U)
#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_MTG1_POS_SEL_SHIFT)
 
/*
 * MTG0_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_MASK (0xFFU)
#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SHIFT (0U)
#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL1_MTG0_POS_SEL_SHIFT)
 
/* Bitfield definition for register: POS_MATRIX_SEL2 */
/*
 * VSC1_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_MASK (0xFF000000UL)
#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SHIFT (24U)
#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_VSC1_POS_SEL_SHIFT)
 
/*
 * VSC0_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_MASK (0xFF0000UL)
#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SHIFT (16U)
#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_VSC0_POS_SEL_SHIFT)
 
/*
 * QEO3_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_MASK (0xFF00U)
#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SHIFT (8U)
#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_QEO3_POS_SEL_SHIFT)
 
/*
 * QEO2_POS_SEL (RW)
 *
 */
#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_MASK (0xFFU)
#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SHIFT (0U)
#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SET(x) (((uint32_t)(x) << TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SHIFT) & TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_MASK)
#define TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_GET(x) (((uint32_t)(x) & TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_MASK) >> TRGM_POS_MATRIX_SEL2_QEO2_POS_SEL_SHIFT)
 
/* Bitfield definition for register array: TRGM_IN */
/*
 * TRGM_IN (RO)
 *
 */
#define TRGM_TRGM_IN_TRGM_IN_MASK (0xFFFFFFFFUL)
#define TRGM_TRGM_IN_TRGM_IN_SHIFT (0U)
#define TRGM_TRGM_IN_TRGM_IN_GET(x) (((uint32_t)(x) & TRGM_TRGM_IN_TRGM_IN_MASK) >> TRGM_TRGM_IN_TRGM_IN_SHIFT)
 
/* Bitfield definition for register array: TRGM_OUT */
/*
 * TRGM_OUT (RO)
 *
 */
#define TRGM_TRGM_OUT_TRGM_OUT_MASK (0xFFFFFFFFUL)
#define TRGM_TRGM_OUT_TRGM_OUT_SHIFT (0U)
#define TRGM_TRGM_OUT_TRGM_OUT_GET(x) (((uint32_t)(x) & TRGM_TRGM_OUT_TRGM_OUT_MASK) >> TRGM_TRGM_OUT_TRGM_OUT_SHIFT)
 
/* Bitfield definition for register: PWM_DELAY_CFG */
/*
 * DELAY_CHAN_CALIB_SW (RW)
 *
 */
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK (0x3FU)
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT (0U)
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SET(x) (((uint32_t)(x) << TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK)
#define TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_GET(x) (((uint32_t)(x) & TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_MASK) >> TRGM_PWM_DELAY_CFG_DELAY_CHAN_CALIB_SW_SHIFT)
 
/* Bitfield definition for register: PWM_CALIB_CFG */
/*
 * CALIB_SW_START (RW)
 *
 * set to trigger calibration once by software, need to be cleared first before setting it
 */
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK (0x8000U)
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT (15U)
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_SET(x) (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK)
#define TRGM_PWM_CALIB_CFG_CALIB_SW_START_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_SW_START_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_SW_START_SHIFT)
 
/*
 * CALIB_HW_ENABLE (RW)
 *
 */
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK (0x80U)
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT (7U)
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SET(x) (((uint32_t)(x) << TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT) & TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK)
#define TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_MASK) >> TRGM_PWM_CALIB_CFG_CALIB_HW_ENABLE_SHIFT)
 
/* Bitfield definition for register: PWM_CALIB_STATUS0 */
/*
 * CALIB_ON (RO)
 *
 */
#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_MASK (0x80000000UL)
#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_SHIFT (31U)
#define TRGM_PWM_CALIB_STATUS0_CALIB_ON_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS0_CALIB_ON_MASK) >> TRGM_PWM_CALIB_STATUS0_CALIB_ON_SHIFT)
 
/*
 * CALIB_RESULT (RO)
 *
 */
#define TRGM_PWM_CALIB_STATUS0_CALIB_RESULT_MASK (0x3FU)
#define TRGM_PWM_CALIB_STATUS0_CALIB_RESULT_SHIFT (0U)
#define TRGM_PWM_CALIB_STATUS0_CALIB_RESULT_GET(x) (((uint32_t)(x) & TRGM_PWM_CALIB_STATUS0_CALIB_RESULT_MASK) >> TRGM_PWM_CALIB_STATUS0_CALIB_RESULT_SHIFT)
 
/* Bitfield definition for register array: TRGOCFG */
/*
 * OUTINV (RW)
 *
 * 1- Invert the output
 */
#define TRGM_TRGOCFG_OUTINV_MASK (0x40000UL)
#define TRGM_TRGOCFG_OUTINV_SHIFT (18U)
#define TRGM_TRGOCFG_OUTINV_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_OUTINV_SHIFT) & TRGM_TRGOCFG_OUTINV_MASK)
#define TRGM_TRGOCFG_OUTINV_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_OUTINV_MASK) >> TRGM_TRGOCFG_OUTINV_SHIFT)
 
/*
 * FEDG2PEN (RW)
 *
 * 1- The selected input signal falling edge will be convert to an pulse on output.
 */
#define TRGM_TRGOCFG_FEDG2PEN_MASK (0x20000UL)
#define TRGM_TRGOCFG_FEDG2PEN_SHIFT (17U)
#define TRGM_TRGOCFG_FEDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_FEDG2PEN_SHIFT) & TRGM_TRGOCFG_FEDG2PEN_MASK)
#define TRGM_TRGOCFG_FEDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_FEDG2PEN_MASK) >> TRGM_TRGOCFG_FEDG2PEN_SHIFT)
 
/*
 * REDG2PEN (RW)
 *
 * 1- The selected input signal rising edge will be convert to an pulse on output.
 */
#define TRGM_TRGOCFG_REDG2PEN_MASK (0x10000UL)
#define TRGM_TRGOCFG_REDG2PEN_SHIFT (16U)
#define TRGM_TRGOCFG_REDG2PEN_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_REDG2PEN_SHIFT) & TRGM_TRGOCFG_REDG2PEN_MASK)
#define TRGM_TRGOCFG_REDG2PEN_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_REDG2PEN_MASK) >> TRGM_TRGOCFG_REDG2PEN_SHIFT)
 
/*
 * TRIGOSEL (RW)
 *
 * This bitfield selects one of the TRGM inputs as output.
 */
#define TRGM_TRGOCFG_TRIGOSEL_MASK (0xFFU)
#define TRGM_TRGOCFG_TRIGOSEL_SHIFT (0U)
#define TRGM_TRGOCFG_TRIGOSEL_SET(x) (((uint32_t)(x) << TRGM_TRGOCFG_TRIGOSEL_SHIFT) & TRGM_TRGOCFG_TRIGOSEL_MASK)
#define TRGM_TRGOCFG_TRIGOSEL_GET(x) (((uint32_t)(x) & TRGM_TRGOCFG_TRIGOSEL_MASK) >> TRGM_TRGOCFG_TRIGOSEL_SHIFT)
 
 
 
/* FILTCFG register group index macro definition */
#define TRGM_FILTCFG_PWM0_IN0 (0UL)
#define TRGM_FILTCFG_PWM0_IN1 (1UL)
#define TRGM_FILTCFG_PWM0_IN2 (2UL)
#define TRGM_FILTCFG_PWM0_IN3 (3UL)
#define TRGM_FILTCFG_PWM0_IN4 (4UL)
#define TRGM_FILTCFG_PWM0_IN5 (5UL)
#define TRGM_FILTCFG_PWM0_IN6 (6UL)
#define TRGM_FILTCFG_PWM0_IN7 (7UL)
#define TRGM_FILTCFG_PWM1_IN0 (8UL)
#define TRGM_FILTCFG_PWM1_IN1 (9UL)
#define TRGM_FILTCFG_PWM1_IN2 (10UL)
#define TRGM_FILTCFG_PWM1_IN3 (11UL)
#define TRGM_FILTCFG_PWM1_IN4 (12UL)
#define TRGM_FILTCFG_PWM1_IN5 (13UL)
#define TRGM_FILTCFG_PWM1_IN6 (14UL)
#define TRGM_FILTCFG_PWM1_IN7 (15UL)
#define TRGM_FILTCFG_PWM2_IN0 (16UL)
#define TRGM_FILTCFG_PWM2_IN1 (17UL)
#define TRGM_FILTCFG_PWM2_IN2 (18UL)
#define TRGM_FILTCFG_PWM2_IN3 (19UL)
#define TRGM_FILTCFG_PWM2_IN4 (20UL)
#define TRGM_FILTCFG_PWM2_IN5 (21UL)
#define TRGM_FILTCFG_PWM2_IN6 (22UL)
#define TRGM_FILTCFG_PWM2_IN7 (23UL)
#define TRGM_FILTCFG_PWM3_IN0 (24UL)
#define TRGM_FILTCFG_PWM3_IN1 (25UL)
#define TRGM_FILTCFG_PWM3_IN2 (26UL)
#define TRGM_FILTCFG_PWM3_IN3 (27UL)
#define TRGM_FILTCFG_PWM3_IN4 (28UL)
#define TRGM_FILTCFG_PWM3_IN5 (29UL)
#define TRGM_FILTCFG_PWM3_IN6 (30UL)
#define TRGM_FILTCFG_PWM3_IN7 (31UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN0 (32UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN1 (33UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN2 (34UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN3 (35UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN4 (36UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN5 (37UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN6 (38UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN7 (39UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN8 (40UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN9 (41UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN10 (42UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN11 (43UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN12 (44UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN13 (45UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN14 (46UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN15 (47UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN16 (48UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN17 (49UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN18 (50UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN19 (51UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN20 (52UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN21 (53UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN22 (54UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN23 (55UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN24 (56UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN25 (57UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN26 (58UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN27 (59UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN28 (60UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN29 (61UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN30 (62UL)
#define TRGM_FILTCFG_MOTO_GPIO_IN31 (63UL)
 
/* DMACFG register group index macro definition */
#define TRGM_DMACFG_0 (0UL)
#define TRGM_DMACFG_1 (1UL)
#define TRGM_DMACFG_2 (2UL)
#define TRGM_DMACFG_3 (3UL)
#define TRGM_DMACFG_4 (4UL)
#define TRGM_DMACFG_5 (5UL)
#define TRGM_DMACFG_6 (6UL)
#define TRGM_DMACFG_7 (7UL)
 
/* TRGM_IN register group index macro definition */
#define TRGM_TRGM_IN_0 (0UL)
#define TRGM_TRGM_IN_1 (1UL)
#define TRGM_TRGM_IN_2 (2UL)
#define TRGM_TRGM_IN_3 (3UL)
#define TRGM_TRGM_IN_4 (4UL)
#define TRGM_TRGM_IN_5 (5UL)
#define TRGM_TRGM_IN_6 (6UL)
#define TRGM_TRGM_IN_7 (7UL)
 
/* TRGM_OUT register group index macro definition */
#define TRGM_TRGM_OUT_0 (0UL)
#define TRGM_TRGM_OUT_1 (1UL)
#define TRGM_TRGM_OUT_2 (2UL)
#define TRGM_TRGM_OUT_3 (3UL)
#define TRGM_TRGM_OUT_4 (4UL)
#define TRGM_TRGM_OUT_5 (5UL)
#define TRGM_TRGM_OUT_6 (6UL)
#define TRGM_TRGM_OUT_7 (7UL)
 
/* TRGOCFG register group index macro definition */
#define TRGM_TRGOCFG_MOT_GPIO0 (0UL)
#define TRGM_TRGOCFG_MOT_GPIO1 (1UL)
#define TRGM_TRGOCFG_MOT_GPIO2 (2UL)
#define TRGM_TRGOCFG_MOT_GPIO3 (3UL)
#define TRGM_TRGOCFG_MOT_GPIO4 (4UL)
#define TRGM_TRGOCFG_MOT_GPIO5 (5UL)
#define TRGM_TRGOCFG_MOT_GPIO6 (6UL)
#define TRGM_TRGOCFG_MOT_GPIO7 (7UL)
#define TRGM_TRGOCFG_MOT_GPIO8 (8UL)
#define TRGM_TRGOCFG_MOT_GPIO9 (9UL)
#define TRGM_TRGOCFG_MOT_GPIO10 (10UL)
#define TRGM_TRGOCFG_MOT_GPIO11 (11UL)
#define TRGM_TRGOCFG_MOT_GPIO12 (12UL)
#define TRGM_TRGOCFG_MOT_GPIO13 (13UL)
#define TRGM_TRGOCFG_MOT_GPIO14 (14UL)
#define TRGM_TRGOCFG_MOT_GPIO15 (15UL)
#define TRGM_TRGOCFG_MOT_GPIO16 (16UL)
#define TRGM_TRGOCFG_MOT_GPIO17 (17UL)
#define TRGM_TRGOCFG_MOT_GPIO18 (18UL)
#define TRGM_TRGOCFG_MOT_GPIO19 (19UL)
#define TRGM_TRGOCFG_MOT_GPIO20 (20UL)
#define TRGM_TRGOCFG_MOT_GPIO21 (21UL)
#define TRGM_TRGOCFG_MOT_GPIO22 (22UL)
#define TRGM_TRGOCFG_MOT_GPIO23 (23UL)
#define TRGM_TRGOCFG_MOT_GPIO24 (24UL)
#define TRGM_TRGOCFG_MOT_GPIO25 (25UL)
#define TRGM_TRGOCFG_MOT_GPIO26 (26UL)
#define TRGM_TRGOCFG_MOT_GPIO27 (27UL)
#define TRGM_TRGOCFG_MOT_GPIO28 (28UL)
#define TRGM_TRGOCFG_MOT_GPIO29 (29UL)
#define TRGM_TRGOCFG_MOT_GPIO30 (30UL)
#define TRGM_TRGOCFG_MOT_GPIO31 (31UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC0 (32UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC1 (33UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC2 (34UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC3 (35UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC4 (36UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC5 (37UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC6 (38UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC7 (39UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC8 (40UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC9 (41UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC10 (42UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC11 (43UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC12 (44UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC13 (45UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC14 (46UL)
#define TRGM_TRGOCFG_SDM_PWM_SOC15 (47UL)
#define TRGM_TRGOCFG_ADC0_STRGI (48UL)
#define TRGM_TRGOCFG_ADC1_STRGI (49UL)
#define TRGM_TRGOCFG_ADC2_STRGI (50UL)
#define TRGM_TRGOCFG_ADC3_STRGI (51UL)
#define TRGM_TRGOCFG_ADCX_PTRGI0A (52UL)
#define TRGM_TRGOCFG_ADCX_PTRGI0B (53UL)
#define TRGM_TRGOCFG_ADCX_PTRGI0C (54UL)
#define TRGM_TRGOCFG_ADCX_PTRGI1A (55UL)
#define TRGM_TRGOCFG_ADCX_PTRGI1B (56UL)
#define TRGM_TRGOCFG_ADCX_PTRGI1C (57UL)
#define TRGM_TRGOCFG_ADCX_PTRGI2A (58UL)
#define TRGM_TRGOCFG_ADCX_PTRGI2B (59UL)
#define TRGM_TRGOCFG_ADCX_PTRGI2C (60UL)
#define TRGM_TRGOCFG_ADCX_PTRGI3A (61UL)
#define TRGM_TRGOCFG_ADCX_PTRGI3B (62UL)
#define TRGM_TRGOCFG_ADCX_PTRGI3C (63UL)
#define TRGM_TRGOCFG_VSC0_TRIG_IN0 (64UL)
#define TRGM_TRGOCFG_VSC0_TRIG_IN1 (65UL)
#define TRGM_TRGOCFG_VSC1_TRIG_IN0 (66UL)
#define TRGM_TRGOCFG_VSC1_TRIG_IN1 (67UL)
#define TRGM_TRGOCFG_RDC0_TRIG_IN0 (68UL)
#define TRGM_TRGOCFG_RDC0_TRIG_IN1 (69UL)
#define TRGM_TRGOCFG_RDC1_TRIG_IN0 (70UL)
#define TRGM_TRGOCFG_RDC1_TRIG_IN1 (71UL)
#define TRGM_TRGOCFG_QEI0_TRIG_IN (72UL)
#define TRGM_TRGOCFG_QEI1_TRIG_IN (73UL)
#define TRGM_TRGOCFG_QEI2_TRIG_IN (74UL)
#define TRGM_TRGOCFG_QEI3_TRIG_IN (75UL)
#define TRGM_TRGOCFG_QEI0_PAUSE (76UL)
#define TRGM_TRGOCFG_QEI1_PAUSE (77UL)
#define TRGM_TRGOCFG_QEI2_PAUSE (78UL)
#define TRGM_TRGOCFG_QEI3_PAUSE (79UL)
#define TRGM_TRGOCFG_QEO0_TRIG_IN0 (80UL)
#define TRGM_TRGOCFG_QEO0_TRIG_IN1 (81UL)
#define TRGM_TRGOCFG_QEO1_TRIG_IN0 (82UL)
#define TRGM_TRGOCFG_QEO1_TRIG_IN1 (83UL)
#define TRGM_TRGOCFG_QEO2_TRIG_IN0 (84UL)
#define TRGM_TRGOCFG_QEO2_TRIG_IN1 (85UL)
#define TRGM_TRGOCFG_QEO3_TRIG_IN0 (86UL)
#define TRGM_TRGOCFG_QEO3_TRIG_IN1 (87UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN0 (88UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN1 (89UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN2 (90UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN3 (91UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN4 (92UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN5 (93UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN6 (94UL)
#define TRGM_TRGOCFG_SEI_TRIG_IN7 (95UL)
#define TRGM_TRGOCFG_CMP0_WIN (96UL)
#define TRGM_TRGOCFG_CMP1_WIN (97UL)
#define TRGM_TRGOCFG_CMP2_WIN (98UL)
#define TRGM_TRGOCFG_CMP3_WIN (99UL)
#define TRGM_TRGOCFG_CMP4_WIN (100UL)
#define TRGM_TRGOCFG_CMP5_WIN (101UL)
#define TRGM_TRGOCFG_CMP6_WIN (102UL)
#define TRGM_TRGOCFG_CMP7_WIN (103UL)
#define TRGM_TRGOCFG_GPTMR0_IN2 (104UL)
#define TRGM_TRGOCFG_GPTMR0_IN3 (105UL)
#define TRGM_TRGOCFG_GPTMR0_SYNCI (106UL)
#define TRGM_TRGOCFG_GPTMR1_IN2 (107UL)
#define TRGM_TRGOCFG_GPTMR1_IN3 (108UL)
#define TRGM_TRGOCFG_GPTMR1_SYNCI (109UL)
#define TRGM_TRGOCFG_GPTMR2_IN2 (110UL)
#define TRGM_TRGOCFG_GPTMR2_IN3 (111UL)
#define TRGM_TRGOCFG_GPTMR2_SYNCI (112UL)
#define TRGM_TRGOCFG_GPTMR3_IN2 (113UL)
#define TRGM_TRGOCFG_GPTMR3_IN3 (114UL)
#define TRGM_TRGOCFG_GPTMR3_SYNCI (115UL)
#define TRGM_TRGOCFG_GPTMR4_IN2 (116UL)
#define TRGM_TRGOCFG_GPTMR4_IN3 (117UL)
#define TRGM_TRGOCFG_GPTMR4_SYNCI (118UL)
#define TRGM_TRGOCFG_GPTMR5_IN2 (119UL)
#define TRGM_TRGOCFG_GPTMR5_IN3 (120UL)
#define TRGM_TRGOCFG_GPTMR5_SYNCI (121UL)
#define TRGM_TRGOCFG_GPTMR6_IN2 (122UL)
#define TRGM_TRGOCFG_GPTMR6_IN3 (123UL)
#define TRGM_TRGOCFG_GPTMR6_SYNCI (124UL)
#define TRGM_TRGOCFG_GPTMR7_IN2 (125UL)
#define TRGM_TRGOCFG_GPTMR7_IN3 (126UL)
#define TRGM_TRGOCFG_GPTMR7_SYNCI (127UL)
#define TRGM_TRGOCFG_PLB_IN_00 (128UL)
#define TRGM_TRGOCFG_PLB_IN_01 (129UL)
#define TRGM_TRGOCFG_PLB_IN_02 (130UL)
#define TRGM_TRGOCFG_PLB_IN_03 (131UL)
#define TRGM_TRGOCFG_PLB_IN_04 (132UL)
#define TRGM_TRGOCFG_PLB_IN_05 (133UL)
#define TRGM_TRGOCFG_PLB_IN_06 (134UL)
#define TRGM_TRGOCFG_PLB_IN_07 (135UL)
#define TRGM_TRGOCFG_PLB_IN_08 (136UL)
#define TRGM_TRGOCFG_PLB_IN_09 (137UL)
#define TRGM_TRGOCFG_PLB_IN_10 (138UL)
#define TRGM_TRGOCFG_PLB_IN_11 (139UL)
#define TRGM_TRGOCFG_PLB_IN_12 (140UL)
#define TRGM_TRGOCFG_PLB_IN_13 (141UL)
#define TRGM_TRGOCFG_PLB_IN_14 (142UL)
#define TRGM_TRGOCFG_PLB_IN_15 (143UL)
#define TRGM_TRGOCFG_PLB_IN_16 (144UL)
#define TRGM_TRGOCFG_PLB_IN_17 (145UL)
#define TRGM_TRGOCFG_PLB_IN_18 (146UL)
#define TRGM_TRGOCFG_PLB_IN_19 (147UL)
#define TRGM_TRGOCFG_PLB_IN_20 (148UL)
#define TRGM_TRGOCFG_PLB_IN_21 (149UL)
#define TRGM_TRGOCFG_PLB_IN_22 (150UL)
#define TRGM_TRGOCFG_PLB_IN_23 (151UL)
#define TRGM_TRGOCFG_PLB_IN_24 (152UL)
#define TRGM_TRGOCFG_PLB_IN_25 (153UL)
#define TRGM_TRGOCFG_PLB_IN_26 (154UL)
#define TRGM_TRGOCFG_PLB_IN_27 (155UL)
#define TRGM_TRGOCFG_PLB_IN_28 (156UL)
#define TRGM_TRGOCFG_PLB_IN_29 (157UL)
#define TRGM_TRGOCFG_PLB_IN_30 (158UL)
#define TRGM_TRGOCFG_PLB_IN_31 (159UL)
#define TRGM_TRGOCFG_PLB_IN_32 (160UL)
#define TRGM_TRGOCFG_PLB_IN_33 (161UL)
#define TRGM_TRGOCFG_PLB_IN_34 (162UL)
#define TRGM_TRGOCFG_PLB_IN_35 (163UL)
#define TRGM_TRGOCFG_PLB_IN_36 (164UL)
#define TRGM_TRGOCFG_PLB_IN_37 (165UL)
#define TRGM_TRGOCFG_PLB_IN_38 (166UL)
#define TRGM_TRGOCFG_PLB_IN_39 (167UL)
#define TRGM_TRGOCFG_PLB_IN_40 (168UL)
#define TRGM_TRGOCFG_PLB_IN_41 (169UL)
#define TRGM_TRGOCFG_PLB_IN_42 (170UL)
#define TRGM_TRGOCFG_PLB_IN_43 (171UL)
#define TRGM_TRGOCFG_PLB_IN_44 (172UL)
#define TRGM_TRGOCFG_PLB_IN_45 (173UL)
#define TRGM_TRGOCFG_PLB_IN_46 (174UL)
#define TRGM_TRGOCFG_PLB_IN_47 (175UL)
#define TRGM_TRGOCFG_PLB_IN_48 (176UL)
#define TRGM_TRGOCFG_PLB_IN_49 (177UL)
#define TRGM_TRGOCFG_PLB_IN_50 (178UL)
#define TRGM_TRGOCFG_PLB_IN_51 (179UL)
#define TRGM_TRGOCFG_PLB_IN_52 (180UL)
#define TRGM_TRGOCFG_PLB_IN_53 (181UL)
#define TRGM_TRGOCFG_PLB_IN_54 (182UL)
#define TRGM_TRGOCFG_PLB_IN_55 (183UL)
#define TRGM_TRGOCFG_PLB_IN_56 (184UL)
#define TRGM_TRGOCFG_PLB_IN_57 (185UL)
#define TRGM_TRGOCFG_PLB_IN_58 (186UL)
#define TRGM_TRGOCFG_PLB_IN_59 (187UL)
#define TRGM_TRGOCFG_PLB_IN_60 (188UL)
#define TRGM_TRGOCFG_PLB_IN_61 (189UL)
#define TRGM_TRGOCFG_PLB_IN_62 (190UL)
#define TRGM_TRGOCFG_PLB_IN_63 (191UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN0 (192UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN1 (193UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN2 (194UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN3 (195UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN4 (196UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN5 (197UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN6 (198UL)
#define TRGM_TRGOCFG_PWM0_TRIG_IN7 (199UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN0 (200UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN1 (201UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN2 (202UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN3 (203UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN4 (204UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN5 (205UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN6 (206UL)
#define TRGM_TRGOCFG_PWM1_TRIG_IN7 (207UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN0 (208UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN1 (209UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN2 (210UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN3 (211UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN4 (212UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN5 (213UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN6 (214UL)
#define TRGM_TRGOCFG_PWM2_TRIG_IN7 (215UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN0 (216UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN1 (217UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN2 (218UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN3 (219UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN4 (220UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN5 (221UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN6 (222UL)
#define TRGM_TRGOCFG_PWM3_TRIG_IN7 (223UL)
#define TRGM_TRGOCFG_CAN_PTPC0_CAP (224UL)
#define TRGM_TRGOCFG_CAN_PTPC1_CAP (225UL)
#define TRGM_TRGOCFG_UART_TRIG0 (226UL)
#define TRGM_TRGOCFG_UART_TRIG1 (227UL)
#define TRGM_TRGOCFG_SYNCTIMER_TRIG (228UL)
#define TRGM_TRGOCFG_TRGM_IRQ0 (229UL)
#define TRGM_TRGOCFG_TRGM_IRQ1 (230UL)
#define TRGM_TRGOCFG_TRGM_DMA0 (231UL)
#define TRGM_TRGOCFG_TRGM_DMA1 (232UL)
#define TRGM_TRGOCFG_MTG0_TRIG_IN0 (233UL)
#define TRGM_TRGOCFG_MTG0_TRIG_IN1 (234UL)
#define TRGM_TRGOCFG_MTG0_TRIG_IN2 (235UL)
#define TRGM_TRGOCFG_MTG0_TRIG_IN3 (236UL)
#define TRGM_TRGOCFG_MTG1_TRIG_IN0 (237UL)
#define TRGM_TRGOCFG_MTG1_TRIG_IN1 (238UL)
#define TRGM_TRGOCFG_MTG1_TRIG_IN2 (239UL)
#define TRGM_TRGOCFG_MTG1_TRIG_IN3 (240UL)
#define TRGM_TRGOCFG_ESC_TRIG_IN (241UL)
 
 
#endif /* HPM_TRGM_H */