hpm_clc_drv.h

Go to the documentation of this file.

/*
 * Copyright (c) 2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_CLC_DRV_H
#define HPM_CLC_DRV_H
 
#include "hpm_common.h"
#include "hpm_clc_regs.h"
#include "hpm_soc_feature.h"
 
typedef enum {
    clc_vd_chn = CLC_VDVQ_CHAN_VD,
    clc_vq_chn = CLC_VDVQ_CHAN_VQ,
} clc_chn_t; 
typedef enum {
    clc_coeff_zone_0 = CLC_COEFF_0,
    clc_coeff_zone_1 = CLC_COEFF_1,
    clc_coeff_zone_2 = CLC_COEFF_2,
} clc_coeff_zone_t; 
typedef enum {
    clc_irq_calc_done = BIT0_MASK,
    clc_irq_eadc_setting_err = BIT1_MASK,
    clc_irq_2p2z_clamp_setting_err = BIT2_MASK,
    clc_irq_2p2z_over_hi = BIT3_MASK,
    clc_irq_2p2z_over_lo = BIT4_MASK,
    clc_irq_2p2z_over_sf = BIT5_MASK,
    clc_irq_3p3z_clamp_setting_err = BIT6_MASK,
    clc_irq_3p3z_over_hi = BIT7_MASK,
    clc_irq_3p3z_over_lo = BIT8_MASK,
    clc_irq_forb_setting_err = BIT9_MASK,
    clc_irq_data_in_forbid = BIT10_MASK
} clc_irq_mask_t;
 
typedef struct {
    int32_t eadc_lowth;
    int32_t eadc_mid_lowth;
    int32_t eadc_mid_highth;
    int32_t eadc_highth;
    int32_t _2p2z_clamp_lowth;
    int32_t _2p2z_clamp_highth;
    int32_t _3p3z_clamp_lowth;
    int32_t _3p3z_clamp_highth;
    int32_t output_forbid_lowth;
    int32_t output_forbid_mid;
    int32_t output_forbid_highth;
} clc_param_config_t;   
typedef struct {
    float b0;
    float b1;
    float b2;
    float b3;
    float a0;
    float a1;
    float a2;
} clc_coeff_config_t;   
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void clc_set_enable(CLC_Type *clc, clc_chn_t chn, bool enable)
{
    if (enable) {
        clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK;
    } else {
        clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK;
    }
}
 
static inline void clc_set_mask_mode_enable(CLC_Type *clc, clc_chn_t chn, bool enable)
{
    if (enable) {
        clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK;
    } else {
        clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK;
    }
}
 
static inline void clc_set_sw_inject_dq_mode_enable(CLC_Type *clc, clc_chn_t chn, bool enable)
{
    if (enable) {
        clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK;
    } else {
        clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK;
    }
}
 
static inline void clc_set_irq_enable(CLC_Type *clc, clc_chn_t chn, uint32_t irq_mask, bool enable)
{
    if (enable) {
        clc->VDVQ_CHAN[chn].MODE |= CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(irq_mask);
    } else {
        clc->VDVQ_CHAN[chn].MODE &= ~CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(irq_mask);
    }
}
 
static inline uint32_t clc_get_irq_status(CLC_Type *clc, clc_chn_t chn)
{
    return CLC_VDVQ_CHAN_STATUS_STATUS_GET(clc->VDVQ_CHAN[chn].STATUS);
}
 
static inline void clc_clear_irq_status(CLC_Type *clc, clc_chn_t chn, uint32_t irq_mask)
{
    clc->VDVQ_CHAN[chn].STATUS = CLC_VDVQ_CHAN_STATUS_STATUS_SET(irq_mask);
}
 
static inline bool clc_get_irq_flag(CLC_Type *clc, clc_chn_t chn, uint32_t irq_mask)
{
    return ((clc->VDVQ_CHAN[chn].STATUS & irq_mask) == irq_mask) ? true : false;
}
 
static inline void clc_set_adc_chn_offset(CLC_Type *clc, clc_chn_t chn, uint32_t adc_chn, uint32_t adc_offset)
{
    clc->VDVQ_CHAN[chn].ADC_CHAN = adc_chn;
    clc->VDVQ_CHAN[chn].ADC_OFFSET = adc_offset;
}
 
static inline void clc_set_pwm_period(CLC_Type *clc, clc_chn_t chn, uint32_t pwm_period)
{
    clc->VDVQ_CHAN[chn].PWM_PERIOD = pwm_period;
}
 
static inline uint32_t clc_get_pwm_period(CLC_Type *clc, clc_chn_t chn)
{
    return clc->VDVQ_CHAN[chn].PWM_PERIOD;
}
 
static inline uint32_t clc_get_output_value(CLC_Type *clc, clc_chn_t chn)
{
    return clc->VDVQ_CHAN[chn].OUTPUT_VALUE;
}
 
static inline uint32_t clc_get_timestamp(CLC_Type *clc, clc_chn_t chn)
{
    return clc->VDVQ_CHAN[chn].TIMESTAMP;
}
 
static inline int32_t clc_get_eadc_current_value(CLC_Type *clc, clc_chn_t chn)
{
    return (int32_t)clc->VDVQ_CHAN[chn].EADC_CURR;
}
 
static inline int32_t clc_get_eadc_previous0_value(CLC_Type *clc, clc_chn_t chn)
{
    return (int32_t)clc->VDVQ_CHAN[chn].EADC_PRE0;
}
 
static inline void clc_sw_inject_eadc_previous0_value(CLC_Type *clc, clc_chn_t chn, int32_t value)
{
    clc->VDVQ_CHAN[chn].EADC_PRE0 = (uint32_t)value;
}
 
static inline int32_t clc_get_eadc_previous1_value(CLC_Type *clc, clc_chn_t chn)
{
    return (int32_t)clc->VDVQ_CHAN[chn].EADC_PRE1;
}
 
static inline void clc_sw_inject_eadc_previous1_value(CLC_Type *clc, clc_chn_t chn, int32_t value)
{
    clc->VDVQ_CHAN[chn].EADC_PRE1 = (uint32_t)value;
}
 
static inline int32_t clc_get_2p2z_current_value(CLC_Type *clc, clc_chn_t chn)
{
    return (int32_t)clc->VDVQ_CHAN[chn].P2Z2_CURR;
}
 
static inline void clc_sw_inject_2p2z_current_value(CLC_Type *clc, clc_chn_t chn, int32_t value)
{
    clc->VDVQ_CHAN[chn].P2Z2_CURR = (uint32_t)value;
}
 
static inline int32_t clc_get_2p2z_previous0_value(CLC_Type *clc, clc_chn_t chn)
{
    return (int32_t)clc->VDVQ_CHAN[chn].P2Z2_PRE0;
}
 
static inline void clc_sw_inject_2p2z_previous0_value(CLC_Type *clc, clc_chn_t chn, int32_t value)
{
    clc->VDVQ_CHAN[chn].P2Z2_PRE0 = (uint32_t)value;
}
 
static inline int32_t clc_get_3p3z_current_value(CLC_Type *clc, clc_chn_t chn)
{
    return (int32_t)clc->VDVQ_CHAN[chn].P3Z3_CURR;
}
 
static inline void clc_sw_inject_3p3z_current_value(CLC_Type *clc, clc_chn_t chn, int32_t value)
{
    clc->VDVQ_CHAN[chn].P3Z3_CURR = (uint32_t)value;
}
 
static inline void clc_set_expect_adc_value(CLC_Type *clc, clc_chn_t chn, int32_t expect)
{
    clc->VDVQ_CHAN[chn].ADC_EXPECT = (uint32_t)expect;
}
 
static inline void clc_sw_inject_adc_value(CLC_Type *clc, clc_chn_t chn, uint32_t value)
{
    clc->VDVQ_CHAN[chn].ADC_SW = value;
}
 
static inline void clc_set_sw_inject_dq_adc_value_ready(CLC_Type *clc)
{
    clc->DQ_ADC_SW_READY = CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK;
}
 
void clc_config_param(CLC_Type *clc, clc_chn_t chn, clc_param_config_t *param);
 
hpm_stat_t clc_config_coeff(CLC_Type *clc, clc_chn_t chn, clc_coeff_zone_t zone, clc_coeff_config_t *coeff);
 
#if defined(HPM_IP_FEATURE_CLC_DECOUPLING) && HPM_IP_FEATURE_CLC_DECOUPLING
static inline void clc_sw_inject_speed_value(CLC_Type *clc, int32_t value)
{
    clc->VDVQ_CHAN[clc_vd_chn].SPEED_SW = value;
}
 
static inline void clc_set_decoupling_scaling(CLC_Type *clc, clc_chn_t chn, uint32_t left_shift_value)
{
    clc->VDVQ_CHAN[chn].DECOUPLE_SCALING = left_shift_value;
}
 
hpm_stat_t clc_set_decoupling_ind_ke(CLC_Type *clc, clc_chn_t chn, float ind, float ke);
#endif
 
void clc_sw_inject_dq_adc_value(CLC_Type *clc, uint32_t d_value, uint32_t q_value);
 
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_CLC_DRV_H */