HPM SDK
HPMicro Software Development Kit
hpm_clc_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_CLC_H
10 #define HPM_CLC_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t MODE; /* 0x0: mode ctrl */
15  __RW uint32_t ADC_EXPECT; /* 0x4: adc expect */
16  __RW uint32_t ADC_CHAN; /* 0x8: adc used channel */
17  __RW uint32_t ADC_OFFSET; /* 0xC: adc used offset */
18  __RW uint32_t EADC_LOWTH; /* 0x10: eadc_lowth value used in error adc cofficient selection */
19  __RW uint32_t EADC_HIGHTH; /* 0x14: eadc_highth value used in error adc cofficient selection */
20  __RW uint32_t EADC_MIDLOWTH; /* 0x18: eadc_midlowth value used in error adc cofficient selection */
21  __RW uint32_t EADC_MIDHIGHTH; /* 0x1C: eadc_midhighth value used in error adc cofficient selection */
22  __RW uint32_t P2Z2_CLAMP_LO; /* 0x20: 2p2z output clamp low threshold */
23  __RW uint32_t P2Z2_CLAMP_HI; /* 0x24: 2p2z output clamp high threshold */
24  __RW uint32_t P3Z3_CLAMP_LO; /* 0x28: 3p3z output clamp low threshold */
25  __RW uint32_t P3Z3_CLAMP_HI; /* 0x2C: 3p3z output clamp high threshold */
26  __R uint8_t RESERVED0[16]; /* 0x30 - 0x3F: Reserved */
27  struct {
28  __RW uint32_t COEFF_B0; /* 0x40: zone b0 */
29  __RW uint32_t COEFF_B1; /* 0x44: zone b1 */
30  __RW uint32_t COEFF_B2; /* 0x48: zone b2 */
31  __RW uint32_t COEFF_B3; /* 0x4C: zone b3 */
32  __RW uint32_t COEFF_A0; /* 0x50: zone a0 */
33  __RW uint32_t COEFF_A1; /* 0x54: zone a1 */
34  __RW uint32_t COEFF_A2; /* 0x58: zone a2 */
35  __RW uint32_t COEFF_KS; /* 0x5C: zone kscaling */
36  } COEFF[3];
37  __RW uint32_t PWM_PERIOD; /* 0xA0: pwm_period */
38  __R uint32_t OUTPUT_VALUE; /* 0xA4: output value */
39  __R uint32_t TIMESTAMP; /* 0xA8: adc timestamp used */
40  __RW uint32_t EADC_CURR; /* 0xAC: error adc latest value */
41  __RW uint32_t EADC_PRE0; /* 0xB0: error adc previous0 value */
42  __RW uint32_t EADC_PRE1; /* 0xB4: error adc previous1 value */
43  __RW uint32_t P2Z2_CURR; /* 0xB8: 2p2z latest value */
44  __RW uint32_t P2Z2_PRE0; /* 0xBC: 2p2z previous0 value */
45  __R uint8_t RESERVED1[4]; /* 0xC0 - 0xC3: Reserved */
46  __RW uint32_t P3Z3_CURR; /* 0xC4: 3p3z latest value */
47  __R uint8_t RESERVED2[4]; /* 0xC8 - 0xCB: Reserved */
48  __RW uint32_t P3Z3_FORBID_LO; /* 0xCC: 3p3z output forbid low threshold */
49  __RW uint32_t P3Z3_FORBID_MD; /* 0xD0: 3p3z output forbid middle threshold */
50  __RW uint32_t P3Z3_FORBID_HI; /* 0xD4: 3p3z output forbid high threshold */
51  __R uint8_t RESERVED3[8]; /* 0xD8 - 0xDF: Reserved */
52  __RW uint32_t ADC_SW; /* 0xE0: adc software inject value */
53  __R uint8_t RESERVED4[24]; /* 0xE4 - 0xFB: Reserved */
54  __W uint32_t STATUS; /* 0xFC: irq_status */
55  } VDVQ_CHAN[2];
56  __W uint32_t DQ_ADC_SW_READY; /* 0x200: enable d/q chan software inject adc value */
57 } CLC_Type;
58 
59 
60 /* Bitfield definition for register of struct array VDVQ_CHAN: MODE */
61 /*
62  * ENABLE_CLC (RW)
63  *
64  * enable CLC
65  */
66 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK (0x80000000UL)
67 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT (31U)
68 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK)
69 #define CLC_VDVQ_CHAN_MODE_ENABLE_CLC_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_CLC_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_CLC_SHIFT)
70 
71 /*
72  * MASK_MODE (RW)
73  *
74  * open mode: CLC keep working even if bad irq status ocurred
75  */
76 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK (0x1000000UL)
77 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT (24U)
78 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK)
79 #define CLC_VDVQ_CHAN_MODE_MASK_MODE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_MASK_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_MASK_MODE_SHIFT)
80 
81 /*
82  * DQ_MODE (RW)
83  *
84  * dq mode
85  */
86 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK (0x10000UL)
87 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT (16U)
88 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK)
89 #define CLC_VDVQ_CHAN_MODE_DQ_MODE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_DQ_MODE_MASK) >> CLC_VDVQ_CHAN_MODE_DQ_MODE_SHIFT)
90 
91 /*
92  * ENABLE_IRQ (RW)
93  *
94  * enable irq:
95  * irq_data_in_forbid , // 10
96  * irq_forb_err_boundary , // 9
97  * irq_p3z3_over_lo , // 8
98  * irq_p3z3_over_hi , // 7
99  * irq_p3z3_err_boundary , // 6
100  * irq_z2_over_sf , // 5
101  * irq_z2_over_lo , // 4
102  * irq_z2_over_hi , // 3
103  * irq_z2_err_boundary , // 2
104  * irq_coef_err_boundary , // 1
105  * irq_valid_clc // 0
106  */
107 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK (0x7FFU)
108 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT (0U)
109 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK)
110 #define CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_MASK) >> CLC_VDVQ_CHAN_MODE_ENABLE_IRQ_SHIFT)
111 
112 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_EXPECT */
113 /*
114  * ADC_EXPECT (RW)
115  *
116  * adc expect value
117  */
118 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK (0xFFFFFFFFUL)
119 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT (0U)
120 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK)
121 #define CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_MASK) >> CLC_VDVQ_CHAN_ADC_EXPECT_ADC_EXPECT_SHIFT)
122 
123 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_CHAN */
124 /*
125  * ADC_CHAN (RW)
126  *
127  * adc used chan ID
128  */
129 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK (0x1FU)
130 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT (0U)
131 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK)
132 #define CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_MASK) >> CLC_VDVQ_CHAN_ADC_CHAN_ADC_CHAN_SHIFT)
133 
134 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_OFFSET */
135 /*
136  * ADC_OFFSET (RW)
137  *
138  * adc used offset
139  */
140 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK (0xFFFFFFFFUL)
141 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT (0U)
142 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK)
143 #define CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_MASK) >> CLC_VDVQ_CHAN_ADC_OFFSET_ADC_OFFSET_SHIFT)
144 
145 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_LOWTH */
146 /*
147  * EADC_LOWTH (RW)
148  *
149  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
150  */
151 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK (0xFFFFFFFFUL)
152 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT (0U)
153 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK)
154 #define CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_LOWTH_EADC_LOWTH_SHIFT)
155 
156 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_HIGHTH */
157 /*
158  * EADC_HIGHTH (RW)
159  *
160  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
161  */
162 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK (0xFFFFFFFFUL)
163 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT (0U)
164 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK)
165 #define CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_HIGHTH_EADC_HIGHTH_SHIFT)
166 
167 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_MIDLOWTH */
168 /*
169  * EADC_MIDLOWTH (RW)
170  *
171  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
172  */
173 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK (0xFFFFFFFFUL)
174 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT (0U)
175 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK)
176 #define CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDLOWTH_EADC_MIDLOWTH_SHIFT)
177 
178 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_MIDHIGHTH */
179 /*
180  * EADC_MIDHIGHTH (RW)
181  *
182  * if error adc not bigger than eadc_lowth or not less than eadc_highth, use zone 2 cofficient；if not less than midlowth and not bigger than midhighth, use zone 0 cofficient；otherwire, use zone 1 cofficient
183  */
184 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK (0xFFFFFFFFUL)
185 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT (0U)
186 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK)
187 #define CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_MASK) >> CLC_VDVQ_CHAN_EADC_MIDHIGHTH_EADC_MIDHIGHTH_SHIFT)
188 
189 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CLAMP_LO */
190 /*
191  * 2P2Z_CLAMP_LO (RW)
192  *
193  * 2p2z output clamp low threshold
194  */
195 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK (0xFFFFFFFFUL)
196 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT (0U)
197 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK)
198 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_LO_2P2Z_CLAMP_LO_SHIFT)
199 
200 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CLAMP_HI */
201 /*
202  * 2P2Z_CLAMP_HI (RW)
203  *
204  * 2p2z output clamp high threshold
205  */
206 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK (0xFFFFFFFFUL)
207 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT (0U)
208 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK)
209 #define CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P2Z2_CLAMP_HI_2P2Z_CLAMP_HI_SHIFT)
210 
211 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CLAMP_LO */
212 /*
213  * 3P3Z_CLAMP_LO (RW)
214  *
215  * 3p3z output clamp low threshold
216  */
217 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK (0xFFFFFFFFUL)
218 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT (0U)
219 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK)
220 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_LO_3P3Z_CLAMP_LO_SHIFT)
221 
222 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CLAMP_HI */
223 /*
224  * 3P3Z_CLAMP_HI (RW)
225  *
226  * 3p3z output clamp high threshold
227  */
228 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK (0xFFFFFFFFUL)
229 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT (0U)
230 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK)
231 #define CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_CLAMP_HI_3P3Z_CLAMP_HI_SHIFT)
232 
233 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B0 */
234 /*
235  * COEFF_B0 (RW)
236  *
237  * coefficient b0
238  */
239 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK (0xFFFFFFFFUL)
240 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT (0U)
241 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK)
242 #define CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B0_COEFF_B0_SHIFT)
243 
244 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B1 */
245 /*
246  * COEFF_B1 (RW)
247  *
248  * coefficient b1
249  */
250 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK (0xFFFFFFFFUL)
251 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT (0U)
252 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK)
253 #define CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B1_COEFF_B1_SHIFT)
254 
255 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B2 */
256 /*
257  * COEFF_B2 (RW)
258  *
259  * coefficient b2
260  */
261 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK (0xFFFFFFFFUL)
262 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT (0U)
263 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK)
264 #define CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B2_COEFF_B2_SHIFT)
265 
266 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_B3 */
267 /*
268  * COEFF_B3 (RW)
269  *
270  * coefficient b3
271  */
272 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK (0xFFFFFFFFUL)
273 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT (0U)
274 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK)
275 #define CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_B3_COEFF_B3_SHIFT)
276 
277 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A0 */
278 /*
279  * COEFF_A0 (RW)
280  *
281  * coefficient a0
282  */
283 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK (0xFFFFFFFFUL)
284 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT (0U)
285 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK)
286 #define CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A0_COEFF_A0_SHIFT)
287 
288 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A1 */
289 /*
290  * COEFF_A1 (RW)
291  *
292  * coefficient a1
293  */
294 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK (0xFFFFFFFFUL)
295 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT (0U)
296 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK)
297 #define CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A1_COEFF_A1_SHIFT)
298 
299 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_A2 */
300 /*
301  * COEFF_A2 (RW)
302  *
303  * coefficient a2
304  */
305 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK (0xFFFFFFFFUL)
306 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT (0U)
307 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK)
308 #define CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_A2_COEFF_A2_SHIFT)
309 
310 /* Bitfield definition for register of struct array VDVQ_CHAN: COEFF_KS */
311 /*
312  * COEFF_KSCALING (RW)
313  *
314  * coefficient kscaling
315  */
316 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK (0x1FU)
317 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT (0U)
318 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK)
319 #define CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_MASK) >> CLC_VDVQ_CHAN_COEFF_COEFF_KS_COEFF_KSCALING_SHIFT)
320 
321 /* Bitfield definition for register of struct array VDVQ_CHAN: PWM_PERIOD */
322 /*
323  * PWM_PERIOD (RW)
324  *
325  * pwm_period
326  */
327 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK (0xFFFFFFFFUL)
328 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT (0U)
329 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK)
330 #define CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_MASK) >> CLC_VDVQ_CHAN_PWM_PERIOD_PWM_PERIOD_SHIFT)
331 
332 /* Bitfield definition for register of struct array VDVQ_CHAN: OUTPUT_VALUE */
333 /*
334  * OUTPUT_VALUE (RO)
335  *
336  * output_value
337  */
338 #define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK (0xFFFFFFFFUL)
339 #define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT (0U)
340 #define CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_MASK) >> CLC_VDVQ_CHAN_OUTPUT_VALUE_OUTPUT_VALUE_SHIFT)
341 
342 /* Bitfield definition for register of struct array VDVQ_CHAN: TIMESTAMP */
343 /*
344  * TIMESTAMP (RO)
345  *
346  * timestamp
347  */
348 #define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL)
349 #define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT (0U)
350 #define CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_MASK) >> CLC_VDVQ_CHAN_TIMESTAMP_TIMESTAMP_SHIFT)
351 
352 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_CURR */
353 /*
354  * EADC_CURR (RW)
355  *
356  * error adc latest value
357  */
358 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK (0xFFFFFFFFUL)
359 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT (0U)
360 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK)
361 #define CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_MASK) >> CLC_VDVQ_CHAN_EADC_CURR_EADC_CURR_SHIFT)
362 
363 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_PRE0 */
364 /*
365  * EADC_PRE0 (RW)
366  *
367  * error adc previous 0 value
368  */
369 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK (0xFFFFFFFFUL)
370 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT (0U)
371 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK)
372 #define CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_MASK) >> CLC_VDVQ_CHAN_EADC_PRE0_EADC_PRE0_SHIFT)
373 
374 /* Bitfield definition for register of struct array VDVQ_CHAN: EADC_PRE1 */
375 /*
376  * EADC_PRE1 (RW)
377  *
378  * error adc previous 1 value
379  */
380 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK (0xFFFFFFFFUL)
381 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT (0U)
382 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK)
383 #define CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_MASK) >> CLC_VDVQ_CHAN_EADC_PRE1_EADC_PRE1_SHIFT)
384 
385 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_CURR */
386 /*
387  * 2P2Z_CURR (RW)
388  *
389  * 2p2z latest value
390  */
391 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK (0xFFFFFFFFUL)
392 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT (0U)
393 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK)
394 #define CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_MASK) >> CLC_VDVQ_CHAN_P2Z2_CURR_2P2Z_CURR_SHIFT)
395 
396 /* Bitfield definition for register of struct array VDVQ_CHAN: P2Z2_PRE0 */
397 /*
398  * 2P2Z_PRE0 (RW)
399  *
400  * 2p2z previous 0 value
401  */
402 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK (0xFFFFFFFFUL)
403 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT (0U)
404 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK)
405 #define CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_MASK) >> CLC_VDVQ_CHAN_P2Z2_PRE0_2P2Z_PRE0_SHIFT)
406 
407 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_CURR */
408 /*
409  * 3P3Z_CURR (RW)
410  *
411  * 3p3z latest value
412  */
413 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK (0xFFFFFFFFUL)
414 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT (0U)
415 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK)
416 #define CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_MASK) >> CLC_VDVQ_CHAN_P3Z3_CURR_3P3Z_CURR_SHIFT)
417 
418 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_LO */
419 /*
420  * 3P3Z_FORBID_LO (RW)
421  *
422  * 3p3z output forbid low threshold
423  */
424 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK (0xFFFFFFFFUL)
425 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT (0U)
426 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK)
427 #define CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_LO_3P3Z_FORBID_LO_SHIFT)
428 
429 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_MD */
430 /*
431  * 3P3Z_FORBID_MD (RW)
432  *
433  * 3p3z output forbid middle threshold
434  */
435 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK (0xFFFFFFFFUL)
436 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT (0U)
437 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK)
438 #define CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_MD_3P3Z_FORBID_MD_SHIFT)
439 
440 /* Bitfield definition for register of struct array VDVQ_CHAN: P3Z3_FORBID_HI */
441 /*
442  * 3P3Z_FORBID_HI (RW)
443  *
444  * 3p3z output forbid high threshold
445  */
446 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK (0xFFFFFFFFUL)
447 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT (0U)
448 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK)
449 #define CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_MASK) >> CLC_VDVQ_CHAN_P3Z3_FORBID_HI_3P3Z_FORBID_HI_SHIFT)
450 
451 /* Bitfield definition for register of struct array VDVQ_CHAN: ADC_SW */
452 /*
453  * ADC_SW (RW)
454  *
455  * adc software inject value
456  */
457 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK (0xFFFFFFFFUL)
458 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT (0U)
459 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK)
460 #define CLC_VDVQ_CHAN_ADC_SW_ADC_SW_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_ADC_SW_ADC_SW_MASK) >> CLC_VDVQ_CHAN_ADC_SW_ADC_SW_SHIFT)
461 
462 /* Bitfield definition for register of struct array VDVQ_CHAN: STATUS */
463 /*
464  * STATUS (W1C)
465  *
466  * status, write 1 to clear it. :
467  * irq_data_in_forbid , // 10
468  * irq_forb_err_boundary , // 9
469  * irq_p3z3_over_lo , // 8
470  * irq_p3z3_over_hi , // 7
471  * irq_p3z3_err_boundary , // 6
472  * irq_z2_over_sf , // 5
473  * irq_z2_over_lo , // 4
474  * irq_z2_over_hi , // 3
475  * irq_z2_err_boundary , // 2
476  * irq_coef_err_boundary , // 1
477  * irq_valid_clc // 0
478  */
479 #define CLC_VDVQ_CHAN_STATUS_STATUS_MASK (0x7FFU)
480 #define CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT (0U)
481 #define CLC_VDVQ_CHAN_STATUS_STATUS_SET(x) (((uint32_t)(x) << CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK)
482 #define CLC_VDVQ_CHAN_STATUS_STATUS_GET(x) (((uint32_t)(x) & CLC_VDVQ_CHAN_STATUS_STATUS_MASK) >> CLC_VDVQ_CHAN_STATUS_STATUS_SHIFT)
483 
484 /* Bitfield definition for register: DQ_ADC_SW_READY */
485 /*
486  * DQ_ADC_SW_READY (W1C)
487  *
488  * enable d/q chan software inject adc value
489  */
490 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK (0x1U)
491 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT (0U)
492 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SET(x) (((uint32_t)(x) << CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK)
493 #define CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_GET(x) (((uint32_t)(x) & CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_MASK) >> CLC_DQ_ADC_SW_READY_DQ_ADC_SW_READY_SHIFT)
494 
495 
496 
497 /* COEFF register group index macro definition */
498 #define CLC_COEFF_0 (0UL)
499 #define CLC_COEFF_1 (1UL)
500 #define CLC_COEFF_2 (2UL)
501 
502 /* VDVQ_CHAN register group index macro definition */
503 #define CLC_VDVQ_CHAN_VD (0UL)
504 #define CLC_VDVQ_CHAN_VQ (1UL)
505 
506 
507 #endif /* HPM_CLC_H */
CLC_Type
Definition: hpm_clc_regs.h:12