hpm_dma_drv.h

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/*
 * Copyright (c) 2021-2022 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
 
#ifndef HPM_DMAV1_DRV_H
#define HPM_DMAV1_DRV_H
#include "hpm_common.h"
#include "hpm_soc_feature.h"
#include "hpm_dma_regs.h"
 
#define DMA_CHANNEL_PRIORITY_LOW                (0U)
#define DMA_CHANNEL_PRIORITY_HIGH               (1U)
 
#define DMA_NUM_TRANSFER_PER_BURST_1T           (0U)
#define DMA_NUM_TRANSFER_PER_BURST_2T           (1U)
#define DMA_NUM_TRANSFER_PER_BURST_4T           (2U)
#define DMA_NUM_TRANSFER_PER_BURST_8T           (3U)
#define DMA_NUM_TRANSFER_PER_BURST_16T          (4U)
#define DMA_NUM_TRANSFER_PER_BURST_32T          (5U)
#define DMA_NUM_TRANSFER_PER_BURST_64T          (6U)
#define DMA_NUM_TRANSFER_PER_BURST_128T         (7U)
#define DMA_NUM_TRANSFER_PER_BURST_256T         (8U)
#define DMA_NUM_TRANSFER_PER_BURST_512T         (9U)
#define DMA_NUM_TRANSFER_PER_BURST_1024T        (10U)
 
#define DMA_TRANSFER_WIDTH_BYTE                 (0U)
#define DMA_TRANSFER_WIDTH_HALF_WORD            (1U)
#define DMA_TRANSFER_WIDTH_WORD                 (2U)
#define DMA_TRANSFER_WIDTH_DOUBLE_WORD          (3U)
 
#define DMA_ALIGN_HALF_WORD(x)                  (x & ~(1u))
#define DMA_ALIGN_WORD(x)                       (x & ~(3u))
#define DMA_ALIGN_DOUBLE_WORD(x)                (x & ~(7u))
 
#define DMA_STATUS_ERROR_SHIFT                  (0U)
#define DMA_STATUS_ABORT_SHIFT                  (8U)
#define DMA_STATUS_TC_SHIFT                     (16U)
 
#define DMA_CHANNEL_STATUS_ONGOING              (1U)
#define DMA_CHANNEL_STATUS_ERROR                (2U)
#define DMA_CHANNEL_STATUS_ABORT                (4U)
#define DMA_CHANNEL_STATUS_TC                   (8U)
 
#define DMA_CHANNEL_IRQ_STATUS_ERROR(x)         (uint32_t)(1 << (DMA_STATUS_ERROR_SHIFT + x))
#define DMA_CHANNEL_IRQ_STATUS_ABORT(x)         (uint32_t)(1 << (DMA_STATUS_ABORT_SHIFT + x))
#define DMA_CHANNEL_IRQ_STATUS_TC(x)            (uint32_t)(1 << (DMA_STATUS_TC_SHIFT + x))
#define DMA_CHANNEL_IRQ_STATUS(x)               (uint32_t)(DMA_CHANNEL_IRQ_STATUS_TC(x) | \
                                                           DMA_CHANNEL_IRQ_STATUS_ABORT(x) | \
                                                           DMA_CHANNEL_IRQ_STATUS_ERROR(x))
 
#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_TC(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_TC_SHIFT))
#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ABORT(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ABORT_SHIFT))
#define DMA_CHANNEL_IRQ_STATUS_GET_ALL_ERROR(x) ((x) & (((0x01UL << DMA_SOC_CHANNEL_NUM) - 1) << DMA_STATUS_ERROR_SHIFT))
 
#define DMA_HANDSHAKE_MODE_NORMAL (0U)
#define DMA_HANDSHAKE_MODE_HANDSHAKE (1U)
 
#define DMA_ADDRESS_CONTROL_INCREMENT (0U)
#define DMA_ADDRESS_CONTROL_DECREMENT (1U)
#define DMA_ADDRESS_CONTROL_FIXED (2U)
 
#define DMA_INTERRUPT_MASK_NONE (0U)
#define DMA_INTERRUPT_MASK_ERROR  DMA_CHCTRL_CTRL_INTERRMASK_MASK
#define DMA_INTERRUPT_MASK_ABORT  DMA_CHCTRL_CTRL_INTABTMASK_MASK
#define DMA_INTERRUPT_MASK_TERMINAL_COUNT DMA_CHCTRL_CTRL_INTTCMASK_MASK
#define DMA_INTERRUPT_MASK_ALL \
    (uint8_t)(DMA_INTERRUPT_MASK_TERMINAL_COUNT \
            | DMA_INTERRUPT_MASK_ABORT \
            | DMA_INTERRUPT_MASK_ERROR)
 
#ifndef DMA_SUPPORT_64BIT_ADDR
#define DMA_SUPPORT_64BIT_ADDR (0)
#endif
 
typedef struct dma_linked_descriptor {
    uint32_t ctrl;              
    uint32_t trans_size;        
    uint32_t src_addr;          
    uint32_t src_addr_high;     
    uint32_t dst_addr;          
    uint32_t dst_addr_high;     
    uint32_t linked_ptr;        
    uint32_t linked_ptr_high;   
} dma_linked_descriptor_t;
 
/* @brief Channel config */
typedef struct dma_channel_config {
    uint8_t priority;               
    uint8_t src_burst_size;         
    uint8_t src_mode;               
    uint8_t dst_mode;               
    uint8_t src_width;              
    uint8_t dst_width;              
    uint8_t src_addr_ctrl;          
    uint8_t dst_addr_ctrl;          
    uint16_t interrupt_mask;        
    uint32_t src_addr;              
    uint32_t dst_addr;              
    uint32_t linked_ptr;            
    uint32_t size_in_byte;          
#if DMA_SUPPORT_64BIT_ADDR
    uint32_t src_addr_high;         
    uint32_t dst_addr_high;         
    uint32_t linked_ptr_high;       
#endif
} dma_channel_config_t;
 
 
/* @brief Channel config */
typedef struct dma_handshake_config {
    uint32_t dst;
    uint32_t src;
    uint32_t size_in_byte;
    uint8_t data_width;            /* data width, value defined by DMA_TRANSFER_WIDTH_xxx */
    uint8_t ch_index;
    bool dst_fixed;
    bool src_fixed;
} dma_handshake_config_t;
 
 
/* @brief DMA specific status */
enum {
    status_dma_transfer_done = MAKE_STATUS(status_group_dma, 0),
    status_dma_transfer_error = MAKE_STATUS(status_group_dma, 1),
    status_dma_transfer_abort = MAKE_STATUS(status_group_dma, 2),
    status_dma_transfer_ongoing = MAKE_STATUS(status_group_dma, 3),
    status_dma_alignment_error = MAKE_STATUS(status_group_dma, 4),
};
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void dma_reset(DMA_Type *ptr)
{
    ptr->DMACTRL |= DMA_DMACTRL_RESET_MASK;
}
 
static inline hpm_stat_t dma_enable_channel(DMA_Type *ptr, uint32_t ch_index)
{
    ptr->CHCTRL[ch_index].CTRL |= DMA_CHCTRL_CTRL_ENABLE_MASK;
 
    if ((ptr->CHEN == 0) || !(ptr->CHEN & 1 << ch_index)) {
        return status_fail;
    }
    return status_success;
}
 
static inline void dma_disable_channel(DMA_Type *ptr, uint32_t ch_index)
{
    ptr->CHCTRL[ch_index].CTRL &= ~DMA_CHCTRL_CTRL_ENABLE_MASK;
}
 
static inline bool dma_channel_is_enable(DMA_Type *ptr, uint32_t ch_index)
{
    return (ptr->CHCTRL[ch_index].CTRL & DMA_CHCTRL_CTRL_ENABLE_MASK) ? true : false;
}
 
static inline void dma_set_priority(DMA_Type *ptr, uint32_t ch_index, uint8_t priority)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_PRIORITY_MASK) | DMA_CHCTRL_CTRL_PRIORITY_SET(priority);
}
 
static inline void dma_set_source_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCMODE_MASK) | DMA_CHCTRL_CTRL_SRCMODE_SET(mode);
}
 
static inline void dma_set_destination_work_mode(DMA_Type *ptr, uint32_t ch_index, uint8_t mode)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTMODE_MASK) | DMA_CHCTRL_CTRL_DSTMODE_SET(mode);
}
 
static inline void dma_set_source_burst_size(DMA_Type *ptr, uint32_t ch_index, uint8_t burstsize)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCBURSTSIZE_MASK) | DMA_CHCTRL_CTRL_SRCBURSTSIZE_SET(burstsize);
}
 
static inline uint32_t dma_get_remaining_transfer_size(DMA_Type *ptr, uint32_t ch_index)
{
    return ptr->CHCTRL[ch_index].TRANSIZE;
}
 
static inline void dma_set_transfer_size(DMA_Type *ptr, uint32_t ch_index, uint32_t size_in_width)
{
    ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_width);
}
 
static inline void dma_set_source_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCWIDTH_MASK) | DMA_CHCTRL_CTRL_SRCWIDTH_SET(width);
}
 
static inline void dma_set_destination_width(DMA_Type *ptr, uint32_t ch_index, uint8_t width)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTWIDTH_MASK) | DMA_CHCTRL_CTRL_DSTWIDTH_SET(width);
}
 
static inline void dma_set_transfer_src_width_byte_size(DMA_Type *ptr, uint32_t ch_index, uint8_t src_width, uint32_t size_in_byte)
{
    assert((src_width == DMA_TRANSFER_WIDTH_BYTE) || (src_width == DMA_TRANSFER_WIDTH_HALF_WORD)
        || (src_width == DMA_TRANSFER_WIDTH_WORD) || (src_width == DMA_TRANSFER_WIDTH_DOUBLE_WORD));
 
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCWIDTH_MASK) | DMA_CHCTRL_CTRL_SRCWIDTH_SET(src_width);
    ptr->CHCTRL[ch_index].TRANSIZE = DMA_CHCTRL_TRANSIZE_TRANSIZE_SET(size_in_byte >> src_width);
}
 
static inline void dma_set_source_address(DMA_Type *ptr, uint32_t ch_index, uint32_t addr)
{
    ptr->CHCTRL[ch_index].SRCADDR = addr;
}
 
static inline void dma_set_destination_address(DMA_Type *ptr, uint32_t ch_index, uint32_t addr)
{
    ptr->CHCTRL[ch_index].DSTADDR = addr;
}
 
static inline void dma_set_source_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_SRCADDRCTRL_MASK) | DMA_CHCTRL_CTRL_SRCADDRCTRL_SET(addr_ctrl);
}
 
static inline void dma_set_destination_address_ctrl(DMA_Type *ptr, uint32_t ch_index, uint8_t addr_ctrl)
{
    ptr->CHCTRL[ch_index].CTRL = (ptr->CHCTRL[ch_index].CTRL & ~DMA_CHCTRL_CTRL_DSTADDRCTRL_MASK) | DMA_CHCTRL_CTRL_DSTADDRCTRL_SET(addr_ctrl);
}
 
static inline void dma_abort_channel(DMA_Type *ptr, uint32_t ch_index_mask)
{
    ptr->CHABORT |= DMA_CHABORT_CHABORT_SET(ch_index_mask);
}
 
static inline uint32_t dma_check_enabled_channel(DMA_Type *ptr,
                                                  uint32_t ch_index_mask)
{
    return (ch_index_mask & ptr->CHEN);
}
 
static inline bool dma_has_linked_pointer_configured(DMA_Type *ptr, uint32_t ch_index)
{
    return ptr->CHCTRL[ch_index].LLPOINTER != 0;
}
 
static inline uint32_t dma_check_transfer_status(DMA_Type *ptr, uint8_t ch_index)
{
    volatile uint32_t tmp = ptr->INTSTATUS;
    volatile uint32_t tmp_channel;
    uint32_t dma_status;
 
    dma_status = 0;
    tmp_channel = tmp & (1 << (DMA_STATUS_TC_SHIFT + ch_index));
    if (tmp_channel) {
        dma_status |= DMA_CHANNEL_STATUS_TC;
        ptr->INTSTATUS = tmp_channel;
    }
    tmp_channel = tmp & (1 << (DMA_STATUS_ERROR_SHIFT + ch_index));
    if (tmp_channel) {
        dma_status |= DMA_CHANNEL_STATUS_ERROR;
        ptr->INTSTATUS = tmp_channel;
    }
    tmp_channel = tmp & (1 << (DMA_STATUS_ABORT_SHIFT + ch_index));
    if (tmp_channel) {
        dma_status |= DMA_CHANNEL_STATUS_ABORT;
        ptr->INTSTATUS = tmp_channel;
    }
    if (dma_status == 0) {
        dma_status = DMA_CHANNEL_STATUS_ONGOING;
    }
    return dma_status;
}
 
static inline void dma_clear_transfer_status(DMA_Type *ptr, uint8_t ch_index)
{
    ptr->INTSTATUS = ((1 << (DMA_STATUS_TC_SHIFT + ch_index)) | (1 << (DMA_STATUS_ERROR_SHIFT + ch_index)) | (1 << (DMA_STATUS_ABORT_SHIFT + ch_index)));
}
 
static inline void dma_enable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask)
{
    ptr->CHCTRL[ch_index].CTRL &= ~(interrupt_mask & DMA_INTERRUPT_MASK_ALL);
}
 
static inline void dma_disable_channel_interrupt(DMA_Type *ptr, uint8_t ch_index, int32_t interrupt_mask)
{
    ptr->CHCTRL[ch_index].CTRL |= (interrupt_mask & DMA_INTERRUPT_MASK_ALL);
}
 
 
static inline uint32_t dma_check_channel_interrupt_mask(DMA_Type *ptr, uint8_t ch_index)
{
    return ptr->CHCTRL[ch_index].CTRL & DMA_INTERRUPT_MASK_ALL;
}
 
static inline void dma_clear_irq_status(DMA_Type *ptr, uint32_t mask)
{
    ptr->INTSTATUS = mask; /* Write-1-Clear */
}
 
static inline uint32_t dma_get_irq_status(DMA_Type *ptr)
{
    return ptr->INTSTATUS;
}
 
void dma_default_channel_config(DMA_Type *ptr, dma_channel_config_t *ch);
 
hpm_stat_t dma_setup_channel(DMA_Type *ptr, uint8_t ch_num,
                            dma_channel_config_t *ch, bool start_transfer);
 
hpm_stat_t dma_config_linked_descriptor(DMA_Type *ptr, dma_linked_descriptor_t *descriptor, uint8_t ch_num, dma_channel_config_t *config);
 
hpm_stat_t dma_start_memcpy(DMA_Type *ptr, uint8_t ch_num,
                               uint32_t dst, uint32_t src,
                               uint32_t size_in_byte, uint32_t burst_len_in_byte);
 
void dma_default_handshake_config(DMA_Type *ptr, dma_handshake_config_t *config);
 
hpm_stat_t dma_setup_handshake(DMA_Type *ptr,  dma_handshake_config_t *pconfig, bool start_transfer);
 
 
#if defined(DMA_SOC_HAS_IDLE_FLAG) && (DMA_SOC_HAS_IDLE_FLAG == 1)
static inline bool dma_is_idle(DMA_Type *ptr)
{
    return ((ptr->IDMISC & DMA_IDMISC_IDLE_FLAG_MASK) != 0U);
}
#endif
 
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_DMAV1_DRV_H */