hpm_dma_mgr.h

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/*
 * Copyright (c) 2022-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_DMA_MGR_H
#define HPM_DMA_MGR_H
 
#include "hpm_common.h"
#include "hpm_dmamux_drv.h"
#include "hpm_dmamux_src.h"
#ifdef HPMSOC_HAS_HPMSDK_DMAV2
#include "hpm_dmav2_drv.h"
#else
#include "hpm_dma_drv.h"
#endif
#include "hpm_soc_feature.h"
 
#ifdef HPMSOC_HAS_HPMSDK_DMAV2
#define DMA_MGR_HAS_INFINITE_LOOP        (1U)
#define DMA_MGR_HAS_HALF_TC_INT          (1U)
#define DMA_MGR_HAS_HANDSHAKE_OPT        (1U)
#define DMA_MGR_HAS_BURST_OPT            (1U)
#if defined(HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS) && (HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS == 1)
#define DMA_MGR_HAS_BURST_IN_FIXED_TRANS HPM_IP_FEATURE_DMAV2_BURST_IN_FIXED_TRANS
#else
#define DMA_MGR_HAS_BURST_IN_FIXED_TRANS 0
#endif
#if defined(HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP) && (HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP == 1)
#define DMA_MGR_HAS_BYTE_ORDER_SWAP HPM_IP_FEATURE_DMAV2_BYTE_ORDER_SWAP
#else
#define DMA_MGR_HAS_BYTE_ORDER_SWAP 0
#endif
#endif
 
#define DMA_MGR_CHANNEL_PRIORITY_LOW  DMA_CHANNEL_PRIORITY_LOW
#define DMA_MGR_CHANNEL_PRIORITY_HIGH DMA_CHANNEL_PRIORITY_HIGH
 
#define DMA_MGR_NUM_TRANSFER_PER_BURST_1T    DMA_NUM_TRANSFER_PER_BURST_1T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_2T    DMA_NUM_TRANSFER_PER_BURST_2T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_4T    DMA_NUM_TRANSFER_PER_BURST_4T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_8T    DMA_NUM_TRANSFER_PER_BURST_8T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_16T   DMA_NUM_TRANSFER_PER_BURST_16T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_32T   DMA_NUM_TRANSFER_PER_BURST_32T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_64T   DMA_NUM_TRANSFER_PER_BURST_64T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_128T  DMA_NUM_TRANSFER_PER_BURST_128T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_256T  DMA_NUM_TRANSFER_PER_BURST_256T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_512T  DMA_NUM_TRANSFER_PER_BURST_512T
#define DMA_MGR_NUM_TRANSFER_PER_BURST_1024T DMA_NUM_TRANSFER_PER_BURST_1024T
 
#define DMA_MGR_TRANSFER_WIDTH_BYTE        DMA_TRANSFER_WIDTH_BYTE
#define DMA_MGR_TRANSFER_WIDTH_HALF_WORD   DMA_TRANSFER_WIDTH_HALF_WORD
#define DMA_MGR_TRANSFER_WIDTH_WORD        DMA_TRANSFER_WIDTH_WORD
#define DMA_MGR_TRANSFER_WIDTH_DOUBLE_WORD DMA_TRANSFER_WIDTH_DOUBLE_WORD
 
#define DMA_MGR_HANDSHAKE_MODE_NORMAL    DMA_HANDSHAKE_MODE_NORMAL
#define DMA_MGR_HANDSHAKE_MODE_HANDSHAKE DMA_HANDSHAKE_MODE_HANDSHAKE
 
#define DMA_MGR_ADDRESS_CONTROL_INCREMENT DMA_ADDRESS_CONTROL_INCREMENT
#define DMA_MGR_ADDRESS_CONTROL_DECREMENT DMA_ADDRESS_CONTROL_DECREMENT
#define DMA_MGR_ADDRESS_CONTROL_FIXED     DMA_ADDRESS_CONTROL_FIXED
 
#if defined(DMA_MGR_HAS_BURST_OPT) && DMA_MGR_HAS_BURST_OPT
#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE DMA_SRC_BURST_OPT_STANDAND_SIZE
#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE   DMA_SRC_BURST_OPT_CUSTOM_SIZE
#else
#define DMA_MGR_SRC_BURST_OPT_STANDAND_SIZE 0
#define DMA_MGR_SRC_BURST_OPT_CUSTOM_SIZE   0
#endif
 
#if defined(DMA_MGR_HAS_HANDSHAKE_OPT) && DMA_MGR_HAS_HANDSHAKE_OPT
#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST    DMA_HANDSHAKE_OPT_ONE_BURST
#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE DMA_HANDSHAKE_OPT_ALL_TRANSIZE
#else
#define DMA_MGR_HANDSHAKE_OPT_ONE_BURST    0
#define DMA_MGR_HANDSHAKE_OPT_ALL_TRANSIZE 0
#endif
 
#define DMA_MGR_CHANNEL_STATUS_ONGOING DMA_CHANNEL_STATUS_ONGOING
#define DMA_MGR_CHANNEL_STATUS_ERROR   DMA_CHANNEL_STATUS_ERROR
#define DMA_MGR_CHANNEL_STATUS_ABORT   DMA_CHANNEL_STATUS_ABORT
#define DMA_MGR_CHANNEL_STATUS_TC      DMA_CHANNEL_STATUS_TC
#if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT
#define DMA_MGR_CHANNEL_STATUS_HALF_TC DMA_CHANNEL_STATUS_HALF_TC
#else
#define DMA_MGR_CHANNEL_STATUS_HALF_TC 0
#endif
#define DMA_MGR_INTERRUPT_MASK_NONE  DMA_INTERRUPT_MASK_NONE
#define DMA_MGR_INTERRUPT_MASK_ERROR DMA_INTERRUPT_MASK_ERROR
#define DMA_MGR_INTERRUPT_MASK_ABORT DMA_INTERRUPT_MASK_ABORT
#define DMA_MGR_INTERRUPT_MASK_TC    DMA_INTERRUPT_MASK_TERMINAL_COUNT
#if defined(DMA_MGR_HAS_HALF_TC_INT) && DMA_MGR_HAS_HALF_TC_INT
#define DMA_MGR_INTERRUPT_MASK_HALF_TC DMA_INTERRUPT_MASK_HALF_TC
#else
#define DMA_MGR_INTERRUPT_MASK_HALF_TC 0
#endif
#define DMA_MGR_INTERRUPT_MASK_ALL DMA_INTERRUPT_MASK_ALL
 
#if defined(DMA_MGR_HAS_BYTE_ORDER_SWAP) && DMA_MGR_HAS_BYTE_ORDER_SWAP
#define DMA_MGR_SWAP_MODE_TABLE     DMA_SWAP_MODE_TABLE
#define DMA_MGR_SWAP_MODE_BYTE      DMA_SWAP_MODE_BYTE
#define DMA_MGR_SWAP_MODE_HALF_WORD DMA_SWAP_MODE_HALF_WORD
#define DMA_MGR_SWAP_MODE_WORD      DMA_SWAP_MODE_WORD
#else
#define DMA_MGR_SWAP_MODE_TABLE     0
#define DMA_MGR_SWAP_MODE_BYTE      0
#define DMA_MGR_SWAP_MODE_HALF_WORD 0
#define DMA_MGR_SWAP_MODE_WORD      0
#endif
 
#ifdef __cplusplus
 
extern "C" {
#endif
 
enum {
    status_dma_mgr_no_resource = MAKE_STATUS(status_group_dma_manager, 0), 
};
 
typedef void (*dma_mgr_chn_cb_t)(DMA_Type *base, uint32_t channel, void *cb_data_ptr);
 
typedef struct _dma_resource {
    DMA_Type *base;   
    uint32_t channel; 
    int32_t irq_num;  
} dma_resource_t;
 
typedef struct hpm_dma_mgr_chn_conf {
    bool en_dmamux;                   
    uint8_t dmamux_src;               
    uint8_t priority;                 
    uint8_t src_burst_size;           
    uint8_t src_mode;                 
    uint8_t dst_mode;                 
    uint8_t src_width;                
    uint8_t dst_width;                
    uint8_t src_addr_ctrl;            
    uint8_t dst_addr_ctrl;            
    uint16_t interrupt_mask;          
    uint32_t src_addr;                
    uint32_t dst_addr;                
    uint32_t linked_ptr;              
    uint32_t size_in_byte;            
    bool en_infiniteloop;             
    uint8_t handshake_opt;            
    uint8_t burst_opt;                
    bool en_src_burst_in_fixed_trans; 
    bool en_dst_burst_in_fixed_trans; 
    uint8_t swap_mode;                
    uint32_t swap_table;              
} dma_mgr_chn_conf_t;
 
typedef struct hpm_dma_mgr_linked_descriptor {
    uint32_t descriptor[8];
} dma_mgr_linked_descriptor_t;
 
void dma_mgr_isr_handler(DMA_Type *ptr, uint32_t instance);
 
void dma_mgr_init(void);
 
hpm_stat_t dma_mgr_request_resource(dma_resource_t *resource);
 
hpm_stat_t dma_mgr_release_resource(const dma_resource_t *resource);
 
hpm_stat_t dma_mgr_enable_dma_irq_with_priority(const dma_resource_t *resource, uint32_t priority);
 
hpm_stat_t dma_mgr_disable_dma_irq(const dma_resource_t *resource);
 
hpm_stat_t dma_mgr_install_chn_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data);
 
hpm_stat_t dma_mgr_install_chn_half_tc_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data);
 
hpm_stat_t dma_mgr_install_chn_error_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data);
 
hpm_stat_t dma_mgr_install_chn_abort_callback(const dma_resource_t *resource, dma_mgr_chn_cb_t callback, void *user_data);
 
void dma_mgr_get_default_chn_config(dma_mgr_chn_conf_t *config);
 
hpm_stat_t dma_mgr_setup_channel(const dma_resource_t *resource, dma_mgr_chn_conf_t *config);
 
hpm_stat_t dma_mgr_config_linked_descriptor(const dma_resource_t *resource, dma_mgr_chn_conf_t *config, dma_mgr_linked_descriptor_t *descriptor);
 
hpm_stat_t dma_mgr_enable_channel(const dma_resource_t *resource);
 
hpm_stat_t dma_mgr_disable_channel(const dma_resource_t *resource);
 
hpm_stat_t dma_mgr_check_chn_enable(const dma_resource_t *resource, bool *enable);
 
hpm_stat_t dma_mgr_enable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask);
 
hpm_stat_t dma_mgr_disable_chn_irq(const dma_resource_t *resource, uint32_t irq_mask);
 
hpm_stat_t dma_mgr_set_chn_priority(const dma_resource_t *resource, uint8_t priority);
 
hpm_stat_t dma_mgr_set_chn_src_work_mode(const dma_resource_t *resource, uint8_t mode);
 
hpm_stat_t dma_mgr_set_chn_dst_work_mode(const dma_resource_t *resource, uint8_t mode);
 
hpm_stat_t dma_mgr_set_chn_src_burst_size(const dma_resource_t *resource, uint8_t burstsize);
 
hpm_stat_t dma_mgr_get_chn_remaining_transize(const dma_resource_t *resource, uint32_t *size);
 
hpm_stat_t dma_mgr_set_chn_transize(const dma_resource_t *resource, uint32_t size);
 
hpm_stat_t dma_mgr_set_chn_src_width(const dma_resource_t *resource, uint8_t width);
 
hpm_stat_t dma_mgr_set_chn_dst_width(const dma_resource_t *resource, uint8_t width);
 
hpm_stat_t dma_mgr_set_chn_src_addr(const dma_resource_t *resource, uint32_t addr);
 
hpm_stat_t dma_mgr_set_chn_dst_addr(const dma_resource_t *resource, uint32_t addr);
 
hpm_stat_t dma_mgr_set_chn_src_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl);
 
hpm_stat_t dma_mgr_set_chn_dst_addr_ctrl(const dma_resource_t *resource, uint8_t addr_ctrl);
 
hpm_stat_t dma_mgr_set_chn_infinite_loop_mode(const dma_resource_t *resource, bool infinite_loop);
 
hpm_stat_t dma_mgr_set_chn_src_busrt_option(const dma_resource_t *resource, uint8_t burst_opt);
 
hpm_stat_t dma_mgr_set_chn_handshake_option(const dma_resource_t *resource, uint8_t handshake_opt);
 
hpm_stat_t dma_mgr_abort_chn_transfer(const dma_resource_t *resource);
 
hpm_stat_t dma_mgr_check_chn_transfer_status(const dma_resource_t *resource, uint32_t *status);
 
hpm_stat_t dma_mgr_set_source_burst_in_fixed_transize_enable(const dma_resource_t *resource, bool enable);
 
hpm_stat_t dma_mgr_set_destination_burst_in_fix_transize_enable(const dma_resource_t *resource, bool enable);
 
hpm_stat_t dma_mgr_set_swap_mode(const dma_resource_t *resource, uint8_t swap_mode);
 
hpm_stat_t dma_mgr_set_swap_table(const dma_resource_t *resource, uint32_t swap_table);
 
#ifdef __cplusplus
}
#endif
 
#endif /* HPM_DMA_MGR_H */