hpm_mcan_drv.h

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/*
 * Copyright (c) 2023-2024 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
#ifndef HPM_MCAN_DRV_H
#define HPM_MCAN_DRV_H
 
#include "hpm_common.h"
#include "hpm_mcan_regs.h"
#include "hpm_mcan_soc.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
enum {
    status_mcan_filter_index_out_of_range = MAKE_STATUS(status_group_mcan, 0),
    status_mcan_rxfifo_empty = MAKE_STATUS(status_group_mcan, 1),
    status_mcan_rxfifo_full = MAKE_STATUS(status_group_mcan, 2),
    status_mcan_txbuf_full = MAKE_STATUS(status_group_mcan, 3),
    status_mcan_txfifo_full = MAKE_STATUS(status_group_mcan, 4),
    status_mcan_rxfifo0_busy = MAKE_STATUS(status_group_mcan, 5),
    status_mcan_rxfifo1_busy = MAKE_STATUS(status_group_mcan, 6),
    status_mcan_txbuf_index_out_of_range = MAKE_STATUS(status_group_mcan, 7),
    status_mcan_rxbuf_index_out_of_range = MAKE_STATUS(status_group_mcan, 8),
    status_mcan_rxbuf_empty = MAKE_STATUS(status_group_mcan, 9),
    status_mcan_tx_evt_fifo_empty = MAKE_STATUS(status_group_mcan, 10),
    status_mcan_timestamp_not_exist = MAKE_STATUS(status_group_mcan, 11),
    status_mcan_ram_out_of_range = MAKE_STATUS(status_group_mcan, 12),
    status_mcan_timeout = MAKE_STATUS(status_group_mcan, 13),
    status_mcan_invalid_bit_timing = MAKE_STATUS(status_group_mcan, 14),
};
 
#define MCAN_INT_ACCESS_TO_RESERVED_ADDR    MCAN_IR_ARA_MASK     
#define MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE MCAN_IR_PED_MASK     
#define MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE  MCAN_IR_PEA_MASK     
#define MCAN_INT_WATCHDOG_INT               MCAN_IR_WDI_MASK     
#define MCAN_INT_BUS_OFF_STATUS             MCAN_IR_BO_MASK      
#define MCAN_INT_WARNING_STATUS             MCAN_IR_EW_MASK      
#define MCAN_INT_ERROR_PASSIVE              MCAN_IR_EP_MASK      
#define MCAN_INT_ERROR_LOGGING_OVERFLOW     MCAN_IR_ELO_MASK     
#define MCAN_INT_BIT_ERROR_UNCORRECTED      MCAN_IR_BEU_MASK     
#define MCAN_INT_BIT_ERROR_CORRECTED        MCAN_IR_BEC_MASK     
#define MCAN_INT_MSG_STORE_TO_RXBUF         MCAN_IR_DRX_MASK    
#define MCAN_INT_TIMEOUT_OCCURRED           MCAN_IR_TOO_MASK    
#define MCAN_INT_MSG_RAM_ACCESS_FAILURE     MCAN_IR_MRAF_MASK   
#define MCAN_INT_TIMESTAMP_WRAPAROUND       MCAN_IR_TSW_MASK    
#define MCAN_INT_TX_EVT_FIFO_EVT_LOST       MCAN_IR_TEFL_MASK   
#define MCAN_INT_TX_EVT_FIFO_FULL           MCAN_IR_TEFF_MASK   
#define MCAN_INT_TX_EVT_FIFO_WMK_REACHED    MCAN_IR_TEFW_MASK   
#define MCAN_INT_TX_EVT_FIFO_NEW_ENTRY      MCAN_IR_TEFN_MASK   
#define MCAN_INT_TXFIFO_EMPTY               MCAN_IR_TFE_MASK    
#define MCAN_INT_TX_CANCEL_FINISHED         MCAN_IR_TCF_MASK    
#define MCAN_INT_TX_COMPLETED               MCAN_IR_TC_MASK     
#define MCAN_INT_HIGH_PRIORITY_MSG          MCAN_IR_HPM_MASK    
#define MCAN_INT_RXFIFO1_MSG_LOST           MCAN_IR_RF1L_MASK   
#define MCAN_INT_RXFIFO1_FULL               MCAN_IR_RF1F_MASK   
#define MCAN_INT_RXFIFO1_WMK_REACHED        MCAN_IR_RF1W_MASK   
#define MCAN_INT_RXFIFO1_NEW_MSG            MCAN_IR_RF1N_MASK   
#define MCAN_INT_RXFIFO0_MSG_LOST           MCAN_IR_RF0L_MASK   
#define MCAN_INT_RXFIFO0_FULL               MCAN_IR_RF0F_MASK   
#define MCAN_INT_RXFIFO0_WMK_REACHED        MCAN_IR_RF0W_MASK   
#define MCAN_INT_RXFIFO0_NEW_MSG            MCAN_IR_RF0N_MASK   
#define MCAN_EVENT_RECEIVE (MCAN_INT_RXFIFO0_NEW_MSG | MCAN_INT_RXFIFO1_NEW_MSG | MCAN_INT_MSG_STORE_TO_RXBUF)
 
#define MCAN_EVENT_TRANSMIT (MCAN_INT_TX_COMPLETED)
#define MCAN_EVENT_ERROR (MCAN_INT_BUS_OFF_STATUS | MCAN_INT_WARNING_STATUS \
                        | MCAN_INT_ERROR_PASSIVE | MCAN_INT_BIT_ERROR_UNCORRECTED \
                        | MCAN_INT_PROTOCOL_ERR_IN_DATA_PHASE | MCAN_INT_PROTOCOL_ERR_IN_ARB_PHASE)
 
#define MCAN_TX_RETRY_COUNT_MAX (10000000UL)
#define MCAN_RX_RETRY_COUNT_MAX (80000000UL)
 
typedef enum mcan_last_error_code {
    mcan_last_error_code_no_error = 0,      
    mcan_last_error_code_stuff_error,       
    mcan_last_error_code_format_error,      
    mcan_last_error_code_ack_error,         
    mcan_last_error_code_bit1_error,        
    mcan_last_error_code_bit0_error,        
    mcan_last_error_code_crc_error,         
    mcan_last_error_code_no_change,         
} mcan_last_err_code_t;
 
typedef enum mcan_activity_enum {
    mcan_activity_sync = 0,                 
    mcan_activity_idle,                     
    mcan_activity_receiver,                 
    mcan_activity_transmitter,              
} mcan_activity_state_t;
 
/***********************************************************************************************************************
 * @brief Default CAN RAM definitions
 **********************************************************************************************************************/
#define MCAN_RAM_WORD_SIZE  (640U)                                  
/* CAN Filter Element Size Definitions */
#define MCAN_FILTER_ELEM_STD_ID_SIZE (4U)                           
#define MCAN_FILTER_ELEM_EXT_ID_SIZE (8U)                           
#define MCAN_STD_FILTER_ELEM_SIZE_MAX (128U)                        
#define MCAN_EXT_FILTER_ELEM_SIZE_MAX  (64U)                        
/* MCAN Default Field Size Definitions for CAN2.0 */
#define MCAN_TXRX_ELEM_SIZE_CAN_MAX (4U * sizeof(uint32_t))
#define MCAN_FILTER_SIZE_CAN_DEFAULT (32U)
#define MCAN_TXBUF_SIZE_CAN_DEFAULT (32U)
#define MCAN_RXFIFO_SIZE_CAN_DEFAULT (32U)
#define MCAN_RXBUF_SIZE_CAN_DEFAULT (16U)
/* MCAN Default Field Size Definitions for CANFD */
#define MCAN_TXRX_ELEM_SIZE_CANFD_MAX (18U * sizeof(uint32_t))
#define MCAN_FILTER_SIZE_CANFD_DEFAULT (16U)
#define MCAN_TXBUF_SIZE_CANFD_DEFAULT (8U)
#define MCAN_RXFIFO_SIZE_CANFD_DEFAULT (8U)
#define MCAN_RXBUF_SIZE_CANFD_DEFAULT (4U)
 
#define MCAN_TXEVT_ELEM_SIZE (8U)
 
typedef struct mcan_bit_timing_param_struct {
    uint16_t prescaler; 
    uint16_t num_seg1;  
    uint16_t num_seg2;  
    uint8_t num_sjw;    
    bool enable_tdc;    
} mcan_bit_timing_param_t;
 
typedef enum mcan_bit_timing_option {
    mcan_bit_timing_can2_0,          
    mcan_bit_timing_canfd_nominal,   
    mcan_bit_timing_canfd_data,      
} mcan_bit_timing_option_t;
 
#define MCAN_MESSAGE_HEADER_SIZE_IN_BYTES (8U)
#define MCAN_MESSAGE_HEADER_SIZE_IN_WORDS (2U)
 
typedef struct mcan_tx_message_struct {
    union {
        struct {
            uint32_t ext_id: 29;                        
            uint32_t rtr: 1;                            
            uint32_t use_ext_id: 1;                     
            uint32_t error_state_indicator: 1;          
        };
        struct {
            uint32_t : 18;
            uint32_t std_id: 11;                        
            uint32_t : 3;
        };
    };
    struct {
        uint32_t : 8;
        uint32_t message_marker_h: 8;                   
        uint32_t dlc: 4;                                
        uint32_t bitrate_switch: 1;                     
        uint32_t canfd_frame: 1;                        
        uint32_t timestamp_capture_enable: 1;           
        uint32_t event_fifo_control: 1;                 
        uint32_t message_marker_l: 8;                   
    };
    union {
        uint8_t data_8[64];                             
        uint32_t data_32[16];                           
    };
} mcan_tx_frame_t;
 
typedef struct mcan_rx_message_struct {
    union {
        struct {
            uint32_t ext_id: 29;                   
            uint32_t rtr: 1;                       
            uint32_t use_ext_id: 1;                
            uint32_t error_state_indicator: 1;     
        };
        struct {
            uint32_t : 18;
            uint32_t std_id: 11;                   
            uint32_t : 3;
        };
    };
    struct {
        union {
            uint16_t rx_timestamp;                  
            struct {
                uint16_t rx_timestamp_pointer: 4;   
                uint16_t rx_timestamp_captured: 1;  
                uint16_t : 11;
            };
        };
    };
    struct {
        uint16_t dlc: 4;                            
        uint16_t bitrate_switch: 1;                 
        uint16_t canfd_frame: 1;                    
        uint16_t : 2;
        uint16_t filter_index: 7;                   
        uint16_t accepted_non_matching_frame: 1;    
    };
    union {
        uint8_t data_8[64];                         
        uint32_t data_32[16];                       
    };
} mcan_rx_message_t;
 
typedef union mcan_tx_event_fifo_elem_struct {
    struct {
        /* First word */
        union {
            struct {
                uint32_t ext_id: 29;                    
                uint32_t rtr: 1;                        
                uint32_t extend_id: 1;                  
                uint32_t error_state_indicator: 1;      
            };
            struct {
                uint32_t : 18;
                uint32_t std_id: 11;
                uint32_t : 3;
            };
        };
 
        /* first 16-bit of the 2nd word */
        union {
            uint16_t tx_timestamp;                      
            struct {
                uint16_t tx_timestamp_pointer: 4;       
                uint16_t tx_timestamp_captured: 1;      
                uint16_t : 11;
            };
        };
        /* high-half 16-bit of the 2nd word */
        struct {
            uint16_t dlc: 4;                            
            uint16_t bitrate_switch: 1;                 
            uint16_t canfd_frame: 1;                    
            uint16_t event_type: 2;                     
            uint16_t message_marker: 8;                 
        };
    };
    uint32_t words[2];
} mcan_tx_event_fifo_elem_t;
 
 
 
#define MCAN_CAN_ID_TYPE_STANDARD (0U)      
#define MCAN_CAN_ID_TYPE_EXTENDED (1U)      
typedef union mcan_filter_config_struct {
    struct {
        uint16_t list_start_addr;       
        uint16_t list_size;             
    };
    uint32_t reg_val;                   
} mcan_filter_config_t;
 
typedef union mcan_rxfifo_config_struct {
    struct {
        uint32_t start_addr: 16;        
        uint32_t fifo_size: 8;          
        uint32_t watermark: 7;          
        uint32_t operation_mode: 1;     
    };
    uint32_t reg_val;                   
} mcan_rxfifo_config_t;
 
typedef struct {
    uint32_t start_addr;                
} mcan_rxbuf_config_t;
 
#define MCAN_DATA_FIELD_SIZE_8BYTES     (0U)
#define MCAN_DATA_FIELD_SIZE_12BYTES    (1U)
#define MCAN_DATA_FIELD_SIZE_16BYTES    (2U)
#define MCAN_DATA_FIELD_SIZE_20BYTES    (3U)
#define MCAN_DATA_FIELD_SIZE_24BYTES    (4U)
#define MCAN_DATA_FIELD_SIZE_32BYTES    (5U)
#define MCAN_DATA_FIELD_SIZE_48BYTES    (6U)
#define MCAN_DATA_FIELD_SIZE_64BYTES    (7U)
 
#define MCAN_FIFO_OPERATION_MODE_BLOCKING (0U)
#define MCAN_FIFO_OPERATION_MODE_OVERWRITE (1U)
 
typedef union mcan_rx_fifo_or_buf_elem_config_struct {
    struct {
        uint32_t fifo0_data_field_size: 4;      
        uint32_t fifo1_data_field_size: 4;      
        uint32_t buf_data_field_size: 4;        
        uint32_t : 20;
    };
    uint32_t reg_val;                           
} mcan_rx_fifo_or_buf_elem_config_t;
 
#define MCAN_TXBUF_OPERATION_MODE_FIFO  (0U)
#define MCAN_TXBUF_OPERATION_MODE_QUEUE (1U)
 
 
typedef union mcan_txbuf_config_struct {
    struct {
        uint32_t start_addr: 16;                
        uint32_t dedicated_tx_buf_size: 6;      
        uint32_t : 2;
        uint32_t fifo_queue_size: 6;            
        uint32_t tx_fifo_queue_mode: 1;         
        uint32_t : 1;
    };
    uint32_t reg_val;                           
} mcan_txbuf_config_t;
 
typedef struct mcan_txbuf_elem_config_struct {
    uint32_t data_field_size;                   
} mcan_txbuf_elem_config_t;
 
typedef union {
    struct {
        uint16_t start_addr;                    
        uint8_t fifo_size;                      
        uint8_t fifo_watermark;                 
    };
    uint32_t reg_val;                           
} mcan_tx_evt_fifo_config_t;
 
typedef struct mcan_ram_flexible_config_struct {
    bool enable_std_filter;                             
    bool enable_ext_filter;                             
    bool enable_rxfifo0;                                
    bool enable_rxfifo1;                                
    bool enable_rxbuf;                                  
    bool enable_txbuf;                                  
    bool enable_tx_evt_fifo;                            
    mcan_filter_config_t std_filter_config;             
    mcan_filter_config_t ext_filter_config;             
    mcan_txbuf_config_t txbuf_config;                   
    mcan_txbuf_elem_config_t txbuf_elem_config;         
    mcan_tx_evt_fifo_config_t tx_evt_fifo_config;       
    mcan_rxfifo_config_t rxfifo0_config;                
    mcan_rxfifo_config_t rxfifo1_config;                
    mcan_rxbuf_config_t rxbuf_config;                   
    mcan_rx_fifo_or_buf_elem_config_t rx_elem_config;   
} mcan_ram_flexible_config_t;
 
typedef struct mcan_ram_config_struct {
    bool enable_std_filter;                             
    uint8_t std_filter_elem_count;                      
    bool enable_ext_filter;                             
    uint8_t ext_filter_elem_count;                      
    struct {
        uint32_t enable: 4;                            
        uint32_t elem_count: 8;                        
        uint32_t watermark: 8;                         
        uint32_t operation_mode: 4;                    
        uint32_t data_field_size: 8;                   
    } rxfifos[2];
 
    bool enable_rxbuf;                                  
    uint8_t rxbuf_elem_count;                           
    uint16_t rxbuf_data_field_size;                     
    bool enable_txbuf;                                  
    uint8_t txbuf_data_field_size;                      
    uint8_t txbuf_dedicated_txbuf_elem_count;           
    uint8_t txbuf_fifo_or_queue_elem_count;             
    uint8_t txfifo_or_txqueue_mode;                     
    bool enable_tx_evt_fifo;                            
    uint8_t tx_evt_fifo_elem_count;                     
    uint8_t tx_evt_fifo_watermark;                      
} mcan_ram_config_t;
 
#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO0 (0U)   
#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_IN_RXFIFO1 (1U)   
#define MCAN_ACCEPT_NON_MATCHING_FRAME_OPTION_REJECT (2U)       
typedef struct mcan_global_filter_config_struct {
    uint8_t accept_non_matching_std_frame_option;   
    uint8_t accept_non_matching_ext_frame_option;   
    bool reject_remote_std_frame;                   
    bool reject_remote_ext_frame;                   
} mcan_global_filter_config_t;
 
#define MCAN_FILTER_TYPE_RANGE_FILTER (0U)              
#define MCAN_FILTER_TYPE_SPECIFIED_ID_FILTER (1U)       
#define MCAN_FILTER_TYPE_CLASSIC_FILTER (2U)            
#define MCAN_FILTER_TYPE_FILTER_DISABLED (3U)           
#define MCAN_FILTER_TYPE_DUAL_ID_EXT_FILTER_IGNORE_MASK 
#define MCAN_FILTER_ELEM_CFG_DISABLED (0)                                   
#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO0_IF_MATCH (1U)                
#define MCAN_FILTER_ELEM_CFG_STORE_IN_RX_FIFO1_IF_MATCH (2U)                
#define MCAN_FILTER_ELEM_CFG_REJECT_ID_IF_MATCH (3U)                        
#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_IF_MATCH (4U)                     
#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO0_IF_MATCH (5U)
#define MCAN_FILTER_ELEM_CFG_SET_PRIORITY_AND_STORE_IN_FIFO1_IF_MATCH (6U)
#define MCAN_FILTER_ELEM_CFG_STORE_INTO_RX_BUFFER_OR_AS_DBG_MSG (7U)        
typedef struct mcan_std_id_filter_elem_struct {
    uint8_t filter_type;            
    uint8_t filter_config;          
    uint8_t can_id_type;            
    uint8_t sync_message;           
    union {
        /* This definition takes effect if the filter type is range filter */
        struct {
            uint32_t start_id;      
            uint32_t end_id;        
        };
        /* This definition takes effect if the filter type is dual id filter */
        struct {
            uint32_t id1;           
            uint32_t id2;           
        };
        /* This definition takes effect if the filter type is classic filter */
        struct {
            uint32_t filter_id;     
            uint32_t filter_mask;   
        };
        /* This definition takes effect if the filter configuration is "store into RX Buffer or as debug message"
         *
         *  In this definition, only the exact ID matching mode is activated
         */
        struct {
            uint32_t match_id;          
            uint32_t offset: 6;         
            uint32_t filter_event: 3;   
            uint32_t store_location: 2; 
            uint32_t : 21;
        };
    };
} mcan_filter_elem_t;
 
typedef struct mcan_filter_elem_list_struct {
    uint32_t mcan_filter_elem_count;            
    const mcan_filter_elem_t *filter_elem_list; 
} mcan_filter_elem_list_t;
 
typedef struct mcan_all_filters_config_struct {
    mcan_global_filter_config_t global_filter_config;   
    uint32_t ext_id_mask;                               
    mcan_filter_elem_list_t std_id_filter_list;         
    mcan_filter_elem_list_t ext_id_filter_list;         
} mcan_all_filters_config_t;
 
typedef enum mcan_node_mode_enum {
    mcan_mode_normal = 0,               
    mcan_mode_loopback_internal = 1,    
    mcan_mode_loopback_external = 2,    
    mcan_mode_listen_only = 3,          
} mcan_node_mode_t;
 
typedef struct mcan_timestamp_value_struct {
    bool is_16bit;                  
    bool is_32bit;                  
    bool is_64bit;                  
    bool is_empty;                  
    union {
        uint16_t ts_16bit;          
        uint32_t ts_32bit;          
        uint64_t ts_64bit;          
        uint32_t words[2];          
    };
} mcan_timestamp_value_t;
 
typedef struct mcan_tsu_config_struct {
    uint16_t prescaler;             
    bool capture_on_sof;            
    bool use_ext_timebase;          
    uint8_t ext_timebase_src;       
    uint8_t tbsel_option;           
    bool enable_tsu;                
    bool enable_64bit_timestamp;    
} mcan_tsu_config_t;
 
#define MCAN_TIMESTAMP_SEL_MIN               (0U)
#define MCAN_TIMESTAMP_SEL_VALUE_ALWAYS_ZERO (0U)     
#define MCAN_TIMESTAMP_SEL_VALUE_INCREMENT   (1U)     
#define MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED   (2U)     
#define MCAN_TIMESTAMP_SEL_MAX               (MCAN_TIMESTAMP_SEL_EXT_TS_VAL_USED)
 
typedef struct mcan_internal_timestamp_config_struct {
    uint8_t counter_prescaler;          
    uint8_t timestamp_selection;        
} mcan_internal_timestamp_config_t;
 
typedef enum mcan_timeout_sel_enum {
    mcan_timeout_continuous_operation     = 0,  
    mcan_timeout_triggered_by_tx_evt_fifo = 1,  
    mcan_timeout_triggered_by_rx_fifo0    = 2,  
    mcan_timeout_triggered_by_rx_fifo1    = 3,  
} mcan_timeout_sel_t;
 
typedef struct mcan_timeout_config_struct {
    bool enable_timeout_counter;        
    mcan_timeout_sel_t timeout_sel;     
    uint16_t timeout_period;            
} mcan_timeout_config_t;
 
typedef struct mcan_tdc_config_t {
    uint8_t ssp_offset;                 
    uint8_t filter_window_length;       
} mcan_tdc_config_t;
 
 
typedef struct mcan_config_struct {
    union {
        /* This struct takes effect if "use_lowlevel_timing_setting = false" */
        struct {
            uint32_t baudrate;                      
            uint32_t baudrate_fd;                   
            uint16_t can20_samplepoint_min;         
            uint16_t can20_samplepoint_max;         
            uint16_t canfd_samplepoint_min;         
            uint16_t canfd_samplepoint_max;         
        };
        /* This struct takes effect if "use_lowlevel_timing_setting = true" */
        struct {
            mcan_bit_timing_param_t can_timing;     
            mcan_bit_timing_param_t canfd_timing;   
        };
    };
    bool use_lowlevel_timing_setting;               
    mcan_node_mode_t mode;                          
    bool enable_non_iso_mode;                       
    bool enable_transmit_pause;                     
    bool enable_edge_filtering;                     
    bool disable_protocol_exception_handling;       
    bool enable_wide_message_marker;                
    bool use_timestamping_unit;                     
    bool enable_canfd;                              
    bool enable_tdc;                                
    bool enable_restricted_operation_mode;          
    bool disable_auto_retransmission;               
    mcan_tdc_config_t tdc_config;                   
    mcan_internal_timestamp_config_t timestamp_cfg; 
    mcan_tsu_config_t tsu_config;                   
    mcan_ram_config_t ram_config;                   
    mcan_all_filters_config_t all_filters_config;   
    mcan_timeout_config_t timeout_cfg;              
    uint32_t interrupt_mask;                        
    uint32_t txbuf_trans_interrupt_mask;            
    uint32_t txbuf_cancel_finish_interrupt_mask;    
} mcan_config_t;
 
#define MCAN_TIMEOUT_SEL_TYPE_CONTINUOUS_OPERATION (0U)
#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_TX_EVT_FIFO (1U)
#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO0 (2U)
#define MCAN_TIMEOUT_SEL_TYPE_TIMEOUT_CTRL_BY_RX_FIFO1 (3U)
 
typedef struct mcan_timeout_counter_config_struct {
    bool enable_timeout_counter;            
    uint8_t timeout_selection;              
    uint16_t timeout_period;                
} mcan_timeout_counter_config_t;
 
typedef struct mcan_error_count_struct {
    uint8_t transmit_error_count;       
    uint8_t receive_error_count;        
    bool receive_error_passive;         
    uint8_t can_error_logging_count;    
} mcan_error_count_t;
 
typedef struct mcan_protocol_status {
    uint8_t tdc_val;                            
    mcan_activity_state_t activity;             
    mcan_last_err_code_t last_error_code;       
    bool protocol_exception_evt_occurred;       
    bool canfd_msg_received;                    
    bool brs_flag_set_in_last_rcv_canfd_msg;    
    bool esi_flag_set_in_last_rcv_canfd_msg;    
    bool in_bus_off_state;                      
    bool in_warning_state;                      
    bool in_error_passive_state;                
} mcan_protocol_status_t;
 
#define MCAN_MESSAGE_STORAGE_INDICATOR_NO_FIFO_SELECTED     (0U)
#define MCAN_MESSAGE_STORAGE_INDICATOR_FIFO_MESSAGE_LOST    (1U)
#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO0              (2U)
#define MCAN_MESSAGE_STORAGE_INDICATOR_RXFIFO1              (3U)
 
typedef struct mcan_high_priority_message_status_struct {
    uint8_t filter_list_type;                            
    uint8_t filter_index;                                
    uint8_t message_storage_indicator;                   
    uint8_t buffer_index;
} mcan_high_priority_message_status_t;
 
static inline void mcan_enable_transmit_pause(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_TXP_MASK;
}
 
static inline void mcan_disable_transmit_pause(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_TXP_MASK;
}
 
static inline void mcan_enable_edge_filtering(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_EFBI_MASK;
}
 
static inline void mcan_disable_edge_filtering(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_EFBI_MASK;
}
 
static inline void mcan_enable_protocol_exception_handling(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_PXHD_MASK;
}
 
static inline void mcan_disable_protocol_exception_handling(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_PXHD_MASK;
}
 
static inline void mcan_enable_wide_message_marker(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_WMM_MASK;
}
 
static inline void mcan_disable_wide_message_marker(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_WMM_MASK;
}
 
static inline void mcan_enable_tsu(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_UTSU_MASK;
}
 
static inline void mcan_disable_tsu(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_UTSU_MASK;
}
 
static inline bool mcan_is_tsu_used(MCAN_Type *ptr)
{
    return ((ptr->CCCR & MCAN_CCCR_UTSU_MASK) != 0U);
}
 
static inline bool mcan_is_64bit_tsu_timestamp_used(MCAN_Type *ptr)
{
    return ((ptr->TSCFG & MCAN_TSCFG_EN64_MASK) != 0U);
}
 
static inline void mcan_enable_bitrate_switch(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_BRSE_MASK;
}
 
static inline void mcan_disable_bitrate_switch(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_BRSE_MASK;
}
 
static inline void mcan_enable_auto_retransmission(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_DAR_MASK;
}
 
static inline void mcan_disable_auto_retransmission(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_DAR_MASK;
}
 
static inline void mcan_enable_bus_monitoring_mode(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_MON_MASK;
}
 
static inline void mcan_stop_clock(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_CSR_MASK;
}
 
static inline void mcan_enable_clock(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_CSR_MASK;
}
 
static inline bool mcan_is_clock_enabled(MCAN_Type *ptr)
{
    return ((ptr->CCCR & MCAN_CCCR_CSR_MASK) == 0UL);
}
 
static inline void mcan_disable_bus_monitoring_mode(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_MON_MASK;
}
 
static inline bool mcan_is_clock_stopped(MCAN_Type *ptr)
{
    return ((ptr->CCCR & MCAN_CCCR_CSA_MASK) != 0U);
}
 
static inline void mcan_enable_restricted_operation_mode(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_ASM_MASK;
}
 
static inline void mcan_disable_restricted_operation_mode(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_ASM_MASK;
}
 
static inline void mcan_enable_write_to_prot_config_registers(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_CCE_MASK;
}
 
static inline void mcan_disable_write_to_prot_config_registers(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_CCE_MASK;
}
 
static inline uint16_t mcan_get_timestamp_counter_value(MCAN_Type *ptr)
{
    return ptr->TSCV;
}
 
static inline void mcan_enter_init_mode(MCAN_Type *ptr)
{
    ptr->CCCR |= MCAN_CCCR_INIT_MASK;
}
 
static inline void mcan_enter_normal_mode(MCAN_Type *ptr)
{
    ptr->CCCR &= ~MCAN_CCCR_INIT_MASK;
}
 
static inline uint16_t mcan_get_timeout_counter_value(MCAN_Type *ptr)
{
    return ptr->TOCV;
}
 
static inline void mcan_reset_timeout_counter_value(MCAN_Type *ptr)
{
    *((volatile uint32_t *) &ptr->TOCV) = 0;
}
 
static inline void mcan_get_error_counter(MCAN_Type *ptr, mcan_error_count_t *err_cnt)
{
    uint32_t ecr = ptr->ECR;
    err_cnt->transmit_error_count = MCAN_ECR_TEC_GET(ecr);
    err_cnt->receive_error_count = MCAN_ECR_REC_GET(ecr);
    err_cnt->receive_error_passive = (MCAN_ECR_RP_GET(ecr) == 1U);
    err_cnt->can_error_logging_count = MCAN_ECR_CEL_GET(ecr);
}
 
static inline uint8_t mcan_get_last_error_code(MCAN_Type *ptr)
{
    return MCAN_PSR_LEC_GET(ptr->PSR);
}
 
static inline uint8_t mcan_get_last_data_error_code(MCAN_Type *ptr)
{
    return MCAN_PSR_DLEC_GET(ptr->PSR);
}
 
static inline uint8_t mcan_get_activity(MCAN_Type *ptr)
{
    return MCAN_PSR_ACT_GET(ptr->PSR);
}
 
static inline bool mcan_is_in_err_passive_state(MCAN_Type *ptr)
{
    return (MCAN_PSR_EP_GET(ptr->PSR) == 1U);
}
 
static inline bool mcan_is_in_error_warning_state(MCAN_Type *ptr)
{
    return (MCAN_PSR_EW_GET(ptr->PSR) == 1U);
}
 
static inline bool mcan_is_in_busoff_state(MCAN_Type *ptr)
{
    return (MCAN_PSR_BO_GET(ptr->PSR) == 1U);
}
 
static inline uint8_t mcan_get_data_phase_last_error_code(MCAN_Type *ptr)
{
    return MCAN_PSR_DLEC_GET(ptr->PSR);
}
 
static inline bool mcan_is_error_state_indicator_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr)
{
    return (MCAN_PSR_RESI_GET(ptr->PSR) == 1U);
}
 
static inline bool mcan_is_bitrate_switch_flag_set_in_last_received_canfd_msg(MCAN_Type *ptr)
{
    return (MCAN_PSR_RBRS_GET(ptr->PSR) == 1U);
}
 
static inline bool mcan_is_canfd_message_received(MCAN_Type *ptr)
{
    return (MCAN_PSR_RFDF_GET(ptr->PSR) == 1U);
}
 
static inline bool mcan_is_protocol_exception_event_occurred(MCAN_Type *ptr)
{
    return (MCAN_PSR_PXE_GET(ptr->PSR) == 1U);
}
 
static inline uint8_t mcan_get_transmitter_delay_compensation_value(MCAN_Type *ptr)
{
    return MCAN_PSR_TDCV_GET(ptr->PSR);
}
 
static inline uint32_t mcan_get_interrupt_flags(MCAN_Type *ptr)
{
    return ptr->IR;
}
 
static inline void mcan_clear_interrupt_flags(MCAN_Type *ptr, uint32_t mask)
{
    ptr->IR = mask;
}
 
static inline void mcan_enable_interrupts(MCAN_Type *ptr, uint32_t mask)
{
    ptr->ILS &= ~mask;
    ptr->IE |= mask;
    ptr->ILE = 1U;
}
 
static inline void mcan_enable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask)
{
    ptr->TXBTIE |= mask;
}
 
static inline void mcan_disable_txbuf_interrupt(MCAN_Type *ptr, uint32_t mask)
{
    ptr->TXBTIE &= ~mask;
}
 
static inline void mcan_disable_interrupts(MCAN_Type *ptr, uint32_t mask)
{
    ptr->IE &= ~mask;
}
 
static inline void mcan_enable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask)
{
    ptr->TXBTIE |= mask;
}
 
static inline void mcan_disable_txbuf_transmission_interrupt(MCAN_Type *ptr, uint32_t mask)
{
    ptr->TXBTIE &= ~mask;
}
 
static inline void mcan_enable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask)
{
    ptr->TXBCIE |= mask;
}
 
static inline void mcan_disable_txbuf_cancel_finish_interrupt(MCAN_Type *ptr, uint32_t mask)
{
    ptr->TXBCIE &= ~mask;
}
 
static inline void mcan_interrupt_line_select(MCAN_Type *ptr, uint32_t mask, uint8_t line_index)
{
    if (line_index == 0) {
        ptr->ILS &= ~mask;
    } else {
        ptr->ILS |= mask;
    }
    ptr->ILE = (1UL << line_index);
}
 
static inline bool mcan_is_transmit_request_pending(MCAN_Type *ptr, uint32_t index)
{
    return ((ptr->TXBRP & ((1UL << index))) != 0U);
}
 
static inline bool mcan_is_txfifo_full(MCAN_Type *ptr)
{
    return ((ptr->TXFQS & MCAN_TXFQS_TFQF_MASK) != 0U);
}
 
static inline uint32_t mcan_get_txfifo_put_index(MCAN_Type *ptr)
{
    return MCAN_TXFQS_TFQPI_GET(ptr->TXFQS);
}
 
static inline void mcan_send_add_request(MCAN_Type *ptr, uint32_t index)
{
    ptr->TXBAR = (1UL << index);
}
 
static inline void mcan_send_add_multiple_requests(MCAN_Type *ptr, uint32_t index_bitmask)
{
    ptr->TXBAR = index_bitmask;
}
 
static inline void mcan_cancel_tx_buf_send_request(MCAN_Type *ptr, uint32_t index)
{
    ptr->TXBCR = (1UL << index);
}
 
static inline bool mcan_is_transmit_occurred(MCAN_Type *ptr, uint32_t index)
{
    return ((ptr->TXBTO & (1UL << index)) != 0U);
}
 
static inline bool mcan_is_rxbuf_data_available(MCAN_Type *ptr, uint32_t index)
{
    bool result;
    if (index < 32U) {
        result = (ptr->NDAT1 & (1UL << index)) != 0U;
    } else if (index < 64U) {
        result = (ptr->NDAT2 & (1UL << (index - 32U))) != 0U;
    } else {
        result = false;
    }
    return result;
}
 
static inline void mcan_clear_rxbuf_data_available_flag(MCAN_Type *ptr, uint32_t index)
{
    if (index < 32U) {
        ptr->NDAT1 = (1UL << index);
    } else if (index < 64U) {
        ptr->NDAT2 = (1UL << (index - 32U));
    } else {
        /* Do nothing */
    }
}
 
static inline bool mcan_is_interrupt_flag_set(MCAN_Type *ptr, uint32_t mask)
{
    return ((ptr->IR & mask) != 0U);
}
 
static inline bool mcan_is_tsu_timestamp_available(MCAN_Type *ptr, uint32_t index)
{
    bool is_available = false;
    if (index < ARRAY_SIZE(ptr->TS_SEL)) {
        is_available = ((ptr->TSS1 & (1UL << index)) != 0U);
    }
    return is_available;
}
 
uint32_t mcan_read_32bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index);
 
uint64_t mcan_read_64bit_tsu_timestamp(MCAN_Type *ptr, uint32_t index);
 
void mcan_get_high_priority_message_status(MCAN_Type *ptr, mcan_high_priority_message_status_t *status);
 
void mcan_get_default_config(MCAN_Type *ptr, mcan_config_t *config);
 
uint8_t mcan_get_message_size_from_dlc(uint8_t dlc);
 
uint8_t mcan_get_data_field_size(uint8_t data_field_size_option);
 
void mcan_get_default_ram_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *ram_config, bool enable_canfd);
 
void mcan_get_default_ram_config(MCAN_Type *ptr, mcan_ram_config_t *simple_config, bool enable_canfd);
 
hpm_stat_t mcan_init(MCAN_Type *ptr, mcan_config_t *config, uint32_t src_clk_freq);
 
void mcan_deinit(MCAN_Type *ptr);
 
hpm_stat_t mcan_config_ram_with_flexible_config(MCAN_Type *ptr, mcan_ram_flexible_config_t *config);
 
hpm_stat_t mcan_config_ram(MCAN_Type *ptr, mcan_ram_config_t *config);
 
hpm_stat_t mcan_config_all_filters(MCAN_Type *ptr, mcan_all_filters_config_t *config);
 
hpm_stat_t mcan_config_transmitter_delay_compensation(MCAN_Type *ptr, mcan_tdc_config_t *config);
 
hpm_stat_t mcan_set_global_filter_config(MCAN_Type *ptr, mcan_global_filter_config_t *filter_config);
 
hpm_stat_t mcan_set_filter_element(MCAN_Type *ptr, const mcan_filter_elem_t *filter_elem, uint32_t index);
 
hpm_stat_t mcan_write_txbuf(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame);
 
hpm_stat_t mcan_write_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame);
 
hpm_stat_t mcan_read_rxbuf(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame);
 
hpm_stat_t mcan_read_rxfifo(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame);
 
hpm_stat_t mcan_read_tx_evt_fifo(MCAN_Type *ptr, mcan_tx_event_fifo_elem_t *tx_evt);
 
hpm_stat_t mcan_transmit_blocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame);
 
hpm_stat_t mcan_request_and_fill_txfifo(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index);
 
hpm_stat_t mcan_transmit_via_txfifo_nonblocking(MCAN_Type *ptr, mcan_tx_frame_t *tx_frame, uint32_t *fifo_index);
 
hpm_stat_t mcan_transmit_via_txbuf_nonblocking(MCAN_Type *ptr, uint32_t index, mcan_tx_frame_t *tx_frame);
 
hpm_stat_t mcan_receive_from_buf_blocking(MCAN_Type *ptr, uint32_t index, mcan_rx_message_t *rx_frame);
 
hpm_stat_t mcan_receive_from_fifo_blocking(MCAN_Type *ptr, uint32_t fifo_index, mcan_rx_message_t *rx_frame);
 
hpm_stat_t mcan_get_timestamp_from_tx_event(MCAN_Type *ptr,
                                            const mcan_tx_event_fifo_elem_t *tx_evt,
                                            mcan_timestamp_value_t *timestamp);
 
hpm_stat_t mcan_get_timestamp_from_received_message(MCAN_Type *ptr,
                                                    const mcan_rx_message_t *rx_msg,
                                                    mcan_timestamp_value_t *timestamp);
 
hpm_stat_t mcan_parse_protocol_status(uint32_t psr, mcan_protocol_status_t *protocol_status);
 
hpm_stat_t mcan_get_protocol_status(MCAN_Type *ptr, mcan_protocol_status_t *protocol_status);
 
#ifdef __cplusplus
}
#endif
 
 
#endif /* HPM_MCAN_DRV_H */