HPM SDK
HPMicro Software Development Kit
hpm_mipi_csi_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_MIPI_CSI_H
10 #define HPM_MIPI_CSI_H
11 
12 typedef struct {
13  __R uint32_t VERSION; /* 0x0: version code */
14  __RW uint32_t N_LANES; /* 0x4: the number of active lanes */
15  __RW uint32_t CSI2_RESETN; /* 0x8: the internal logic of the controller goes into the reset state when active */
16  __R uint32_t INT_ST_MAIN; /* 0xC: contains the stateus of individual interrupt sources */
17  __RW uint32_t DATA_IDS_1; /* 0x10: programs data type fields for data ID monitors */
18  __RW uint32_t DATA_IDS_2; /* 0x14: programs data type fields for data ID monitors */
19  __R uint8_t RESERVED0[20]; /* 0x18 - 0x2B: Reserved */
20  __R uint32_t INT_ST_AP_MAIN; /* 0x2C: contains the status of individual interrupt sources */
21  __R uint8_t RESERVED1[16]; /* 0x30 - 0x3F: Reserved */
22  __RW uint32_t PHY_SHUTDOWNZ; /* 0x40: controls the phy shutdown mode */
23  __RW uint32_t DPHY_RSTZ; /* 0x44: controls the phy reset mode */
24  __R uint32_t PHY_RX; /* 0x48: contains the status of rx-related signals from phy */
25  __R uint32_t PHY_STOPSTATE; /* 0x4C: contains the stopstate signal status from phy */
26  __R uint8_t RESERVED2[48]; /* 0x50 - 0x7F: Reserved */
27  __RW uint32_t IPI_MODE; /* 0x80: selects how the ipi interface generates the video frame */
28  __RW uint32_t IPI_VCID; /* 0x84: selects the vritual channel processed by ipi */
29  __RW uint32_t IPI_DATA_TYPE; /* 0x88: selects the data type processed by ipi */
30  __RW uint32_t IPI_MEM_FLASH; /* 0x8C: control the flush of ipi memory */
31  __RW uint32_t IPI_HSA_TIME; /* 0x90: configures the video horizontal synchronism active time */
32  __RW uint32_t IPI_HBP_TIME; /* 0x94: configures the video horizontal synchronism back porch time */
33  __RW uint32_t IPI_HSD_TIME; /* 0x98: configures the vedeo Horizontal Sync Delay time */
34  __RW uint32_t IPI_HLINE_TIME; /* 0x9C: configures the overall tiem for each video line */
35  __RW uint32_t IPI_SOFTRSTN; /* 0xA0: congtrols the ipi logic reset state */
36  __R uint8_t RESERVED3[8]; /* 0xA4 - 0xAB: Reserved */
37  __RW uint32_t IPI_ADV_FEATURES; /* 0xAC: configures advanced features for ipi mode */
38  __RW uint32_t IPI_VSA_LINES; /* 0xB0: configures the vertical synchronism active period */
39  __RW uint32_t IPI_VBP_LINES; /* 0xB4: configures the verticall back porch period */
40  __RW uint32_t IPI_VFP_LINES; /* 0xB8: configures the vertical front porch period */
41  __RW uint32_t IPI_VACTIVE_LINES; /* 0xBC: configures the vertical resolution of video */
42  __R uint8_t RESERVED4[8]; /* 0xC0 - 0xC7: Reserved */
43  __RW uint32_t VC_EXTENSION; /* 0xC8: active extra bits for virtual channel */
44  __R uint32_t PHY_CAL; /* 0xCC: contains the calibration signal status from synopsys d-phy */
45  __R uint8_t RESERVED5[16]; /* 0xD0 - 0xDF: Reserved */
46  __R uint32_t INT_ST_PHY_FATAL; /* 0xE0: groups the phy interruptions caused by phy packets discarded */
47  __RW uint32_t INT_MSK_PHY_FATAL; /* 0xE4: interrupt mask for int_st_phy_fatal */
48  __RW uint32_t INT_FORCE_PHY_FATAL; /* 0xE8: interrupt force register for test purposes */
49  __R uint8_t RESERVED6[4]; /* 0xEC - 0xEF: Reserved */
50  __R uint32_t INT_ST_PKT_FATAL; /* 0xF0: groups the fatal interruption related with packet construction */
51  __RW uint32_t INT_MSK_PKT_FATAL; /* 0xF4: interrupt mask for int_st_pkt_fatal */
52  __RW uint32_t INT_FORCE_PKT_FATAL; /* 0xF8: interrupt force register is used for test purpos */
53  __R uint8_t RESERVED7[20]; /* 0xFC - 0x10F: Reserved */
54  __R uint32_t INT_ST_PHY; /* 0x110: interruption caused by phy */
55  __RW uint32_t INT_MSK_PHY; /* 0x114: interrupt mask for int_st_phy */
56  __RW uint32_t INT_FORCE_PHY; /* 0x118: interrupt force register */
57  __R uint8_t RESERVED8[36]; /* 0x11C - 0x13F: Reserved */
58  __R uint32_t INT_ST_IPI_FATAL; /* 0x140: fatal interruption caused by ipi interface */
59  __RW uint32_t INT_MSK_IPI_FATAL; /* 0x144: interrupt mask for int_st_ipi_fatal */
60  __RW uint32_t INT_FORCE_IPI_FATAL; /* 0x148: interrupt force register */
61  __R uint8_t RESERVED9[52]; /* 0x14C - 0x17F: Reserved */
62  __R uint32_t INT_ST_AP_GENERIC; /* 0x180: groups and notifies which interruption bits caused the interruption */
63  __RW uint32_t INT_MSK_AP_GENERIC; /* 0x184: interrupt mask for int_st_ap_generic */
64  __RW uint32_t INT_FORCE_AP_GENERIC; /* 0x188: interrupt force register used for test purposes */
65  __R uint8_t RESERVED10[4]; /* 0x18C - 0x18F: Reserved */
66  __R uint32_t INT_ST_AP_IPI_FATAL; /* 0x190: groups and notifies which interruption bits */
67  __R uint32_t INT_MSK_AP_IPI_FATAL; /* 0x194: interrupt mask for int_st_ap_ipi_fatal controls */
68  __R uint32_t INT_FORCE_AP_IPI_FATAL; /* 0x198: interrupt force register */
69  __R uint8_t RESERVED11[228]; /* 0x19C - 0x27F: Reserved */
70  __R uint32_t INT_ST_BNDRY_FRAME_FATAL; /* 0x280: fatal interruption related with matching frame start with frame end for a specific virtual channel */
71  __RW uint32_t INT_MSK_BNDRY_FRAME_FATAL; /* 0x284: interrupt mask for int_st_bndry_frame_fatal */
72  __RW uint32_t INT_FORCE_BNDRY_FRAME_FATAL; /* 0x288: interrupt force register is used for test purposes */
73  __R uint8_t RESERVED12[4]; /* 0x28C - 0x28F: Reserved */
74  __R uint32_t INT_ST_SEQ_FRAME_FATAL; /* 0x290: fatal interruption related with matching frame start with frame end for a specific virtual channel */
75  __RW uint32_t INT_MSK_SEQ_FRAME_FATAL; /* 0x294: interrupt mask for int_st_seq_frame_fatal */
76  __RW uint32_t INT_FORCE_SEQ_FRAME_FATAL; /* 0x298: interrupt force register is used for test purposes */
77  __R uint8_t RESERVED13[4]; /* 0x29C - 0x29F: Reserved */
78  __R uint32_t INT_ST_CRC_FRAME_FATAL; /* 0x2A0: fatal interruption related with matching frame start with frame end for a specific virtual channel */
79  __RW uint32_t INT_MSK_CRC_FRAME_FATAL; /* 0x2A4: interrupt mask for int_st_crc_frame_fatal */
80  __RW uint32_t INT_FORCE_CRC_FRAME_FATAL; /* 0x2A8: interrupt force register is used for test purposes */
81  __R uint8_t RESERVED14[4]; /* 0x2AC - 0x2AF: Reserved */
82  __R uint32_t INT_ST_PLD_CRC_FRAME_FATAL; /* 0x2B0: fatal interruption related with matching frame start with frame end for a specific virtual channel */
83  __RW uint32_t INT_MSK_PLD_CRC_FRAME_FATAL; /* 0x2B4: interrupt mask for int_st_crc_frame_fatal */
84  __RW uint32_t INT_FORCE_PLD_CRC_FRAME_FATAL; /* 0x2B8: interrupt force register is used for test purposes */
85 } MIPI_CSI_Type;
86 
87 
88 /* Bitfield definition for register: VERSION */
89 /*
90  * VERSION (RO)
91  *
92  * version code
93  */
94 #define MIPI_CSI_VERSION_VERSION_MASK (0xFFFFFFFFUL)
95 #define MIPI_CSI_VERSION_VERSION_SHIFT (0U)
96 #define MIPI_CSI_VERSION_VERSION_GET(x) (((uint32_t)(x) & MIPI_CSI_VERSION_VERSION_MASK) >> MIPI_CSI_VERSION_VERSION_SHIFT)
97 
98 /* Bitfield definition for register: N_LANES */
99 /*
100  * N_LANES (RW)
101  *
102  * number of active data lanes
103  */
104 #define MIPI_CSI_N_LANES_N_LANES_MASK (0x7U)
105 #define MIPI_CSI_N_LANES_N_LANES_SHIFT (0U)
106 #define MIPI_CSI_N_LANES_N_LANES_SET(x) (((uint32_t)(x) << MIPI_CSI_N_LANES_N_LANES_SHIFT) & MIPI_CSI_N_LANES_N_LANES_MASK)
107 #define MIPI_CSI_N_LANES_N_LANES_GET(x) (((uint32_t)(x) & MIPI_CSI_N_LANES_N_LANES_MASK) >> MIPI_CSI_N_LANES_N_LANES_SHIFT)
108 
109 /* Bitfield definition for register: CSI2_RESETN */
110 /*
111  * CSI2_RESETN (RW)
112  *
113  * DWC_mipi_csi2_host reset output, active low
114  */
115 #define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK (0x1U)
116 #define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT (0U)
117 #define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SET(x) (((uint32_t)(x) << MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT) & MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK)
118 #define MIPI_CSI_CSI2_RESETN_CSI2_RESETN_GET(x) (((uint32_t)(x) & MIPI_CSI_CSI2_RESETN_CSI2_RESETN_MASK) >> MIPI_CSI_CSI2_RESETN_CSI2_RESETN_SHIFT)
119 
120 /* Bitfield definition for register: INT_ST_MAIN */
121 /*
122  * STATUS_INT_IPI4_FATAL (RC)
123  *
124  * status of int_st_ipi_fatal
125  */
126 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_MASK (0x40000UL)
127 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_SHIFT (18U)
128 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_IPI4_FATAL_SHIFT)
129 
130 /*
131  * STATUS_INT_LINE (RC)
132  *
133  * status of int_st_line
134  */
135 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_MASK (0x20000UL)
136 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_SHIFT (17U)
137 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_LINE_SHIFT)
138 
139 /*
140  * STATUS_INT_PHY (RC)
141  *
142  * status of int_st_phy
143  */
144 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_MASK (0x10000UL)
145 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_SHIFT (16U)
146 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_SHIFT)
147 
148 /*
149  * STATUS_INT_ECC_CORRECTED (RC)
150  *
151  * status of status_int_ecc_corrected
152  */
153 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_MASK (0x80U)
154 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT (7U)
155 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT)
156 
157 /*
158  * STATUS_INT_DATA_ID (RC)
159  *
160  * status of status_int_data_id
161  */
162 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_MASK (0x40U)
163 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_SHIFT (6U)
164 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_DATA_ID_SHIFT)
165 
166 /*
167  * STATUS_INT_PLD_CRC_FATAL (RC)
168  *
169  * status of status_int_pld_crc_fatal
170  */
171 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK (0x20U)
172 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT (5U)
173 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT)
174 
175 /*
176  * STATUS_INT_CRC_FRAME_FATAL (RC)
177  *
178  * status of status_int_crc_frame_fatal
179  */
180 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK (0x10U)
181 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT (4U)
182 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT)
183 
184 /*
185  * STATUS_INT_SEQ_FRAME_FATAL (RC)
186  *
187  * status of status_int_seq_frame_fatal
188  */
189 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK (0x8U)
190 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT (3U)
191 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT)
192 
193 /*
194  * STATUS_INT_BNDRY_FRAME_FATAL (RC)
195  *
196  * status of int_st_bndry_frame_fatal
197  */
198 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK (0x4U)
199 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT (2U)
200 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT)
201 
202 /*
203  * STATUS_INT_PKT_FATAL (RC)
204  *
205  * status of int_st_pkt_fatal
206  */
207 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_MASK (0x2U)
208 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_SHIFT (1U)
209 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PKT_FATAL_SHIFT)
210 
211 /*
212  * STATUS_INT_PHY_FATAL (RC)
213  *
214  * status of int_st_phy_fatal
215  */
216 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_MASK (0x1U)
217 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_SHIFT (0U)
218 #define MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_MASK) >> MIPI_CSI_INT_ST_MAIN_STATUS_INT_PHY_FATAL_SHIFT)
219 
220 /* Bitfield definition for register: DATA_IDS_1 */
221 /*
222  * DI3_DT (RW)
223  *
224  * data type for programmed data ID 3
225  */
226 #define MIPI_CSI_DATA_IDS_1_DI3_DT_MASK (0x3F000000UL)
227 #define MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT (24U)
228 #define MIPI_CSI_DATA_IDS_1_DI3_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI3_DT_MASK)
229 #define MIPI_CSI_DATA_IDS_1_DI3_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI3_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI3_DT_SHIFT)
230 
231 /*
232  * DI2_DT (RW)
233  *
234  * data type for programmed data ID 2
235  */
236 #define MIPI_CSI_DATA_IDS_1_DI2_DT_MASK (0x3F0000UL)
237 #define MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT (16U)
238 #define MIPI_CSI_DATA_IDS_1_DI2_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI2_DT_MASK)
239 #define MIPI_CSI_DATA_IDS_1_DI2_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI2_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI2_DT_SHIFT)
240 
241 /*
242  * DI1_DT (RW)
243  *
244  * data type for programmed data ID 1
245  */
246 #define MIPI_CSI_DATA_IDS_1_DI1_DT_MASK (0x3F00U)
247 #define MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT (8U)
248 #define MIPI_CSI_DATA_IDS_1_DI1_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI1_DT_MASK)
249 #define MIPI_CSI_DATA_IDS_1_DI1_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI1_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI1_DT_SHIFT)
250 
251 /*
252  * DI0_DT (RW)
253  *
254  * data type for programmed data ID 0
255  */
256 #define MIPI_CSI_DATA_IDS_1_DI0_DT_MASK (0x3FU)
257 #define MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT (0U)
258 #define MIPI_CSI_DATA_IDS_1_DI0_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT) & MIPI_CSI_DATA_IDS_1_DI0_DT_MASK)
259 #define MIPI_CSI_DATA_IDS_1_DI0_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_1_DI0_DT_MASK) >> MIPI_CSI_DATA_IDS_1_DI0_DT_SHIFT)
260 
261 /* Bitfield definition for register: DATA_IDS_2 */
262 /*
263  * DI7_DT (RW)
264  *
265  * data type for programmed data ID 7
266  */
267 #define MIPI_CSI_DATA_IDS_2_DI7_DT_MASK (0x3F000000UL)
268 #define MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT (24U)
269 #define MIPI_CSI_DATA_IDS_2_DI7_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI7_DT_MASK)
270 #define MIPI_CSI_DATA_IDS_2_DI7_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI7_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI7_DT_SHIFT)
271 
272 /*
273  * DI6_DT (RW)
274  *
275  * data type for programmed data ID 6
276  */
277 #define MIPI_CSI_DATA_IDS_2_DI6_DT_MASK (0x3F0000UL)
278 #define MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT (16U)
279 #define MIPI_CSI_DATA_IDS_2_DI6_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI6_DT_MASK)
280 #define MIPI_CSI_DATA_IDS_2_DI6_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI6_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI6_DT_SHIFT)
281 
282 /*
283  * DI5_DT (RW)
284  *
285  * data type for programmed data ID 5
286  */
287 #define MIPI_CSI_DATA_IDS_2_DI5_DT_MASK (0x3F00U)
288 #define MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT (8U)
289 #define MIPI_CSI_DATA_IDS_2_DI5_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI5_DT_MASK)
290 #define MIPI_CSI_DATA_IDS_2_DI5_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI5_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI5_DT_SHIFT)
291 
292 /*
293  * DI4_DT (RW)
294  *
295  * data type for programmed data ID 4
296  */
297 #define MIPI_CSI_DATA_IDS_2_DI4_DT_MASK (0x3FU)
298 #define MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT (0U)
299 #define MIPI_CSI_DATA_IDS_2_DI4_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT) & MIPI_CSI_DATA_IDS_2_DI4_DT_MASK)
300 #define MIPI_CSI_DATA_IDS_2_DI4_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_DATA_IDS_2_DI4_DT_MASK) >> MIPI_CSI_DATA_IDS_2_DI4_DT_SHIFT)
301 
302 /* Bitfield definition for register: INT_ST_AP_MAIN */
303 /*
304  * STATUS_INT_IPI_FATAL (RC)
305  *
306  * status of int_st_ipi_fatal
307  */
308 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_MASK (0x1000U)
309 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_SHIFT (12U)
310 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_IPI_FATAL_SHIFT)
311 
312 /*
313  * STATUS_INT_ST_AP_IPI_FATAL (RC)
314  *
315  * status of int_st_ap_ipi_fatal
316  */
317 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_MASK (0x800U)
318 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_SHIFT (11U)
319 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_IPI_FATAL_SHIFT)
320 
321 /*
322  * STATUS_INT_LINE (RC)
323  *
324  * status of int_st_line
325  */
326 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_MASK (0x400U)
327 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_SHIFT (10U)
328 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_LINE_SHIFT)
329 
330 /*
331  * STATUS_INT_ECC_CORRECTED (RC)
332  *
333  * status of status_int_ecc_corrected
334  */
335 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_MASK (0x200U)
336 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT (9U)
337 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ECC_CORRECTED_SHIFT)
338 
339 /*
340  * STATUS_INT_DATA_ID (RC)
341  *
342  * status of status_int_data_id
343  */
344 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_MASK (0x100U)
345 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_SHIFT (8U)
346 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_DATA_ID_SHIFT)
347 
348 /*
349  * STATUS_INT_PLD_CRC_FATAL (RC)
350  *
351  * status of status_int_pld_crc_fatal
352  */
353 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK (0x80U)
354 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT (7U)
355 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PLD_CRC_FATAL_SHIFT)
356 
357 /*
358  * STATUS_INT_PHY (RC)
359  *
360  * status of int_st_phy
361  */
362 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_MASK (0x40U)
363 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_SHIFT (6U)
364 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_SHIFT)
365 
366 /*
367  * STATUS_INT_CRC_FRAME_FATAL (RC)
368  *
369  * status of status_int_crc_frame_fatal
370  */
371 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK (0x20U)
372 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT (5U)
373 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_CRC_FRAME_FATAL_SHIFT)
374 
375 /*
376  * STATUS_INT_SEQ_FRAME_FATAL (RC)
377  *
378  * status of status_int_seq_frame_fatal
379  */
380 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK (0x10U)
381 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT (4U)
382 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_SEQ_FRAME_FATAL_SHIFT)
383 
384 /*
385  * STATUS_INT_BNDRY_FRAME_FATAL (RC)
386  *
387  * status of int_st_bndry_frame_fatal
388  */
389 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK (0x8U)
390 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT (3U)
391 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_BNDRY_FRAME_FATAL_SHIFT)
392 
393 /*
394  * STATUS_INT_PKT_FATAL (RC)
395  *
396  * status of int_st_pkt_fatal
397  */
398 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_MASK (0x4U)
399 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_SHIFT (2U)
400 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PKT_FATAL_SHIFT)
401 
402 /*
403  * STATUS_INT_PHY_FATAL (RC)
404  *
405  * status of int_st_phy_fatal
406  */
407 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_MASK (0x2U)
408 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_SHIFT (1U)
409 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_PHY_FATAL_SHIFT)
410 
411 /*
412  * STATUS_INT_ST_AP_GENERIC (RC)
413  *
414  * status of int_st_ap_generic
415  */
416 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_MASK (0x1U)
417 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_SHIFT (0U)
418 #define MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_MASK) >> MIPI_CSI_INT_ST_AP_MAIN_STATUS_INT_ST_AP_GENERIC_SHIFT)
419 
420 /* Bitfield definition for register: PHY_SHUTDOWNZ */
421 /*
422  * PHY_SHUTDOWNZ (RW)
423  *
424  * shutdown input,active low
425  */
426 #define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK (0x1U)
427 #define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT (0U)
428 #define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT) & MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK)
429 #define MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_MASK) >> MIPI_CSI_PHY_SHUTDOWNZ_PHY_SHUTDOWNZ_SHIFT)
430 
431 /* Bitfield definition for register: DPHY_RSTZ */
432 /*
433  * DPHY_RSTZ (RW)
434  *
435  * phy reset output, active low
436  */
437 #define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK (0x1U)
438 #define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT (0U)
439 #define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SET(x) (((uint32_t)(x) << MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT) & MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK)
440 #define MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_GET(x) (((uint32_t)(x) & MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_MASK) >> MIPI_CSI_DPHY_RSTZ_DPHY_RSTZ_SHIFT)
441 
442 /* Bitfield definition for register: PHY_RX */
443 /*
444  * PHY_RXCLKACTIVEHS (RO)
445  *
446  * indicates the d-phy clock lane is actively receiving a ddr clock
447  */
448 #define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK (0x20000UL)
449 #define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_SHIFT (17U)
450 #define MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_MASK) >> MIPI_CSI_PHY_RX_PHY_RXCLKACTIVEHS_SHIFT)
451 
452 /*
453  * PHY_RXULPSCLKNOT (RO)
454  *
455  * active low. Indicates the d-phy clock lane module has entered the Ultra low power state
456  */
457 #define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_MASK (0x10000UL)
458 #define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_SHIFT (16U)
459 #define MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULPSCLKNOT_SHIFT)
460 
461 /*
462  * PHY_RXULLPSESC_1 (RO)
463  *
464  * lane module 1 has entered the ultra low power mode
465  */
466 #define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_MASK (0x2U)
467 #define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_SHIFT (1U)
468 #define MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULLPSESC_1_SHIFT)
469 
470 /*
471  * PHY_RXULPSESC_0 (RO)
472  *
473  * lane module 0 has entered the ultra low power mode
474  */
475 #define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_MASK (0x1U)
476 #define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_SHIFT (0U)
477 #define MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_MASK) >> MIPI_CSI_PHY_RX_PHY_RXULPSESC_0_SHIFT)
478 
479 /* Bitfield definition for register: PHY_STOPSTATE */
480 /*
481  * PHY_STOPSTATECLK (RO)
482  *
483  * d-phy clock lane in stop state
484  */
485 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_MASK (0x10000UL)
486 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_SHIFT (16U)
487 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATECLK_SHIFT)
488 
489 /*
490  * PHY_STOPSTATEDATA_1 (RO)
491  *
492  * data lane 1 in stop state
493  */
494 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_MASK (0x2U)
495 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_SHIFT (1U)
496 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_1_SHIFT)
497 
498 /*
499  * PHY_STOPSTATEDATA_0 (RO)
500  *
501  * data lane 0 in stop state
502  */
503 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_MASK (0x1U)
504 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_SHIFT (0U)
505 #define MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_MASK) >> MIPI_CSI_PHY_STOPSTATE_PHY_STOPSTATEDATA_0_SHIFT)
506 
507 /* Bitfield definition for register: IPI_MODE */
508 /*
509  * IPI_ENABLE (RW)
510  *
511  * enables the interface
512  */
513 #define MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK (0x1000000UL)
514 #define MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT (24U)
515 #define MIPI_CSI_IPI_MODE_IPI_ENABLE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT) & MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK)
516 #define MIPI_CSI_IPI_MODE_IPI_ENABLE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_ENABLE_MASK) >> MIPI_CSI_IPI_MODE_IPI_ENABLE_SHIFT)
517 
518 /*
519  * IPI_CUT_THROUGH (RW)
520  *
521  * cut-through mode state active when high
522  */
523 #define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK (0x10000UL)
524 #define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT (16U)
525 #define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT) & MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK)
526 #define MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_MASK) >> MIPI_CSI_IPI_MODE_IPI_CUT_THROUGH_SHIFT)
527 
528 /*
529  * IPI_COLOR_COM (RW)
530  *
531  * if color mode components are deliverd as follows: 0x0 48bit intercase 0x1: 16bit interface
532  */
533 #define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK (0x100U)
534 #define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT (8U)
535 #define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT) & MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK)
536 #define MIPI_CSI_IPI_MODE_IPI_COLOR_COM_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_COLOR_COM_MASK) >> MIPI_CSI_IPI_MODE_IPI_COLOR_COM_SHIFT)
537 
538 /*
539  * IPI_MODE (RW)
540  *
541  * indicates the video mode transmission type 0x0: camera timing 0x1:controller timing
542  */
543 #define MIPI_CSI_IPI_MODE_IPI_MODE_MASK (0x1U)
544 #define MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT (0U)
545 #define MIPI_CSI_IPI_MODE_IPI_MODE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT) & MIPI_CSI_IPI_MODE_IPI_MODE_MASK)
546 #define MIPI_CSI_IPI_MODE_IPI_MODE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MODE_IPI_MODE_MASK) >> MIPI_CSI_IPI_MODE_IPI_MODE_SHIFT)
547 
548 /* Bitfield definition for register: IPI_VCID */
549 /*
550  * IPI_VCX_0_1 (RW)
551  *
552  * virtual channel extension of data to be processed by pixel interface
553  */
554 #define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK (0xCU)
555 #define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT (2U)
556 #define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT) & MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK)
557 #define MIPI_CSI_IPI_VCID_IPI_VCX_0_1_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VCID_IPI_VCX_0_1_MASK) >> MIPI_CSI_IPI_VCID_IPI_VCX_0_1_SHIFT)
558 
559 /*
560  * IP_VCID (RW)
561  *
562  * virtual channel of data to be processed by pixel interface
563  */
564 #define MIPI_CSI_IPI_VCID_IP_VCID_MASK (0x3U)
565 #define MIPI_CSI_IPI_VCID_IP_VCID_SHIFT (0U)
566 #define MIPI_CSI_IPI_VCID_IP_VCID_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VCID_IP_VCID_SHIFT) & MIPI_CSI_IPI_VCID_IP_VCID_MASK)
567 #define MIPI_CSI_IPI_VCID_IP_VCID_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VCID_IP_VCID_MASK) >> MIPI_CSI_IPI_VCID_IP_VCID_SHIFT)
568 
569 /* Bitfield definition for register: IPI_DATA_TYPE */
570 /*
571  * EMBENDED_DATA (RW)
572  *
573  * enable embedded data processing on ipi interface
574  */
575 #define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK (0x100U)
576 #define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT (8U)
577 #define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT) & MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK)
578 #define MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_MASK) >> MIPI_CSI_IPI_DATA_TYPE_EMBENDED_DATA_SHIFT)
579 
580 /*
581  * IPI_DATA_TYPE (RW)
582  *
583  * data type of data to be processed by pixel interface
584  */
585 #define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK (0x3FU)
586 #define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT (0U)
587 #define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT) & MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK)
588 #define MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_MASK) >> MIPI_CSI_IPI_DATA_TYPE_IPI_DATA_TYPE_SHIFT)
589 
590 /* Bitfield definition for register: IPI_MEM_FLASH */
591 /*
592  * IPI_AUTO_FLUSH (RW)
593  *
594  * memory is automatically flashed at each vsync
595  */
596 #define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK (0x100U)
597 #define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT (8U)
598 #define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT) & MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK)
599 #define MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_MASK) >> MIPI_CSI_IPI_MEM_FLASH_IPI_AUTO_FLUSH_SHIFT)
600 
601 /*
602  * IPI_FLUSH (RW)
603  *
604  * flush ipi memory, this bit is auto clear
605  */
606 #define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK (0x1U)
607 #define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT (0U)
608 #define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT) & MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK)
609 #define MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_MASK) >> MIPI_CSI_IPI_MEM_FLASH_IPI_FLUSH_SHIFT)
610 
611 /* Bitfield definition for register: IPI_HSA_TIME */
612 /*
613  * IPI_HSA_TIME (RW)
614  *
615  * configures the Horizontal Synchronism Active period in pixclk cycles
616  */
617 #define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK (0xFFFU)
618 #define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT (0U)
619 #define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT) & MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK)
620 #define MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_MASK) >> MIPI_CSI_IPI_HSA_TIME_IPI_HSA_TIME_SHIFT)
621 
622 /* Bitfield definition for register: IPI_HBP_TIME */
623 /*
624  * IPI_HBP_TIME (RW)
625  *
626  * configures the Horizontal Synchronism back porch period in pixclk cycles
627  */
628 #define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK (0xFFFU)
629 #define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT (0U)
630 #define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT) & MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK)
631 #define MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_MASK) >> MIPI_CSI_IPI_HBP_TIME_IPI_HBP_TIME_SHIFT)
632 
633 /* Bitfield definition for register: IPI_HSD_TIME */
634 /*
635  * IPI_HSD_TIME (RW)
636  *
637  * configures the Horizontal Sync Porch delay period in pixclk cycles
638  */
639 #define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK (0xFFFU)
640 #define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT (0U)
641 #define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT) & MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK)
642 #define MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_MASK) >> MIPI_CSI_IPI_HSD_TIME_IPI_HSD_TIME_SHIFT)
643 
644 /* Bitfield definition for register: IPI_HLINE_TIME */
645 /*
646  * IPI_HLIN_TIME (RW)
647  *
648  * configures the size of the line time counted in pixclk cycles
649  */
650 #define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK (0x7FFFU)
651 #define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT (0U)
652 #define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT) & MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK)
653 #define MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_MASK) >> MIPI_CSI_IPI_HLINE_TIME_IPI_HLIN_TIME_SHIFT)
654 
655 /* Bitfield definition for register: IPI_SOFTRSTN */
656 /*
657  * IPI_SOFTRSTN (RW)
658  *
659  * resets ipi one, active low
660  */
661 #define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK (0x1U)
662 #define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT (0U)
663 #define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT) & MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK)
664 #define MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_MASK) >> MIPI_CSI_IPI_SOFTRSTN_IPI_SOFTRSTN_SHIFT)
665 
666 /* Bitfield definition for register: IPI_ADV_FEATURES */
667 /*
668  * IPI_SYNC_EVENT_MODE (RW)
669  *
670  * for camera mode: 0x0- frame start do not trigger any sync event
671  */
672 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK (0x1000000UL)
673 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT (24U)
674 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK)
675 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_SYNC_EVENT_MODE_SHIFT)
676 
677 /*
678  * EN_EMBEDDED (RW)
679  *
680  * allows the use of embendded packets for ipi synchronization events
681  */
682 #define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK (0x200000UL)
683 #define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT (21U)
684 #define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK)
685 #define MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_EMBEDDED_SHIFT)
686 
687 /*
688  * EN_BLANKING (RW)
689  *
690  * allows the use of blankong packets for IPI synchronization events
691  */
692 #define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK (0x100000UL)
693 #define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT (20U)
694 #define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK)
695 #define MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_BLANKING_SHIFT)
696 
697 /*
698  * EN_NULL (RW)
699  *
700  * allows the use of null packets for IPI synchronization events
701  */
702 #define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK (0x80000UL)
703 #define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT (19U)
704 #define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK)
705 #define MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_NULL_SHIFT)
706 
707 /*
708  * EN_LINE_START (RW)
709  *
710  * allows the use of line start packets for ipi synchronization events
711  */
712 #define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK (0x40000UL)
713 #define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT (18U)
714 #define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK)
715 #define MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_LINE_START_SHIFT)
716 
717 /*
718  * EN_VIDEO (RW)
719  *
720  * allows the use of video packets for ipi synchronization events
721  */
722 #define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK (0x20000UL)
723 #define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT (17U)
724 #define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK)
725 #define MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_EN_VIDEO_SHIFT)
726 
727 /*
728  * LINE_EVENT_SELECTION (RW)
729  *
730  * for camero mode, allows manual selection of the packet fo line delimiter as follows: 0x0-controller seletc it automaticlly 0x1-select packets from list programmed in 17:21
731  */
732 #define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK (0x10000UL)
733 #define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT (16U)
734 #define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK)
735 #define MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_LINE_EVENT_SELECTION_SHIFT)
736 
737 /*
738  * IPI_DT (RW)
739  *
740  * datatype to overwrite
741  */
742 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK (0x3F00U)
743 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT (8U)
744 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK)
745 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_SHIFT)
746 
747 /*
748  * IPI_DT_OVERWRITE (RW)
749  *
750  * ignore datatype of the header using the programmed datatype for decoding
751  */
752 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK (0x1U)
753 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT (0U)
754 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK)
755 #define MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_MASK) >> MIPI_CSI_IPI_ADV_FEATURES_IPI_DT_OVERWRITE_SHIFT)
756 
757 /* Bitfield definition for register: IPI_VSA_LINES */
758 /*
759  * IPI_VSA_LINES (RW)
760  *
761  * configures the vertical synchronism active period measured in number of horizontal lines
762  */
763 #define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK (0x3FFU)
764 #define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT (0U)
765 #define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT) & MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK)
766 #define MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_MASK) >> MIPI_CSI_IPI_VSA_LINES_IPI_VSA_LINES_SHIFT)
767 
768 /* Bitfield definition for register: IPI_VBP_LINES */
769 /*
770  * IPI_VBP_LINES (RW)
771  *
772  * configuress the vertical back porch period measured in number of horizontal lines
773  */
774 #define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK (0x3FFU)
775 #define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT (0U)
776 #define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT) & MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK)
777 #define MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_MASK) >> MIPI_CSI_IPI_VBP_LINES_IPI_VBP_LINES_SHIFT)
778 
779 /* Bitfield definition for register: IPI_VFP_LINES */
780 /*
781  * IPI_VFP_LINES (RW)
782  *
783  * configures the vertical front porch period measured in number of horizontall lines
784  */
785 #define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK (0x3FFU)
786 #define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT (0U)
787 #define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT) & MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK)
788 #define MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_MASK) >> MIPI_CSI_IPI_VFP_LINES_IPI_VFP_LINES_SHIFT)
789 
790 /* Bitfield definition for register: IPI_VACTIVE_LINES */
791 /*
792  * IPI_VACTIVE_LINES (RW)
793  *
794  * configures the vertical active period measured in bumber of horizontal lines
795  */
796 #define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK (0x3FFFU)
797 #define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT (0U)
798 #define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SET(x) (((uint32_t)(x) << MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT) & MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK)
799 #define MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_GET(x) (((uint32_t)(x) & MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_MASK) >> MIPI_CSI_IPI_VACTIVE_LINES_IPI_VACTIVE_LINES_SHIFT)
800 
801 /* Bitfield definition for register: VC_EXTENSION */
802 /*
803  * VCX (RW)
804  *
805  * indicates status of virtual channel extension: 0-virtual channel extension is enable 1-legacy mode
806  */
807 #define MIPI_CSI_VC_EXTENSION_VCX_MASK (0x1U)
808 #define MIPI_CSI_VC_EXTENSION_VCX_SHIFT (0U)
809 #define MIPI_CSI_VC_EXTENSION_VCX_SET(x) (((uint32_t)(x) << MIPI_CSI_VC_EXTENSION_VCX_SHIFT) & MIPI_CSI_VC_EXTENSION_VCX_MASK)
810 #define MIPI_CSI_VC_EXTENSION_VCX_GET(x) (((uint32_t)(x) & MIPI_CSI_VC_EXTENSION_VCX_MASK) >> MIPI_CSI_VC_EXTENSION_VCX_SHIFT)
811 
812 /* Bitfield definition for register: PHY_CAL */
813 /*
814  * RXSKEWCALHS (RC)
815  *
816  * a low-to-high transition on rxskewcalhs signal means the the phy has initiated the de-skew calibration
817  */
818 #define MIPI_CSI_PHY_CAL_RXSKEWCALHS_MASK (0x1U)
819 #define MIPI_CSI_PHY_CAL_RXSKEWCALHS_SHIFT (0U)
820 #define MIPI_CSI_PHY_CAL_RXSKEWCALHS_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CAL_RXSKEWCALHS_MASK) >> MIPI_CSI_PHY_CAL_RXSKEWCALHS_SHIFT)
821 
822 /* Bitfield definition for register: INT_ST_PHY_FATAL */
823 /*
824  * ERR_DESKEW (RC)
825  *
826  * reports whenever data is lost due to an existent skew between lanes greater than 2 rxwordclkhs
827  */
828 #define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_MASK (0x100U)
829 #define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_SHIFT (8U)
830 #define MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_ERR_DESKEW_SHIFT)
831 
832 /*
833  * PHY_ERRSOTSYNCHS_1 (RC)
834  *
835  * start of transmission error on data lane1
836  */
837 #define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_MASK (0x2U)
838 #define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_SHIFT (1U)
839 #define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_1_SHIFT)
840 
841 /*
842  * PHY_ERRSOTSYNCHS_0 (RC)
843  *
844  * start of transmission error on data lane0
845  */
846 #define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_MASK (0x1U)
847 #define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_SHIFT (0U)
848 #define MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_ST_PHY_FATAL_PHY_ERRSOTSYNCHS_0_SHIFT)
849 
850 /* Bitfield definition for register: INT_MSK_PHY_FATAL */
851 /*
852  * ERR_DESKEW (RW)
853  *
854  * mask for err_deskew
855  */
856 #define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK (0x100U)
857 #define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT (8U)
858 #define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK)
859 #define MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_ERR_DESKEW_SHIFT)
860 
861 /*
862  * MASK_PHY_ERRSOTSYNCHS_1 (RW)
863  *
864  * mask for phy_errsotsynchs_1
865  */
866 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK (0x2U)
867 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT (1U)
868 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK)
869 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_1_SHIFT)
870 
871 /*
872  * MASK_PHY_ERRSOTSYNCHS_0 (RW)
873  *
874  * mask for phy_errsotsynchs_0
875  */
876 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK (0x1U)
877 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT (0U)
878 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK)
879 #define MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_MSK_PHY_FATAL_MASK_PHY_ERRSOTSYNCHS_0_SHIFT)
880 
881 /* Bitfield definition for register: INT_FORCE_PHY_FATAL */
882 /*
883  * ERR_DESKEW (RW)
884  *
885  * force err_deskew
886  */
887 #define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK (0x100U)
888 #define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT (8U)
889 #define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK)
890 #define MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_ERR_DESKEW_SHIFT)
891 
892 /*
893  * FORCE_PHY_ERRSOTSYNCHS_1 (RW)
894  *
895  * force phy_errsotsynchs_1
896  */
897 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK (0x2U)
898 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT (1U)
899 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK)
900 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_1_SHIFT)
901 
902 /*
903  * FORCE_PHY_ERRSOTSYNCHS_0 (RW)
904  *
905  * force phy_errsotsynchs_0
906  */
907 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK (0x1U)
908 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT (0U)
909 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK)
910 #define MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FATAL_FORCE_PHY_ERRSOTSYNCHS_0_SHIFT)
911 
912 /* Bitfield definition for register: INT_ST_PKT_FATAL */
913 /*
914  * ERR_ECC_DOUBLE (RC)
915  *
916  * header ecc contains at least 2 errors
917  */
918 #define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_MASK (0x1U)
919 #define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_SHIFT (0U)
920 #define MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_ST_PKT_FATAL_ERR_ECC_DOUBLE_SHIFT)
921 
922 /* Bitfield definition for register: INT_MSK_PKT_FATAL */
923 /*
924  * MASK_ERR_ECC_DOUBLE (RW)
925  *
926  * mask for err_ecc_double
927  */
928 #define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK (0x1U)
929 #define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT (0U)
930 #define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT) & MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK)
931 #define MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_MSK_PKT_FATAL_MASK_ERR_ECC_DOUBLE_SHIFT)
932 
933 /* Bitfield definition for register: INT_FORCE_PKT_FATAL */
934 /*
935  * FORCE_ERR_ECC_DOUBLE (RW)
936  *
937  * force err_ecc_double
938  */
939 #define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK (0x1U)
940 #define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT (0U)
941 #define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT) & MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK)
942 #define MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_MASK) >> MIPI_CSI_INT_FORCE_PKT_FATAL_FORCE_ERR_ECC_DOUBLE_SHIFT)
943 
944 /* Bitfield definition for register: INT_ST_PHY */
945 /*
946  * PHY_ERRESC_1 (RC)
947  *
948  * start of transmission error on data lane 1
949  */
950 #define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_MASK (0x20000UL)
951 #define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_SHIFT (17U)
952 #define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRESC_1_SHIFT)
953 
954 /*
955  * PHY_ERRESC_0 (RC)
956  *
957  * start of transmission error on data lane 0
958  */
959 #define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_MASK (0x10000UL)
960 #define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_SHIFT (16U)
961 #define MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRESC_0_SHIFT)
962 
963 /*
964  * PHY_ERRSOTHS_1 (RC)
965  *
966  * start of transmission error on data lane 1
967  */
968 #define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_MASK (0x2U)
969 #define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_SHIFT (1U)
970 #define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_1_SHIFT)
971 
972 /*
973  * PHY_ERRSOTHS_0 (RC)
974  *
975  * start of transmission error on data lane 0
976  */
977 #define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_MASK (0x1U)
978 #define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_SHIFT (0U)
979 #define MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_ST_PHY_PHY_ERRSOTHS_0_SHIFT)
980 
981 /* Bitfield definition for register: INT_MSK_PHY */
982 /*
983  * MASK_PHY_ERRESC_1 (RW)
984  *
985  * mask for phy_erresc_1
986  */
987 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK (0x20000UL)
988 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT (17U)
989 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK)
990 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_1_SHIFT)
991 
992 /*
993  * MASK_PHY_ERRESC_0 (RW)
994  *
995  * mask for phy_erresc_0
996  */
997 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK (0x10000UL)
998 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT (16U)
999 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK)
1000 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRESC_0_SHIFT)
1001 
1002 /*
1003  * MASK_PHY_ERRSOTHS_1 (RW)
1004  *
1005  * mask for phy_errsoths_1
1006  */
1007 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK (0x2U)
1008 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT (1U)
1009 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK)
1010 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_1_SHIFT)
1011 
1012 /*
1013  * MASK_PHY_ERRSOTHS_0 (RW)
1014  *
1015  * mask for phy_errsoths_0
1016  */
1017 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK (0x1U)
1018 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT (0U)
1019 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK)
1020 #define MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_MSK_PHY_MASK_PHY_ERRSOTHS_0_SHIFT)
1021 
1022 /* Bitfield definition for register: INT_FORCE_PHY */
1023 /*
1024  * FORCE_PHY_ERRESC_1 (RW)
1025  *
1026  * force phy_erresc_1
1027  */
1028 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK (0x20000UL)
1029 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT (17U)
1030 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK)
1031 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_1_SHIFT)
1032 
1033 /*
1034  * FORCE_PHY_ERRESC_0 (RW)
1035  *
1036  * force phy_erresc_0
1037  */
1038 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK (0x10000UL)
1039 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT (16U)
1040 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK)
1041 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRESC_0_SHIFT)
1042 
1043 /*
1044  * FORCE_PHY_ERRSOTHS_1 (RW)
1045  *
1046  * force phy_errsoths_1
1047  */
1048 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK (0x2U)
1049 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT (1U)
1050 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK)
1051 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_1_SHIFT)
1052 
1053 /*
1054  * FORCE_PHY_ERRSOTHS_0 (RW)
1055  *
1056  * force phy_errsoths_0
1057  */
1058 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK (0x1U)
1059 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT (0U)
1060 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK)
1061 #define MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_MASK) >> MIPI_CSI_INT_FORCE_PHY_FORCE_PHY_ERRSOTHS_0_SHIFT)
1062 
1063 /* Bitfield definition for register: INT_ST_IPI_FATAL */
1064 /*
1065  * INT_EVENT_FIFO_OVERFLOW (RC)
1066  *
1067  * reporting internal fifo overflow
1068  */
1069 #define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U)
1070 #define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U)
1071 #define MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_INT_EVENT_FIFO_OVERFLOW_SHIFT)
1072 
1073 /*
1074  * PIXEL_IF_HLINE_ERR (RC)
1075  *
1076  * horizontal line time error
1077  */
1078 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_MASK (0x10U)
1079 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_SHIFT (4U)
1080 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_HLINE_ERR_SHIFT)
1081 
1082 /*
1083  * PIXEL_IF_FIFO_NEMPTY_FS (RC)
1084  *
1085  * the fifo of pixel interface is not empty at the starat of a new frame
1086  */
1087 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U)
1088 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U)
1089 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT)
1090 
1091 /*
1092  * PIXEL_IF_FRAME_SYNC_ERR (RC)
1093  *
1094  * whenever in controller mode, notifies if a new frame is received but previous has not been completed
1095  */
1096 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_MASK (0x4U)
1097 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_SHIFT (2U)
1098 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FRAME_SYNC_ERR_SHIFT)
1099 
1100 /*
1101  * PIXEL_IF_FIFO_OVERFLOW (RC)
1102  *
1103  * the fifo of pixel interface has lost information because some data arrived and fifo is already full
1104  */
1105 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U)
1106 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U)
1107 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_OVERFLOW_SHIFT)
1108 
1109 /*
1110  * PIXEL_IF_FIFO_UNDERFLOW (RC)
1111  *
1112  * the fifo has become empty before the expected bumber of pixels could be extracted to the pixel intefcese
1113  */
1114 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U)
1115 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U)
1116 #define MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_ST_IPI_FATAL_PIXEL_IF_FIFO_UNDERFLOW_SHIFT)
1117 
1118 /* Bitfield definition for register: INT_MSK_IPI_FATAL */
1119 /*
1120  * MSK_INT_EVENT_FIFO_OVERFLOW (RW)
1121  *
1122  * mask int_event_fifo_overflow
1123  */
1124 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U)
1125 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U)
1126 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK)
1127 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_INT_EVENT_FIFO_OVERFLOW_SHIFT)
1128 
1129 /*
1130  * MSK_PIXEL_IF_HLINE_ERR (RW)
1131  *
1132  * mask pixel_if_hline_err
1133  */
1134 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK (0x10U)
1135 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT (4U)
1136 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK)
1137 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_HLINE_ERR_SHIFT)
1138 
1139 /*
1140  * MSK_PIXEL_IF_FIFO_NEMPTY_FS (RW)
1141  *
1142  * mask pixel_if_fifo_nempty_fs
1143  */
1144 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U)
1145 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U)
1146 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK)
1147 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT)
1148 
1149 /*
1150  * MSK_FRAME_SYNC_ERR (RW)
1151  *
1152  * mask for pixel_if_frame_sync_err
1153  */
1154 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK (0x4U)
1155 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT (2U)
1156 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK)
1157 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_FRAME_SYNC_ERR_SHIFT)
1158 
1159 /*
1160  * MSK_PIXEL_IF_FIFO_OVERFLOW (RW)
1161  *
1162  * mask for pixel_if_fifo_overflow
1163  */
1164 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U)
1165 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U)
1166 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK)
1167 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_OVERFLOW_SHIFT)
1168 
1169 /*
1170  * MSK_PIXEL_IF_FIFO_UNDERFLOW (RW)
1171  *
1172  * mask for pixel_if_fifo_unterflow
1173  */
1174 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U)
1175 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U)
1176 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK)
1177 #define MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_MSK_IPI_FATAL_MSK_PIXEL_IF_FIFO_UNDERFLOW_SHIFT)
1178 
1179 /* Bitfield definition for register: INT_FORCE_IPI_FATAL */
1180 /*
1181  * FORCE_INT_EVENT_FIFO_OVERFLOW (RW)
1182  *
1183  * force int_event_fifo_overflow
1184  */
1185 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK (0x20U)
1186 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT (5U)
1187 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK)
1188 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_INT_EVENT_FIFO_OVERFLOW_SHIFT)
1189 
1190 /*
1191  * FORCE_PIXEL_IF_HLINE_ERR (RW)
1192  *
1193  * force pixel_if_hline_err
1194  */
1195 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK (0x10U)
1196 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT (4U)
1197 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK)
1198 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_HLINE_ERR_SHIFT)
1199 
1200 /*
1201  * FORCE_PIXEL_IF_FIFO_NEMPTY_FS (RW)
1202  *
1203  * force pixel_if_fifo_nempty_fs
1204  */
1205 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK (0x8U)
1206 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT (3U)
1207 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK)
1208 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_NEMPTY_FS_SHIFT)
1209 
1210 /*
1211  * FORCE_FRAME_SYNC_ERR (RW)
1212  *
1213  * force for frame_sync_err
1214  */
1215 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK (0x4U)
1216 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT (2U)
1217 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK)
1218 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_FRAME_SYNC_ERR_SHIFT)
1219 
1220 /*
1221  * FORCE_PIXEL_IF_FIFO_OVERFLOW (RW)
1222  *
1223  * force for pixel_if_fifo_overflow
1224  */
1225 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK (0x2U)
1226 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT (1U)
1227 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK)
1228 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_OVERFLOW_SHIFT)
1229 
1230 /*
1231  * FORCE_PIXEL_IF_FIFO_UNDERFLOW (RW)
1232  *
1233  * force for pixel_if_fifo_underflow
1234  */
1235 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK (0x1U)
1236 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT (0U)
1237 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK)
1238 #define MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_MASK) >> MIPI_CSI_INT_FORCE_IPI_FATAL_FORCE_PIXEL_IF_FIFO_UNDERFLOW_SHIFT)
1239 
1240 /* Bitfield definition for register: INT_ST_AP_GENERIC */
1241 /*
1242  * SYNCHRONIZER_PIXCLK_AP_ERR (RC)
1243  *
1244  * ap error in synchronizer block for pixclk domain
1245  */
1246 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL)
1247 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U)
1248 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT)
1249 
1250 /*
1251  * SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RC)
1252  *
1253  * ap error in synchronizer block for rxbyteclkhs domain
1254  */
1255 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U)
1256 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U)
1257 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT)
1258 
1259 /*
1260  * SYNCHRONIZER_FPCLK_AP_ERR (RC)
1261  *
1262  * ap error in synchronizer block for fpclk domain
1263  */
1264 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U)
1265 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U)
1266 #define MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT)
1267 
1268 /*
1269  * ERR_HANDLE_AP_ERR (RC)
1270  *
1271  * ap error in error handler block
1272  */
1273 #define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_MASK (0x2000U)
1274 #define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_SHIFT (13U)
1275 #define MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_ERR_HANDLE_AP_ERR_SHIFT)
1276 
1277 /*
1278  * ERR_MSGR_AP_ERR (RC)
1279  *
1280  * ap error in err msgr block
1281  */
1282 #define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_MASK (0x1000U)
1283 #define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_SHIFT (12U)
1284 #define MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_ERR_MSGR_AP_ERR_SHIFT)
1285 
1286 /*
1287  * PREP_OUTS_AP_ERR (RC)
1288  *
1289  * ap error in prepare outs block
1290  */
1291 #define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_MASK (0xC00U)
1292 #define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_SHIFT (10U)
1293 #define MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PREP_OUTS_AP_ERR_SHIFT)
1294 
1295 /*
1296  * PACKET_ANALYZER_AP_ERR (RC)
1297  *
1298  * ap error in packet analyzer block
1299  */
1300 #define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_MASK (0x300U)
1301 #define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_SHIFT (8U)
1302 #define MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PACKET_ANALYZER_AP_ERR_SHIFT)
1303 
1304 /*
1305  * PHY_ADAPTER_AP_ERR (RC)
1306  *
1307  * ap error in phy adapter block
1308  */
1309 #define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_MASK (0x80U)
1310 #define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_SHIFT (7U)
1311 #define MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PHY_ADAPTER_AP_ERR_SHIFT)
1312 
1313 /*
1314  * DESCRAMBLER_AP_ERR (RC)
1315  *
1316  * ap error in descrambler block
1317  */
1318 #define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_MASK (0x40U)
1319 #define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_SHIFT (6U)
1320 #define MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_DESCRAMBLER_AP_ERR_SHIFT)
1321 
1322 /*
1323  * PIPELINE_DELAY_AP_ERR (RC)
1324  *
1325  * ap error in pipeline delay block
1326  */
1327 #define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_MASK (0x20U)
1328 #define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_SHIFT (5U)
1329 #define MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_PIPELINE_DELAY_AP_ERR_SHIFT)
1330 
1331 /*
1332  * DE_SKEW_AP_ERR (RC)
1333  *
1334  * ap error in de-skew block
1335  */
1336 #define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_MASK (0x10U)
1337 #define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_SHIFT (4U)
1338 #define MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_DE_SKEW_AP_ERR_SHIFT)
1339 
1340 /*
1341  * REG_BANK_AP_ERR (RC)
1342  *
1343  * ap error in register bank block
1344  */
1345 #define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_MASK (0xCU)
1346 #define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_SHIFT (2U)
1347 #define MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_REG_BANK_AP_ERR_SHIFT)
1348 
1349 /*
1350  * APB_AP_ERR (RC)
1351  *
1352  * ap error in apb block
1353  */
1354 #define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_MASK (0x3U)
1355 #define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_SHIFT (0U)
1356 #define MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_MASK) >> MIPI_CSI_INT_ST_AP_GENERIC_APB_AP_ERR_SHIFT)
1357 
1358 /* Bitfield definition for register: INT_MSK_AP_GENERIC */
1359 /*
1360  * MSK_SYNCHRONIZER_PIXCLK_AP_ERR (RW)
1361  *
1362  */
1363 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL)
1364 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U)
1365 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK)
1366 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT)
1367 
1368 /*
1369  * MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RW)
1370  *
1371  */
1372 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U)
1373 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U)
1374 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK)
1375 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT)
1376 
1377 /*
1378  * MSK_SYNCHRONIZER_FPCLK_AP_ERR (RW)
1379  *
1380  */
1381 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U)
1382 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U)
1383 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK)
1384 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT)
1385 
1386 /*
1387  * MSK_ERR_HANDLE_AP_ERR (RW)
1388  *
1389  */
1390 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK (0x2000U)
1391 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT (13U)
1392 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK)
1393 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_HANDLE_AP_ERR_SHIFT)
1394 
1395 /*
1396  * MSK_ERR_MSGR_AP_ERR (RW)
1397  *
1398  */
1399 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK (0x1000U)
1400 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT (12U)
1401 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK)
1402 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_ERR_MSGR_AP_ERR_SHIFT)
1403 
1404 /*
1405  * MSK_PREP_OUTS_AP_ERR (RW)
1406  *
1407  */
1408 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK (0xC00U)
1409 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT (10U)
1410 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK)
1411 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PREP_OUTS_AP_ERR_SHIFT)
1412 
1413 /*
1414  * MSK_PACKET_ANALYZER_AP_ERR (RW)
1415  *
1416  */
1417 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK (0x300U)
1418 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT (8U)
1419 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK)
1420 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PACKET_ANALYZER_AP_ERR_SHIFT)
1421 
1422 /*
1423  * MSK_PHY_ADAPTER_AP_ERR (RW)
1424  *
1425  */
1426 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK (0x80U)
1427 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT (7U)
1428 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK)
1429 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PHY_ADAPTER_AP_ERR_SHIFT)
1430 
1431 /*
1432  * MSK_DESCRAMBLER_AP_ERR (RW)
1433  *
1434  */
1435 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK (0x40U)
1436 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT (6U)
1437 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK)
1438 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DESCRAMBLER_AP_ERR_SHIFT)
1439 
1440 /*
1441  * MSK_PIPELINE_DELAY_AP_ERR (RW)
1442  *
1443  */
1444 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK (0x20U)
1445 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT (5U)
1446 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK)
1447 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_PIPELINE_DELAY_AP_ERR_SHIFT)
1448 
1449 /*
1450  * MSK_DE_SKEW_AP_ERR (RW)
1451  *
1452  */
1453 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK (0x10U)
1454 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT (4U)
1455 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK)
1456 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_DE_SKEW_AP_ERR_SHIFT)
1457 
1458 /*
1459  * MSK_REG_BANK_AP_ERR (RW)
1460  *
1461  */
1462 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK (0xCU)
1463 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT (2U)
1464 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK)
1465 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_REG_BANK_AP_ERR_SHIFT)
1466 
1467 /*
1468  * MSK_APB_AP_ERR (RW)
1469  *
1470  */
1471 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK (0x3U)
1472 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT (0U)
1473 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK)
1474 #define MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_GENERIC_MSK_APB_AP_ERR_SHIFT)
1475 
1476 /* Bitfield definition for register: INT_FORCE_AP_GENERIC */
1477 /*
1478  * FORCE_SYNCHRONIZER_PIXCLK_AP_ERR (RW)
1479  *
1480  */
1481 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK (0x10000UL)
1482 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT (16U)
1483 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK)
1484 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_PIXCLK_AP_ERR_SHIFT)
1485 
1486 /*
1487  * FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR (RW)
1488  *
1489  */
1490 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK (0x8000U)
1491 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT (15U)
1492 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK)
1493 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_RXBYTECLKHS_AP_ERR_SHIFT)
1494 
1495 /*
1496  * FORCE_SYNCHRONIZER_FPCLK_AP_ERR (RW)
1497  *
1498  */
1499 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK (0x4000U)
1500 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT (14U)
1501 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK)
1502 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_SYNCHRONIZER_FPCLK_AP_ERR_SHIFT)
1503 
1504 /*
1505  * FORCE_ERR_HANDLE_AP_ERR (RW)
1506  *
1507  */
1508 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK (0x2000U)
1509 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT (13U)
1510 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK)
1511 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_HANDLE_AP_ERR_SHIFT)
1512 
1513 /*
1514  * FORCE_ERR_MSGR_AP_ERR (RW)
1515  *
1516  */
1517 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK (0x1000U)
1518 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT (12U)
1519 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK)
1520 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_ERR_MSGR_AP_ERR_SHIFT)
1521 
1522 /*
1523  * FORCE_PREP_OUTS_AP_ERR (RW)
1524  *
1525  */
1526 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK (0xC00U)
1527 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT (10U)
1528 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK)
1529 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PREP_OUTS_AP_ERR_SHIFT)
1530 
1531 /*
1532  * FORCE_PACKET_ANALYZER_AP_ERR (RW)
1533  *
1534  */
1535 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK (0x300U)
1536 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT (8U)
1537 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK)
1538 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PACKET_ANALYZER_AP_ERR_SHIFT)
1539 
1540 /*
1541  * FORCE_PHY_ADAPTER_AP_ERR (RW)
1542  *
1543  */
1544 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK (0x80U)
1545 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT (7U)
1546 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK)
1547 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PHY_ADAPTER_AP_ERR_SHIFT)
1548 
1549 /*
1550  * FORCE_DESCRAMBLER_AP_ERR (RW)
1551  *
1552  */
1553 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK (0x40U)
1554 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT (6U)
1555 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK)
1556 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DESCRAMBLER_AP_ERR_SHIFT)
1557 
1558 /*
1559  * FORCE_PIPELINE_DELAY_AP_ERR (RW)
1560  *
1561  */
1562 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK (0x20U)
1563 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT (5U)
1564 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK)
1565 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_PIPELINE_DELAY_AP_ERR_SHIFT)
1566 
1567 /*
1568  * FORCE_DE_SKEW_AP_ERR (RW)
1569  *
1570  */
1571 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK (0x10U)
1572 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT (4U)
1573 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK)
1574 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_DE_SKEW_AP_ERR_SHIFT)
1575 
1576 /*
1577  * FORCE_REG_BANK_AP_ERR (RW)
1578  *
1579  */
1580 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK (0xCU)
1581 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT (2U)
1582 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK)
1583 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_REG_BANK_AP_ERR_SHIFT)
1584 
1585 /*
1586  * FORCE_APB_AP_ERR (RW)
1587  *
1588  */
1589 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK (0x3U)
1590 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT (0U)
1591 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK)
1592 #define MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_GENERIC_FORCE_APB_AP_ERR_SHIFT)
1593 
1594 /* Bitfield definition for register: INT_ST_AP_IPI_FATAL */
1595 /*
1596  * REDUNDANCY_ERR (RC)
1597  *
1598  * ap redundancy error in ipi1
1599  */
1600 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_MASK (0x20U)
1601 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_SHIFT (5U)
1602 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_REDUNDANCY_ERR_SHIFT)
1603 
1604 /*
1605  * CRC_ERR (RC)
1606  *
1607  * ap crc error in ipi1
1608  */
1609 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_MASK (0x10U)
1610 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_SHIFT (4U)
1611 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_CRC_ERR_SHIFT)
1612 
1613 /*
1614  * ECC_MULTIPLE_ERR (RC)
1615  *
1616  * ap ecc multiple error in ipi1
1617  */
1618 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_MASK (0x8U)
1619 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_SHIFT (3U)
1620 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_MULTIPLE_ERR_SHIFT)
1621 
1622 /*
1623  * ECC_SINGLE_ERR (RC)
1624  *
1625  * ap ecc sigle error in ipi1
1626  */
1627 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_MASK (0x4U)
1628 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_SHIFT (2U)
1629 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_ECC_SINGLE_ERR_SHIFT)
1630 
1631 /*
1632  * PARITY_RX_ERR (RC)
1633  *
1634  * ap parity rx error in ipi1
1635  */
1636 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_MASK (0x2U)
1637 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_SHIFT (1U)
1638 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_RX_ERR_SHIFT)
1639 
1640 /*
1641  * PARITY_TX_ERR (RC)
1642  *
1643  * ap parity tx error in ipi1
1644  */
1645 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_MASK (0x1U)
1646 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_SHIFT (0U)
1647 #define MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_ST_AP_IPI_FATAL_PARITY_TX_ERR_SHIFT)
1648 
1649 /* Bitfield definition for register: INT_MSK_AP_IPI_FATAL */
1650 /*
1651  * MASK_REDUNDANCY_ERR (RC)
1652  *
1653  */
1654 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_MASK (0x20U)
1655 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_SHIFT (5U)
1656 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_REDUNDANCY_ERR_SHIFT)
1657 
1658 /*
1659  * MASK_CRC_ERR (RC)
1660  *
1661  */
1662 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_MASK (0x10U)
1663 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_SHIFT (4U)
1664 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_CRC_ERR_SHIFT)
1665 
1666 /*
1667  * MASK_ECC_MULTIPLE_ERR (RC)
1668  *
1669  */
1670 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_MASK (0x8U)
1671 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_SHIFT (3U)
1672 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_MULTIPLE_ERR_SHIFT)
1673 
1674 /*
1675  * MASK_ECC_SINGLE_ERR (RC)
1676  *
1677  */
1678 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_MASK (0x4U)
1679 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_SHIFT (2U)
1680 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_ECC_SINGLE_ERR_SHIFT)
1681 
1682 /*
1683  * MASK_PARITY_RX_ERR (RC)
1684  *
1685  */
1686 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_MASK (0x2U)
1687 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_SHIFT (1U)
1688 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_RX_ERR_SHIFT)
1689 
1690 /*
1691  * MASK_PARITY_TX_ERR (RC)
1692  *
1693  */
1694 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_MASK (0x1U)
1695 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_SHIFT (0U)
1696 #define MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_MSK_AP_IPI_FATAL_MASK_PARITY_TX_ERR_SHIFT)
1697 
1698 /* Bitfield definition for register: INT_FORCE_AP_IPI_FATAL */
1699 /*
1700  * FORCE_REDUNDANCY_ERR (RC)
1701  *
1702  */
1703 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_MASK (0x20U)
1704 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_SHIFT (5U)
1705 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_REDUNDANCY_ERR_SHIFT)
1706 
1707 /*
1708  * FORCE_CRC_ERR (RC)
1709  *
1710  */
1711 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_MASK (0x10U)
1712 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_SHIFT (4U)
1713 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_CRC_ERR_SHIFT)
1714 
1715 /*
1716  * FORCE_ECC_MULTIPLE_ERR (RC)
1717  *
1718  */
1719 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_MASK (0x8U)
1720 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_SHIFT (3U)
1721 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_MULTIPLE_ERR_SHIFT)
1722 
1723 /*
1724  * FORCE_ECC_SINGLE_ERR (RC)
1725  *
1726  */
1727 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_MASK (0x4U)
1728 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_SHIFT (2U)
1729 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_ECC_SINGLE_ERR_SHIFT)
1730 
1731 /*
1732  * FORCE_PARITY_RX_ERR (RC)
1733  *
1734  */
1735 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_MASK (0x2U)
1736 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_SHIFT (1U)
1737 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_RX_ERR_SHIFT)
1738 
1739 /*
1740  * FORCE_PARITY_TX_ERR (RC)
1741  *
1742  */
1743 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_MASK (0x1U)
1744 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_SHIFT (0U)
1745 #define MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_MASK) >> MIPI_CSI_INT_FORCE_AP_IPI_FATAL_FORCE_PARITY_TX_ERR_SHIFT)
1746 
1747 /* Bitfield definition for register: INT_ST_BNDRY_FRAME_FATAL */
1748 /*
1749  * ERR_F_BNDRY_MATCH_VC15 (RC)
1750  *
1751  * error matching frame start with frame end for virtual channel 15
1752  */
1753 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U)
1754 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U)
1755 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC15_SHIFT)
1756 
1757 /*
1758  * ERR_F_BNDRY_MATCH_VC14 (RC)
1759  *
1760  * error matching frame start with frame end for virtual channel 14
1761  */
1762 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U)
1763 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U)
1764 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC14_SHIFT)
1765 
1766 /*
1767  * ERR_F_BNDRY_MATCH_VC13 (RC)
1768  *
1769  * error matching frame start with frame end for virtual channel 13
1770  */
1771 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U)
1772 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U)
1773 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC13_SHIFT)
1774 
1775 /*
1776  * ERR_F_BNDRY_MATCH_VC12 (RC)
1777  *
1778  * error matching frame start with frame end for virtual channel 12
1779  */
1780 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U)
1781 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U)
1782 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC12_SHIFT)
1783 
1784 /*
1785  * ERR_F_BNDRY_MATCH_VC11 (RC)
1786  *
1787  * error matching frame start with frame end for virtual channel 11
1788  */
1789 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U)
1790 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U)
1791 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC11_SHIFT)
1792 
1793 /*
1794  * ERR_F_BNDRY_MATCH_VC10 (RC)
1795  *
1796  * error matching frame start with frame end for virtual channel 10
1797  */
1798 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U)
1799 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U)
1800 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC10_SHIFT)
1801 
1802 /*
1803  * ERR_F_BNDRY_MATCH_VC9 (RC)
1804  *
1805  * error matching frame start with frame end for virtual channel 9
1806  */
1807 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U)
1808 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U)
1809 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC9_SHIFT)
1810 
1811 /*
1812  * ERR_F_BNDRY_MATCH_VC8 (RC)
1813  *
1814  * error matching frame start with frame end for virtual channel 8
1815  */
1816 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U)
1817 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U)
1818 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC8_SHIFT)
1819 
1820 /*
1821  * ERR_F_BNDRY_MATCH_VC7 (RC)
1822  *
1823  * error matching frame start with frame end for virtual channel 7
1824  */
1825 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U)
1826 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U)
1827 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC7_SHIFT)
1828 
1829 /*
1830  * ERR_F_BNDRY_MATCH_VC6 (RC)
1831  *
1832  * error matching frame start with frame end for virtual channel 6
1833  */
1834 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U)
1835 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U)
1836 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC6_SHIFT)
1837 
1838 /*
1839  * ERR_F_BNDRY_MATCH_VC5 (RC)
1840  *
1841  * error matching frame start with frame end for virtual channel 5
1842  */
1843 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U)
1844 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U)
1845 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC5_SHIFT)
1846 
1847 /*
1848  * ERR_F_BNDRY_MATCH_VC4 (RC)
1849  *
1850  * error matching frame start with frame end for virtual channel 4
1851  */
1852 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U)
1853 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U)
1854 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC4_SHIFT)
1855 
1856 /*
1857  * ERR_F_BNDRY_MATCH_VC3 (RC)
1858  *
1859  * error matching frame start with frame end for virtual channel 3
1860  */
1861 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U)
1862 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U)
1863 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC3_SHIFT)
1864 
1865 /*
1866  * ERR_F_BNDRY_MATCH_VC2 (RC)
1867  *
1868  * error matching frame start with frame end for virtual channel 2
1869  */
1870 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U)
1871 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U)
1872 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC2_SHIFT)
1873 
1874 /*
1875  * ERR_F_BNDRY_MATCH_VC1 (RC)
1876  *
1877  * error matching frame start with frame end for virtual channel 1
1878  */
1879 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U)
1880 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U)
1881 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC1_SHIFT)
1882 
1883 /*
1884  * ERR_F_BNDRY_MATCH_VC0 (RC)
1885  *
1886  * error matching frame start with frame end for virtual channel 0
1887  */
1888 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U)
1889 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U)
1890 #define MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_BNDRY_FRAME_FATAL_ERR_F_BNDRY_MATCH_VC0_SHIFT)
1891 
1892 /* Bitfield definition for register: INT_MSK_BNDRY_FRAME_FATAL */
1893 /*
1894  * MSK_ERR_F_BNDRY_MATCH_VC15 (RW)
1895  *
1896  * error matching frame start with frame end for virtual channel 15
1897  */
1898 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U)
1899 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U)
1900 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK)
1901 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC15_SHIFT)
1902 
1903 /*
1904  * MSK_ERR_F_BNDRY_MATCH_VC14 (RW)
1905  *
1906  * error matching frame start with frame end for virtual channel 14
1907  */
1908 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U)
1909 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U)
1910 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK)
1911 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC14_SHIFT)
1912 
1913 /*
1914  * MSK_ERR_F_BNDRY_MATCH_VC13 (RW)
1915  *
1916  * error matching frame start with frame end for virtual channel 13
1917  */
1918 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U)
1919 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U)
1920 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK)
1921 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC13_SHIFT)
1922 
1923 /*
1924  * MSK_ERR_F_BNDRY_MATCH_VC12 (RW)
1925  *
1926  * error matching frame start with frame end for virtual channel 12
1927  */
1928 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U)
1929 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U)
1930 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK)
1931 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC12_SHIFT)
1932 
1933 /*
1934  * MSK_ERR_F_BNDRY_MATCH_VC11 (RW)
1935  *
1936  * error matching frame start with frame end for virtual channel 11
1937  */
1938 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U)
1939 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U)
1940 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK)
1941 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC11_SHIFT)
1942 
1943 /*
1944  * MSK_ERR_F_BNDRY_MATCH_VC10 (RW)
1945  *
1946  * error matching frame start with frame end for virtual channel 10
1947  */
1948 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U)
1949 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U)
1950 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK)
1951 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC10_SHIFT)
1952 
1953 /*
1954  * MSK_ERR_F_BNDRY_MATCH_VC9 (RW)
1955  *
1956  * error matching frame start with frame end for virtual channel 9
1957  */
1958 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U)
1959 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U)
1960 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK)
1961 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC9_SHIFT)
1962 
1963 /*
1964  * MSK_ERR_F_BNDRY_MATCH_VC8 (RW)
1965  *
1966  * error matching frame start with frame end for virtual channel 8
1967  */
1968 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U)
1969 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U)
1970 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK)
1971 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC8_SHIFT)
1972 
1973 /*
1974  * MSK_ERR_F_BNDRY_MATCH_VC7 (RW)
1975  *
1976  * error matching frame start with frame end for virtual channel 7
1977  */
1978 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U)
1979 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U)
1980 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK)
1981 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC7_SHIFT)
1982 
1983 /*
1984  * MSK_ERR_F_BNDRY_MATCH_VC6 (RW)
1985  *
1986  * error matching frame start with frame end for virtual channel 6
1987  */
1988 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U)
1989 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U)
1990 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK)
1991 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC6_SHIFT)
1992 
1993 /*
1994  * MSK_ERR_F_BNDRY_MATCH_VC5 (RW)
1995  *
1996  * error matching frame start with frame end for virtual channel 5
1997  */
1998 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U)
1999 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U)
2000 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK)
2001 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC5_SHIFT)
2002 
2003 /*
2004  * MSK_ERR_F_BNDRY_MATCH_VC4 (RW)
2005  *
2006  * error matching frame start with frame end for virtual channel 4
2007  */
2008 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U)
2009 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U)
2010 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK)
2011 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC4_SHIFT)
2012 
2013 /*
2014  * MSK_ERR_F_BNDRY_MATCH_VC3 (RW)
2015  *
2016  * error matching frame start with frame end for virtual channel 3
2017  */
2018 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U)
2019 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U)
2020 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK)
2021 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC3_SHIFT)
2022 
2023 /*
2024  * MSK_ERR_F_BNDRY_MATCH_VC2 (RW)
2025  *
2026  * error matching frame start with frame end for virtual channel 2
2027  */
2028 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U)
2029 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U)
2030 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK)
2031 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC2_SHIFT)
2032 
2033 /*
2034  * MSK_ERR_F_BNDRY_MATCH_VC1 (RW)
2035  *
2036  * error matching frame start with frame end for virtual channel 1
2037  */
2038 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U)
2039 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U)
2040 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK)
2041 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC1_SHIFT)
2042 
2043 /*
2044  * MSK_ERR_F_BNDRY_MATCH_VC0 (RW)
2045  *
2046  * error matching frame start with frame end for virtual channel 0
2047  */
2048 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U)
2049 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U)
2050 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK)
2051 #define MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_BNDRY_FRAME_FATAL_MSK_ERR_F_BNDRY_MATCH_VC0_SHIFT)
2052 
2053 /* Bitfield definition for register: INT_FORCE_BNDRY_FRAME_FATAL */
2054 /*
2055  * FORCE_ERR_F_BNDRY_MATCH_VC15 (RW)
2056  *
2057  * error matching frame start with frame end for virtual channel 15
2058  */
2059 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK (0x8000U)
2060 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT (15U)
2061 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK)
2062 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC15_SHIFT)
2063 
2064 /*
2065  * FORCE_ERR_F_BNDRY_MATCH_VC14 (RW)
2066  *
2067  * error matching frame start with frame end for virtual channel 14
2068  */
2069 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK (0x4000U)
2070 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT (14U)
2071 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK)
2072 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC14_SHIFT)
2073 
2074 /*
2075  * FORCE_ERR_F_BNDRY_MATCH_VC13 (RW)
2076  *
2077  * error matching frame start with frame end for virtual channel 13
2078  */
2079 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK (0x2000U)
2080 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT (13U)
2081 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK)
2082 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC13_SHIFT)
2083 
2084 /*
2085  * FORCE_ERR_F_BNDRY_MATCH_VC12 (RW)
2086  *
2087  * error matching frame start with frame end for virtual channel 12
2088  */
2089 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK (0x1000U)
2090 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT (12U)
2091 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK)
2092 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC12_SHIFT)
2093 
2094 /*
2095  * FORCE_ERR_F_BNDRY_MATCH_VC11 (RW)
2096  *
2097  * error matching frame start with frame end for virtual channel 11
2098  */
2099 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK (0x800U)
2100 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT (11U)
2101 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK)
2102 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC11_SHIFT)
2103 
2104 /*
2105  * FORCE_ERR_F_BNDRY_MATCH_VC10 (RW)
2106  *
2107  * error matching frame start with frame end for virtual channel 10
2108  */
2109 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK (0x400U)
2110 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT (10U)
2111 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK)
2112 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC10_SHIFT)
2113 
2114 /*
2115  * FORCE_ERR_F_BNDRY_MATCH_VC9 (RW)
2116  *
2117  * error matching frame start with frame end for virtual channel 9
2118  */
2119 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK (0x200U)
2120 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT (9U)
2121 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK)
2122 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC9_SHIFT)
2123 
2124 /*
2125  * FORCE_ERR_F_BNDRY_MATCH_VC8 (RW)
2126  *
2127  * error matching frame start with frame end for virtual channel 8
2128  */
2129 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK (0x100U)
2130 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT (8U)
2131 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK)
2132 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC8_SHIFT)
2133 
2134 /*
2135  * FORCE_ERR_F_BNDRY_MATCH_VC7 (RW)
2136  *
2137  * error matching frame start with frame end for virtual channel 7
2138  */
2139 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK (0x80U)
2140 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT (7U)
2141 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK)
2142 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC7_SHIFT)
2143 
2144 /*
2145  * FORCE_ERR_F_BNDRY_MATCH_VC6 (RW)
2146  *
2147  * error matching frame start with frame end for virtual channel 6
2148  */
2149 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK (0x40U)
2150 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT (6U)
2151 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK)
2152 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC6_SHIFT)
2153 
2154 /*
2155  * FORCE_ERR_F_BNDRY_MATCH_VC5 (RW)
2156  *
2157  * error matching frame start with frame end for virtual channel 5
2158  */
2159 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK (0x20U)
2160 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT (5U)
2161 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK)
2162 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC5_SHIFT)
2163 
2164 /*
2165  * FORCE_ERR_F_BNDRY_MATCH_VC4 (RW)
2166  *
2167  * error matching frame start with frame end for virtual channel 4
2168  */
2169 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK (0x10U)
2170 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT (4U)
2171 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK)
2172 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC4_SHIFT)
2173 
2174 /*
2175  * FORCE_ERR_F_BNDRY_MATCH_VC3 (RW)
2176  *
2177  * error matching frame start with frame end for virtual channel 3
2178  */
2179 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK (0x8U)
2180 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT (3U)
2181 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK)
2182 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC3_SHIFT)
2183 
2184 /*
2185  * FORCE_ERR_F_BNDRY_MATCH_VC2 (RW)
2186  *
2187  * error matching frame start with frame end for virtual channel 2
2188  */
2189 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK (0x4U)
2190 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT (2U)
2191 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK)
2192 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC2_SHIFT)
2193 
2194 /*
2195  * FORCE_ERR_F_BNDRY_MATCH_VC1 (RW)
2196  *
2197  * error matching frame start with frame end for virtual channel 1
2198  */
2199 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK (0x2U)
2200 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT (1U)
2201 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK)
2202 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC1_SHIFT)
2203 
2204 /*
2205  * FORCE_ERR_F_BNDRY_MATCH_VC0 (RW)
2206  *
2207  * error matching frame start with frame end for virtual channel 0
2208  */
2209 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK (0x1U)
2210 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT (0U)
2211 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK)
2212 #define MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_BNDRY_FRAME_FATAL_FORCE_ERR_F_BNDRY_MATCH_VC0_SHIFT)
2213 
2214 /* Bitfield definition for register: INT_ST_SEQ_FRAME_FATAL */
2215 /*
2216  * ERR_F_SEQ_MATCH_VC15 (RC)
2217  *
2218  * error matching frame start with frame end for virtual channel 15
2219  */
2220 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U)
2221 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_SHIFT (15U)
2222 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC15_SHIFT)
2223 
2224 /*
2225  * ERR_F_SEQ_MATCH_VC14 (RC)
2226  *
2227  * error matching frame start with frame end for virtual channel 14
2228  */
2229 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U)
2230 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_SHIFT (14U)
2231 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC14_SHIFT)
2232 
2233 /*
2234  * ERR_F_SEQ_MATCH_VC13 (RC)
2235  *
2236  * error matching frame start with frame end for virtual channel 13
2237  */
2238 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U)
2239 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_SHIFT (13U)
2240 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC13_SHIFT)
2241 
2242 /*
2243  * ERR_F_SEQ_MATCH_VC12 (RC)
2244  *
2245  * error matching frame start with frame end for virtual channel 12
2246  */
2247 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U)
2248 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_SHIFT (12U)
2249 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC12_SHIFT)
2250 
2251 /*
2252  * ERR_F_SEQ_MATCH_VC11 (RC)
2253  *
2254  * error matching frame start with frame end for virtual channel 11
2255  */
2256 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_MASK (0x800U)
2257 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_SHIFT (11U)
2258 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC11_SHIFT)
2259 
2260 /*
2261  * ERR_F_SEQ_MATCH_VC10 (RC)
2262  *
2263  * error matching frame start with frame end for virtual channel 10
2264  */
2265 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_MASK (0x400U)
2266 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_SHIFT (10U)
2267 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC10_SHIFT)
2268 
2269 /*
2270  * ERR_F_SEQ_MATCH_VC9 (RC)
2271  *
2272  * error matching frame start with frame end for virtual channel 9
2273  */
2274 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_MASK (0x200U)
2275 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_SHIFT (9U)
2276 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC9_SHIFT)
2277 
2278 /*
2279  * ERR_F_SEQ_MATCH_VC8 (RC)
2280  *
2281  * error matching frame start with frame end for virtual channel 8
2282  */
2283 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_MASK (0x100U)
2284 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_SHIFT (8U)
2285 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC8_SHIFT)
2286 
2287 /*
2288  * ERR_F_SEQ_MATCH_VC7 (RC)
2289  *
2290  * error matching frame start with frame end for virtual channel 7
2291  */
2292 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_MASK (0x80U)
2293 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_SHIFT (7U)
2294 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC7_SHIFT)
2295 
2296 /*
2297  * ERR_F_SEQ_MATCH_VC6 (RC)
2298  *
2299  * error matching frame start with frame end for virtual channel 6
2300  */
2301 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_MASK (0x40U)
2302 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_SHIFT (6U)
2303 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC6_SHIFT)
2304 
2305 /*
2306  * ERR_F_SEQ_MATCH_VC5 (RC)
2307  *
2308  * error matching frame start with frame end for virtual channel 5
2309  */
2310 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_MASK (0x20U)
2311 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_SHIFT (5U)
2312 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC5_SHIFT)
2313 
2314 /*
2315  * ERR_F_SEQ_MATCH_VC4 (RC)
2316  *
2317  * error matching frame start with frame end for virtual channel 4
2318  */
2319 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_MASK (0x10U)
2320 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_SHIFT (4U)
2321 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC4_SHIFT)
2322 
2323 /*
2324  * ERR_F_SEQ_MATCH_VC3 (RC)
2325  *
2326  * error matching frame start with frame end for virtual channel 3
2327  */
2328 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_MASK (0x8U)
2329 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_SHIFT (3U)
2330 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC3_SHIFT)
2331 
2332 /*
2333  * ERR_F_SEQ_MATCH_VC2 (RC)
2334  *
2335  * error matching frame start with frame end for virtual channel 2
2336  */
2337 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_MASK (0x4U)
2338 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_SHIFT (2U)
2339 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC2_SHIFT)
2340 
2341 /*
2342  * ERR_F_SEQ_MATCH_VC1 (RC)
2343  *
2344  * error matching frame start with frame end for virtual channel 1
2345  */
2346 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_MASK (0x2U)
2347 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_SHIFT (1U)
2348 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC1_SHIFT)
2349 
2350 /*
2351  * ERR_F_SEQ_MATCH_VC0 (RC)
2352  *
2353  * error matching frame start with frame end for virtual channel 0
2354  */
2355 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_MASK (0x1U)
2356 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_SHIFT (0U)
2357 #define MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_SEQ_FRAME_FATAL_ERR_F_SEQ_MATCH_VC0_SHIFT)
2358 
2359 /* Bitfield definition for register: INT_MSK_SEQ_FRAME_FATAL */
2360 /*
2361  * MSK_ERR_F_SEQ_MATCH_VC15 (RW)
2362  *
2363  * error matching frame start with frame end for virtual channel 15
2364  */
2365 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U)
2366 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT (15U)
2367 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK)
2368 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC15_SHIFT)
2369 
2370 /*
2371  * MSK_ERR_F_SEQ_MATCH_VC14 (RW)
2372  *
2373  * error matching frame start with frame end for virtual channel 14
2374  */
2375 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U)
2376 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT (14U)
2377 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK)
2378 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC14_SHIFT)
2379 
2380 /*
2381  * MSK_ERR_F_SEQ_MATCH_VC13 (RW)
2382  *
2383  * error matching frame start with frame end for virtual channel 13
2384  */
2385 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U)
2386 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT (13U)
2387 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK)
2388 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC13_SHIFT)
2389 
2390 /*
2391  * MSK_ERR_F_SEQ_MATCH_VC12 (RW)
2392  *
2393  * error matching frame start with frame end for virtual channel 12
2394  */
2395 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U)
2396 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT (12U)
2397 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK)
2398 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC12_SHIFT)
2399 
2400 /*
2401  * MSK_ERR_F_SEQ_MATCH_VC11 (RW)
2402  *
2403  * error matching frame start with frame end for virtual channel 11
2404  */
2405 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK (0x800U)
2406 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT (11U)
2407 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK)
2408 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC11_SHIFT)
2409 
2410 /*
2411  * MSK_ERR_F_SEQ_MATCH_VC10 (RW)
2412  *
2413  * error matching frame start with frame end for virtual channel 10
2414  */
2415 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK (0x400U)
2416 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT (10U)
2417 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK)
2418 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC10_SHIFT)
2419 
2420 /*
2421  * MSK_ERR_F_SEQ_MATCH_VC9 (RW)
2422  *
2423  * error matching frame start with frame end for virtual channel 9
2424  */
2425 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK (0x200U)
2426 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT (9U)
2427 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK)
2428 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC9_SHIFT)
2429 
2430 /*
2431  * MSK_ERR_F_SEQ_MATCH_VC8 (RW)
2432  *
2433  * error matching frame start with frame end for virtual channel 8
2434  */
2435 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK (0x100U)
2436 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT (8U)
2437 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK)
2438 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC8_SHIFT)
2439 
2440 /*
2441  * MSK_ERR_F_SEQ_MATCH_VC7 (RW)
2442  *
2443  * error matching frame start with frame end for virtual channel 7
2444  */
2445 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK (0x80U)
2446 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT (7U)
2447 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK)
2448 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC7_SHIFT)
2449 
2450 /*
2451  * MSK_ERR_F_SEQ_MATCH_VC6 (RW)
2452  *
2453  * error matching frame start with frame end for virtual channel 6
2454  */
2455 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK (0x40U)
2456 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT (6U)
2457 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK)
2458 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC6_SHIFT)
2459 
2460 /*
2461  * MSK_ERR_F_SEQ_MATCH_VC5 (RW)
2462  *
2463  * error matching frame start with frame end for virtual channel 5
2464  */
2465 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK (0x20U)
2466 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT (5U)
2467 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK)
2468 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC5_SHIFT)
2469 
2470 /*
2471  * MSK_ERR_F_SEQ_MATCH_VC4 (RW)
2472  *
2473  * error matching frame start with frame end for virtual channel 4
2474  */
2475 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK (0x10U)
2476 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT (4U)
2477 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK)
2478 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC4_SHIFT)
2479 
2480 /*
2481  * MSK_ERR_F_SEQ_MATCH_VC3 (RW)
2482  *
2483  * error matching frame start with frame end for virtual channel 3
2484  */
2485 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK (0x8U)
2486 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT (3U)
2487 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK)
2488 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC3_SHIFT)
2489 
2490 /*
2491  * MSK_ERR_F_SEQ_MATCH_VC2 (RW)
2492  *
2493  * error matching frame start with frame end for virtual channel 2
2494  */
2495 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK (0x4U)
2496 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT (2U)
2497 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK)
2498 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC2_SHIFT)
2499 
2500 /*
2501  * MSK_ERR_F_SEQ_MATCH_VC1 (RW)
2502  *
2503  * error matching frame start with frame end for virtual channel 1
2504  */
2505 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK (0x2U)
2506 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT (1U)
2507 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK)
2508 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC1_SHIFT)
2509 
2510 /*
2511  * MSK_ERR_F_SEQ_MATCH_VC0 (RW)
2512  *
2513  * error matching frame start with frame end for virtual channel 0
2514  */
2515 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK (0x1U)
2516 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT (0U)
2517 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK)
2518 #define MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_SEQ_FRAME_FATAL_MSK_ERR_F_SEQ_MATCH_VC0_SHIFT)
2519 
2520 /* Bitfield definition for register: INT_FORCE_SEQ_FRAME_FATAL */
2521 /*
2522  * FORCE_ERR_F_SEQ_MATCH_VC15 (RW)
2523  *
2524  * error matching frame start with frame end for virtual channel 15
2525  */
2526 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK (0x8000U)
2527 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT (15U)
2528 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK)
2529 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC15_SHIFT)
2530 
2531 /*
2532  * FORCE_ERR_F_SEQ_MATCH_VC14 (RW)
2533  *
2534  * error matching frame start with frame end for virtual channel 14
2535  */
2536 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK (0x4000U)
2537 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT (14U)
2538 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK)
2539 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC14_SHIFT)
2540 
2541 /*
2542  * FORCE_ERR_F_SEQ_MATCH_VC13 (RW)
2543  *
2544  * error matching frame start with frame end for virtual channel 13
2545  */
2546 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK (0x2000U)
2547 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT (13U)
2548 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK)
2549 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC13_SHIFT)
2550 
2551 /*
2552  * FORCE_ERR_F_SEQ_MATCH_VC12 (RW)
2553  *
2554  * error matching frame start with frame end for virtual channel 12
2555  */
2556 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK (0x1000U)
2557 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT (12U)
2558 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK)
2559 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC12_SHIFT)
2560 
2561 /*
2562  * FORCE_ERR_F_SEQ_MATCH_VC11 (RW)
2563  *
2564  * error matching frame start with frame end for virtual channel 11
2565  */
2566 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK (0x800U)
2567 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT (11U)
2568 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK)
2569 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC11_SHIFT)
2570 
2571 /*
2572  * FORCE_ERR_F_SEQ_MATCH_VC10 (RW)
2573  *
2574  * error matching frame start with frame end for virtual channel 10
2575  */
2576 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK (0x400U)
2577 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT (10U)
2578 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK)
2579 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC10_SHIFT)
2580 
2581 /*
2582  * FORCE_ERR_F_SEQ_MATCH_VC9 (RW)
2583  *
2584  * error matching frame start with frame end for virtual channel 9
2585  */
2586 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK (0x200U)
2587 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT (9U)
2588 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK)
2589 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC9_SHIFT)
2590 
2591 /*
2592  * FORCE_ERR_F_SEQ_MATCH_VC8 (RW)
2593  *
2594  * error matching frame start with frame end for virtual channel 8
2595  */
2596 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK (0x100U)
2597 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT (8U)
2598 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK)
2599 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC8_SHIFT)
2600 
2601 /*
2602  * FORCE_ERR_F_SEQ_MATCH_VC7 (RW)
2603  *
2604  * error matching frame start with frame end for virtual channel 7
2605  */
2606 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK (0x80U)
2607 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT (7U)
2608 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK)
2609 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC7_SHIFT)
2610 
2611 /*
2612  * FORCE_ERR_F_SEQ_MATCH_VC6 (RW)
2613  *
2614  * error matching frame start with frame end for virtual channel 6
2615  */
2616 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK (0x40U)
2617 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT (6U)
2618 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK)
2619 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC6_SHIFT)
2620 
2621 /*
2622  * FORCE_ERR_F_SEQ_MATCH_VC5 (RW)
2623  *
2624  * error matching frame start with frame end for virtual channel 5
2625  */
2626 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK (0x20U)
2627 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT (5U)
2628 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK)
2629 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC5_SHIFT)
2630 
2631 /*
2632  * FORCE_ERR_F_SEQ_MATCH_VC4 (RW)
2633  *
2634  * error matching frame start with frame end for virtual channel 4
2635  */
2636 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK (0x10U)
2637 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT (4U)
2638 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK)
2639 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC4_SHIFT)
2640 
2641 /*
2642  * FORCE_ERR_F_SEQ_MATCH_VC3 (RW)
2643  *
2644  * error matching frame start with frame end for virtual channel 3
2645  */
2646 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK (0x8U)
2647 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT (3U)
2648 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK)
2649 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC3_SHIFT)
2650 
2651 /*
2652  * FORCE_ERR_F_SEQ_MATCH_VC2 (RW)
2653  *
2654  * error matching frame start with frame end for virtual channel 2
2655  */
2656 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK (0x4U)
2657 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT (2U)
2658 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK)
2659 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC2_SHIFT)
2660 
2661 /*
2662  * FORCE_ERR_F_SEQ_MATCH_VC1 (RW)
2663  *
2664  * error matching frame start with frame end for virtual channel 1
2665  */
2666 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK (0x2U)
2667 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT (1U)
2668 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK)
2669 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC1_SHIFT)
2670 
2671 /*
2672  * FORCE_ERR_F_SEQ_MATCH_VC0 (RW)
2673  *
2674  * error matching frame start with frame end for virtual channel 0
2675  */
2676 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK (0x1U)
2677 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT (0U)
2678 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK)
2679 #define MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_SEQ_FRAME_FATAL_FORCE_ERR_F_SEQ_MATCH_VC0_SHIFT)
2680 
2681 /* Bitfield definition for register: INT_ST_CRC_FRAME_FATAL */
2682 /*
2683  * ERR_F_CRC_MATCH_VC15 (RC)
2684  *
2685  * error matching frame start with frame end for virtual channel 15
2686  */
2687 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_MASK (0x8000U)
2688 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_SHIFT (15U)
2689 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC15_SHIFT)
2690 
2691 /*
2692  * ERR_F_CRC_MATCH_VC14 (RC)
2693  *
2694  * error matching frame start with frame end for virtual channel 14
2695  */
2696 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_MASK (0x4000U)
2697 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_SHIFT (14U)
2698 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC14_SHIFT)
2699 
2700 /*
2701  * ERR_F_CRC_MATCH_VC13 (RC)
2702  *
2703  * error matching frame start with frame end for virtual channel 13
2704  */
2705 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_MASK (0x2000U)
2706 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_SHIFT (13U)
2707 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC13_SHIFT)
2708 
2709 /*
2710  * ERR_F_CRC_MATCH_VC12 (RC)
2711  *
2712  * error matching frame start with frame end for virtual channel 12
2713  */
2714 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_MASK (0x1000U)
2715 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_SHIFT (12U)
2716 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC12_SHIFT)
2717 
2718 /*
2719  * ERR_F_CRC_MATCH_VC11 (RC)
2720  *
2721  * error matching frame start with frame end for virtual channel 11
2722  */
2723 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_MASK (0x800U)
2724 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_SHIFT (11U)
2725 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC11_SHIFT)
2726 
2727 /*
2728  * ERR_F_CRC_MATCH_VC10 (RC)
2729  *
2730  * error matching frame start with frame end for virtual channel 10
2731  */
2732 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_MASK (0x400U)
2733 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_SHIFT (10U)
2734 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC10_SHIFT)
2735 
2736 /*
2737  * ERR_F_CRC_MATCH_VC9 (RC)
2738  *
2739  * error matching frame start with frame end for virtual channel 9
2740  */
2741 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_MASK (0x200U)
2742 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_SHIFT (9U)
2743 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC9_SHIFT)
2744 
2745 /*
2746  * ERR_F_CRC_MATCH_VC8 (RC)
2747  *
2748  * error matching frame start with frame end for virtual channel 8
2749  */
2750 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_MASK (0x100U)
2751 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_SHIFT (8U)
2752 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC8_SHIFT)
2753 
2754 /*
2755  * ERR_F_CRC_MATCH_VC7 (RC)
2756  *
2757  * error matching frame start with frame end for virtual channel 7
2758  */
2759 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_MASK (0x80U)
2760 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_SHIFT (7U)
2761 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC7_SHIFT)
2762 
2763 /*
2764  * ERR_F_CRC_MATCH_VC6 (RC)
2765  *
2766  * error matching frame start with frame end for virtual channel 6
2767  */
2768 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_MASK (0x40U)
2769 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_SHIFT (6U)
2770 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC6_SHIFT)
2771 
2772 /*
2773  * ERR_F_CRC_MATCH_VC5 (RC)
2774  *
2775  * error matching frame start with frame end for virtual channel 5
2776  */
2777 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_MASK (0x20U)
2778 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_SHIFT (5U)
2779 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC5_SHIFT)
2780 
2781 /*
2782  * ERR_F_CRC_MATCH_VC4 (RC)
2783  *
2784  * error matching frame start with frame end for virtual channel 4
2785  */
2786 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_MASK (0x10U)
2787 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_SHIFT (4U)
2788 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC4_SHIFT)
2789 
2790 /*
2791  * ERR_F_CRC_MATCH_VC3 (RC)
2792  *
2793  * error matching frame start with frame end for virtual channel 3
2794  */
2795 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_MASK (0x8U)
2796 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_SHIFT (3U)
2797 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC3_SHIFT)
2798 
2799 /*
2800  * ERR_F_CRC_MATCH_VC2 (RC)
2801  *
2802  * error matching frame start with frame end for virtual channel 2
2803  */
2804 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_MASK (0x4U)
2805 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_SHIFT (2U)
2806 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC2_SHIFT)
2807 
2808 /*
2809  * ERR_F_CRC_MATCH_VC1 (RC)
2810  *
2811  * error matching frame start with frame end for virtual channel 1
2812  */
2813 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_MASK (0x2U)
2814 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_SHIFT (1U)
2815 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC1_SHIFT)
2816 
2817 /*
2818  * ERR_F_CRC_MATCH_VC0 (RC)
2819  *
2820  * error matching frame start with frame end for virtual channel 0
2821  */
2822 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_MASK (0x1U)
2823 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_SHIFT (0U)
2824 #define MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_CRC_FRAME_FATAL_ERR_F_CRC_MATCH_VC0_SHIFT)
2825 
2826 /* Bitfield definition for register: INT_MSK_CRC_FRAME_FATAL */
2827 /*
2828  * MSK_ERR_F_CRC_MATCH_VC15 (RW)
2829  *
2830  * error matching frame start with frame end for virtual channel 15
2831  */
2832 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK (0x8000U)
2833 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT (15U)
2834 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK)
2835 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC15_SHIFT)
2836 
2837 /*
2838  * MSK_ERR_F_CRC_MATCH_VC14 (RW)
2839  *
2840  * error matching frame start with frame end for virtual channel 14
2841  */
2842 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK (0x4000U)
2843 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT (14U)
2844 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK)
2845 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC14_SHIFT)
2846 
2847 /*
2848  * MSK_ERR_F_CRC_MATCH_VC13 (RW)
2849  *
2850  * error matching frame start with frame end for virtual channel 13
2851  */
2852 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK (0x2000U)
2853 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT (13U)
2854 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK)
2855 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC13_SHIFT)
2856 
2857 /*
2858  * MSK_ERR_F_CRC_MATCH_VC12 (RW)
2859  *
2860  * error matching frame start with frame end for virtual channel 12
2861  */
2862 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK (0x1000U)
2863 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT (12U)
2864 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK)
2865 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC12_SHIFT)
2866 
2867 /*
2868  * MSK_ERR_F_CRC_MATCH_VC11 (RW)
2869  *
2870  * error matching frame start with frame end for virtual channel 11
2871  */
2872 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK (0x800U)
2873 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT (11U)
2874 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK)
2875 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC11_SHIFT)
2876 
2877 /*
2878  * MSK_ERR_F_CRC_MATCH_VC10 (RW)
2879  *
2880  * error matching frame start with frame end for virtual channel 10
2881  */
2882 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK (0x400U)
2883 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT (10U)
2884 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK)
2885 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC10_SHIFT)
2886 
2887 /*
2888  * MSK_ERR_F_CRC_MATCH_VC9 (RW)
2889  *
2890  * error matching frame start with frame end for virtual channel 9
2891  */
2892 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK (0x200U)
2893 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT (9U)
2894 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK)
2895 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC9_SHIFT)
2896 
2897 /*
2898  * MSK_ERR_F_CRC_MATCH_VC8 (RW)
2899  *
2900  * error matching frame start with frame end for virtual channel 8
2901  */
2902 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK (0x100U)
2903 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT (8U)
2904 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK)
2905 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC8_SHIFT)
2906 
2907 /*
2908  * MSK_ERR_F_CRC_MATCH_VC7 (RW)
2909  *
2910  * error matching frame start with frame end for virtual channel 7
2911  */
2912 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK (0x80U)
2913 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT (7U)
2914 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK)
2915 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC7_SHIFT)
2916 
2917 /*
2918  * MSK_ERR_F_CRC_MATCH_VC6 (RW)
2919  *
2920  * error matching frame start with frame end for virtual channel 6
2921  */
2922 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK (0x40U)
2923 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT (6U)
2924 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK)
2925 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC6_SHIFT)
2926 
2927 /*
2928  * MSK_ERR_F_CRC_MATCH_VC5 (RW)
2929  *
2930  * error matching frame start with frame end for virtual channel 5
2931  */
2932 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK (0x20U)
2933 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT (5U)
2934 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK)
2935 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC5_SHIFT)
2936 
2937 /*
2938  * MSK_ERR_F_CRC_MATCH_VC4 (RW)
2939  *
2940  * error matching frame start with frame end for virtual channel 4
2941  */
2942 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK (0x10U)
2943 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT (4U)
2944 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK)
2945 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC4_SHIFT)
2946 
2947 /*
2948  * MSK_ERR_F_CRC_MATCH_VC3 (RW)
2949  *
2950  * error matching frame start with frame end for virtual channel 3
2951  */
2952 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK (0x8U)
2953 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT (3U)
2954 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK)
2955 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC3_SHIFT)
2956 
2957 /*
2958  * MSK_ERR_F_CRC_MATCH_VC2 (RW)
2959  *
2960  * error matching frame start with frame end for virtual channel 2
2961  */
2962 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK (0x4U)
2963 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT (2U)
2964 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK)
2965 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC2_SHIFT)
2966 
2967 /*
2968  * MSK_ERR_F_CRC_MATCH_VC1 (RW)
2969  *
2970  * error matching frame start with frame end for virtual channel 1
2971  */
2972 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK (0x2U)
2973 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT (1U)
2974 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK)
2975 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC1_SHIFT)
2976 
2977 /*
2978  * MSK_ERR_F_CRC_MATCH_VC0 (RW)
2979  *
2980  * error matching frame start with frame end for virtual channel 0
2981  */
2982 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK (0x1U)
2983 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT (0U)
2984 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK)
2985 #define MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_CRC_FRAME_FATAL_MSK_ERR_F_CRC_MATCH_VC0_SHIFT)
2986 
2987 /* Bitfield definition for register: INT_FORCE_CRC_FRAME_FATAL */
2988 /*
2989  * FORCE_ERR_F_CRC_MATCH_VC15 (RW)
2990  *
2991  * error matching frame start with frame end for virtual channel 15
2992  */
2993 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK (0x8000U)
2994 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT (15U)
2995 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK)
2996 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC15_SHIFT)
2997 
2998 /*
2999  * FORCE_ERR_F_CRC_MATCH_VC14 (RW)
3000  *
3001  * error matching frame start with frame end for virtual channel 14
3002  */
3003 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK (0x4000U)
3004 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT (14U)
3005 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK)
3006 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC14_SHIFT)
3007 
3008 /*
3009  * FORCE_ERR_F_CRC_MATCH_VC13 (RW)
3010  *
3011  * error matching frame start with frame end for virtual channel 13
3012  */
3013 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK (0x2000U)
3014 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT (13U)
3015 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK)
3016 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC13_SHIFT)
3017 
3018 /*
3019  * FORCE_ERR_F_CRC_MATCH_VC12 (RW)
3020  *
3021  * error matching frame start with frame end for virtual channel 12
3022  */
3023 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK (0x1000U)
3024 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT (12U)
3025 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK)
3026 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC12_SHIFT)
3027 
3028 /*
3029  * FORCE_ERR_F_CRC_MATCH_VC11 (RW)
3030  *
3031  * error matching frame start with frame end for virtual channel 11
3032  */
3033 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK (0x800U)
3034 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT (11U)
3035 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK)
3036 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC11_SHIFT)
3037 
3038 /*
3039  * FORCE_ERR_F_CRC_MATCH_VC10 (RW)
3040  *
3041  * error matching frame start with frame end for virtual channel 10
3042  */
3043 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK (0x400U)
3044 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT (10U)
3045 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK)
3046 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC10_SHIFT)
3047 
3048 /*
3049  * FORCE_ERR_F_CRC_MATCH_VC9 (RW)
3050  *
3051  * error matching frame start with frame end for virtual channel 9
3052  */
3053 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK (0x200U)
3054 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT (9U)
3055 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK)
3056 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC9_SHIFT)
3057 
3058 /*
3059  * FORCE_ERR_F_CRC_MATCH_VC8 (RW)
3060  *
3061  * error matching frame start with frame end for virtual channel 8
3062  */
3063 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK (0x100U)
3064 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT (8U)
3065 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK)
3066 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC8_SHIFT)
3067 
3068 /*
3069  * FORCE_ERR_F_CRC_MATCH_VC7 (RW)
3070  *
3071  * error matching frame start with frame end for virtual channel 7
3072  */
3073 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK (0x80U)
3074 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT (7U)
3075 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK)
3076 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC7_SHIFT)
3077 
3078 /*
3079  * FORCE_ERR_F_CRC_MATCH_VC6 (RW)
3080  *
3081  * error matching frame start with frame end for virtual channel 6
3082  */
3083 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK (0x40U)
3084 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT (6U)
3085 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK)
3086 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC6_SHIFT)
3087 
3088 /*
3089  * FORCE_ERR_F_CRC_MATCH_VC5 (RW)
3090  *
3091  * error matching frame start with frame end for virtual channel 5
3092  */
3093 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK (0x20U)
3094 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT (5U)
3095 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK)
3096 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC5_SHIFT)
3097 
3098 /*
3099  * FORCE_ERR_F_CRC_MATCH_VC4 (RW)
3100  *
3101  * error matching frame start with frame end for virtual channel 4
3102  */
3103 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK (0x10U)
3104 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT (4U)
3105 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK)
3106 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC4_SHIFT)
3107 
3108 /*
3109  * FORCE_ERR_F_CRC_MATCH_VC3 (RW)
3110  *
3111  * error matching frame start with frame end for virtual channel 3
3112  */
3113 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK (0x8U)
3114 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT (3U)
3115 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK)
3116 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC3_SHIFT)
3117 
3118 /*
3119  * FORCE_ERR_F_CRC_MATCH_VC2 (RW)
3120  *
3121  * error matching frame start with frame end for virtual channel 2
3122  */
3123 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK (0x4U)
3124 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT (2U)
3125 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK)
3126 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC2_SHIFT)
3127 
3128 /*
3129  * FORCE_ERR_F_CRC_MATCH_VC1 (RW)
3130  *
3131  * error matching frame start with frame end for virtual channel 1
3132  */
3133 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK (0x2U)
3134 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT (1U)
3135 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK)
3136 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC1_SHIFT)
3137 
3138 /*
3139  * FORCE_ERR_F_CRC_MATCH_VC0 (RW)
3140  *
3141  * error matching frame start with frame end for virtual channel 0
3142  */
3143 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK (0x1U)
3144 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT (0U)
3145 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK)
3146 #define MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_CRC_FRAME_FATAL_FORCE_ERR_F_CRC_MATCH_VC0_SHIFT)
3147 
3148 /* Bitfield definition for register: INT_ST_PLD_CRC_FRAME_FATAL */
3149 /*
3150  * ERR_CRC_MATCH_VC15 (RC)
3151  *
3152  * error matching frame start with frame end for virtual channel 15
3153  */
3154 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_MASK (0x8000U)
3155 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_SHIFT (15U)
3156 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC15_SHIFT)
3157 
3158 /*
3159  * ERR_CRC_MATCH_VC14 (RC)
3160  *
3161  * error matching frame start with frame end for virtual channel 14
3162  */
3163 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_MASK (0x4000U)
3164 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_SHIFT (14U)
3165 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC14_SHIFT)
3166 
3167 /*
3168  * ERR_CRC_MATCH_VC13 (RC)
3169  *
3170  * error matching frame start with frame end for virtual channel 13
3171  */
3172 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_MASK (0x2000U)
3173 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_SHIFT (13U)
3174 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC13_SHIFT)
3175 
3176 /*
3177  * ERR_CRC_MATCH_VC12 (RC)
3178  *
3179  * error matching frame start with frame end for virtual channel 12
3180  */
3181 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_MASK (0x1000U)
3182 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_SHIFT (12U)
3183 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC12_SHIFT)
3184 
3185 /*
3186  * ERR_CRC_MATCH_VC11 (RC)
3187  *
3188  * error matching frame start with frame end for virtual channel 11
3189  */
3190 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_MASK (0x800U)
3191 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_SHIFT (11U)
3192 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC11_SHIFT)
3193 
3194 /*
3195  * ERR_CRC_MATCH_VC10 (RC)
3196  *
3197  * error matching frame start with frame end for virtual channel 10
3198  */
3199 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_MASK (0x400U)
3200 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_SHIFT (10U)
3201 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC10_SHIFT)
3202 
3203 /*
3204  * ERR_CRC_MATCH_VC9 (RC)
3205  *
3206  * error matching frame start with frame end for virtual channel 9
3207  */
3208 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_MASK (0x200U)
3209 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_SHIFT (9U)
3210 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC9_SHIFT)
3211 
3212 /*
3213  * ERR_CRC_MATCH_VC8 (RC)
3214  *
3215  * error matching frame start with frame end for virtual channel 8
3216  */
3217 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_MASK (0x100U)
3218 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_SHIFT (8U)
3219 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC8_SHIFT)
3220 
3221 /*
3222  * ERR_CRC_MATCH_VC7 (RC)
3223  *
3224  * error matching frame start with frame end for virtual channel 7
3225  */
3226 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_MASK (0x80U)
3227 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_SHIFT (7U)
3228 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC7_SHIFT)
3229 
3230 /*
3231  * ERR_CRC_MATCH_VC6 (RC)
3232  *
3233  * error matching frame start with frame end for virtual channel 6
3234  */
3235 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_MASK (0x40U)
3236 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_SHIFT (6U)
3237 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC6_SHIFT)
3238 
3239 /*
3240  * ERR_CRC_MATCH_VC5 (RC)
3241  *
3242  * error matching frame start with frame end for virtual channel 5
3243  */
3244 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_MASK (0x20U)
3245 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_SHIFT (5U)
3246 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC5_SHIFT)
3247 
3248 /*
3249  * ERR_CRC_MATCH_VC4 (RC)
3250  *
3251  * error matching frame start with frame end for virtual channel 4
3252  */
3253 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_MASK (0x10U)
3254 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_SHIFT (4U)
3255 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC4_SHIFT)
3256 
3257 /*
3258  * ERR_CRC_MATCH_VC3 (RC)
3259  *
3260  * error matching frame start with frame end for virtual channel 3
3261  */
3262 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_MASK (0x8U)
3263 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_SHIFT (3U)
3264 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC3_SHIFT)
3265 
3266 /*
3267  * ERR_CRC_MATCH_VC2 (RC)
3268  *
3269  * error matching frame start with frame end for virtual channel 2
3270  */
3271 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_MASK (0x4U)
3272 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_SHIFT (2U)
3273 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC2_SHIFT)
3274 
3275 /*
3276  * ERR_CRC_MATCH_VC1 (RC)
3277  *
3278  * error matching frame start with frame end for virtual channel 1
3279  */
3280 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_MASK (0x2U)
3281 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_SHIFT (1U)
3282 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC1_SHIFT)
3283 
3284 /*
3285  * ERR_CRC_MATCH_VC0 (RC)
3286  *
3287  * error matching frame start with frame end for virtual channel 0
3288  */
3289 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_MASK (0x1U)
3290 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_SHIFT (0U)
3291 #define MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_ST_PLD_CRC_FRAME_FATAL_ERR_CRC_MATCH_VC0_SHIFT)
3292 
3293 /* Bitfield definition for register: INT_MSK_PLD_CRC_FRAME_FATAL */
3294 /*
3295  * MSK_ERR_CRC_MATCH_VC15 (RW)
3296  *
3297  * error matching frame start with frame end for virtual channel 15
3298  */
3299 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK (0x8000U)
3300 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT (15U)
3301 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK)
3302 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC15_SHIFT)
3303 
3304 /*
3305  * MSK_ERR_CRC_MATCH_VC14 (RW)
3306  *
3307  * error matching frame start with frame end for virtual channel 14
3308  */
3309 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK (0x4000U)
3310 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT (14U)
3311 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK)
3312 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC14_SHIFT)
3313 
3314 /*
3315  * MSK_ERR_CRC_MATCH_VC13 (RW)
3316  *
3317  * error matching frame start with frame end for virtual channel 13
3318  */
3319 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK (0x2000U)
3320 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT (13U)
3321 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK)
3322 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC13_SHIFT)
3323 
3324 /*
3325  * MSK_ERR_CRC_MATCH_VC12 (RW)
3326  *
3327  * error matching frame start with frame end for virtual channel 12
3328  */
3329 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK (0x1000U)
3330 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT (12U)
3331 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK)
3332 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC12_SHIFT)
3333 
3334 /*
3335  * MSK_ERR_CRC_MATCH_VC11 (RW)
3336  *
3337  * error matching frame start with frame end for virtual channel 11
3338  */
3339 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK (0x800U)
3340 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT (11U)
3341 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK)
3342 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC11_SHIFT)
3343 
3344 /*
3345  * MSK_ERR_CRC_MATCH_VC10 (RW)
3346  *
3347  * error matching frame start with frame end for virtual channel 10
3348  */
3349 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK (0x400U)
3350 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT (10U)
3351 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK)
3352 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC10_SHIFT)
3353 
3354 /*
3355  * MSK_ERR_CRC_MATCH_VC9 (RW)
3356  *
3357  * error matching frame start with frame end for virtual channel 9
3358  */
3359 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK (0x200U)
3360 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT (9U)
3361 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK)
3362 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC9_SHIFT)
3363 
3364 /*
3365  * MSK_ERR_CRC_MATCH_VC8 (RW)
3366  *
3367  * error matching frame start with frame end for virtual channel 8
3368  */
3369 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK (0x100U)
3370 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT (8U)
3371 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK)
3372 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC8_SHIFT)
3373 
3374 /*
3375  * MSK_ERR_CRC_MATCH_VC7 (RW)
3376  *
3377  * error matching frame start with frame end for virtual channel 7
3378  */
3379 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK (0x80U)
3380 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT (7U)
3381 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK)
3382 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC7_SHIFT)
3383 
3384 /*
3385  * MSK_ERR_CRC_MATCH_VC6 (RW)
3386  *
3387  * error matching frame start with frame end for virtual channel 6
3388  */
3389 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK (0x40U)
3390 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT (6U)
3391 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK)
3392 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC6_SHIFT)
3393 
3394 /*
3395  * MSK_ERR_CRC_MATCH_VC5 (RW)
3396  *
3397  * error matching frame start with frame end for virtual channel 5
3398  */
3399 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK (0x20U)
3400 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT (5U)
3401 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK)
3402 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC5_SHIFT)
3403 
3404 /*
3405  * MSK_ERR_CRC_MATCH_VC4 (RW)
3406  *
3407  * error matching frame start with frame end for virtual channel 4
3408  */
3409 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK (0x10U)
3410 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT (4U)
3411 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK)
3412 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC4_SHIFT)
3413 
3414 /*
3415  * MSK_ERR_CRC_MATCH_VC3 (RW)
3416  *
3417  * error matching frame start with frame end for virtual channel 3
3418  */
3419 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK (0x8U)
3420 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT (3U)
3421 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK)
3422 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC3_SHIFT)
3423 
3424 /*
3425  * MSK_ERR_CRC_MATCH_VC2 (RW)
3426  *
3427  * error matching frame start with frame end for virtual channel 2
3428  */
3429 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK (0x4U)
3430 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT (2U)
3431 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK)
3432 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC2_SHIFT)
3433 
3434 /*
3435  * MSK_ERR_CRC_MATCH_VC1 (RW)
3436  *
3437  * error matching frame start with frame end for virtual channel 1
3438  */
3439 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK (0x2U)
3440 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT (1U)
3441 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK)
3442 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC1_SHIFT)
3443 
3444 /*
3445  * MSK_ERR_CRC_MATCH_VC0 (RW)
3446  *
3447  * error matching frame start with frame end for virtual channel 0
3448  */
3449 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK (0x1U)
3450 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT (0U)
3451 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK)
3452 #define MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_MSK_PLD_CRC_FRAME_FATAL_MSK_ERR_CRC_MATCH_VC0_SHIFT)
3453 
3454 /* Bitfield definition for register: INT_FORCE_PLD_CRC_FRAME_FATAL */
3455 /*
3456  * FORCE_ERR_CRC_MATCH_VC15 (RW)
3457  *
3458  * error matching frame start with frame end for virtual channel 15
3459  */
3460 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK (0x8000U)
3461 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT (15U)
3462 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK)
3463 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC15_SHIFT)
3464 
3465 /*
3466  * FORCE_ERR_CRC_MATCH_VC14 (RW)
3467  *
3468  * error matching frame start with frame end for virtual channel 14
3469  */
3470 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK (0x4000U)
3471 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT (14U)
3472 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK)
3473 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC14_SHIFT)
3474 
3475 /*
3476  * FORCE_ERR_CRC_MATCH_VC13 (RW)
3477  *
3478  * error matching frame start with frame end for virtual channel 13
3479  */
3480 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK (0x2000U)
3481 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT (13U)
3482 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK)
3483 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC13_SHIFT)
3484 
3485 /*
3486  * FORCE_ERR_CRC_MATCH_VC12 (RW)
3487  *
3488  * error matching frame start with frame end for virtual channel 12
3489  */
3490 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK (0x1000U)
3491 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT (12U)
3492 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK)
3493 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC12_SHIFT)
3494 
3495 /*
3496  * FORCE_ERR_CRC_MATCH_VC11 (RW)
3497  *
3498  * error matching frame start with frame end for virtual channel 11
3499  */
3500 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK (0x800U)
3501 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT (11U)
3502 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK)
3503 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC11_SHIFT)
3504 
3505 /*
3506  * FORCE_ERR_CRC_MATCH_VC10 (RW)
3507  *
3508  * error matching frame start with frame end for virtual channel 10
3509  */
3510 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK (0x400U)
3511 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT (10U)
3512 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK)
3513 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC10_SHIFT)
3514 
3515 /*
3516  * FORCE_ERR_CRC_MATCH_VC9 (RW)
3517  *
3518  * error matching frame start with frame end for virtual channel 9
3519  */
3520 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK (0x200U)
3521 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT (9U)
3522 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK)
3523 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC9_SHIFT)
3524 
3525 /*
3526  * FORCE_ERR_CRC_MATCH_VC8 (RW)
3527  *
3528  * error matching frame start with frame end for virtual channel 8
3529  */
3530 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK (0x100U)
3531 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT (8U)
3532 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK)
3533 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC8_SHIFT)
3534 
3535 /*
3536  * FORCE_ERR_CRC_MATCH_VC7 (RW)
3537  *
3538  * error matching frame start with frame end for virtual channel 7
3539  */
3540 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK (0x80U)
3541 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT (7U)
3542 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK)
3543 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC7_SHIFT)
3544 
3545 /*
3546  * FORCE_ERR_CRC_MATCH_VC6 (RW)
3547  *
3548  * error matching frame start with frame end for virtual channel 6
3549  */
3550 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK (0x40U)
3551 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT (6U)
3552 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK)
3553 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC6_SHIFT)
3554 
3555 /*
3556  * FORCE_ERR_CRC_MATCH_VC5 (RW)
3557  *
3558  * error matching frame start with frame end for virtual channel 5
3559  */
3560 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK (0x20U)
3561 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT (5U)
3562 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK)
3563 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC5_SHIFT)
3564 
3565 /*
3566  * FORCE_ERR_CRC_MATCH_VC4 (RW)
3567  *
3568  * error matching frame start with frame end for virtual channel 4
3569  */
3570 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK (0x10U)
3571 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT (4U)
3572 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK)
3573 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC4_SHIFT)
3574 
3575 /*
3576  * FORCE_ERR_CRC_MATCH_VC3 (RW)
3577  *
3578  * error matching frame start with frame end for virtual channel 3
3579  */
3580 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK (0x8U)
3581 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT (3U)
3582 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK)
3583 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC3_SHIFT)
3584 
3585 /*
3586  * FORCE_ERR_CRC_MATCH_VC2 (RW)
3587  *
3588  * error matching frame start with frame end for virtual channel 2
3589  */
3590 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK (0x4U)
3591 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT (2U)
3592 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK)
3593 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC2_SHIFT)
3594 
3595 /*
3596  * FORCE_ERR_CRC_MATCH_VC1 (RW)
3597  *
3598  * error matching frame start with frame end for virtual channel 1
3599  */
3600 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK (0x2U)
3601 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT (1U)
3602 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK)
3603 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC1_SHIFT)
3604 
3605 /*
3606  * FORCE_ERR_CRC_MATCH_VC0 (RW)
3607  *
3608  * error matching frame start with frame end for virtual channel 0
3609  */
3610 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK (0x1U)
3611 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT (0U)
3612 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SET(x) (((uint32_t)(x) << MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK)
3613 #define MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_GET(x) (((uint32_t)(x) & MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_MASK) >> MIPI_CSI_INT_FORCE_PLD_CRC_FRAME_FATAL_FORCE_ERR_CRC_MATCH_VC0_SHIFT)
3614 
3615 
3616 
3617 
3618 #endif /* HPM_MIPI_CSI_H */
MIPI_CSI_Type
Definition: hpm_mipi_csi_regs.h:12