hpm_mmc_drv.h

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/*
 * Copyright (c) 2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
 
#ifndef HPM_MMC_DRV_H
#define HPM_MMC_DRV_H
 
#include "hpm_common.h"
#include "hpm_mmc_regs.h"
/* trigger source to update position parameter */
typedef enum {
    mmc_pos_update_by_timestamp = 0,
    mmc_pos_update_by_intrgr0_rise_edge = 1,
    mmc_pos_update_by_intrgr1_rise_edge = 2,
    mmc_pos_update_by_outtrgr0_rise_edge = 3,
    mmc_pos_update_by_outtrgr1_rise_edge = 4,
    mmc_pos_update_by_self_pos_thr = 5,
    mmc_pos_update_by_self_speed_thr = 6,
} mmc_pos_update_trigger_t;
 
 
/* cmd mask to update position parameter */
typedef enum {
    mmc_pos_update_none = 0,
    mmc_pos_update_position = 1 << 0,
    mmc_pos_update_revolution = 1 << 1,
    mmc_pos_update_speed = 1 << 2,
    mmc_pos_update_accel = 1 << 3,
    mmc_pos_update_all = 0b1111,
} mmc_pos_update_cmd_mask_t;
 
typedef enum {
    mmc_coef_not_update = 0,
    mmc_coef_p_update = 1 << 0,
    mmc_coef_i_update = 1 << 1,
    mmc_coef_a_update = 1 << 2,
    mmc_coef_update_all = 0b111,
} mmc_coef_update_cmd_mask_t;
 
typedef struct {
    bool discrete_pos_mode;
    uint32_t discrete_line;
    uint32_t continuous_step_thr;
    uint32_t continuous_circ_thr;
    uint32_t oosync_theta_thr;
} mmc_track_pos_mode_t;
 
typedef struct {
    bool force_accel_to_zero;
    bool en_ms_coef;
    bool open_loop_mode;
    bool pos_16bit_type;      /* true for output 16bit position, false for output 32bit position */
    bool sync_new_pos;        /* predictor base new track position data */
    mmc_track_pos_mode_t pos_mode;
} mmc_track_mode_t;
 
typedef struct {
    uint32_t pos_time;
    uint32_t position;
    int32_t revolution;
    double speed;
    double accel;
    uint32_t cmd_mask; 
    uint32_t trigger;  
} mmc_pos_or_delta_pos_input_t;
 
typedef struct {
    uint32_t coef_time;
    double coef_p;
    double coef_i;
    double coef_a;
    uint32_t cmd_mask; /* cmd to select change which parameter */
} mmc_coef_input_t;
 
typedef struct {
    uint32_t err_thr;
    uint32_t hold_time;
    double coef_p;
    double coef_i;
    double coef_a;
} mmc_coef_trig_config_t;
 
typedef struct {
    uint32_t time;
    uint32_t position;
    int32_t revolution;
    double speed;
    double accel;
} mmc_pos_out_t;
 
typedef struct {
    double coef_p;
    double coef_i;
    double coef_a;
} mmc_coef_out_t;
 
/* track event, definition align with interrupt mask and status mask */
typedef enum {
    mmc_track_shadow_read_done = 1 << 0,
    mmc_track_init_coefs_done = 1 << 1,
    mmc_track_init_pos_done = 1 << 2,
    mmc_track_oosync = 1 << 4,
    mmc_track_idle = 1 << 5, 
    mmc_pred1_init_pos_done = 1 << 6,
    mmc_pred0_init_pos_done = 1 << 7,
    mmc_track_init_delta_pos_done = 1 << 8,
    mmc_track_pos_trig_valid = 1 << 9,
    mmc_track_speed_trig_valid = 1 << 10,
} mmc_track_event_t;
 
typedef enum {
    mmc_pred_idle = MMC_BR_BR_ST_IDLE_MASK,
    mmc_pred_init_delta_pos_done = MMC_BR_BR_ST_INI_DELTA_POS_DONE_MASK,
    mmc_pred_pos_trig_valid = MMC_BR_BR_ST_POS_TRG_VLD_MASK,
    mmc_pred_speed_trig_valid = MMC_BR_BR_ST_SPEED_TRG_VLD_MASK,
    mmc_pred_open_loop = MMC_BR_BR_ST_OPEN_LOOP_ST_MASK,
} mmc_pred_event_t;
 
typedef enum {
    mmc_pred_pos_trig_valid_int = MMC_BR_BR_CTRL_POS_TRG_VALID_IE_MASK,
    mmc_pred_speed_trig_valid_int = MMC_BR_BR_CTRL_SPEED_TRG_VALID_IE_MASK,
    mmc_pred_init_delta_pos_done_int = MMC_BR_BR_CTRL_INI_DELTA_POS_DONE_IE_MASK
} mmc_pred_int_t;
 
typedef struct {
    bool speed_trig_int;
    bool position_trig_int;
    bool delta_pos_done_trig_int;
    bool open_loop_mode;
    uint8_t pred_mode;
    uint8_t not_first_pred_trig_type;
    uint8_t first_pred_trig_type;
} mmc_pred_mode_t;
 
typedef enum {
    mmc_pred_not_reload_pos_cmd = 0,
    mmc_pred_0_reload_pos_cmd = 2,
    mmc_pred_1_reload_pos_cmd = 1,
    mmc_pred_both_reload_pos_cmd = 3,
} mmc_pred_reload_pos_cmd_t;
 
typedef enum {
    mmc_pred_by_period = 0,
    mmc_pred_continuously_repeat = 1,
    mmc_pred_only_once = 2,
} mmc_pred_time_t;
 
/* using for mmc_pred_by_period mode */
typedef struct {
    uint32_t offset_time;
    uint32_t period_time;
    uint32_t first_time;
} mmc_pred_period_time_t;
 
typedef struct {
    bool less_than;         
    bool enable;
    uint32_t position_thr;  
    int32_t revolution_thr; 
} mmc_pos_trig_t;
 
typedef struct {
    bool absolute_compare; 
    bool less_than;        
    bool enable;
    int32_t speed_thr;
} mmc_speed_trig_t;
 
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void mmc_set_sysclk_freq(MMC_Type *base, uint32_t freq)
{
    uint32_t period;
    base->SYSCLK_FREQ = freq;
    /* 1/freq *(2^24)*(2^20) */
    period = (uint32_t)((double)(1 << 20) * (1 << 24) / freq);
    base->SYSCLK_PERIOD = period;
}
 
static inline void mmc_software_reset(MMC_Type *base)
{
    base->CR |= MMC_CR_SFTRST_MASK;
    base->CR &= ~MMC_CR_SFTRST_MASK;
}
 
static inline void mmc_enable_module(MMC_Type *base)
{
    base->CR |= MMC_CR_MOD_EN_MASK;
}
 
static inline void mmc_disable_module(MMC_Type *base)
{
    base->CR &= ~MMC_CR_MOD_EN_MASK;
}
 
static inline void mmc_track_set_open_loop_mode(MMC_Type *base, bool open_loop)
{
    if (open_loop) {
        base->CR |= MMC_CR_OPEN_LOOP_MODE_MASK;
    } else {
        base->CR &= ~MMC_CR_OPEN_LOOP_MODE_MASK;
    }
}
 
static inline void mmc_track_set_adjop_mode(MMC_Type *base, bool adjop)
{
    if (adjop) {
        base->CR |= MMC_CR_ADJOP_MASK;
    } else {
        base->CR &= ~MMC_CR_ADJOP_MASK;
    }
}
 
static inline void mmc_track_enable_shadow_read(MMC_Type *base)
{
    base->CR |= MMC_CR_SHADOW_RD_REQ_MASK;
    /* SHADOW_RD_REQ clear indicates that the shadow is complete */
    while ((base->CR & MMC_CR_SHADOW_RD_REQ_MASK) == MMC_CR_SHADOW_RD_REQ_MASK) {
    }
}
 
static inline void mmc_track_enable_interrupt(MMC_Type *base, uint32_t int_mask)
{
    base->INT_EN = int_mask;
}
 
static inline void mmc_track_disable_interrupt(MMC_Type *base, uint32_t int_mask)
{
    base->INT_EN &= ~int_mask;
}
 
static inline uint32_t mmc_track_get_status(MMC_Type *base)
{
    return base->STA;
}
 
static inline void mmc_track_clear_status(MMC_Type *base, uint32_t clr_mask)
{
    base->STA = clr_mask; /* W1C */
}
 
static inline void mmc_track_set_oosync_theta_threshold(MMC_Type *base, uint32_t threshold)
{
    base->OOSYNC_THETA_THR = MMC_OOSYNC_THETA_THR_VAL_SET(threshold);
}
 
void mmc_track_config_pos_mode(MMC_Type *base, mmc_track_pos_mode_t *mode);
 
void mmc_track_get_default_mode_config(MMC_Type *base, mmc_track_mode_t *config);
 
void mmc_track_config_mode(MMC_Type *base, mmc_track_mode_t *config);
 
void mmc_track_config_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para);
 
void mmc_track_config_delta_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para);
 
void mmc_track_config_coef_para(MMC_Type *base, mmc_coef_input_t *para);
 
void mmc_track_config_position_trig(MMC_Type *base, mmc_pos_trig_t *trig);
 
void mmc_track_config_speed_trig(MMC_Type *base, mmc_speed_trig_t *trig);
 
static inline void mmc_track_disable_position_trig(MMC_Type *base)
{
    base->POS_TRG_CFG &= ~MMC_POS_TRG_CFG_EN_MASK;
}
 
static inline void mmc_track_disable_speed_trig(MMC_Type *base)
{
    base->SPEED_TRG_CFG &= ~MMC_SPEED_TRG_CFG_EN_MASK;
}
 
void mmc_track_config_coef_trig(MMC_Type *base, uint8_t index, mmc_coef_trig_config_t *config);
 
void mmc_track_get_result(MMC_Type *base, mmc_pos_out_t *pos_out, mmc_coef_out_t *coef_out);
 
/* predictor */
static inline void mmc_enable_pred(MMC_Type *base, uint8_t index)
{
    base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_BR_EN_MASK;
}
 
static inline void mmc_disable_pred(MMC_Type *base, uint8_t index)
{
    base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_BR_EN_MASK;
}
 
static inline void mmc_pred_set_open_loop_mode(MMC_Type *base, uint8_t index, bool open_loop)
{
    if (open_loop) {
        base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK;
    } else {
        base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_OPEN_LOOP_MODE_MASK;
    }
}
 
static inline void mmc_pred_set_pred_time(MMC_Type *base, uint8_t index, mmc_pred_time_t time)
{
    base->BR[index].BR_CTRL &= ~MMC_BR_BR_CTRL_PRED_MODE_MASK;
    base->BR[index].BR_CTRL |= MMC_BR_BR_CTRL_PRED_MODE_SET(time);
}
 
static inline void mmc_pred_enable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask)
{
    base->BR[index].BR_CTRL |= int_mask;
}
 
static inline void mmc_pred_disable_interrupt(MMC_Type *base, uint8_t index, uint32_t int_mask)
{
    base->BR[index].BR_CTRL &= ~int_mask;
}
 
static inline uint32_t mmc_pred_get_status(MMC_Type *base, uint8_t index)
{
    return base->BR[index].BR_ST;
}
 
static inline void mmc_pred_clear_status(MMC_Type *base, uint8_t index, uint32_t clr_mask)
{
    base->BR[index].BR_ST = clr_mask; 
}
 
void mmc_pred_get_default_mode_config(MMC_Type *base, mmc_pred_mode_t *config);
 
void mmc_pred_config_mode(MMC_Type *base, uint8_t index, mmc_pred_mode_t *config);
 
void mmc_pred_config_pos_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para, bool req_reload);
 
static inline void mmc_pred_reload_pos_cmd(MMC_Type *base, mmc_pred_reload_pos_cmd_t cmd)
{
    base->CR &= ~(MMC_CR_INI_BR0_POS_REQ_MASK | MMC_CR_INI_BR0_POS_REQ_MASK);
    base->CR |= cmd << MMC_CR_INI_BR1_POS_REQ_SHIFT;
}
 
void mmc_pred_config_delta_para(MMC_Type *base, uint8_t index, mmc_pos_or_delta_pos_input_t *para);
 
void mmc_pred_config_period_time(MMC_Type *base, uint8_t index, mmc_pred_period_time_t *time);
 
void mmc_pred_config_position_trig(MMC_Type *base, uint8_t index, mmc_pos_trig_t *trig);
 
void mmc_pred_config_speed_trig(MMC_Type *base, uint8_t index, mmc_speed_trig_t *trig);
 
static inline void mmc_pred_disable_position_trig(MMC_Type *base, uint8_t index)
{
    base->BR[index].BR_TRG_POS_CFG &= ~MMC_BR_BR_TRG_POS_CFG_EN_MASK;
}
 
static inline void mmc_pred_disable_speed_trig(MMC_Type *base, uint8_t index)
{
    base->BR[index].BR_TRG_SPEED_CFG &= ~MMC_BR_BR_TRG_SPEED_CFG_EN_MASK;
}
 
void mmc_pred_get_result(MMC_Type *base, uint8_t index, mmc_pos_out_t *pos_out);
 
void mmc_get_default_pos_or_delta_pos_para(MMC_Type *base, mmc_pos_or_delta_pos_input_t *para);
 
 
#ifdef __cplusplus
}
#endif
#endif /* HPM_MMC_DRV_H */