HPM SDK
HPMicro Software Development Kit
hpm_tsw_regs.h
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1 /*
2  * Copyright (c) 2021-2024 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_TSW_H
10 #define HPM_TSW_H
11 
12 typedef struct {
13  __R uint8_t RESERVED0[4]; /* 0x0 - 0x3: Reserved */
14  __RW uint32_t LU_MAIN_CTRL; /* 0x4: LU_MAIN control */
15  __RW uint32_t LU_MAIN_HITMEM; /* 0x8: LU_MAIN hit */
16  __R uint32_t LU_MAIN_PARAM; /* 0xC: LU_MAIN parameter */
17  __RW uint32_t LU_MAIN_BYPASS; /* 0x10: LU_MAIN bypass */
18  __RW uint32_t LU_MAIN_PCP_REMAP; /* 0x14: LU_MAIN PCP remap */
19  __R uint32_t LU_MAIN_VERSION; /* 0x18: LU_MAIN version */
20  __R uint8_t RESERVED1[4]; /* 0x1C - 0x1F: Reserved */
21  __RW uint32_t LU_MAIN_INTF_ACTION; /* 0x20: LU_MAIN low word of action data for internal frames */
22  __R uint8_t RESERVED2[4]; /* 0x24 - 0x27: Reserved */
23  __RW uint32_t LU_MAIN_BC_ACTION; /* 0x28: LU_MAIN low word of action data for broadcast frames */
24  __R uint8_t RESERVED3[4]; /* 0x2C - 0x2F: Reserved */
25  __RW uint32_t LU_MAIN_NN_ACTION; /* 0x30: LU_MAIN low word of action data for unknown frames */
26  __R uint8_t RESERVED4[204]; /* 0x34 - 0xFF: Reserved */
27  __R uint32_t APB2AXIS_CAM_STS; /* 0x100: status register */
28  __R uint8_t RESERVED5[12]; /* 0x104 - 0x10F: Reserved */
29  __R uint32_t APB2AXIS_CAM_REQ_CNT; /* 0x110: request count */
30  __R uint32_t APB2AXIS_CAM_FILLSTS; /* 0x114: fill status */
31  __W uint32_t APB2AXIS_CAM_RESET; /* 0x118: reset */
32  __R uint32_t APB2AXIS_CAM_PARAM; /* 0x11C: parameter */
33  __RW uint32_t APB2AXI_CAM_REQDATA_0; /* 0x120: data0 */
34  __RW uint32_t APB2AXI_CAM_REQDATA_1; /* 0x124: data1 */
35  __RW uint32_t APB2AXI_CAM_REQDATA_2; /* 0x128: data2 */
36  __R uint8_t RESERVED6[212]; /* 0x12C - 0x1FF: Reserved */
37  __R uint32_t APB2AXIS_ALMEM_STS; /* 0x200: status register */
38  __R uint8_t RESERVED7[12]; /* 0x204 - 0x20F: Reserved */
39  __R uint32_t APB2AXIS_ALMEM_REQ_CNT; /* 0x210: request count */
40  __R uint32_t APB2AXIS_ALMEM_FILLSTS; /* 0x214: fill status */
41  __W uint32_t APB2AXIS_ALMEM_RESET; /* 0x218: reset */
42  __R uint32_t APB2AXIS_ALMEM_PARAM; /* 0x21C: parameter */
43  __RW uint32_t APB2AXIS_ALMEM_REQDATA_0; /* 0x220: data0 */
44  __RW uint32_t APB2AXIS_ALMEM_REQDATA_1; /* 0x224: data1 */
45  __R uint8_t RESERVED8[88]; /* 0x228 - 0x27F: Reserved */
46  __R uint32_t AXIS2APB_ALMEM_STS; /* 0x280: status register */
47  __R uint8_t RESERVED9[12]; /* 0x284 - 0x28F: Reserved */
48  __R uint32_t AXIS2APB_ALMEM_RESP_CNT; /* 0x290: response count */
49  __R uint32_t AXIS2APB_ALMEM_FILLSTS; /* 0x294: fill status */
50  __RW uint32_t AXIS2APB_ALMEM_RESET; /* 0x298: reset */
51  __R uint32_t AXIS2APB_ALMEM_PARAM; /* 0x29C: parameter */
52  __RW uint32_t AXIS2APB_ALMEM_RESPDATA_0; /* 0x2A0: data0 */
53  __RW uint32_t AXIS2APB_ALMEM_RESPDATA_1; /* 0x2A4: data1 */
54  __R uint8_t RESERVED10[344]; /* 0x2A8 - 0x3FF: Reserved */
55  __RW uint32_t HITMEM[4]; /* 0x400 - 0x40C: hitmem */
56  __R uint8_t RESERVED11[3056]; /* 0x410 - 0xFFF: Reserved */
57  __R uint32_t APB2AXIS_LOOKUP_STS; /* 0x1000: status register */
58  __R uint8_t RESERVED12[12]; /* 0x1004 - 0x100F: Reserved */
59  __R uint32_t APB2AXIS_LOOKUP_REQ_CNT; /* 0x1010: response count */
60  __R uint32_t APB2AXIS_LOOKUP_FILLSTS; /* 0x1014: fill status */
61  __RW uint32_t APB2AXIS_LOOKUP_RESET; /* 0x1018: reset */
62  __R uint32_t APB2AXIS_LOOKUP_PARAM; /* 0x101C: parameter */
63  __RW uint32_t APB2AXIS_LOOKUP_REQDATA_0; /* 0x1020: LOOKUP REQUEST Register REQ_DATA_0 */
64  __RW uint32_t APB2AXIS_LOOKUP_REQDATA_1; /* 0x1024: LOOKUP REQUEST Register REQ_DATA_1 */
65  __R uint8_t RESERVED13[4]; /* 0x1028 - 0x102B: Reserved */
66  __RW uint32_t APB2AXIS_LOOKUP_REQDATA_3; /* 0x102C: LOOKUP REQUEST Register REQ_DATA_2 */
67  __R uint8_t RESERVED14[80]; /* 0x1030 - 0x107F: Reserved */
68  __R uint32_t AXIS2APB_LOOKUP_STS; /* 0x1080: status register */
69  __R uint8_t RESERVED15[12]; /* 0x1084 - 0x108F: Reserved */
70  __R uint32_t AXIS2APB_LOOKUP_RESP_CNT; /* 0x1090: response count */
71  __R uint32_t AXIS2APB_LOOKUP_FILLSTS; /* 0x1094: fill status */
72  __RW uint32_t AXIS2APB_LOOKUP_RESET; /* 0x1098: reset */
73  __R uint32_t AXIS2APB_LOOKUP_PARAM; /* 0x109C: parameter */
74  __RW uint32_t AXIS2APB_LOOKUP_RESPDATA_0; /* 0x10A0: LOOKUP RESPONSE Data Register */
75  __R uint8_t RESERVED16[4]; /* 0x10A4 - 0x10A7: Reserved */
76  __RW uint32_t AXIS2APB_LOOKUP_RESPDATA_1; /* 0x10A8: LOOKUP RESPONSE Data Register */
77  __R uint8_t RESERVED17[3924]; /* 0x10AC - 0x1FFF: Reserved */
78  __R uint32_t CENTRAL_CSR_VERSION; /* 0x2000: version register */
79  __R uint32_t CENTRAL_CSR_PARAM; /* 0x2004: Parameter Register */
80  __RW uint32_t CENTRAL_CSR_CONFIG; /* 0x2008: Configuration Register */
81  __R uint32_t CENTRAL_CSR_CB_PARAM; /* 0x200C: CB Parameter Register */
82  __R uint32_t CENTRAL_CSR_QCI_CTRL_PARAM; /* 0x2010: QCI Control Parameter Register */
83  __R uint8_t RESERVED18[240]; /* 0x2014 - 0x2103: Reserved */
84  __R uint32_t CENTRAL_QCI_HWCFG; /* 0x2104: PSPF General CTRAL */
85  __R uint8_t RESERVED19[8]; /* 0x2108 - 0x210F: Reserved */
86  __RW uint32_t CENTRAL_QCI_FILTERSEL; /* 0x2110: Filter select index */
87  __RW uint32_t CENTRAL_QCI_METERSEL; /* 0x2114: Flowmeter select index */
88  __RW uint32_t CENTRAL_QCI_GATESEL; /* 0x2118: Gate select index */
89  __R uint8_t RESERVED20[4]; /* 0x211C - 0x211F: Reserved */
90  __RW uint32_t CENTRAL_QCI_FCTRL; /* 0x2120: FILTER SETTING */
91  __RW uint32_t CENTRAL_QCI_FSIZE; /* 0x2124: */
92  __R uint8_t RESERVED21[24]; /* 0x2128 - 0x213F: Reserved */
93  __R uint32_t QCI_CNT[6]; /* 0x2140 - 0x2154: FILTER COUNTER */
94  __R uint8_t RESERVED22[8]; /* 0x2158 - 0x215F: Reserved */
95  __RW uint32_t CENTRAL_QCI_MCTRL; /* 0x2160: Flow meter settings */
96  __R uint8_t RESERVED23[12]; /* 0x2164 - 0x216F: Reserved */
97  __RW uint32_t CENTRAL_QCI_CIR; /* 0x2170: */
98  __RW uint32_t CENTRAL_QCI_CBS; /* 0x2174: */
99  __RW uint32_t CENTRAL_QCI_EIR; /* 0x2178: */
100  __RW uint32_t CENTRAL_QCI_EBS; /* 0x217C: */
101  __RW uint32_t CENTRAL_QCI_GCTRL; /* 0x2180: Gate settings */
102  __RW uint32_t CENTRAL_QCI_GSTATUS; /* 0x2184: */
103  __RW uint32_t CENTRAL_QCI_GLISTINDEX; /* 0x2188: */
104  __RW uint32_t CENTRAL_QCI_LISTLEN; /* 0x218C: */
105  __RW uint32_t CENTRAL_QCI_ACYCLETM; /* 0x2190: */
106  __RW uint32_t CENTRAL_QCI_ABASETM_L; /* 0x2194: */
107  __RW uint32_t CENTRAL_QCI_ABASETM_H; /* 0x2198: */
108  __R uint8_t RESERVED24[4]; /* 0x219C - 0x219F: Reserved */
109  __RW uint32_t CENTRAL_QCI_AENTRY_CTRL; /* 0x21A0: */
110  __RW uint32_t CENTRAL_QCI_AENTRY_AENTRY_IVAL; /* 0x21A4: */
111  __R uint32_t CENTRAL_QCI_AENTRY_OCYCLETM; /* 0x21A8: */
112  __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_L;/* 0x21AC: */
113  __R uint32_t CENTRAL_QCI_AENTRY_OBASETM_H;/* 0x21B0: */
114  __R uint8_t RESERVED25[7756]; /* 0x21B4 - 0x3FFF: Reserved */
115  __RW uint32_t MM2S_DMA_CR; /* 0x4000: mm2s control register */
116  __RW uint32_t MM2S_DMA_SR; /* 0x4004: mm2s status */
117  __R uint32_t MM2S_DMA_FILL; /* 0x4008: mm2s dma fill status */
118  __R uint8_t RESERVED26[16]; /* 0x400C - 0x401B: Reserved */
119  __R uint32_t MM2S_DMA_CFG; /* 0x401C: mm2s dma configure */
120  __RW uint32_t MM2S_ADDRLO; /* 0x4020: mm2s axi address */
121  __R uint8_t RESERVED27[4]; /* 0x4024 - 0x4027: Reserved */
122  __RW uint32_t MM2S_LENGTH; /* 0x4028: mm2s axi length */
123  __RW uint32_t MM2S_CTRL; /* 0x402C: mm2s command control */
124  __R uint32_t MM2S_RESP; /* 0x4030: mm2s response buffer */
125  __R uint8_t RESERVED28[76]; /* 0x4034 - 0x407F: Reserved */
126  __RW uint32_t S2MM_DMA_CR; /* 0x4080: s2mm dma control */
127  __RW uint32_t S2MM_DMA_SR; /* 0x4084: s2mm state */
128  __R uint32_t S2MM_DMA_FILL; /* 0x4088: s2mm buffer fill status */
129  __R uint8_t RESERVED29[16]; /* 0x408C - 0x409B: Reserved */
130  __R uint32_t S2MM_DMA_CFG; /* 0x409C: s2mm dma config status */
131  __RW uint32_t S2MM_ADDRLO; /* 0x40A0: s2mm axi address */
132  __R uint8_t RESERVED30[4]; /* 0x40A4 - 0x40A7: Reserved */
133  __RW uint32_t S2MM_LENGTH; /* 0x40A8: s2mm axi length */
134  __RW uint32_t S2MM_CTRL; /* 0x40AC: s2mm command control */
135  __R uint32_t S2MM_RESP; /* 0x40B0: s2mm response buffer */
136  __R uint8_t RESERVED31[8012]; /* 0x40B4 - 0x5FFF: Reserved */
137  __RW uint32_t PTP_EVT_TS_CTL; /* 0x6000: timestamp control */
138  __R uint8_t RESERVED32[4]; /* 0x6004 - 0x6007: Reserved */
139  __R uint32_t PTP_EVT_PPS_TOD_SEC; /* 0x6008: pps tod seconds */
140  __R uint32_t PTP_EVT_PPS_TOD_NS; /* 0x600C: pps tod sun seconds */
141  __R uint8_t RESERVED33[12]; /* 0x6010 - 0x601B: Reserved */
142  __RW uint32_t PTP_EVT_SCP_SEC0; /* 0x601C: target time seconds */
143  __RW uint32_t PTP_EVT_SCP_NS0; /* 0x6020: target time sub seconds */
144  __R uint8_t RESERVED34[4]; /* 0x6024 - 0x6027: Reserved */
145  __R uint32_t PTP_EVT_TMR_STS; /* 0x6028: timer status */
146  __RW uint32_t PTP_EVT_PPS_CMD; /* 0x602C: pps command control */
147  __R uint32_t PTP_EVT_ATSLO; /* 0x6030: auxiliray read data sub seconds */
148  __R uint32_t PTP_EVT_ATSHI; /* 0x6034: auxiliray read data seconds */
149  __R uint8_t RESERVED35[40]; /* 0x6038 - 0x605F: Reserved */
150  __RW uint32_t PTP_EVT_PPS0_INTERVAL; /* 0x6060: pps0 interval configure */
151  __RW uint32_t PTP_EVT_PPS0_WIDTH; /* 0x6064: pps0 width configure */
152  __R uint8_t RESERVED36[24]; /* 0x6068 - 0x607F: Reserved */
153  __RW uint32_t PTP_EVT_SCP_SEC1; /* 0x6080: target time seconds */
154  __RW uint32_t PTP_EVT_SCP_NS1; /* 0x6084: target time sub seconds */
155  __RW uint32_t PTP_EVT_PPS1_INTERVAL; /* 0x6088: pps1 interval configure */
156  __RW uint32_t PTP_EVT_PPS1_WIDTH; /* 0x608C: pps1 width configure */
157  __R uint8_t RESERVED37[16]; /* 0x6090 - 0x609F: Reserved */
158  __RW uint32_t PTP_EVT_SCP_SEC2; /* 0x60A0: target time seconds */
159  __RW uint32_t PTP_EVT_SCP_NS2; /* 0x60A4: target time sub seconds */
160  __RW uint32_t PTP_EVT_PPS2_INTERVAL; /* 0x60A8: pps2 interval configure */
161  __RW uint32_t PTP_EVT_PPS2_WIDTH; /* 0x60AC: pps2 width configure */
162  __R uint8_t RESERVED38[16]; /* 0x60B0 - 0x60BF: Reserved */
163  __RW uint32_t PTP_EVT_SCP_SEC3; /* 0x60C0: target time seconds */
164  __RW uint32_t PTP_EVT_SCP_NS3; /* 0x60C4: target time sub seconds */
165  __RW uint32_t PTP_EVT_PPS3_INTERVAL; /* 0x60C8: pps3 interval configure */
166  __RW uint32_t PTP_EVT_PPS3_WIDTH; /* 0x60CC: pps3 width configure */
167  __R uint8_t RESERVED39[16]; /* 0x60D0 - 0x60DF: Reserved */
168  __RW uint32_t PTP_EVT_PPS_CTRL0; /* 0x60E0: pps control 0 register */
169  __RW uint32_t PTP_EVT_PPS_SEL; /* 0x60E4: */
170  __R uint8_t RESERVED40[8]; /* 0x60E8 - 0x60EF: Reserved */
171  __RW uint32_t SOFT_RST_CTRL; /* 0x60F0: softer reset control */
172  __R uint8_t RESERVED41[40716]; /* 0x60F4 - 0xFFFF: Reserved */
173  __RW uint32_t CPU_PORT_PORT_MAIN_TAGGING; /* 0x10000: PVID Tagging Register */
174  __RW uint32_t CPU_PORT_PORT_MAIN_ENNABLE; /* 0x10004: Port Module Enable Register */
175  __R uint8_t RESERVED42[10232]; /* 0x10008 - 0x127FF: Reserved */
176  __RW uint32_t CPU_PORT_EGRESS_STMID_ESELECT; /* 0x12800: Stream Identification */
177  __R uint8_t RESERVED43[60]; /* 0x12804 - 0x1283F: Reserved */
178  __RW uint32_t CPU_PORT_EGRESS_STMID_CONTROL; /* 0x12840: */
179  __RW uint32_t CPU_PORT_EGRESS_STMID_SEQNO; /* 0x12844: */
180  __RW uint32_t CPU_PORT_EGRESS_STMID_MATCHCNT; /* 0x12848: */
181  __R uint8_t RESERVED44[4]; /* 0x1284C - 0x1284F: Reserved */
182  __RW uint32_t CPU_PORT_EGRESS_STMID_MACLO; /* 0x12850: */
183  __RW uint32_t CPU_PORT_EGRESS_STMID_MACHI; /* 0x12854: */
184  __RW uint32_t CPU_PORT_EGRESS_STMID_AMACLO;/* 0x12858: */
185  __RW uint32_t CPU_PORT_EGRESS_STMID_AMACHI;/* 0x1285C: */
186  __R uint8_t RESERVED45[160]; /* 0x12860 - 0x128FF: Reserved */
187  __RW uint32_t CPU_PORT_EGRESS_FRER_CONTROL;/* 0x12900: Frame Replication and Elimination */
188  __RW uint32_t CPU_PORT_EGRESS_FRER_SIDSEL; /* 0x12904: */
189  __RW uint32_t CPU_PORT_EGRESS_FRER_IRFUNC; /* 0x12908: */
190  __RW uint32_t CPU_PORT_EGRESS_FRER_SRFUNC; /* 0x1290C: */
191  __RW uint32_t CPU_PORT_EGRESS_FRER_FSELECT;/* 0x12910: */
192  __R uint8_t RESERVED46[44]; /* 0x12914 - 0x1293F: Reserved */
193  __RW uint32_t CPU_PORT_EGRESS_FRER_FCTRL; /* 0x12940: */
194  __RW uint32_t CPU_PORT_EGRESS_FRER_RESETMSEC; /* 0x12944: */
195  __RW uint32_t CPU_PORT_EGRESS_FRER_LATRSPERIOD; /* 0x12948: */
196  __RW uint32_t CPU_PORT_EGRESS_FRER_LATTESTPERIOD; /* 0x1294C: */
197  __RW uint32_t CPU_PORT_EGRESS_FRER_LATERRDIFFALW; /* 0x12950: */
198  __RW uint32_t CPU_PORT_EGRESS_FRER_LATERRCNT; /* 0x12954: */
199  __R uint8_t RESERVED47[8]; /* 0x12958 - 0x1295F: Reserved */
200  __R uint32_t EGFRCNT[8]; /* 0x12960 - 0x1297C: */
201  __R uint8_t RESERVED48[5760]; /* 0x12980 - 0x13FFF: Reserved */
202  __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE; /* 0x14000: */
203  __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS; /* 0x14004: */
204  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG; /* 0x14008: */
205  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG; /* 0x1400C: */
206  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG; /* 0x14010: */
207  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG; /* 0x14014: */
208  __W uint32_t CPU_PORT_IGRESS_RX_FDFIFO_RESET; /* 0x14018: */
209  __R uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PARAM; /* 0x1401C: */
210  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_STRFWD; /* 0x14020: */
211  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK; /* 0x14024: */
212  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR; /* 0x14028: */
213  __RW uint32_t CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX; /* 0x1402C: */
214  __R uint8_t RESERVED49[2000]; /* 0x14030 - 0x147FF: Reserved */
215  __RW uint32_t CPU_PORT_IGRESS_STMID_ESELECT; /* 0x14800: Stream Identification */
216  __R uint8_t RESERVED50[60]; /* 0x14804 - 0x1483F: Reserved */
217  __RW uint32_t CPU_PORT_IGRESS_STMID_CONTROL; /* 0x14840: */
218  __RW uint32_t CPU_PORT_IGRESS_STMID_SEQNO; /* 0x14844: */
219  __RW uint32_t CPU_PORT_IGRESS_STMID_MATCHCNT; /* 0x14848: */
220  __R uint8_t RESERVED51[4]; /* 0x1484C - 0x1484F: Reserved */
221  __RW uint32_t CPU_PORT_IGRESS_STMID_MACLO; /* 0x14850: */
222  __RW uint32_t CPU_PORT_IGRESS_STMID_MACHI; /* 0x14854: */
223  __RW uint32_t CPU_PORT_IGRESS_STMID_AMACLO;/* 0x14858: */
224  __RW uint32_t CPU_PORT_IGRESS_STMID_AMACHI;/* 0x1485C: */
225  __R uint8_t RESERVED52[160]; /* 0x14860 - 0x148FF: Reserved */
226  __RW uint32_t CPU_PORT_IGRESS_FRER_CONTROL;/* 0x14900: Frame Replication and Elimination */
227  __RW uint32_t CPU_PORT_IGRESS_FRER_SIDSEL; /* 0x14904: */
228  __RW uint32_t CPU_PORT_IGRESS_FRER_IRFUNC; /* 0x14908: */
229  __RW uint32_t CPU_PORT_IGRESS_FRER_SRFUNC; /* 0x1490C: */
230  __RW uint32_t CPU_PORT_IGRESS_FRER_FSELECT;/* 0x14910: */
231  __R uint8_t RESERVED53[44]; /* 0x14914 - 0x1493F: Reserved */
232  __RW uint32_t CPU_PORT_IGRESS_FRER_FCTRL; /* 0x14940: */
233  __RW uint32_t CPU_PORT_IGRESS_FRER_RESETMSEC; /* 0x14944: */
234  __RW uint32_t CPU_PORT_IGRESS_FRER_LATRSPERIOD; /* 0x14948: */
235  __RW uint32_t CPU_PORT_IGRESS_FRER_LATTESTPERIOD; /* 0x1494C: */
236  __RW uint32_t CPU_PORT_IGRESS_FRER_LATERRDIFFALW; /* 0x14950: */
237  __RW uint32_t CPU_PORT_IGRESS_FRER_LATERRCNT; /* 0x14954: */
238  __R uint8_t RESERVED54[8]; /* 0x14958 - 0x1495F: Reserved */
239  __R uint32_t IGFRCNT[8]; /* 0x14960 - 0x1497C: */
240  __R uint8_t RESERVED55[13956]; /* 0x14980 - 0x18003: Reserved */
241  __RW uint32_t CPU_PORT_MONITOR_CTRL; /* 0x18004: */
242  __W uint32_t CPU_PORT_MONITOR_RESET; /* 0x18008: */
243  __R uint32_t CPU_PORT_MONITOR_PARAM; /* 0x1800C: */
244  __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD; /* 0x18010: */
245  __R uint8_t RESERVED56[4]; /* 0x18014 - 0x18017: Reserved */
246  __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR; /* 0x18018: */
247  __R uint8_t RESERVED57[4]; /* 0x1801C - 0x1801F: Reserved */
248  __R uint32_t CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x18020: */
249  __R uint8_t RESERVED58[28]; /* 0x18024 - 0x1803F: Reserved */
250  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD; /* 0x18040: */
251  __R uint8_t RESERVED59[4]; /* 0x18044 - 0x18047: Reserved */
252  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR; /* 0x18048: */
253  __R uint8_t RESERVED60[4]; /* 0x1804C - 0x1804F: Reserved */
254  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN; /* 0x18050: */
255  __R uint8_t RESERVED61[4]; /* 0x18054 - 0x18057: Reserved */
256  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x18058: */
257  __R uint8_t RESERVED62[4]; /* 0x1805C - 0x1805F: Reserved */
258  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_UC; /* 0x18060: */
259  __R uint8_t RESERVED63[4]; /* 0x18064 - 0x18067: Reserved */
260  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN; /* 0x18068: */
261  __R uint8_t RESERVED64[4]; /* 0x1806C - 0x1806F: Reserved */
262  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_BC; /* 0x18070: */
263  __R uint8_t RESERVED65[4]; /* 0x18074 - 0x18077: Reserved */
264  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI; /* 0x18078: */
265  __R uint8_t RESERVED66[4]; /* 0x1807C - 0x1807F: Reserved */
266  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN; /* 0x18080: */
267  __R uint8_t RESERVED67[4]; /* 0x18084 - 0x18087: Reserved */
268  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x18088: */
269  __R uint8_t RESERVED68[4]; /* 0x1808C - 0x1808F: Reserved */
270  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x18090: */
271  __R uint8_t RESERVED69[4]; /* 0x18094 - 0x18097: Reserved */
272  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x18098: */
273  __R uint8_t RESERVED70[4]; /* 0x1809C - 0x1809F: Reserved */
274  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x180A0: */
275  __R uint8_t RESERVED71[4]; /* 0x180A4 - 0x180A7: Reserved */
276  __R uint32_t CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x180A8: */
277  __R uint8_t RESERVED72[32596]; /* 0x180AC - 0x1FFFF: Reserved */
278  struct {
279  struct {
280  __R uint32_t MAC_VER; /* 0x20000: */
281  __RW uint32_t MAC_MACADDR_L; /* 0x20004: */
282  __RW uint32_t MAC_MACADDR_H; /* 0x20008: */
283  __RW uint32_t MAC_MAC_CTRL; /* 0x2000C: */
284  __R uint32_t MAC_TX_FRAMES; /* 0x20010: */
285  __R uint32_t MAC_RX_FRAMES; /* 0x20014: */
286  __R uint32_t MAC_TX_OCTETS; /* 0x20018: */
287  __R uint32_t MAC_RX_OCTETS; /* 0x2001C: */
288  __RW uint32_t MAC_MDIO_CFG; /* 0x20020: */
289  __RW uint32_t MAC_MDIO_CTRL; /* 0x20024: */
290  __R uint32_t MAC_MDIO_RD_DATA; /* 0x20028: */
291  __RW uint32_t MAC_MDIO_WR_DATA; /* 0x2002C: */
292  __RW uint32_t MAC_IRQ_CTRL; /* 0x20030: */
293  __R uint8_t RESERVED0[460]; /* 0x20034 - 0x201FF: Reserved */
294  } MAC[2];
295  __R uint8_t RESERVED0[1024]; /* 0x20400 - 0x207FF: Reserved */
296  __RW uint32_t RTC_CR; /* 0x20800: ONLY IN PORT1 */
297  __RW uint32_t RTC_SR; /* 0x20804: ONLY IN PORT1 */
298  __R uint8_t RESERVED1[8]; /* 0x20808 - 0x2080F: Reserved */
299  __RW uint32_t RTC_CT_CURTIME_NS; /* 0x20810: ONLY IN PORT1 */
300  __R uint32_t RTC_CT_CURTIME_SEC; /* 0x20814: ONLY IN PORT1 */
301  __R uint8_t RESERVED2[4]; /* 0x20818 - 0x2081B: Reserved */
302  __RW uint32_t RTC_CT_TIMER_INCR; /* 0x2081C: ONLY IN PORT1 */
303  __RW uint32_t RTC_OFS_NS; /* 0x20820: ONLY IN PORT1 */
304  __RW uint32_t RTC_OFS_SL; /* 0x20824: ONLY IN PORT1 */
305  __RW uint32_t RTC_OFS_SH; /* 0x20828: ONLY IN PORT1 */
306  __RW uint32_t RTC_OFS_CH; /* 0x2082C: ONLY IN PORT1 */
307  __RW uint32_t RTC_ALARM_NS; /* 0x20830: ONLY IN PORT1 */
308  __RW uint32_t RTC_ALARM_SL; /* 0x20834: ONLY IN PORT1 */
309  __RW uint32_t RTC_ALARM_SH; /* 0x20838: ONLY IN PORT1 */
310  __R uint8_t RESERVED3[4]; /* 0x2083C - 0x2083F: Reserved */
311  __RW uint32_t RTC_TIMER_A_PERIOD; /* 0x20840: ONLY IN PORT1 */
312  __R uint8_t RESERVED4[1984]; /* 0x20844 - 0x21003: Reserved */
313  __RW uint32_t TSYN_CR; /* 0x21004: */
314  __RW uint32_t TSYN_SR; /* 0x21008: */
315  __R uint8_t RESERVED5[4]; /* 0x2100C - 0x2100F: Reserved */
316  __R uint32_t TSYN_PTP_TX_STS; /* 0x21010: */
317  __RW uint32_t TSYN_PTP_TX_DONE; /* 0x21014: */
318  __W uint32_t TSYN_PTP_TX_TRIG; /* 0x21018: */
319  __RW uint32_t TSYN_PTP_RX_STS; /* 0x2101C: */
320  __RW uint32_t TSYNTMR[5]; /* 0x21020 - 0x21030: */
321  __R uint8_t RESERVED6[8]; /* 0x21034 - 0x2103B: Reserved */
322  __RW uint32_t TSYN_HCLKDIV; /* 0x2103C: */
323  __R uint8_t RESERVED7[1472]; /* 0x21040 - 0x215FF: Reserved */
324  __R uint32_t TSYN_RXBUF_RX_FRAME_LENGTH_BYTES; /* 0x21600: */
325  __R uint8_t RESERVED8[4]; /* 0x21604 - 0x21607: Reserved */
326  __R uint32_t TSYN_RXBUF_RX_TIME_STAMP_L; /* 0x21608: */
327  __R uint32_t TSYN_RXBUF_RX_TIME_STAMP_H; /* 0x2160C: */
328  __R uint32_t RXDATA[60]; /* 0x21610 - 0x216FC: */
329  __R uint8_t RESERVED9[256]; /* 0x21700 - 0x217FF: Reserved */
330  struct {
331  __W uint32_t TXDATA[60]; /* 0x21800 - 0x218EC: */
332  __W uint32_t TSYN_TXBUF_TQUE_AND_TX_LEN; /* 0x218F0: */
333  __R uint8_t RESERVED0[4]; /* 0x218F4 - 0x218F7: Reserved */
334  __R uint32_t TSYN_TXBUF_TX_TIMESTAMP_L; /* 0x218F8: */
335  __R uint32_t TSYN_TXBUF_TX_TIMESTAMP_H; /* 0x218FC: */
336  } BIN[8];
337  __R uint8_t RESERVED10[4]; /* 0x22000 - 0x22003: Reserved */
338  __R uint32_t TSN_SHAPER_HWCFG1; /* 0x22004: */
339  __R uint8_t RESERVED11[4]; /* 0x22008 - 0x2200B: Reserved */
340  __RW uint32_t TSN_SHAPER_TQAV; /* 0x2200C: */
341  __R uint32_t TSN_SHAPER_TQEM; /* 0x22010: */
342  __RW uint32_t TSN_SHAPER_FPST; /* 0x22014: */
343  __RW uint32_t TSN_SHAPER_MMCT; /* 0x22018: */
344  __RW uint32_t TSN_SHAPER_HOLDADV; /* 0x2201C: */
345  __R uint8_t RESERVED12[224]; /* 0x22020 - 0x220FF: Reserved */
346  __RW uint32_t MXSDU[8]; /* 0x22100 - 0x2211C: */
347  __RW uint32_t TXSEL[8]; /* 0x22120 - 0x2213C: */
348  __RW uint32_t IDSEL[8]; /* 0x22140 - 0x2215C: */
349  __R uint8_t RESERVED13[1696]; /* 0x22160 - 0x227FF: Reserved */
350  __RW uint32_t PORT1_QCH0_CFG; /* 0x22800: qch channel0 control */
351  __RW uint32_t PORT1_QCH1_CFG; /* 0x22804: qch channel1 control */
352  __RW uint32_t PORT1_QCH2_CFG; /* 0x22808: qch channel2 control */
353  __RW uint32_t PORT1_QCH3_CFG; /* 0x2280C: qch channel3 control */
354  __RW uint32_t PORT1_QCH_ERR_CFG; /* 0x22810: qch clear */
355  __R uint8_t RESERVED14[2028]; /* 0x22814 - 0x22FFF: Reserved */
356  __RW uint32_t TSN_SHAPER_TAS_CRSR; /* 0x23000: */
357  __RW uint32_t TSN_SHAPER_TAS_ACYCLETM; /* 0x23004: */
358  __RW uint32_t TSN_SHAPER_TAS_ABASETM_L;/* 0x23008: */
359  __RW uint32_t TSN_SHAPER_TAS_ABASETM_H;/* 0x2300C: */
360  __RW uint32_t TSN_SHAPER_TAS_LISTLEN; /* 0x23010: */
361  __R uint32_t TSN_SHAPER_TAS_OCYCLETM; /* 0x23014: */
362  __R uint32_t TSN_SHAPER_TAS_OBASETM_L;/* 0x23018: */
363  __R uint32_t TSN_SHAPER_TAS_OBASETM_H;/* 0x2301C: */
364  __RW uint32_t MXTK[8]; /* 0x23020 - 0x2303C: */
365  __RW uint32_t TXOV[8]; /* 0x23040 - 0x2305C: */
366  __R uint8_t RESERVED15[1952]; /* 0x23060 - 0x237FF: Reserved */
367  struct {
368  __RW uint32_t TSN_SHAPER_ACLIST_ENTRY_L; /* 0x23800: */
369  __RW uint32_t TSN_SHAPER_ACLIST_ENTRY_H; /* 0x23804: */
370  } SHACL[256];
371  __R uint8_t RESERVED16[45056]; /* 0x24000 - 0x2EFFF: Reserved */
372  __R uint32_t TSN_EP_VER; /* 0x2F000: */
373  __RW uint32_t TSN_EP_CTRL; /* 0x2F004: */
374  __R uint8_t RESERVED17[8]; /* 0x2F008 - 0x2F00F: Reserved */
375  __RW uint32_t TSN_EP_TXUF; /* 0x2F010: */
376  __R uint32_t TSN_EP_IPCFG; /* 0x2F014: */
377  __R uint8_t RESERVED18[8]; /* 0x2F018 - 0x2F01F: Reserved */
378  __R uint32_t TSN_EP_TSF_D0; /* 0x2F020: */
379  __R uint32_t TSN_EP_TSF_D1; /* 0x2F024: */
380  __R uint32_t TSN_EP_TSF_D2; /* 0x2F028: */
381  __RW uint32_t TSN_EP_TSF_SR; /* 0x2F02C: */
382  __RW uint32_t TSN_EP_MMS_CTRL; /* 0x2F030: */
383  __R uint32_t TSN_EP_MMS_STS; /* 0x2F034: */
384  __RW uint32_t TSN_EP_MMS_VTIME; /* 0x2F038: */
385  __RW uint32_t TSN_EP_MMS_STAT; /* 0x2F03C: */
386  __W uint32_t TSN_EP_PTP_UPTM_NS; /* 0x2F040: */
387  __W uint32_t TSN_EP_PTP_UPTM_S; /* 0x2F044: */
388  __R uint32_t TSN_EP_PTP_SR; /* 0x2F048: */
389  __R uint8_t RESERVED19[4020]; /* 0x2F04C - 0x2FFFF: Reserved */
390  __RW uint32_t SW_CTRL_PORT_MAIN_TAGGING; /* 0x30000: PVID Tagging Register */
391  __RW uint32_t SW_CTRL_PORT_MAIN_ENNABLE; /* 0x30004: Port Module Enable Register */
392  __R uint8_t RESERVED20[8184]; /* 0x30008 - 0x31FFF: Reserved */
393  __RW uint32_t SW_CTRL_EGRESS_ECSR_QDROP; /* 0x32000: */
394  __R uint8_t RESERVED21[8188]; /* 0x32004 - 0x33FFF: Reserved */
395  struct {
396  __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE; /* 0x34000: */
397  __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS; /* 0x34004: */
398  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG; /* 0x34008: */
399  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG; /* 0x3400C: */
400  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG; /* 0x34010: */
401  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG; /* 0x34014: */
402  __W uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_RESET; /* 0x34018: */
403  __R uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM; /* 0x3401C: */
404  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD; /* 0x34020: */
405  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK; /* 0x34024: */
406  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR; /* 0x34028: */
407  __RW uint32_t SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX; /* 0x3402C: */
408  __R uint8_t RESERVED0[208]; /* 0x34030 - 0x340FF: Reserved */
409  } RXFIFO[2];
410  __R uint8_t RESERVED22[15876]; /* 0x34200 - 0x38003: Reserved */
411  __RW uint32_t SW_CTRL_MONITOR_CTRL; /* 0x38004: */
412  __W uint32_t SW_CTRL_MONITOR_RESET; /* 0x38008: */
413  __R uint32_t SW_CTRL_MONITOR_PARAM; /* 0x3800C: */
414  __R uint32_t MONITOR_TX_COUNTER_TX_FGOOD; /* 0x38010: */
415  __R uint8_t RESERVED23[4]; /* 0x38014 - 0x38017: Reserved */
416  __R uint32_t MONITOR_TX_COUNTER_TX_FERROR; /* 0x38018: */
417  __R uint8_t RESERVED24[4]; /* 0x3801C - 0x3801F: Reserved */
418  __R uint32_t MONITOR_TX_COUNTER_TX_DROP_OVFL; /* 0x38020: */
419  __R uint8_t RESERVED25[28]; /* 0x38024 - 0x3803F: Reserved */
420  __R uint32_t MONITOR_RX_COUNTER_RX_FGOOD; /* 0x38040: */
421  __R uint8_t RESERVED26[4]; /* 0x38044 - 0x38047: Reserved */
422  __R uint32_t MONITOR_RX_COUNTER_RX_FERROR; /* 0x38048: */
423  __R uint8_t RESERVED27[4]; /* 0x3804C - 0x3804F: Reserved */
424  __R uint32_t MONITOR_RX_COUNTER_RX_KNOWN; /* 0x38050: */
425  __R uint8_t RESERVED28[4]; /* 0x38054 - 0x38057: Reserved */
426  __R uint32_t MONITOR_RX_COUNTER_RX_UNKNOWN; /* 0x38058: */
427  __R uint8_t RESERVED29[4]; /* 0x3805C - 0x3805F: Reserved */
428  __R uint32_t MONITOR_RX_COUNTER_RX_UC;/* 0x38060: */
429  __R uint8_t RESERVED30[4]; /* 0x38064 - 0x38067: Reserved */
430  __R uint32_t MONITOR_RX_COUNTER_RX_INTERN; /* 0x38068: */
431  __R uint8_t RESERVED31[4]; /* 0x3806C - 0x3806F: Reserved */
432  __R uint32_t MONITOR_RX_COUNTER_RX_BC;/* 0x38070: */
433  __R uint8_t RESERVED32[4]; /* 0x38074 - 0x38077: Reserved */
434  __R uint32_t MONITOR_RX_COUNTER_RX_MULTI; /* 0x38078: */
435  __R uint8_t RESERVED33[4]; /* 0x3807C - 0x3807F: Reserved */
436  __R uint32_t MONITOR_RX_COUNTER_RX_VLAN; /* 0x38080: */
437  __R uint8_t RESERVED34[4]; /* 0x38084 - 0x38087: Reserved */
438  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_OVFL; /* 0x38088: */
439  __R uint8_t RESERVED35[4]; /* 0x3808C - 0x3808F: Reserved */
440  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_LU; /* 0x38090: */
441  __R uint8_t RESERVED36[4]; /* 0x38094 - 0x38097: Reserved */
442  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_ERR; /* 0x38098: */
443  __R uint8_t RESERVED37[4]; /* 0x3809C - 0x3809F: Reserved */
444  __R uint32_t MONITOR_RX_COUNTER_RX_DROP_VLAN; /* 0x380A0: */
445  __R uint8_t RESERVED38[4]; /* 0x380A4 - 0x380A7: Reserved */
446  __R uint32_t MONITOR_RX_COUNTER_RX_FPE_FGOOD; /* 0x380A8: */
447  __R uint8_t RESERVED39[16212]; /* 0x380AC - 0x3BFFF: Reserved */
448  __RW uint32_t GPR_CTRL0; /* 0x3C000: control register0 */
449  __R uint8_t RESERVED40[4]; /* 0x3C004 - 0x3C007: Reserved */
450  __RW uint32_t GPR_CTRL2; /* 0x3C008: control register2 */
451  __R uint8_t RESERVED41[16372]; /* 0x3C00C - 0x3FFFF: Reserved */
452  } TSNPORT[3];
453 } TSW_Type;
454 
455 
456 /* Bitfield definition for register: LU_MAIN_CTRL */
457 /*
458  * BYP_EN (R/W)
459  *
460  * MAC lookup bypass
461  */
462 #define TSW_LU_MAIN_CTRL_BYP_EN_MASK (0x1U)
463 #define TSW_LU_MAIN_CTRL_BYP_EN_SHIFT (0U)
464 #define TSW_LU_MAIN_CTRL_BYP_EN_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_CTRL_BYP_EN_SHIFT) & TSW_LU_MAIN_CTRL_BYP_EN_MASK)
465 #define TSW_LU_MAIN_CTRL_BYP_EN_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_CTRL_BYP_EN_MASK) >> TSW_LU_MAIN_CTRL_BYP_EN_SHIFT)
466 
467 /* Bitfield definition for register: LU_MAIN_HITMEM */
468 /*
469  * CAMMEMCLR (R/W)
470  *
471  * clear the cam memory
472  */
473 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK (0x2U)
474 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT (1U)
475 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK)
476 #define TSW_LU_MAIN_HITMEM_CAMMEMCLR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_CAMMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_CAMMEMCLR_SHIFT)
477 
478 /*
479  * HITMEMCLR (R/W)
480  *
481  * clears the hit memory
482  */
483 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK (0x1U)
484 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT (0U)
485 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK)
486 #define TSW_LU_MAIN_HITMEM_HITMEMCLR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_HITMEM_HITMEMCLR_MASK) >> TSW_LU_MAIN_HITMEM_HITMEMCLR_SHIFT)
487 
488 /* Bitfield definition for register: LU_MAIN_PARAM */
489 /*
490  * NSTR (RO)
491  *
492  * number of supported streams
493  */
494 #define TSW_LU_MAIN_PARAM_NSTR_MASK (0xFF00U)
495 #define TSW_LU_MAIN_PARAM_NSTR_SHIFT (8U)
496 #define TSW_LU_MAIN_PARAM_NSTR_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PARAM_NSTR_MASK) >> TSW_LU_MAIN_PARAM_NSTR_SHIFT)
497 
498 /*
499  * ADDRW_ENTRY (RO)
500  *
501  * bit width of entry address vector
502  */
503 #define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK (0xFFU)
504 #define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT (0U)
505 #define TSW_LU_MAIN_PARAM_ADDRW_ENTRY_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PARAM_ADDRW_ENTRY_MASK) >> TSW_LU_MAIN_PARAM_ADDRW_ENTRY_SHIFT)
506 
507 /* Bitfield definition for register: LU_MAIN_BYPASS */
508 /*
509  * HIT (R/W)
510  *
511  * set hit bit to frame, only for debugging
512  */
513 #define TSW_LU_MAIN_BYPASS_HIT_MASK (0x1000000UL)
514 #define TSW_LU_MAIN_BYPASS_HIT_SHIFT (24U)
515 #define TSW_LU_MAIN_BYPASS_HIT_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_MASK)
516 #define TSW_LU_MAIN_BYPASS_HIT_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_MASK) >> TSW_LU_MAIN_BYPASS_HIT_SHIFT)
517 
518 /*
519  * UTAG (R/W)
520  *
521  * set internal user tag field
522  */
523 #define TSW_LU_MAIN_BYPASS_UTAG_MASK (0xE00000UL)
524 #define TSW_LU_MAIN_BYPASS_UTAG_SHIFT (21U)
525 #define TSW_LU_MAIN_BYPASS_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_UTAG_SHIFT) & TSW_LU_MAIN_BYPASS_UTAG_MASK)
526 #define TSW_LU_MAIN_BYPASS_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_UTAG_MASK) >> TSW_LU_MAIN_BYPASS_UTAG_SHIFT)
527 
528 /*
529  * HIT_VLAN (R/W)
530  *
531  * mark frame to be vlan-tagged
532  */
533 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK (0x100000UL)
534 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT (20U)
535 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK)
536 #define TSW_LU_MAIN_BYPASS_HIT_VLAN_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_HIT_VLAN_MASK) >> TSW_LU_MAIN_BYPASS_HIT_VLAN_SHIFT)
537 
538 /*
539  * DROP (R/W)
540  *
541  * mark frame to be dropped
542  */
543 #define TSW_LU_MAIN_BYPASS_DROP_MASK (0x80000UL)
544 #define TSW_LU_MAIN_BYPASS_DROP_SHIFT (19U)
545 #define TSW_LU_MAIN_BYPASS_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DROP_SHIFT) & TSW_LU_MAIN_BYPASS_DROP_MASK)
546 #define TSW_LU_MAIN_BYPASS_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DROP_MASK) >> TSW_LU_MAIN_BYPASS_DROP_SHIFT)
547 
548 /*
549  * QUEUE (R/W)
550  *
551  * number of configured buffer depth
552  */
553 #define TSW_LU_MAIN_BYPASS_QUEUE_MASK (0x70000UL)
554 #define TSW_LU_MAIN_BYPASS_QUEUE_SHIFT (16U)
555 #define TSW_LU_MAIN_BYPASS_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_QUEUE_SHIFT) & TSW_LU_MAIN_BYPASS_QUEUE_MASK)
556 #define TSW_LU_MAIN_BYPASS_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_QUEUE_MASK) >> TSW_LU_MAIN_BYPASS_QUEUE_SHIFT)
557 
558 /*
559  * DEST (R/W)
560  *
561  * target destination ports of frame
562  */
563 #define TSW_LU_MAIN_BYPASS_DEST_MASK (0xFFFFU)
564 #define TSW_LU_MAIN_BYPASS_DEST_SHIFT (0U)
565 #define TSW_LU_MAIN_BYPASS_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BYPASS_DEST_SHIFT) & TSW_LU_MAIN_BYPASS_DEST_MASK)
566 #define TSW_LU_MAIN_BYPASS_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BYPASS_DEST_MASK) >> TSW_LU_MAIN_BYPASS_DEST_SHIFT)
567 
568 /* Bitfield definition for register: LU_MAIN_PCP_REMAP */
569 /*
570  * PCP7 (R/W)
571  *
572  * queue value for PCP=7
573  */
574 #define TSW_LU_MAIN_PCP_REMAP_PCP7_MASK (0xE00000UL)
575 #define TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT (21U)
576 #define TSW_LU_MAIN_PCP_REMAP_PCP7_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK)
577 #define TSW_LU_MAIN_PCP_REMAP_PCP7_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP7_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP7_SHIFT)
578 
579 /*
580  * PCP6 (R/W)
581  *
582  * queue value for PCP=6
583  */
584 #define TSW_LU_MAIN_PCP_REMAP_PCP6_MASK (0x1C0000UL)
585 #define TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT (18U)
586 #define TSW_LU_MAIN_PCP_REMAP_PCP6_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK)
587 #define TSW_LU_MAIN_PCP_REMAP_PCP6_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP6_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP6_SHIFT)
588 
589 /*
590  * PCP5 (R/W)
591  *
592  * queue value for PCP=5
593  */
594 #define TSW_LU_MAIN_PCP_REMAP_PCP5_MASK (0x38000UL)
595 #define TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT (15U)
596 #define TSW_LU_MAIN_PCP_REMAP_PCP5_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK)
597 #define TSW_LU_MAIN_PCP_REMAP_PCP5_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP5_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP5_SHIFT)
598 
599 /*
600  * PCP4 (R/W)
601  *
602  * queue value for PCP=4
603  */
604 #define TSW_LU_MAIN_PCP_REMAP_PCP4_MASK (0x7000U)
605 #define TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT (12U)
606 #define TSW_LU_MAIN_PCP_REMAP_PCP4_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK)
607 #define TSW_LU_MAIN_PCP_REMAP_PCP4_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP4_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP4_SHIFT)
608 
609 /*
610  * PCP3 (R/W)
611  *
612  * queue value for PCP=3
613  */
614 #define TSW_LU_MAIN_PCP_REMAP_PCP3_MASK (0xE00U)
615 #define TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT (9U)
616 #define TSW_LU_MAIN_PCP_REMAP_PCP3_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK)
617 #define TSW_LU_MAIN_PCP_REMAP_PCP3_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP3_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP3_SHIFT)
618 
619 /*
620  * PCP2 (R/W)
621  *
622  * queue value for PCP=2
623  */
624 #define TSW_LU_MAIN_PCP_REMAP_PCP2_MASK (0x1C0U)
625 #define TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT (6U)
626 #define TSW_LU_MAIN_PCP_REMAP_PCP2_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK)
627 #define TSW_LU_MAIN_PCP_REMAP_PCP2_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP2_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP2_SHIFT)
628 
629 /*
630  * PCP1 (R/W)
631  *
632  * queue value for PCP=1
633  */
634 #define TSW_LU_MAIN_PCP_REMAP_PCP1_MASK (0x38U)
635 #define TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT (3U)
636 #define TSW_LU_MAIN_PCP_REMAP_PCP1_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK)
637 #define TSW_LU_MAIN_PCP_REMAP_PCP1_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP1_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP1_SHIFT)
638 
639 /*
640  * PCP0 (R/W)
641  *
642  * queue value for PCP=0
643  */
644 #define TSW_LU_MAIN_PCP_REMAP_PCP0_MASK (0x7U)
645 #define TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT (0U)
646 #define TSW_LU_MAIN_PCP_REMAP_PCP0_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK)
647 #define TSW_LU_MAIN_PCP_REMAP_PCP0_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_PCP_REMAP_PCP0_MASK) >> TSW_LU_MAIN_PCP_REMAP_PCP0_SHIFT)
648 
649 /* Bitfield definition for register: LU_MAIN_VERSION */
650 /*
651  * VER_HI (RO)
652  *
653  * major version
654  */
655 #define TSW_LU_MAIN_VERSION_VER_HI_MASK (0xFF000000UL)
656 #define TSW_LU_MAIN_VERSION_VER_HI_SHIFT (24U)
657 #define TSW_LU_MAIN_VERSION_VER_HI_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_HI_MASK) >> TSW_LU_MAIN_VERSION_VER_HI_SHIFT)
658 
659 /*
660  * VER_LO (RO)
661  *
662  * minor version
663  */
664 #define TSW_LU_MAIN_VERSION_VER_LO_MASK (0xFF0000UL)
665 #define TSW_LU_MAIN_VERSION_VER_LO_SHIFT (16U)
666 #define TSW_LU_MAIN_VERSION_VER_LO_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_LO_MASK) >> TSW_LU_MAIN_VERSION_VER_LO_SHIFT)
667 
668 /*
669  * VER_REV (RO)
670  *
671  * revision number
672  */
673 #define TSW_LU_MAIN_VERSION_VER_REV_MASK (0xFFU)
674 #define TSW_LU_MAIN_VERSION_VER_REV_SHIFT (0U)
675 #define TSW_LU_MAIN_VERSION_VER_REV_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_VERSION_VER_REV_MASK) >> TSW_LU_MAIN_VERSION_VER_REV_SHIFT)
676 
677 /* Bitfield definition for register: LU_MAIN_INTF_ACTION */
678 /*
679  * UTAG (R/W)
680  *
681  * TSN user sideband information from ALMEM
682  */
683 #define TSW_LU_MAIN_INTF_ACTION_UTAG_MASK (0x1C00000UL)
684 #define TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT (22U)
685 #define TSW_LU_MAIN_INTF_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK)
686 #define TSW_LU_MAIN_INTF_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_UTAG_MASK) >> TSW_LU_MAIN_INTF_ACTION_UTAG_SHIFT)
687 
688 /*
689  * QSEL (R/W)
690  *
691  * Define the traffic queue selection:
692  * 00 – use PCP field of VLAN, untagged frames use PCP of PVID
693  * 01 – use PCP field with global remapping list
694  * 10 – reserved
695  * 11 – use value QUEUE of Action List
696  */
697 #define TSW_LU_MAIN_INTF_ACTION_QSEL_MASK (0x300000UL)
698 #define TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT (20U)
699 #define TSW_LU_MAIN_INTF_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK)
700 #define TSW_LU_MAIN_INTF_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QSEL_MASK) >> TSW_LU_MAIN_INTF_ACTION_QSEL_SHIFT)
701 
702 /*
703  * DROP (R/W)
704  *
705  * 1 if frame should be dropped.
706  */
707 #define TSW_LU_MAIN_INTF_ACTION_DROP_MASK (0x80000UL)
708 #define TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT (19U)
709 #define TSW_LU_MAIN_INTF_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK)
710 #define TSW_LU_MAIN_INTF_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DROP_MASK) >> TSW_LU_MAIN_INTF_ACTION_DROP_SHIFT)
711 
712 /*
713  * QUEUE (R/W)
714  *
715  * Select the Priority Queue for TSN TX, only used if QSEL=11
716  */
717 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK (0x70000UL)
718 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT (16U)
719 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK)
720 #define TSW_LU_MAIN_INTF_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_INTF_ACTION_QUEUE_SHIFT)
721 
722 /*
723  * DEST (R/W)
724  *
725  * Select the destination ports of forwarded frame. It is coded in onehot/select way,
726  * where 0 is always route to null. Every bit is mapped to a port.
727  * 00000 – to null (frame to clear)
728  * 00001 – to port 0 (CPU Port)
729  * 00010 – to port 1
730  * 00100 – to port 2
731  * 01000 – to port 3
732  */
733 #define TSW_LU_MAIN_INTF_ACTION_DEST_MASK (0xFFFFU)
734 #define TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT (0U)
735 #define TSW_LU_MAIN_INTF_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK)
736 #define TSW_LU_MAIN_INTF_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_INTF_ACTION_DEST_MASK) >> TSW_LU_MAIN_INTF_ACTION_DEST_SHIFT)
737 
738 /* Bitfield definition for register: LU_MAIN_BC_ACTION */
739 /*
740  * UTAG (R/W)
741  *
742  * TSN user sideband information from ALMEM
743  */
744 #define TSW_LU_MAIN_BC_ACTION_UTAG_MASK (0x1C00000UL)
745 #define TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT (22U)
746 #define TSW_LU_MAIN_BC_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK)
747 #define TSW_LU_MAIN_BC_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_UTAG_MASK) >> TSW_LU_MAIN_BC_ACTION_UTAG_SHIFT)
748 
749 /*
750  * QSEL (R/W)
751  *
752  * Define the traffic queue selection:
753  * 00 – use PCP field of VLAN, untagged frames use PCP of PVID
754  * 01 – use PCP field with global remapping list
755  * 10 – reserved
756  * 11 – use value QUEUE of Action List
757  */
758 #define TSW_LU_MAIN_BC_ACTION_QSEL_MASK (0x300000UL)
759 #define TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT (20U)
760 #define TSW_LU_MAIN_BC_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK)
761 #define TSW_LU_MAIN_BC_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QSEL_MASK) >> TSW_LU_MAIN_BC_ACTION_QSEL_SHIFT)
762 
763 /*
764  * DROP (R/W)
765  *
766  * 1 if frame should be dropped.
767  */
768 #define TSW_LU_MAIN_BC_ACTION_DROP_MASK (0x80000UL)
769 #define TSW_LU_MAIN_BC_ACTION_DROP_SHIFT (19U)
770 #define TSW_LU_MAIN_BC_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DROP_SHIFT) & TSW_LU_MAIN_BC_ACTION_DROP_MASK)
771 #define TSW_LU_MAIN_BC_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DROP_MASK) >> TSW_LU_MAIN_BC_ACTION_DROP_SHIFT)
772 
773 /*
774  * QUEUE (R/W)
775  *
776  * Select the Priority Queue for TSN TX, only used if QSEL=11
777  */
778 #define TSW_LU_MAIN_BC_ACTION_QUEUE_MASK (0x70000UL)
779 #define TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT (16U)
780 #define TSW_LU_MAIN_BC_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK)
781 #define TSW_LU_MAIN_BC_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_BC_ACTION_QUEUE_SHIFT)
782 
783 /*
784  * DEST (R/W)
785  *
786  * Select the destination ports of forwarded frame. It is coded in onehot/select way,
787  * where 0 is always route to null. Every bit is mapped to a port.
788  * 00000 – to null (frame to clear)
789  * 00001 – to port 0 (CPU Port)
790  * 00010 – to port 1
791  * 00100 – to port 2
792  * 01000 – to port 3
793  */
794 #define TSW_LU_MAIN_BC_ACTION_DEST_MASK (0xFFFFU)
795 #define TSW_LU_MAIN_BC_ACTION_DEST_SHIFT (0U)
796 #define TSW_LU_MAIN_BC_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_BC_ACTION_DEST_SHIFT) & TSW_LU_MAIN_BC_ACTION_DEST_MASK)
797 #define TSW_LU_MAIN_BC_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_BC_ACTION_DEST_MASK) >> TSW_LU_MAIN_BC_ACTION_DEST_SHIFT)
798 
799 /* Bitfield definition for register: LU_MAIN_NN_ACTION */
800 /*
801  * UTAG (R/W)
802  *
803  * TSN user sideband information from ALMEM
804  */
805 #define TSW_LU_MAIN_NN_ACTION_UTAG_MASK (0x1C00000UL)
806 #define TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT (22U)
807 #define TSW_LU_MAIN_NN_ACTION_UTAG_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK)
808 #define TSW_LU_MAIN_NN_ACTION_UTAG_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_UTAG_MASK) >> TSW_LU_MAIN_NN_ACTION_UTAG_SHIFT)
809 
810 /*
811  * QSEL (R/W)
812  *
813  * Define the traffic queue selection:
814  * 00 – use PCP field of VLAN, untagged frames use PCP of PVID
815  * 01 – use PCP field with global remapping list
816  * 10 – reserved
817  * 11 – use value QUEUE of Action List
818  */
819 #define TSW_LU_MAIN_NN_ACTION_QSEL_MASK (0x300000UL)
820 #define TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT (20U)
821 #define TSW_LU_MAIN_NN_ACTION_QSEL_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK)
822 #define TSW_LU_MAIN_NN_ACTION_QSEL_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QSEL_MASK) >> TSW_LU_MAIN_NN_ACTION_QSEL_SHIFT)
823 
824 /*
825  * DROP (R/W)
826  *
827  * 1 if frame should be dropped.
828  */
829 #define TSW_LU_MAIN_NN_ACTION_DROP_MASK (0x80000UL)
830 #define TSW_LU_MAIN_NN_ACTION_DROP_SHIFT (19U)
831 #define TSW_LU_MAIN_NN_ACTION_DROP_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DROP_SHIFT) & TSW_LU_MAIN_NN_ACTION_DROP_MASK)
832 #define TSW_LU_MAIN_NN_ACTION_DROP_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DROP_MASK) >> TSW_LU_MAIN_NN_ACTION_DROP_SHIFT)
833 
834 /*
835  * QUEUE (R/W)
836  *
837  * Select the Priority Queue for TSN TX, only used if QSEL=11
838  */
839 #define TSW_LU_MAIN_NN_ACTION_QUEUE_MASK (0x70000UL)
840 #define TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT (16U)
841 #define TSW_LU_MAIN_NN_ACTION_QUEUE_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK)
842 #define TSW_LU_MAIN_NN_ACTION_QUEUE_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_QUEUE_MASK) >> TSW_LU_MAIN_NN_ACTION_QUEUE_SHIFT)
843 
844 /*
845  * DEST (R/W)
846  *
847  * Select the destination ports of forwarded frame. It is coded in onehot/select way,
848  * where 0 is always route to null. Every bit is mapped to a port.
849  * 00000 – to null (frame to clear)
850  * 00001 – to port 0 (CPU Port)
851  * 00010 – to port 1
852  * 00100 – to port 2
853  * 01000 – to port 3
854  */
855 #define TSW_LU_MAIN_NN_ACTION_DEST_MASK (0xFFFFU)
856 #define TSW_LU_MAIN_NN_ACTION_DEST_SHIFT (0U)
857 #define TSW_LU_MAIN_NN_ACTION_DEST_SET(x) (((uint32_t)(x) << TSW_LU_MAIN_NN_ACTION_DEST_SHIFT) & TSW_LU_MAIN_NN_ACTION_DEST_MASK)
858 #define TSW_LU_MAIN_NN_ACTION_DEST_GET(x) (((uint32_t)(x) & TSW_LU_MAIN_NN_ACTION_DEST_MASK) >> TSW_LU_MAIN_NN_ACTION_DEST_SHIFT)
859 
860 /* Bitfield definition for register: APB2AXIS_CAM_STS */
861 /*
862  * BUSY (RO)
863  *
864  * the controller is writing data and/or data is pending
865  */
866 #define TSW_APB2AXIS_CAM_STS_BUSY_MASK (0x2U)
867 #define TSW_APB2AXIS_CAM_STS_BUSY_SHIFT (1U)
868 #define TSW_APB2AXIS_CAM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_BUSY_MASK) >> TSW_APB2AXIS_CAM_STS_BUSY_SHIFT)
869 
870 /*
871  * RDY (RO)
872  *
873  * the new data is written to data register
874  */
875 #define TSW_APB2AXIS_CAM_STS_RDY_MASK (0x1U)
876 #define TSW_APB2AXIS_CAM_STS_RDY_SHIFT (0U)
877 #define TSW_APB2AXIS_CAM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_STS_RDY_MASK) >> TSW_APB2AXIS_CAM_STS_RDY_SHIFT)
878 
879 /* Bitfield definition for register: APB2AXIS_CAM_REQ_CNT */
880 /*
881  * WRCNT (RO)
882  *
883  * number of streams in queue
884  */
885 #define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK (0xFFU)
886 #define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT (0U)
887 #define TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_CAM_REQ_CNT_WRCNT_SHIFT)
888 
889 /* Bitfield definition for register: APB2AXIS_CAM_FILLSTS */
890 /*
891  * FULL (RO)
892  *
893  * frame was dropped because the internal descriptor FIFO is full
894  */
895 #define TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK (0x10U)
896 #define TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT (4U)
897 #define TSW_APB2AXIS_CAM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_FULL_SHIFT)
898 
899 /*
900  * EMPTY (RO)
901  *
902  * FD FIFO failure, internal controller lost synchronization
903  */
904 #define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK (0x1U)
905 #define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT (0U)
906 #define TSW_APB2AXIS_CAM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_CAM_FILLSTS_EMPTY_SHIFT)
907 
908 /* Bitfield definition for register: APB2AXIS_CAM_RESET */
909 /*
910  * RESET (W1C)
911  *
912  * resets controller and clears all pending stream data
913  */
914 #define TSW_APB2AXIS_CAM_RESET_RESET_MASK (0x1U)
915 #define TSW_APB2AXIS_CAM_RESET_RESET_SHIFT (0U)
916 #define TSW_APB2AXIS_CAM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_CAM_RESET_RESET_SHIFT) & TSW_APB2AXIS_CAM_RESET_RESET_MASK)
917 #define TSW_APB2AXIS_CAM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_RESET_RESET_MASK) >> TSW_APB2AXIS_CAM_RESET_RESET_SHIFT)
918 
919 /* Bitfield definition for register: APB2AXIS_CAM_PARAM */
920 /*
921  * DEPTH (RO)
922  *
923  * number of configured buffer depth
924  */
925 #define TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK (0xFF00U)
926 #define TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT (8U)
927 #define TSW_APB2AXIS_CAM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_CAM_PARAM_DEPTH_SHIFT)
928 
929 /*
930  * WORDLEN_BYTE (RO)
931  *
932  * number of configured 32bit words for this controller
933  */
934 #define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK (0xFFU)
935 #define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT (0U)
936 #define TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_CAM_PARAM_WORDLEN_BYTE_SHIFT)
937 
938 /* Bitfield definition for register: APB2AXI_CAM_REQDATA_0 */
939 /*
940  * ENTRY_NUM (R/W)
941  *
942  * entry number
943  */
944 #define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK (0xFFFF0000UL)
945 #define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT (16U)
946 #define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK)
947 #define TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_ENTRY_NUM_SHIFT)
948 
949 /*
950  * TYPE (R/W)
951  *
952  * select between set, clear or clear all
953  */
954 #define TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK (0x300U)
955 #define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT (8U)
956 #define TSW_APB2AXI_CAM_REQDATA_0_TYPE_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK)
957 #define TSW_APB2AXI_CAM_REQDATA_0_TYPE_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_TYPE_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_TYPE_SHIFT)
958 
959 /*
960  * CH (R/W)
961  *
962  * CAM APB2AXIS channel selection
963  */
964 #define TSW_APB2AXI_CAM_REQDATA_0_CH_MASK (0x1U)
965 #define TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT (0U)
966 #define TSW_APB2AXI_CAM_REQDATA_0_CH_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK)
967 #define TSW_APB2AXI_CAM_REQDATA_0_CH_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_0_CH_MASK) >> TSW_APB2AXI_CAM_REQDATA_0_CH_SHIFT)
968 
969 /* Bitfield definition for register: APB2AXI_CAM_REQDATA_1 */
970 /*
971  * DESTMAC_LO_PORT_VEC (R/W)
972  *
973  * dest-mac[31:0] when CH=0；PORT_VEC when CH=1
974  */
975 #define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK (0xFFFFFFFFUL)
976 #define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT (0U)
977 #define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK)
978 #define TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_MASK) >> TSW_APB2AXI_CAM_REQDATA_1_DESTMAC_LO_PORT_VEC_SHIFT)
979 
980 /* Bitfield definition for register: APB2AXI_CAM_REQDATA_2 */
981 /*
982  * VID (R/W)
983  *
984  * VLAN-ID value (12 bit) for the VLAN_ID table. Use the fefault VLAN-ID(VID=1), if setup an entry for non-VLAN traffic.
985  */
986 #define TSW_APB2AXI_CAM_REQDATA_2_VID_MASK (0xFFF0000UL)
987 #define TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT (16U)
988 #define TSW_APB2AXI_CAM_REQDATA_2_VID_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK)
989 #define TSW_APB2AXI_CAM_REQDATA_2_VID_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_VID_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_VID_SHIFT)
990 
991 /*
992  * DESTMAC_HI (R/W)
993  *
994  * dest-mac[47:32] when CH=0
995  */
996 #define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK (0xFFFFU)
997 #define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT (0U)
998 #define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SET(x) (((uint32_t)(x) << TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK)
999 #define TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_GET(x) (((uint32_t)(x) & TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_MASK) >> TSW_APB2AXI_CAM_REQDATA_2_DESTMAC_HI_SHIFT)
1000 
1001 /* Bitfield definition for register: APB2AXIS_ALMEM_STS */
1002 /*
1003  * BUSY (RO)
1004  *
1005  * the controller is writing data and/or data is pending
1006  */
1007 #define TSW_APB2AXIS_ALMEM_STS_BUSY_MASK (0x2U)
1008 #define TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT (1U)
1009 #define TSW_APB2AXIS_ALMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_BUSY_MASK) >> TSW_APB2AXIS_ALMEM_STS_BUSY_SHIFT)
1010 
1011 /*
1012  * RDY (RO)
1013  *
1014  * the new data is written to data register
1015  */
1016 #define TSW_APB2AXIS_ALMEM_STS_RDY_MASK (0x1U)
1017 #define TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT (0U)
1018 #define TSW_APB2AXIS_ALMEM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_STS_RDY_MASK) >> TSW_APB2AXIS_ALMEM_STS_RDY_SHIFT)
1019 
1020 /* Bitfield definition for register: APB2AXIS_ALMEM_REQ_CNT */
1021 /*
1022  * WRCNT (RO)
1023  *
1024  * number of streams in queue
1025  */
1026 #define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK (0xFFU)
1027 #define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT (0U)
1028 #define TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_ALMEM_REQ_CNT_WRCNT_SHIFT)
1029 
1030 /* Bitfield definition for register: APB2AXIS_ALMEM_FILLSTS */
1031 /*
1032  * FULL (RO)
1033  *
1034  * frame was dropped because the internal descriptor FIFO is full
1035  */
1036 #define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK (0x10U)
1037 #define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT (4U)
1038 #define TSW_APB2AXIS_ALMEM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_FULL_SHIFT)
1039 
1040 /*
1041  * EMPTY (RO)
1042  *
1043  * FD FIFO failure, internal controller lost synchronization
1044  */
1045 #define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK (0x1U)
1046 #define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT (0U)
1047 #define TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_ALMEM_FILLSTS_EMPTY_SHIFT)
1048 
1049 /* Bitfield definition for register: APB2AXIS_ALMEM_RESET */
1050 /*
1051  * RESET (W1C)
1052  *
1053  * resets controller and clears all pending stream data
1054  */
1055 #define TSW_APB2AXIS_ALMEM_RESET_RESET_MASK (0x1U)
1056 #define TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT (0U)
1057 #define TSW_APB2AXIS_ALMEM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK)
1058 #define TSW_APB2AXIS_ALMEM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_RESET_RESET_MASK) >> TSW_APB2AXIS_ALMEM_RESET_RESET_SHIFT)
1059 
1060 /* Bitfield definition for register: APB2AXIS_ALMEM_PARAM */
1061 /*
1062  * DEPTH (RO)
1063  *
1064  * number of configured buffer depth
1065  */
1066 #define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK (0xFF00U)
1067 #define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT (8U)
1068 #define TSW_APB2AXIS_ALMEM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_DEPTH_SHIFT)
1069 
1070 /*
1071  * WORDLEN_BYTE (RO)
1072  *
1073  * number of configured 32bit words for this controller
1074  */
1075 #define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1076 #define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT (0U)
1077 #define TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)
1078 
1079 /* Bitfield definition for register: APB2AXIS_ALMEM_REQDATA_0 */
1080 /*
1081  * UTAG (R/W)
1082  *
1083  * user sideband information
1084  */
1085 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK (0x1C00000UL)
1086 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT (22U)
1087 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK)
1088 #define TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_UTAG_SHIFT)
1089 
1090 /*
1091  * QSEL (R/W)
1092  *
1093  * define the traffic queue selection
1094  */
1095 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK (0x300000UL)
1096 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT (20U)
1097 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK)
1098 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QSEL_SHIFT)
1099 
1100 /*
1101  * DROP (R/W)
1102  *
1103  * frame should dropped
1104  */
1105 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK (0x80000UL)
1106 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT (19U)
1107 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK)
1108 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DROP_SHIFT)
1109 
1110 /*
1111  * QUEUE (R/W)
1112  *
1113  * select the priority queue if qsel=11
1114  */
1115 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK (0x70000UL)
1116 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT (16U)
1117 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK)
1118 #define TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_QUEUE_SHIFT)
1119 
1120 /*
1121  * DEST (R/W)
1122  *
1123  * destination ports
1124  */
1125 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK (0xFFFFU)
1126 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT (0U)
1127 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK)
1128 #define TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_0_DEST_SHIFT)
1129 
1130 /* Bitfield definition for register: APB2AXIS_ALMEM_REQDATA_1 */
1131 /*
1132  * WR_NRD (R/W)
1133  *
1134  * 1 for write and 0 for read
1135  */
1136 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK (0x80000000UL)
1137 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT (31U)
1138 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK)
1139 #define TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_WR_NRD_SHIFT)
1140 
1141 /*
1142  * RESP (R/W)
1143  *
1144  * write response enable
1145  */
1146 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK (0x40000000UL)
1147 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT (30U)
1148 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK)
1149 #define TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_RESP_SHIFT)
1150 
1151 /*
1152  * ENTRY_NUM (R/W)
1153  *
1154  * define the entry number for reading and writing
1155  */
1156 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK (0xFFFFU)
1157 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT (0U)
1158 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK)
1159 #define TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_MASK) >> TSW_APB2AXIS_ALMEM_REQDATA_1_ENTRY_NUM_SHIFT)
1160 
1161 /* Bitfield definition for register: AXIS2APB_ALMEM_STS */
1162 /*
1163  * BUSY (RO)
1164  *
1165  * the controller is writing data and/or data is pending
1166  */
1167 #define TSW_AXIS2APB_ALMEM_STS_BUSY_MASK (0x2U)
1168 #define TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT (1U)
1169 #define TSW_AXIS2APB_ALMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_BUSY_MASK) >> TSW_AXIS2APB_ALMEM_STS_BUSY_SHIFT)
1170 
1171 /*
1172  * RDY (RO)
1173  *
1174  * the new data is written to data register
1175  */
1176 #define TSW_AXIS2APB_ALMEM_STS_RDY_MASK (0x1U)
1177 #define TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT (0U)
1178 #define TSW_AXIS2APB_ALMEM_STS_RDY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_STS_RDY_MASK) >> TSW_AXIS2APB_ALMEM_STS_RDY_SHIFT)
1179 
1180 /* Bitfield definition for register: AXIS2APB_ALMEM_RESP_CNT */
1181 /*
1182  * RDCNT (RO)
1183  *
1184  * number of streams in queue
1185  */
1186 #define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK (0xFFU)
1187 #define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT (0U)
1188 #define TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_ALMEM_RESP_CNT_RDCNT_SHIFT)
1189 
1190 /* Bitfield definition for register: AXIS2APB_ALMEM_FILLSTS */
1191 /*
1192  * FULL (RO)
1193  *
1194  * FD FIFO full
1195  */
1196 #define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK (0x10U)
1197 #define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT (4U)
1198 #define TSW_AXIS2APB_ALMEM_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_FULL_SHIFT)
1199 
1200 /*
1201  * EMPTY (RO)
1202  *
1203  * FD FIFO failure
1204  */
1205 #define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK (0x1U)
1206 #define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT (0U)
1207 #define TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_ALMEM_FILLSTS_EMPTY_SHIFT)
1208 
1209 /* Bitfield definition for register: AXIS2APB_ALMEM_RESET */
1210 /*
1211  * RESET (R/W)
1212  *
1213  * Resets controller and clears all pending stream data
1214  */
1215 #define TSW_AXIS2APB_ALMEM_RESET_RESET_MASK (0x1U)
1216 #define TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT (0U)
1217 #define TSW_AXIS2APB_ALMEM_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK)
1218 #define TSW_AXIS2APB_ALMEM_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESET_RESET_MASK) >> TSW_AXIS2APB_ALMEM_RESET_RESET_SHIFT)
1219 
1220 /* Bitfield definition for register: AXIS2APB_ALMEM_PARAM */
1221 /*
1222  * DEPTH (RO)
1223  *
1224  * number of configured buffer depth
1225  */
1226 #define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK (0xFF00U)
1227 #define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT (8U)
1228 #define TSW_AXIS2APB_ALMEM_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_DEPTH_SHIFT)
1229 
1230 /*
1231  * WORDLEN_BYTE (RO)
1232  *
1233  * number of configured 32bit for this controller
1234  */
1235 #define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1236 #define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT (0U)
1237 #define TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_ALMEM_PARAM_WORDLEN_BYTE_SHIFT)
1238 
1239 /* Bitfield definition for register: AXIS2APB_ALMEM_RESPDATA_0 */
1240 /*
1241  * UTAG (R/W)
1242  *
1243  * user sideband information
1244  */
1245 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK (0x1C00000UL)
1246 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT (22U)
1247 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK)
1248 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_UTAG_SHIFT)
1249 
1250 /*
1251  * QSEL (R/W)
1252  *
1253  * define the traffic queue selection
1254  */
1255 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK (0x300000UL)
1256 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT (20U)
1257 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK)
1258 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QSEL_SHIFT)
1259 
1260 /*
1261  * DROP (R/W)
1262  *
1263  * frame should dropped
1264  */
1265 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK (0x80000UL)
1266 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT (19U)
1267 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK)
1268 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DROP_SHIFT)
1269 
1270 /*
1271  * QUEUE (R/W)
1272  *
1273  * select the priority queue if qsel=11
1274  */
1275 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK (0x70000UL)
1276 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT (16U)
1277 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK)
1278 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_QUEUE_SHIFT)
1279 
1280 /*
1281  * DEST (R/W)
1282  *
1283  * destination ports
1284  */
1285 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK (0xFFFFU)
1286 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT (0U)
1287 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK)
1288 #define TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_0_DEST_SHIFT)
1289 
1290 /* Bitfield definition for register: AXIS2APB_ALMEM_RESPDATA_1 */
1291 /*
1292  * WR_NRD (R/W)
1293  *
1294  * 1 for write and 0 for read
1295  */
1296 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK (0x80000000UL)
1297 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT (31U)
1298 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK)
1299 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_WR_NRD_SHIFT)
1300 
1301 /*
1302  * RESP (R/W)
1303  *
1304  * write response enable
1305  */
1306 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK (0x40000000UL)
1307 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT (30U)
1308 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK)
1309 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_RESP_SHIFT)
1310 
1311 /*
1312  * ENTRY_NUM (R/W)
1313  *
1314  * define the entry number for reading and writing
1315  */
1316 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK (0xFFFFU)
1317 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT (0U)
1318 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK)
1319 #define TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_ALMEM_RESPDATA_1_ENTRY_NUM_SHIFT)
1320 
1321 /* Bitfield definition for register array: HITMEM */
1322 /*
1323  * HITMEM_REG (RW)
1324  *
1325  * Every bit represents a lookup entry starting with bit 0
1326  * as entry 0. The memory can be written and cleared by the host system via common memory-mapped
1327  * bus access.
1328  */
1329 #define TSW_HITMEM_HITMEM_REG_MASK (0xFFFFFFFFUL)
1330 #define TSW_HITMEM_HITMEM_REG_SHIFT (0U)
1331 #define TSW_HITMEM_HITMEM_REG_SET(x) (((uint32_t)(x) << TSW_HITMEM_HITMEM_REG_SHIFT) & TSW_HITMEM_HITMEM_REG_MASK)
1332 #define TSW_HITMEM_HITMEM_REG_GET(x) (((uint32_t)(x) & TSW_HITMEM_HITMEM_REG_MASK) >> TSW_HITMEM_HITMEM_REG_SHIFT)
1333 
1334 /* Bitfield definition for register: APB2AXIS_LOOKUP_STS */
1335 /*
1336  * BUSY (RO)
1337  *
1338  * the controller is writing data and/or data is pending
1339  */
1340 #define TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK (0x2U)
1341 #define TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT (1U)
1342 #define TSW_APB2AXIS_LOOKUP_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_BUSY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_BUSY_SHIFT)
1343 
1344 /*
1345  * RDY (RO)
1346  *
1347  * the new data is written to data register
1348  */
1349 #define TSW_APB2AXIS_LOOKUP_STS_RDY_MASK (0x1U)
1350 #define TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT (0U)
1351 #define TSW_APB2AXIS_LOOKUP_STS_RDY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_STS_RDY_MASK) >> TSW_APB2AXIS_LOOKUP_STS_RDY_SHIFT)
1352 
1353 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQ_CNT */
1354 /*
1355  * WRCNT (RO)
1356  *
1357  * number of streams in queue
1358  */
1359 #define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK (0xFFU)
1360 #define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT (0U)
1361 #define TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_MASK) >> TSW_APB2AXIS_LOOKUP_REQ_CNT_WRCNT_SHIFT)
1362 
1363 /* Bitfield definition for register: APB2AXIS_LOOKUP_FILLSTS */
1364 /*
1365  * FULL (RO)
1366  *
1367  * FD FIFO full
1368  */
1369 #define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK (0x10U)
1370 #define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT (4U)
1371 #define TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_FULL_SHIFT)
1372 
1373 /*
1374  * EMPTY (RO)
1375  *
1376  * FD FIFO failure
1377  */
1378 #define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK (0x1U)
1379 #define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT (0U)
1380 #define TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_APB2AXIS_LOOKUP_FILLSTS_EMPTY_SHIFT)
1381 
1382 /* Bitfield definition for register: APB2AXIS_LOOKUP_RESET */
1383 /*
1384  * RESET (R/W)
1385  *
1386  * Resets controller and clears all pending stream data
1387  */
1388 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK (0x1U)
1389 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT (0U)
1390 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK)
1391 #define TSW_APB2AXIS_LOOKUP_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_RESET_RESET_MASK) >> TSW_APB2AXIS_LOOKUP_RESET_RESET_SHIFT)
1392 
1393 /* Bitfield definition for register: APB2AXIS_LOOKUP_PARAM */
1394 /*
1395  * DEPTH (RO)
1396  *
1397  * number of configured buffer depth
1398  */
1399 #define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK (0xFF00U)
1400 #define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT (8U)
1401 #define TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_DEPTH_SHIFT)
1402 
1403 /*
1404  * WORDLEN_BYTE (RO)
1405  *
1406  * number of configured 32bit for this controller
1407  */
1408 #define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1409 #define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT (0U)
1410 #define TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_APB2AXIS_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)
1411 
1412 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_0 */
1413 /*
1414  * DESTMAC (RW)
1415  *
1416  * Holding the first four bytes of requested MAC address.
1417  */
1418 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK (0xFFFFFFFFUL)
1419 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT (0U)
1420 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK)
1421 #define TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_0_DESTMAC_SHIFT)
1422 
1423 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_1 */
1424 /*
1425  * DESTMAC (RW)
1426  *
1427  * Holding the last two bytes of requested MAC address.
1428  */
1429 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK (0xFFFFU)
1430 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT (0U)
1431 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK)
1432 #define TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_1_DESTMAC_SHIFT)
1433 
1434 /* Bitfield definition for register: APB2AXIS_LOOKUP_REQDATA_3 */
1435 /*
1436  * IS_VLAN (RW)
1437  *
1438  * Tell the LOOKUP module the requested traffic is VLAN tagged.
1439  */
1440 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK (0x10000UL)
1441 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT (16U)
1442 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK)
1443 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_IS_VLAN_SHIFT)
1444 
1445 /*
1446  * VLAN_TCI (RW)
1447  *
1448  * Set the requested traffic VLAN_TCI, if IS_VLAN=1.
1449  */
1450 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK (0xFFFFU)
1451 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT (0U)
1452 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SET(x) (((uint32_t)(x) << TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK)
1453 #define TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_GET(x) (((uint32_t)(x) & TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_MASK) >> TSW_APB2AXIS_LOOKUP_REQDATA_3_VLAN_TCI_SHIFT)
1454 
1455 /* Bitfield definition for register: AXIS2APB_LOOKUP_STS */
1456 /*
1457  * BUSY (RO)
1458  *
1459  * the controller is writing data and/or data is pending
1460  */
1461 #define TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK (0x2U)
1462 #define TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT (1U)
1463 #define TSW_AXIS2APB_LOOKUP_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_BUSY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_BUSY_SHIFT)
1464 
1465 /*
1466  * RDY (RO)
1467  *
1468  * the new data is written to data register
1469  */
1470 #define TSW_AXIS2APB_LOOKUP_STS_RDY_MASK (0x1U)
1471 #define TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT (0U)
1472 #define TSW_AXIS2APB_LOOKUP_STS_RDY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_STS_RDY_MASK) >> TSW_AXIS2APB_LOOKUP_STS_RDY_SHIFT)
1473 
1474 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESP_CNT */
1475 /*
1476  * RDCNT (RO)
1477  *
1478  * number of streams in queue
1479  */
1480 #define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK (0xFFU)
1481 #define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT (0U)
1482 #define TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_MASK) >> TSW_AXIS2APB_LOOKUP_RESP_CNT_RDCNT_SHIFT)
1483 
1484 /* Bitfield definition for register: AXIS2APB_LOOKUP_FILLSTS */
1485 /*
1486  * FULL (RO)
1487  *
1488  * FD FIFO full
1489  */
1490 #define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK (0x10U)
1491 #define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT (4U)
1492 #define TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_FULL_SHIFT)
1493 
1494 /*
1495  * EMPTY (RO)
1496  *
1497  * FD FIFO failure
1498  */
1499 #define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK (0x1U)
1500 #define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT (0U)
1501 #define TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_MASK) >> TSW_AXIS2APB_LOOKUP_FILLSTS_EMPTY_SHIFT)
1502 
1503 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESET */
1504 /*
1505  * RESET (R/W)
1506  *
1507  * Resets controller and clears all pending stream data
1508  */
1509 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK (0x1U)
1510 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT (0U)
1511 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK)
1512 #define TSW_AXIS2APB_LOOKUP_RESET_RESET_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESET_RESET_MASK) >> TSW_AXIS2APB_LOOKUP_RESET_RESET_SHIFT)
1513 
1514 /* Bitfield definition for register: AXIS2APB_LOOKUP_PARAM */
1515 /*
1516  * DEPTH (RO)
1517  *
1518  * number of configured buffer depth
1519  */
1520 #define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK (0xFF00U)
1521 #define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT (8U)
1522 #define TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_DEPTH_SHIFT)
1523 
1524 /*
1525  * WORDLEN_BYTE (RO)
1526  *
1527  * number of configured 32bit for this controller
1528  */
1529 #define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK (0xFFU)
1530 #define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT (0U)
1531 #define TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_MASK) >> TSW_AXIS2APB_LOOKUP_PARAM_WORDLEN_BYTE_SHIFT)
1532 
1533 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESPDATA_0 */
1534 /*
1535  * DROP_VLAN (RW)
1536  *
1537  * Used for statistics. Shows that drop occurs by VLAN-ID
1538  */
1539 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK (0x2000000UL)
1540 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT (25U)
1541 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK)
1542 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_VLAN_SHIFT)
1543 
1544 /*
1545  * HIT (RW)
1546  *
1547  * Is 1, if DESTMAC and VID hit an entry.
1548  */
1549 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK (0x1000000UL)
1550 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT (24U)
1551 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK)
1552 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_SHIFT)
1553 
1554 /*
1555  * UTAG (RW)
1556  *
1557  * TSN user sideband information from ALMEM.
1558  */
1559 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK (0xE00000UL)
1560 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT (21U)
1561 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK)
1562 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_UTAG_SHIFT)
1563 
1564 /*
1565  * HIT_VLAN (RW)
1566  *
1567  * Is 1, if VID hit entry in VLAN_PORT table.
1568  */
1569 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK (0x100000UL)
1570 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT (20U)
1571 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK)
1572 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_HIT_VLAN_SHIFT)
1573 
1574 /*
1575  * DROP (RW)
1576  *
1577  * Indicate that the frame should be dropped.
1578  */
1579 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK (0x80000UL)
1580 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT (19U)
1581 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK)
1582 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DROP_SHIFT)
1583 
1584 /*
1585  * QUEUE (RW)
1586  *
1587  * TX traffic queue selection.
1588  */
1589 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK (0x70000UL)
1590 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT (16U)
1591 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK)
1592 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_QUEUE_SHIFT)
1593 
1594 /*
1595  * DEST (RW)
1596  *
1597  * Forwarding ports from 0 to 15, Bit 0 is CPU port.
1598  */
1599 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK (0xFFFFU)
1600 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT (0U)
1601 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK)
1602 #define TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_0_DEST_SHIFT)
1603 
1604 /* Bitfield definition for register: AXIS2APB_LOOKUP_RESPDATA_1 */
1605 /*
1606  * ENTRY_NUM (RW)
1607  *
1608  * Entry number of ALMEM.
1609  */
1610 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK (0xFFFFU)
1611 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT (0U)
1612 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SET(x) (((uint32_t)(x) << TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK)
1613 #define TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_GET(x) (((uint32_t)(x) & TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_MASK) >> TSW_AXIS2APB_LOOKUP_RESPDATA_1_ENTRY_NUM_SHIFT)
1614 
1615 /* Bitfield definition for register: CENTRAL_CSR_VERSION */
1616 /*
1617  * VER_HI (RO)
1618  *
1619  * Major Version number of TSN-SW core.
1620  */
1621 #define TSW_CENTRAL_CSR_VERSION_VER_HI_MASK (0xFF000000UL)
1622 #define TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT (24U)
1623 #define TSW_CENTRAL_CSR_VERSION_VER_HI_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_HI_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_HI_SHIFT)
1624 
1625 /*
1626  * VER_LO (RO)
1627  *
1628  * Minor Version number of TSN-SW core.
1629  */
1630 #define TSW_CENTRAL_CSR_VERSION_VER_LO_MASK (0xFF0000UL)
1631 #define TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT (16U)
1632 #define TSW_CENTRAL_CSR_VERSION_VER_LO_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_LO_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_LO_SHIFT)
1633 
1634 /*
1635  * VER_REV (RO)
1636  *
1637  * Reversion number of TSN-SW core.
1638  */
1639 #define TSW_CENTRAL_CSR_VERSION_VER_REV_MASK (0xFFU)
1640 #define TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT (0U)
1641 #define TSW_CENTRAL_CSR_VERSION_VER_REV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_VERSION_VER_REV_MASK) >> TSW_CENTRAL_CSR_VERSION_VER_REV_SHIFT)
1642 
1643 /* Bitfield definition for register: CENTRAL_CSR_PARAM */
1644 /*
1645  * INCL_QCI (RO)
1646  *
1647  * Shows if QCI module is present.
1648  */
1649 #define TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK (0x40000UL)
1650 #define TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT (18U)
1651 #define TSW_CENTRAL_CSR_PARAM_INCL_QCI_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_QCI_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_QCI_SHIFT)
1652 
1653 /*
1654  * INCL_CB0 (RO)
1655  *
1656  * Shows if IP is configured with “lightweight” 802.1CB at CPU-Port.
1657  */
1658 #define TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK (0x20000UL)
1659 #define TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT (17U)
1660 #define TSW_CENTRAL_CSR_PARAM_INCL_CB0_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_INCL_CB0_MASK) >> TSW_CENTRAL_CSR_PARAM_INCL_CB0_SHIFT)
1661 
1662 /*
1663  * TESTMODE (RO)
1664  *
1665  * Shows if IP is configured in TESTMODE.
1666  */
1667 #define TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK (0x10000UL)
1668 #define TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT (16U)
1669 #define TSW_CENTRAL_CSR_PARAM_TESTMODE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TESTMODE_MASK) >> TSW_CENTRAL_CSR_PARAM_TESTMODE_SHIFT)
1670 
1671 /*
1672  * TYPE (RO)
1673  *
1674  * Specify type of switch core
1675  */
1676 #define TSW_CENTRAL_CSR_PARAM_TYPE_MASK (0xFF00U)
1677 #define TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT (8U)
1678 #define TSW_CENTRAL_CSR_PARAM_TYPE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_TYPE_MASK) >> TSW_CENTRAL_CSR_PARAM_TYPE_SHIFT)
1679 
1680 /*
1681  * NPORTS (RO)
1682  *
1683  * Number of TSN ports without counting internal CPU port. For TSN-SE, it returns always 2
1684  */
1685 #define TSW_CENTRAL_CSR_PARAM_NPORTS_MASK (0xFFU)
1686 #define TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT (0U)
1687 #define TSW_CENTRAL_CSR_PARAM_NPORTS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_PARAM_NPORTS_MASK) >> TSW_CENTRAL_CSR_PARAM_NPORTS_SHIFT)
1688 
1689 /* Bitfield definition for register: CENTRAL_CSR_CONFIG */
1690 /*
1691  * MSEC_CYCLES (R/W)
1692  *
1693  * Number of SYS_CLK cycles during 1 ms. It is required to calculate a correct time
1694  */
1695 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK (0xFFFFFFUL)
1696 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT (0U)
1697 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SET(x) (((uint32_t)(x) << TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK)
1698 #define TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_MASK) >> TSW_CENTRAL_CSR_CONFIG_MSEC_CYCLES_SHIFT)
1699 
1700 /* Bitfield definition for register: CENTRAL_CSR_CB_PARAM */
1701 /*
1702  * SID_D (RO)
1703  *
1704  * Number of 802.1CB Stream Identification entries. 2^SID_D entries
1705  */
1706 #define TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK (0xFF00U)
1707 #define TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT (8U)
1708 #define TSW_CENTRAL_CSR_CB_PARAM_SID_D_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_SID_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_SID_D_SHIFT)
1709 
1710 /*
1711  * FRER_D (RO)
1712  *
1713  * Number of 802.1CB Recovery Function entries. 2^FRER_D entries.
1714  */
1715 #define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK (0xFFU)
1716 #define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT (0U)
1717 #define TSW_CENTRAL_CSR_CB_PARAM_FRER_D_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_CB_PARAM_FRER_D_MASK) >> TSW_CENTRAL_CSR_CB_PARAM_FRER_D_SHIFT)
1718 
1719 /* Bitfield definition for register: CENTRAL_CSR_QCI_CTRL_PARAM */
1720 /*
1721  * QCI_GTD (RO)
1722  *
1723  * (Log) gate table depth. 2**GTD entries.
1724  */
1725 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK (0xFF0000UL)
1726 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT (16U)
1727 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_GTD_SHIFT)
1728 
1729 /*
1730  * QCI_FMD (RO)
1731  *
1732  * (Log) flow meter depth. 2**FMD entries.
1733  */
1734 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK (0xFF00U)
1735 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT (8U)
1736 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FMD_SHIFT)
1737 
1738 /*
1739  * QCI_FTD (RO)
1740  *
1741  * (Log) filter table depth. 2**FTD entries.
1742  */
1743 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK (0xFFU)
1744 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT (0U)
1745 #define TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_MASK) >> TSW_CENTRAL_CSR_QCI_CTRL_PARAM_QCI_FTD_SHIFT)
1746 
1747 /* Bitfield definition for register: CENTRAL_QCI_HWCFG */
1748 /*
1749  * FMD (RO)
1750  *
1751  * FMD – parameter
1752  */
1753 #define TSW_CENTRAL_QCI_HWCFG_FMD_MASK (0xFF0000UL)
1754 #define TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT (16U)
1755 #define TSW_CENTRAL_QCI_HWCFG_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FMD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FMD_SHIFT)
1756 
1757 /*
1758  * GTD (RO)
1759  *
1760  * GTD – parameter
1761  */
1762 #define TSW_CENTRAL_QCI_HWCFG_GTD_MASK (0xFF00U)
1763 #define TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT (8U)
1764 #define TSW_CENTRAL_QCI_HWCFG_GTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_GTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_GTD_SHIFT)
1765 
1766 /*
1767  * FTD (RO)
1768  *
1769  * FTD – parameter
1770  */
1771 #define TSW_CENTRAL_QCI_HWCFG_FTD_MASK (0xFFU)
1772 #define TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT (0U)
1773 #define TSW_CENTRAL_QCI_HWCFG_FTD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_HWCFG_FTD_MASK) >> TSW_CENTRAL_QCI_HWCFG_FTD_SHIFT)
1774 
1775 /* Bitfield definition for register: CENTRAL_QCI_FILTERSEL */
1776 /*
1777  * INDEX (R/W)
1778  *
1779  * Filter select index
1780  * Any written value larger than the maximum index
1781  * (2**FTD-1) will result in a read-back value of <0>.
1782  */
1783 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK (0xFFU)
1784 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT (0U)
1785 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK)
1786 #define TSW_CENTRAL_QCI_FILTERSEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FILTERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_FILTERSEL_INDEX_SHIFT)
1787 
1788 /* Bitfield definition for register: CENTRAL_QCI_METERSEL */
1789 /*
1790  * INDEX (R/W)
1791  *
1792  * Flowmeter select index
1793  * Any written value larger than the maximum index
1794  * (2**FMD-1) will result in a read-back value of <0>.
1795  */
1796 #define TSW_CENTRAL_QCI_METERSEL_INDEX_MASK (0xFFU)
1797 #define TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT (0U)
1798 #define TSW_CENTRAL_QCI_METERSEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK)
1799 #define TSW_CENTRAL_QCI_METERSEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_METERSEL_INDEX_MASK) >> TSW_CENTRAL_QCI_METERSEL_INDEX_SHIFT)
1800 
1801 /* Bitfield definition for register: CENTRAL_QCI_GATESEL */
1802 /*
1803  * INDEX (R/W)
1804  *
1805  * Gate select index
1806  * Any written value larger than the maximum index
1807  * (2**GTD-1) will result in a read-back value of <0>.
1808  */
1809 #define TSW_CENTRAL_QCI_GATESEL_INDEX_MASK (0xFFU)
1810 #define TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT (0U)
1811 #define TSW_CENTRAL_QCI_GATESEL_INDEX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK)
1812 #define TSW_CENTRAL_QCI_GATESEL_INDEX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GATESEL_INDEX_MASK) >> TSW_CENTRAL_QCI_GATESEL_INDEX_SHIFT)
1813 
1814 /* Bitfield definition for register: CENTRAL_QCI_FCTRL */
1815 /*
1816  * ENBLK (R/W)
1817  *
1818  * Enable blocking of oversized frames
1819  * (802.1Qci – 8.6.5.1.1 (g))
1820  */
1821 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK (0x80000000UL)
1822 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT (31U)
1823 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK)
1824 #define TSW_CENTRAL_QCI_FCTRL_ENBLK_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENBLK_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENBLK_SHIFT)
1825 
1826 /*
1827  * ENFSZ (R/W)
1828  *
1829  * 0: No frame size check
1830  * 1: Frame size checking, size defined by FSIZE.MXSZ
1831  * (802.1Qci – 8.6.5.1.1 (e.1))
1832  */
1833 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK (0x40000000UL)
1834 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT (30U)
1835 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK)
1836 #define TSW_CENTRAL_QCI_FCTRL_ENFSZ_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFSZ_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFSZ_SHIFT)
1837 
1838 /*
1839  * ENFID (R/W)
1840  *
1841  * 0: No Flow Meter
1842  * 1: Enable Flow Metering
1843  * (802.1Qci – 8.6.5.1.1 (e.2))
1844  */
1845 #define TSW_CENTRAL_QCI_FCTRL_ENFID_MASK (0x20000000UL)
1846 #define TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT (29U)
1847 #define TSW_CENTRAL_QCI_FCTRL_ENFID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK)
1848 #define TSW_CENTRAL_QCI_FCTRL_ENFID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENFID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENFID_SHIFT)
1849 
1850 /*
1851  * ENSID (R/W)
1852  *
1853  * 0: Filter match any SID value
1854  * 1: Filter match SID value
1855  * (802.1Qci – 8.6.5.1.1 (b))
1856  */
1857 #define TSW_CENTRAL_QCI_FCTRL_ENSID_MASK (0x10000000UL)
1858 #define TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT (28U)
1859 #define TSW_CENTRAL_QCI_FCTRL_ENSID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK)
1860 #define TSW_CENTRAL_QCI_FCTRL_ENSID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENSID_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENSID_SHIFT)
1861 
1862 /*
1863  * ENPCP (R/W)
1864  *
1865  * 0: Filter match any PCP value
1866  * 1: Filter match PCP value
1867  * (802.1Qci – 8.6.5.1.1 (c))
1868  */
1869 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK (0x8000000UL)
1870 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT (27U)
1871 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK)
1872 #define TSW_CENTRAL_QCI_FCTRL_ENPCP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_ENPCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_ENPCP_SHIFT)
1873 
1874 /*
1875  * PCP (R/W)
1876  *
1877  * Filter priority code point, if enabled by ENPCP
1878  */
1879 #define TSW_CENTRAL_QCI_FCTRL_PCP_MASK (0x7000000UL)
1880 #define TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT (24U)
1881 #define TSW_CENTRAL_QCI_FCTRL_PCP_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK)
1882 #define TSW_CENTRAL_QCI_FCTRL_PCP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_PCP_MASK) >> TSW_CENTRAL_QCI_FCTRL_PCP_SHIFT)
1883 
1884 /*
1885  * FMD (R/W)
1886  *
1887  * Associated Flow Meter – if enabled by ENFID
1888  */
1889 #define TSW_CENTRAL_QCI_FCTRL_FMD_MASK (0xFF0000UL)
1890 #define TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT (16U)
1891 #define TSW_CENTRAL_QCI_FCTRL_FMD_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK)
1892 #define TSW_CENTRAL_QCI_FCTRL_FMD_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_FMD_MASK) >> TSW_CENTRAL_QCI_FCTRL_FMD_SHIFT)
1893 
1894 /*
1895  * GID (R/W)
1896  *
1897  * Associated Gate
1898  */
1899 #define TSW_CENTRAL_QCI_FCTRL_GID_MASK (0xFF00U)
1900 #define TSW_CENTRAL_QCI_FCTRL_GID_SHIFT (8U)
1901 #define TSW_CENTRAL_QCI_FCTRL_GID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_GID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_GID_MASK)
1902 #define TSW_CENTRAL_QCI_FCTRL_GID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_GID_MASK) >> TSW_CENTRAL_QCI_FCTRL_GID_SHIFT)
1903 
1904 /*
1905  * SID (R/W)
1906  *
1907  * Filter Stream ID – if enabled by ENSID
1908  */
1909 #define TSW_CENTRAL_QCI_FCTRL_SID_MASK (0xFFU)
1910 #define TSW_CENTRAL_QCI_FCTRL_SID_SHIFT (0U)
1911 #define TSW_CENTRAL_QCI_FCTRL_SID_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FCTRL_SID_SHIFT) & TSW_CENTRAL_QCI_FCTRL_SID_MASK)
1912 #define TSW_CENTRAL_QCI_FCTRL_SID_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FCTRL_SID_MASK) >> TSW_CENTRAL_QCI_FCTRL_SID_SHIFT)
1913 
1914 /* Bitfield definition for register: CENTRAL_QCI_FSIZE */
1915 /*
1916  * BLK (R/WC)
1917  *
1918  * Stream blocked due to oversize frame.
1919  * Write <1> to clear.
1920  * (802.1Qci – 8.6.5.1.1 (h))
1921  */
1922 #define TSW_CENTRAL_QCI_FSIZE_BLK_MASK (0x80000000UL)
1923 #define TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT (31U)
1924 #define TSW_CENTRAL_QCI_FSIZE_BLK_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK)
1925 #define TSW_CENTRAL_QCI_FSIZE_BLK_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_BLK_MASK) >> TSW_CENTRAL_QCI_FSIZE_BLK_SHIFT)
1926 
1927 /*
1928  * MXSZ (R/W)
1929  *
1930  * Maximum-SDU size in octets
1931  */
1932 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK (0xFFFFU)
1933 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT (0U)
1934 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK)
1935 #define TSW_CENTRAL_QCI_FSIZE_MXSZ_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_FSIZE_MXSZ_MASK) >> TSW_CENTRAL_QCI_FSIZE_MXSZ_SHIFT)
1936 
1937 /* Bitfield definition for register array: QCI_CNT */
1938 /*
1939  * VALUE (RO)
1940  *
1941  * Filter counter (see 802.1Qci 8.6.5.1.1 f)
1942  * CNT0: Frames that matched filter
1943  * CNT1: Frames that passed gate
1944  * CNT2: Frames that did not pass gate
1945  * CNT3: Frames that passed Maximum-SDU size check
1946  * CNT4: Frames that did not pass size check
1947  * CNT5: Frames discarded by Flow Meter operation
1948  * Counters starting at value <0> after reset.
1949  */
1950 #define TSW_QCI_CNT_VALUE_MASK (0xFFFFFFFFUL)
1951 #define TSW_QCI_CNT_VALUE_SHIFT (0U)
1952 #define TSW_QCI_CNT_VALUE_GET(x) (((uint32_t)(x) & TSW_QCI_CNT_VALUE_MASK) >> TSW_QCI_CNT_VALUE_SHIFT)
1953 
1954 /* Bitfield definition for register: CENTRAL_QCI_MCTRL */
1955 /*
1956  * RESET (WO)
1957  *
1958  * Flow Meter reset – self-resetting to <0>
1959  */
1960 #define TSW_CENTRAL_QCI_MCTRL_RESET_MASK (0x80000000UL)
1961 #define TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT (31U)
1962 #define TSW_CENTRAL_QCI_MCTRL_RESET_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK)
1963 #define TSW_CENTRAL_QCI_MCTRL_RESET_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_RESET_MASK) >> TSW_CENTRAL_QCI_MCTRL_RESET_SHIFT)
1964 
1965 /*
1966  * MAFR (RO)
1967  *
1968  * MarkAllFramesRed – cleared by RESET
1969  * (802.1Qci – 8.6.5.1.3 (j))
1970  */
1971 #define TSW_CENTRAL_QCI_MCTRL_MAFR_MASK (0x10U)
1972 #define TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT (4U)
1973 #define TSW_CENTRAL_QCI_MCTRL_MAFR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFR_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFR_SHIFT)
1974 
1975 /*
1976  * MAFREN (R/W)
1977  *
1978  * MarkAllFramesRedEnable
1979  * (802.1Qci – 8.6.5.1.3 (i))
1980  */
1981 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK (0x8U)
1982 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT (3U)
1983 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK)
1984 #define TSW_CENTRAL_QCI_MCTRL_MAFREN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_MAFREN_MASK) >> TSW_CENTRAL_QCI_MCTRL_MAFREN_SHIFT)
1985 
1986 /*
1987  * DOY (R/W)
1988  *
1989  * DropOnYellow
1990  * (802.1Qci – 8.6.5.1.3 (h))
1991  */
1992 #define TSW_CENTRAL_QCI_MCTRL_DOY_MASK (0x4U)
1993 #define TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT (2U)
1994 #define TSW_CENTRAL_QCI_MCTRL_DOY_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK)
1995 #define TSW_CENTRAL_QCI_MCTRL_DOY_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_DOY_MASK) >> TSW_CENTRAL_QCI_MCTRL_DOY_SHIFT)
1996 
1997 /*
1998  * CM (R/W)
1999  *
2000  * Color mode – functionally unused
2001  * (802.1Qci – 8.6.5.1.3 (g))
2002  */
2003 #define TSW_CENTRAL_QCI_MCTRL_CM_MASK (0x2U)
2004 #define TSW_CENTRAL_QCI_MCTRL_CM_SHIFT (1U)
2005 #define TSW_CENTRAL_QCI_MCTRL_CM_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CM_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CM_MASK)
2006 #define TSW_CENTRAL_QCI_MCTRL_CM_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CM_MASK) >> TSW_CENTRAL_QCI_MCTRL_CM_SHIFT)
2007 
2008 /*
2009  * CF (R/W)
2010  *
2011  * Coupling flag
2012  * (802.1Qci – 8.6.5.1.3 (f))
2013  */
2014 #define TSW_CENTRAL_QCI_MCTRL_CF_MASK (0x1U)
2015 #define TSW_CENTRAL_QCI_MCTRL_CF_SHIFT (0U)
2016 #define TSW_CENTRAL_QCI_MCTRL_CF_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_MCTRL_CF_SHIFT) & TSW_CENTRAL_QCI_MCTRL_CF_MASK)
2017 #define TSW_CENTRAL_QCI_MCTRL_CF_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_MCTRL_CF_MASK) >> TSW_CENTRAL_QCI_MCTRL_CF_SHIFT)
2018 
2019 /* Bitfield definition for register: CENTRAL_QCI_CIR */
2020 /*
2021  * CIR (R/W)
2022  *
2023  * Committed information rate – see Chapter 7.5.2.4.
2024  * (802.1Qci – 8.6.5.1.3 (b))
2025  */
2026 #define TSW_CENTRAL_QCI_CIR_CIR_MASK (0xFFFFFFUL)
2027 #define TSW_CENTRAL_QCI_CIR_CIR_SHIFT (0U)
2028 #define TSW_CENTRAL_QCI_CIR_CIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_CIR_CIR_SHIFT) & TSW_CENTRAL_QCI_CIR_CIR_MASK)
2029 #define TSW_CENTRAL_QCI_CIR_CIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_CIR_CIR_MASK) >> TSW_CENTRAL_QCI_CIR_CIR_SHIFT)
2030 
2031 /* Bitfield definition for register: CENTRAL_QCI_CBS */
2032 /*
2033  * CBS (R/W)
2034  *
2035  * Committed burst size, in bits (not octets!)
2036  * (802.1Qci – 8.6.5.1.3 (c))
2037  */
2038 #define TSW_CENTRAL_QCI_CBS_CBS_MASK (0xFFFFFFFFUL)
2039 #define TSW_CENTRAL_QCI_CBS_CBS_SHIFT (0U)
2040 #define TSW_CENTRAL_QCI_CBS_CBS_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_CBS_CBS_SHIFT) & TSW_CENTRAL_QCI_CBS_CBS_MASK)
2041 #define TSW_CENTRAL_QCI_CBS_CBS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_CBS_CBS_MASK) >> TSW_CENTRAL_QCI_CBS_CBS_SHIFT)
2042 
2043 /* Bitfield definition for register: CENTRAL_QCI_EIR */
2044 /*
2045  * EIR (R/W)
2046  *
2047  * Excess information rate – see Chapter 7.5.2.4.
2048  * (802.1Qci – 8.6.5.1.3 (d))
2049  */
2050 #define TSW_CENTRAL_QCI_EIR_EIR_MASK (0xFFFFFFUL)
2051 #define TSW_CENTRAL_QCI_EIR_EIR_SHIFT (0U)
2052 #define TSW_CENTRAL_QCI_EIR_EIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_EIR_EIR_SHIFT) & TSW_CENTRAL_QCI_EIR_EIR_MASK)
2053 #define TSW_CENTRAL_QCI_EIR_EIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_EIR_EIR_MASK) >> TSW_CENTRAL_QCI_EIR_EIR_SHIFT)
2054 
2055 /* Bitfield definition for register: CENTRAL_QCI_EBS */
2056 /*
2057  * EBS (R/W)
2058  *
2059  * Excess burst size, in bits (not octets)
2060  * (802.1Qci – 8.6.5.1.3 (e))
2061  */
2062 #define TSW_CENTRAL_QCI_EBS_EBS_MASK (0xFFFFFFFFUL)
2063 #define TSW_CENTRAL_QCI_EBS_EBS_SHIFT (0U)
2064 #define TSW_CENTRAL_QCI_EBS_EBS_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_EBS_EBS_SHIFT) & TSW_CENTRAL_QCI_EBS_EBS_MASK)
2065 #define TSW_CENTRAL_QCI_EBS_EBS_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_EBS_EBS_MASK) >> TSW_CENTRAL_QCI_EBS_EBS_SHIFT)
2066 
2067 /* Bitfield definition for register: CENTRAL_QCI_GCTRL */
2068 /*
2069  * IPV (R/W)
2070  *
2071  * Administrative internal priority value specification
2072  * (802.1Qci – 8.6.5.1.2 (c))
2073  */
2074 #define TSW_CENTRAL_QCI_GCTRL_IPV_MASK (0xE0U)
2075 #define TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT (5U)
2076 #define TSW_CENTRAL_QCI_GCTRL_IPV_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK)
2077 #define TSW_CENTRAL_QCI_GCTRL_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_IPV_MASK) >> TSW_CENTRAL_QCI_GCTRL_IPV_SHIFT)
2078 
2079 /*
2080  * STATE (R/W)
2081  *
2082  * Administrative stream gate state
2083  * (802.1Qci – 8.6.5.1.2 (b))
2084  */
2085 #define TSW_CENTRAL_QCI_GCTRL_STATE_MASK (0x10U)
2086 #define TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT (4U)
2087 #define TSW_CENTRAL_QCI_GCTRL_STATE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK)
2088 #define TSW_CENTRAL_QCI_GCTRL_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_STATE_MASK) >> TSW_CENTRAL_QCI_GCTRL_STATE_SHIFT)
2089 
2090 /*
2091  * CDOEE (R/W)
2092  *
2093  * Gate – ClosedDueToOctetsExceededEnable
2094  * (802.1Qci – 8.6.5.1.2 (f))
2095  */
2096 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK (0x8U)
2097 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT (3U)
2098 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK)
2099 #define TSW_CENTRAL_QCI_GCTRL_CDOEE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDOEE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDOEE_SHIFT)
2100 
2101 /*
2102  * CDIRE (R/W)
2103  *
2104  * Gate – ClosedDueToInvalidRxEnable
2105  * (802.1Qci – 8.6.5.1.2 (d))
2106  */
2107 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK (0x4U)
2108 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT (2U)
2109 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK)
2110 #define TSW_CENTRAL_QCI_GCTRL_CDIRE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CDIRE_MASK) >> TSW_CENTRAL_QCI_GCTRL_CDIRE_SHIFT)
2111 
2112 /*
2113  * CFGCH (R/W)
2114  *
2115  * Gate – change config (self-resetting to <0>)
2116  */
2117 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK (0x2U)
2118 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT (1U)
2119 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK)
2120 #define TSW_CENTRAL_QCI_GCTRL_CFGCH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_CFGCH_MASK) >> TSW_CENTRAL_QCI_GCTRL_CFGCH_SHIFT)
2121 
2122 /*
2123  * EN (R/W)
2124  *
2125  * Gate control – enable
2126  */
2127 #define TSW_CENTRAL_QCI_GCTRL_EN_MASK (0x1U)
2128 #define TSW_CENTRAL_QCI_GCTRL_EN_SHIFT (0U)
2129 #define TSW_CENTRAL_QCI_GCTRL_EN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GCTRL_EN_SHIFT) & TSW_CENTRAL_QCI_GCTRL_EN_MASK)
2130 #define TSW_CENTRAL_QCI_GCTRL_EN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GCTRL_EN_MASK) >> TSW_CENTRAL_QCI_GCTRL_EN_SHIFT)
2131 
2132 /* Bitfield definition for register: CENTRAL_QCI_GSTATUS */
2133 /*
2134  * IPV (RO)
2135  *
2136  * Operational internal priority value specification
2137  * (802.1Qci – 8.6.5.1.2 (c))
2138  */
2139 #define TSW_CENTRAL_QCI_GSTATUS_IPV_MASK (0xE0U)
2140 #define TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT (5U)
2141 #define TSW_CENTRAL_QCI_GSTATUS_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_IPV_MASK) >> TSW_CENTRAL_QCI_GSTATUS_IPV_SHIFT)
2142 
2143 /*
2144  * STATE (RO)
2145  *
2146  * Operational stream gate state
2147  * (802.1Qci – 8.6.5.1.2 (b))
2148  */
2149 #define TSW_CENTRAL_QCI_GSTATUS_STATE_MASK (0x10U)
2150 #define TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT (4U)
2151 #define TSW_CENTRAL_QCI_GSTATUS_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_STATE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_STATE_SHIFT)
2152 
2153 /*
2154  * CDOE (WC)
2155  *
2156  * Gate – ClosedDueToOctetsExceeded. Write <1> to
2157  * clear.
2158  * (802.1Qci – 8.6.5.1.2 (g))
2159  */
2160 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK (0x8U)
2161 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT (3U)
2162 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK)
2163 #define TSW_CENTRAL_QCI_GSTATUS_CDOE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDOE_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDOE_SHIFT)
2164 
2165 /*
2166  * CDIR (WC)
2167  *
2168  * Gate – ClosedDueToInvalidRx. Write <1> to clear.
2169  * (802.1Qci – 8.6.5.1.2 (e))
2170  */
2171 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK (0x4U)
2172 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT (2U)
2173 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK)
2174 #define TSW_CENTRAL_QCI_GSTATUS_CDIR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CDIR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CDIR_SHIFT)
2175 
2176 /*
2177  * CFGP (RO)
2178  *
2179  * Configuration change pending
2180  */
2181 #define TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK (0x2U)
2182 #define TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT (1U)
2183 #define TSW_CENTRAL_QCI_GSTATUS_CFGP_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGP_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGP_SHIFT)
2184 
2185 /*
2186  * CFGERR (WC)
2187  *
2188  * Configuration change error. Write <1> to clear.
2189  */
2190 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK (0x1U)
2191 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT (0U)
2192 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK)
2193 #define TSW_CENTRAL_QCI_GSTATUS_CFGERR_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GSTATUS_CFGERR_MASK) >> TSW_CENTRAL_QCI_GSTATUS_CFGERR_SHIFT)
2194 
2195 /* Bitfield definition for register: CENTRAL_QCI_GLISTINDEX */
2196 /*
2197  * IDX (R/W)
2198  *
2199  * Admin list pointer, select entry 0 – 15.
2200  */
2201 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK (0xFU)
2202 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT (0U)
2203 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK)
2204 #define TSW_CENTRAL_QCI_GLISTINDEX_IDX_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_GLISTINDEX_IDX_MASK) >> TSW_CENTRAL_QCI_GLISTINDEX_IDX_SHIFT)
2205 
2206 /* Bitfield definition for register: CENTRAL_QCI_LISTLEN */
2207 /*
2208  * OLEN (RO)
2209  *
2210  * Operational list length
2211  */
2212 #define TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK (0xF0000UL)
2213 #define TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT (16U)
2214 #define TSW_CENTRAL_QCI_LISTLEN_OLEN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_OLEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_OLEN_SHIFT)
2215 
2216 /*
2217  * ALEN (R/W)
2218  *
2219  * Administrative list length
2220  */
2221 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK (0xFU)
2222 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT (0U)
2223 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK)
2224 #define TSW_CENTRAL_QCI_LISTLEN_ALEN_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_LISTLEN_ALEN_MASK) >> TSW_CENTRAL_QCI_LISTLEN_ALEN_SHIFT)
2225 
2226 /* Bitfield definition for register: CENTRAL_QCI_ACYCLETM */
2227 /*
2228  * ACT (R/W)
2229  *
2230  * Administrative cycle time length, nanoseconds.
2231  */
2232 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK (0x3FFFFFFFUL)
2233 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT (0U)
2234 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK)
2235 #define TSW_CENTRAL_QCI_ACYCLETM_ACT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ACYCLETM_ACT_MASK) >> TSW_CENTRAL_QCI_ACYCLETM_ACT_SHIFT)
2236 
2237 /* Bitfield definition for register: CENTRAL_QCI_ABASETM_L */
2238 /*
2239  * ABTL (R/W)
2240  *
2241  * Administrative base time. Nanoseconds and seconds part. Cycle starts after becoming operational when time is reached by inputs <rtc_sec> and <rtc_ns>.
2242  */
2243 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK (0x3FFFFFFFUL)
2244 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT (0U)
2245 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK)
2246 #define TSW_CENTRAL_QCI_ABASETM_L_ABTL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_L_ABTL_MASK) >> TSW_CENTRAL_QCI_ABASETM_L_ABTL_SHIFT)
2247 
2248 /* Bitfield definition for register: CENTRAL_QCI_ABASETM_H */
2249 /*
2250  * ABTH (R/W)
2251  *
2252  */
2253 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK (0xFFFFFFFFUL)
2254 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT (0U)
2255 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK)
2256 #define TSW_CENTRAL_QCI_ABASETM_H_ABTH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_ABASETM_H_ABTH_MASK) >> TSW_CENTRAL_QCI_ABASETM_H_ABTH_SHIFT)
2257 
2258 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_CTRL */
2259 /*
2260  * STATE (R/W)
2261  *
2262  * AdminList – gate state (1: open)
2263  */
2264 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK (0x80000000UL)
2265 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT (31U)
2266 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK)
2267 #define TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_STATE_SHIFT)
2268 
2269 /*
2270  * IPV (R/W)
2271  *
2272  * AdminList – IPV
2273  */
2274 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK (0x70000000UL)
2275 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT (28U)
2276 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK)
2277 #define TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_IPV_SHIFT)
2278 
2279 /*
2280  * OCT (R/W)
2281  *
2282  * AdminList – maximum octets (0 – disabled)
2283  */
2284 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK (0xFFFFFFFUL)
2285 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT (0U)
2286 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK)
2287 #define TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_CTRL_OCT_SHIFT)
2288 
2289 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_AENTRY_IVAL */
2290 /*
2291  * IVAL (R/W)
2292  *
2293  * AdminList – time interval in clock ticks
2294  */
2295 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK (0xFFFFFFFFUL)
2296 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT (0U)
2297 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SET(x) (((uint32_t)(x) << TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK)
2298 #define TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_MASK) >> TSW_CENTRAL_QCI_AENTRY_AENTRY_IVAL_IVAL_SHIFT)
2299 
2300 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_OCYCLETM */
2301 /*
2302  * OCT (RO)
2303  *
2304  * OperCycleTime in nanoseconds
2305  */
2306 #define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK (0xFFFFFFFFUL)
2307 #define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT (0U)
2308 #define TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_MASK) >> TSW_CENTRAL_QCI_AENTRY_OCYCLETM_OCT_SHIFT)
2309 
2310 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_OBASETM_L */
2311 /*
2312  * OBTL (RO)
2313  *
2314  * OperBaseTime – nanoseconds and seconds. Constantly
2315  * updated – OperBaseTime + N * OperCycleTimt. Might
2316  * be non-normalized.
2317  */
2318 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK (0xFFFFFFFFUL)
2319 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT (0U)
2320 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_L_OBTL_SHIFT)
2321 
2322 /* Bitfield definition for register: CENTRAL_QCI_AENTRY_OBASETM_H */
2323 /*
2324  * OBTH (RO)
2325  *
2326  */
2327 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK (0xFFFFFFFFUL)
2328 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT (0U)
2329 #define TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_GET(x) (((uint32_t)(x) & TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_MASK) >> TSW_CENTRAL_QCI_AENTRY_OBASETM_H_OBTH_SHIFT)
2330 
2331 /* Bitfield definition for register: MM2S_DMA_CR */
2332 /*
2333  * MXLEN (RW)
2334  *
2335  * max axi burst size
2336  */
2337 #define TSW_MM2S_DMA_CR_MXLEN_MASK (0xFF000000UL)
2338 #define TSW_MM2S_DMA_CR_MXLEN_SHIFT (24U)
2339 #define TSW_MM2S_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_MXLEN_SHIFT) & TSW_MM2S_DMA_CR_MXLEN_MASK)
2340 #define TSW_MM2S_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_MXLEN_MASK) >> TSW_MM2S_DMA_CR_MXLEN_SHIFT)
2341 
2342 /*
2343  * IRQEN (RW)
2344  *
2345  * interrupt request enable
2346  */
2347 #define TSW_MM2S_DMA_CR_IRQEN_MASK (0x8U)
2348 #define TSW_MM2S_DMA_CR_IRQEN_SHIFT (3U)
2349 #define TSW_MM2S_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_IRQEN_SHIFT) & TSW_MM2S_DMA_CR_IRQEN_MASK)
2350 #define TSW_MM2S_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_IRQEN_MASK) >> TSW_MM2S_DMA_CR_IRQEN_SHIFT)
2351 
2352 /*
2353  * RESET (WO)
2354  *
2355  * do reset when active
2356  */
2357 #define TSW_MM2S_DMA_CR_RESET_MASK (0x4U)
2358 #define TSW_MM2S_DMA_CR_RESET_SHIFT (2U)
2359 #define TSW_MM2S_DMA_CR_RESET_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_RESET_SHIFT) & TSW_MM2S_DMA_CR_RESET_MASK)
2360 #define TSW_MM2S_DMA_CR_RESET_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_RESET_MASK) >> TSW_MM2S_DMA_CR_RESET_SHIFT)
2361 
2362 /*
2363  * SOE (RW)
2364  *
2365  * stop on error flag
2366  */
2367 #define TSW_MM2S_DMA_CR_SOE_MASK (0x2U)
2368 #define TSW_MM2S_DMA_CR_SOE_SHIFT (1U)
2369 #define TSW_MM2S_DMA_CR_SOE_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_SOE_SHIFT) & TSW_MM2S_DMA_CR_SOE_MASK)
2370 #define TSW_MM2S_DMA_CR_SOE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_SOE_MASK) >> TSW_MM2S_DMA_CR_SOE_SHIFT)
2371 
2372 /*
2373  * RUN (RW)
2374  *
2375  * run command from queue to data mover
2376  */
2377 #define TSW_MM2S_DMA_CR_RUN_MASK (0x1U)
2378 #define TSW_MM2S_DMA_CR_RUN_SHIFT (0U)
2379 #define TSW_MM2S_DMA_CR_RUN_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_CR_RUN_SHIFT) & TSW_MM2S_DMA_CR_RUN_MASK)
2380 #define TSW_MM2S_DMA_CR_RUN_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CR_RUN_MASK) >> TSW_MM2S_DMA_CR_RUN_SHIFT)
2381 
2382 /* Bitfield definition for register: MM2S_DMA_SR */
2383 /*
2384  * RBUFF (RO)
2385  *
2386  * response buffer full
2387  */
2388 #define TSW_MM2S_DMA_SR_RBUFF_MASK (0x80U)
2389 #define TSW_MM2S_DMA_SR_RBUFF_SHIFT (7U)
2390 #define TSW_MM2S_DMA_SR_RBUFF_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFF_MASK) >> TSW_MM2S_DMA_SR_RBUFF_SHIFT)
2391 
2392 /*
2393  * RBUFE (RO)
2394  *
2395  * response buffer empty
2396  */
2397 #define TSW_MM2S_DMA_SR_RBUFE_MASK (0x40U)
2398 #define TSW_MM2S_DMA_SR_RBUFE_SHIFT (6U)
2399 #define TSW_MM2S_DMA_SR_RBUFE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RBUFE_MASK) >> TSW_MM2S_DMA_SR_RBUFE_SHIFT)
2400 
2401 /*
2402  * CBUFF (RO)
2403  *
2404  * command buffer full
2405  */
2406 #define TSW_MM2S_DMA_SR_CBUFF_MASK (0x20U)
2407 #define TSW_MM2S_DMA_SR_CBUFF_SHIFT (5U)
2408 #define TSW_MM2S_DMA_SR_CBUFF_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFF_MASK) >> TSW_MM2S_DMA_SR_CBUFF_SHIFT)
2409 
2410 /*
2411  * CBUFE (RO)
2412  *
2413  * command buffer empty
2414  */
2415 #define TSW_MM2S_DMA_SR_CBUFE_MASK (0x10U)
2416 #define TSW_MM2S_DMA_SR_CBUFE_SHIFT (4U)
2417 #define TSW_MM2S_DMA_SR_CBUFE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_CBUFE_MASK) >> TSW_MM2S_DMA_SR_CBUFE_SHIFT)
2418 
2419 /*
2420  * IRQ (RWC)
2421  *
2422  * interrupt request pending
2423  */
2424 #define TSW_MM2S_DMA_SR_IRQ_MASK (0x8U)
2425 #define TSW_MM2S_DMA_SR_IRQ_SHIFT (3U)
2426 #define TSW_MM2S_DMA_SR_IRQ_SET(x) (((uint32_t)(x) << TSW_MM2S_DMA_SR_IRQ_SHIFT) & TSW_MM2S_DMA_SR_IRQ_MASK)
2427 #define TSW_MM2S_DMA_SR_IRQ_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_IRQ_MASK) >> TSW_MM2S_DMA_SR_IRQ_SHIFT)
2428 
2429 /*
2430  * RSET (RO)
2431  *
2432  * resetting status
2433  */
2434 #define TSW_MM2S_DMA_SR_RSET_MASK (0x4U)
2435 #define TSW_MM2S_DMA_SR_RSET_SHIFT (2U)
2436 #define TSW_MM2S_DMA_SR_RSET_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_RSET_MASK) >> TSW_MM2S_DMA_SR_RSET_SHIFT)
2437 
2438 /*
2439  * BUSY (RO)
2440  *
2441  * busy
2442  */
2443 #define TSW_MM2S_DMA_SR_BUSY_MASK (0x2U)
2444 #define TSW_MM2S_DMA_SR_BUSY_SHIFT (1U)
2445 #define TSW_MM2S_DMA_SR_BUSY_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_BUSY_MASK) >> TSW_MM2S_DMA_SR_BUSY_SHIFT)
2446 
2447 /*
2448  * STOP (RO)
2449  *
2450  * mm2s is stopped
2451  */
2452 #define TSW_MM2S_DMA_SR_STOP_MASK (0x1U)
2453 #define TSW_MM2S_DMA_SR_STOP_SHIFT (0U)
2454 #define TSW_MM2S_DMA_SR_STOP_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_SR_STOP_MASK) >> TSW_MM2S_DMA_SR_STOP_SHIFT)
2455 
2456 /* Bitfield definition for register: MM2S_DMA_FILL */
2457 /*
2458  * RFILL (RO)
2459  *
2460  * response buffer fill level
2461  */
2462 #define TSW_MM2S_DMA_FILL_RFILL_MASK (0xFFFF0000UL)
2463 #define TSW_MM2S_DMA_FILL_RFILL_SHIFT (16U)
2464 #define TSW_MM2S_DMA_FILL_RFILL_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_FILL_RFILL_MASK) >> TSW_MM2S_DMA_FILL_RFILL_SHIFT)
2465 
2466 /*
2467  * CFILL (RO)
2468  *
2469  * command buffer fill level
2470  */
2471 #define TSW_MM2S_DMA_FILL_CFILL_MASK (0xFFFFU)
2472 #define TSW_MM2S_DMA_FILL_CFILL_SHIFT (0U)
2473 #define TSW_MM2S_DMA_FILL_CFILL_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_FILL_CFILL_MASK) >> TSW_MM2S_DMA_FILL_CFILL_SHIFT)
2474 
2475 /* Bitfield definition for register: MM2S_DMA_CFG */
2476 /*
2477  * DBUFD (RO)
2478  *
2479  * data buffer depth
2480  */
2481 #define TSW_MM2S_DMA_CFG_DBUFD_MASK (0xF000000UL)
2482 #define TSW_MM2S_DMA_CFG_DBUFD_SHIFT (24U)
2483 #define TSW_MM2S_DMA_CFG_DBUFD_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_DBUFD_MASK) >> TSW_MM2S_DMA_CFG_DBUFD_SHIFT)
2484 
2485 /*
2486  * CBUFD (RO)
2487  *
2488  * command buffer depth
2489  */
2490 #define TSW_MM2S_DMA_CFG_CBUFD_MASK (0xF00000UL)
2491 #define TSW_MM2S_DMA_CFG_CBUFD_SHIFT (20U)
2492 #define TSW_MM2S_DMA_CFG_CBUFD_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_CBUFD_MASK) >> TSW_MM2S_DMA_CFG_CBUFD_SHIFT)
2493 
2494 /*
2495  * ENA64 (RO)
2496  *
2497  * enable support for 64 bit addressing
2498  */
2499 #define TSW_MM2S_DMA_CFG_ENA64_MASK (0x80000UL)
2500 #define TSW_MM2S_DMA_CFG_ENA64_SHIFT (19U)
2501 #define TSW_MM2S_DMA_CFG_ENA64_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ENA64_MASK) >> TSW_MM2S_DMA_CFG_ENA64_SHIFT)
2502 
2503 /*
2504  * ASIZE (RO)
2505  *
2506  * axi data bus width
2507  */
2508 #define TSW_MM2S_DMA_CFG_ASIZE_MASK (0x70000UL)
2509 #define TSW_MM2S_DMA_CFG_ASIZE_SHIFT (16U)
2510 #define TSW_MM2S_DMA_CFG_ASIZE_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_ASIZE_MASK) >> TSW_MM2S_DMA_CFG_ASIZE_SHIFT)
2511 
2512 /*
2513  * VER (RO)
2514  *
2515  * ip version
2516  */
2517 #define TSW_MM2S_DMA_CFG_VER_MASK (0xFFFFU)
2518 #define TSW_MM2S_DMA_CFG_VER_SHIFT (0U)
2519 #define TSW_MM2S_DMA_CFG_VER_GET(x) (((uint32_t)(x) & TSW_MM2S_DMA_CFG_VER_MASK) >> TSW_MM2S_DMA_CFG_VER_SHIFT)
2520 
2521 /* Bitfield definition for register: MM2S_ADDRLO */
2522 /*
2523  * ADDRLO (RW)
2524  *
2525  * axi address
2526  */
2527 #define TSW_MM2S_ADDRLO_ADDRLO_MASK (0xFFFFFFFFUL)
2528 #define TSW_MM2S_ADDRLO_ADDRLO_SHIFT (0U)
2529 #define TSW_MM2S_ADDRLO_ADDRLO_SET(x) (((uint32_t)(x) << TSW_MM2S_ADDRLO_ADDRLO_SHIFT) & TSW_MM2S_ADDRLO_ADDRLO_MASK)
2530 #define TSW_MM2S_ADDRLO_ADDRLO_GET(x) (((uint32_t)(x) & TSW_MM2S_ADDRLO_ADDRLO_MASK) >> TSW_MM2S_ADDRLO_ADDRLO_SHIFT)
2531 
2532 /* Bitfield definition for register: MM2S_LENGTH */
2533 /*
2534  * LENGTH (RW)
2535  *
2536  * transfer request length in bytes
2537  */
2538 #define TSW_MM2S_LENGTH_LENGTH_MASK (0xFFFFU)
2539 #define TSW_MM2S_LENGTH_LENGTH_SHIFT (0U)
2540 #define TSW_MM2S_LENGTH_LENGTH_SET(x) (((uint32_t)(x) << TSW_MM2S_LENGTH_LENGTH_SHIFT) & TSW_MM2S_LENGTH_LENGTH_MASK)
2541 #define TSW_MM2S_LENGTH_LENGTH_GET(x) (((uint32_t)(x) & TSW_MM2S_LENGTH_LENGTH_MASK) >> TSW_MM2S_LENGTH_LENGTH_SHIFT)
2542 
2543 /* Bitfield definition for register: MM2S_CTRL */
2544 /*
2545  * GO (WO)
2546  *
2547  * commit buffered descriptor to command queue
2548  */
2549 #define TSW_MM2S_CTRL_GO_MASK (0x80000000UL)
2550 #define TSW_MM2S_CTRL_GO_SHIFT (31U)
2551 #define TSW_MM2S_CTRL_GO_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_GO_SHIFT) & TSW_MM2S_CTRL_GO_MASK)
2552 #define TSW_MM2S_CTRL_GO_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_GO_MASK) >> TSW_MM2S_CTRL_GO_SHIFT)
2553 
2554 /*
2555  * NGENLAST (RW)
2556  *
2557  * no generation of TLAST
2558  */
2559 #define TSW_MM2S_CTRL_NGENLAST_MASK (0x10U)
2560 #define TSW_MM2S_CTRL_NGENLAST_SHIFT (4U)
2561 #define TSW_MM2S_CTRL_NGENLAST_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_NGENLAST_SHIFT) & TSW_MM2S_CTRL_NGENLAST_MASK)
2562 #define TSW_MM2S_CTRL_NGENLAST_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_NGENLAST_MASK) >> TSW_MM2S_CTRL_NGENLAST_SHIFT)
2563 
2564 /*
2565  * ID (RW)
2566  *
2567  * command id
2568  */
2569 #define TSW_MM2S_CTRL_ID_MASK (0xFU)
2570 #define TSW_MM2S_CTRL_ID_SHIFT (0U)
2571 #define TSW_MM2S_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_MM2S_CTRL_ID_SHIFT) & TSW_MM2S_CTRL_ID_MASK)
2572 #define TSW_MM2S_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_MM2S_CTRL_ID_MASK) >> TSW_MM2S_CTRL_ID_SHIFT)
2573 
2574 /* Bitfield definition for register: MM2S_RESP */
2575 /*
2576  * LAST (RO)
2577  *
2578  * axi-stream with TLAST
2579  */
2580 #define TSW_MM2S_RESP_LAST_MASK (0x40000000UL)
2581 #define TSW_MM2S_RESP_LAST_SHIFT (30U)
2582 #define TSW_MM2S_RESP_LAST_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_LAST_MASK) >> TSW_MM2S_RESP_LAST_SHIFT)
2583 
2584 /*
2585  * DECERR (RO)
2586  *
2587  * decode error
2588  */
2589 #define TSW_MM2S_RESP_DECERR_MASK (0x20000000UL)
2590 #define TSW_MM2S_RESP_DECERR_SHIFT (29U)
2591 #define TSW_MM2S_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_DECERR_MASK) >> TSW_MM2S_RESP_DECERR_SHIFT)
2592 
2593 /*
2594  * SLVERR (RO)
2595  *
2596  * slave error
2597  */
2598 #define TSW_MM2S_RESP_SLVERR_MASK (0x10000000UL)
2599 #define TSW_MM2S_RESP_SLVERR_SHIFT (28U)
2600 #define TSW_MM2S_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_SLVERR_MASK) >> TSW_MM2S_RESP_SLVERR_SHIFT)
2601 
2602 /*
2603  * ID (RO)
2604  *
2605  * command ID feedback
2606  */
2607 #define TSW_MM2S_RESP_ID_MASK (0xF000000UL)
2608 #define TSW_MM2S_RESP_ID_SHIFT (24U)
2609 #define TSW_MM2S_RESP_ID_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_ID_MASK) >> TSW_MM2S_RESP_ID_SHIFT)
2610 
2611 /*
2612  * LENGTH (RO)
2613  *
2614  * requested length of tansfer in bytes from command
2615  */
2616 #define TSW_MM2S_RESP_LENGTH_MASK (0xFFFFU)
2617 #define TSW_MM2S_RESP_LENGTH_SHIFT (0U)
2618 #define TSW_MM2S_RESP_LENGTH_GET(x) (((uint32_t)(x) & TSW_MM2S_RESP_LENGTH_MASK) >> TSW_MM2S_RESP_LENGTH_SHIFT)
2619 
2620 /* Bitfield definition for register: S2MM_DMA_CR */
2621 /*
2622  * MXLEN (RW)
2623  *
2624  * max axi burst size
2625  */
2626 #define TSW_S2MM_DMA_CR_MXLEN_MASK (0xFF000000UL)
2627 #define TSW_S2MM_DMA_CR_MXLEN_SHIFT (24U)
2628 #define TSW_S2MM_DMA_CR_MXLEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_MXLEN_SHIFT) & TSW_S2MM_DMA_CR_MXLEN_MASK)
2629 #define TSW_S2MM_DMA_CR_MXLEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_MXLEN_MASK) >> TSW_S2MM_DMA_CR_MXLEN_SHIFT)
2630 
2631 /*
2632  * IRQEN (RW)
2633  *
2634  * interrupt request enable
2635  */
2636 #define TSW_S2MM_DMA_CR_IRQEN_MASK (0x8U)
2637 #define TSW_S2MM_DMA_CR_IRQEN_SHIFT (3U)
2638 #define TSW_S2MM_DMA_CR_IRQEN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_IRQEN_SHIFT) & TSW_S2MM_DMA_CR_IRQEN_MASK)
2639 #define TSW_S2MM_DMA_CR_IRQEN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_IRQEN_MASK) >> TSW_S2MM_DMA_CR_IRQEN_SHIFT)
2640 
2641 /*
2642  * RESET (WO)
2643  *
2644  * do reset when writing 1
2645  */
2646 #define TSW_S2MM_DMA_CR_RESET_MASK (0x4U)
2647 #define TSW_S2MM_DMA_CR_RESET_SHIFT (2U)
2648 #define TSW_S2MM_DMA_CR_RESET_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_RESET_SHIFT) & TSW_S2MM_DMA_CR_RESET_MASK)
2649 #define TSW_S2MM_DMA_CR_RESET_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_RESET_MASK) >> TSW_S2MM_DMA_CR_RESET_SHIFT)
2650 
2651 /*
2652  * SOE (RW)
2653  *
2654  * stop on error flag
2655  */
2656 #define TSW_S2MM_DMA_CR_SOE_MASK (0x2U)
2657 #define TSW_S2MM_DMA_CR_SOE_SHIFT (1U)
2658 #define TSW_S2MM_DMA_CR_SOE_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_SOE_SHIFT) & TSW_S2MM_DMA_CR_SOE_MASK)
2659 #define TSW_S2MM_DMA_CR_SOE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_SOE_MASK) >> TSW_S2MM_DMA_CR_SOE_SHIFT)
2660 
2661 /*
2662  * RUN (RW)
2663  *
2664  * run commands from queue to data mover
2665  */
2666 #define TSW_S2MM_DMA_CR_RUN_MASK (0x1U)
2667 #define TSW_S2MM_DMA_CR_RUN_SHIFT (0U)
2668 #define TSW_S2MM_DMA_CR_RUN_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_CR_RUN_SHIFT) & TSW_S2MM_DMA_CR_RUN_MASK)
2669 #define TSW_S2MM_DMA_CR_RUN_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CR_RUN_MASK) >> TSW_S2MM_DMA_CR_RUN_SHIFT)
2670 
2671 /* Bitfield definition for register: S2MM_DMA_SR */
2672 /*
2673  * RBUFF (RO)
2674  *
2675  * response buffer full
2676  */
2677 #define TSW_S2MM_DMA_SR_RBUFF_MASK (0x80U)
2678 #define TSW_S2MM_DMA_SR_RBUFF_SHIFT (7U)
2679 #define TSW_S2MM_DMA_SR_RBUFF_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFF_MASK) >> TSW_S2MM_DMA_SR_RBUFF_SHIFT)
2680 
2681 /*
2682  * RBUFE (RO)
2683  *
2684  * response buffer empty
2685  */
2686 #define TSW_S2MM_DMA_SR_RBUFE_MASK (0x40U)
2687 #define TSW_S2MM_DMA_SR_RBUFE_SHIFT (6U)
2688 #define TSW_S2MM_DMA_SR_RBUFE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RBUFE_MASK) >> TSW_S2MM_DMA_SR_RBUFE_SHIFT)
2689 
2690 /*
2691  * CBUFF (RO)
2692  *
2693  * command buffer full
2694  */
2695 #define TSW_S2MM_DMA_SR_CBUFF_MASK (0x20U)
2696 #define TSW_S2MM_DMA_SR_CBUFF_SHIFT (5U)
2697 #define TSW_S2MM_DMA_SR_CBUFF_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFF_MASK) >> TSW_S2MM_DMA_SR_CBUFF_SHIFT)
2698 
2699 /*
2700  * CBUFE (RO)
2701  *
2702  * command buffer empty
2703  */
2704 #define TSW_S2MM_DMA_SR_CBUFE_MASK (0x10U)
2705 #define TSW_S2MM_DMA_SR_CBUFE_SHIFT (4U)
2706 #define TSW_S2MM_DMA_SR_CBUFE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_CBUFE_MASK) >> TSW_S2MM_DMA_SR_CBUFE_SHIFT)
2707 
2708 /*
2709  * IRQ (RWC)
2710  *
2711  * interrupt request pending
2712  */
2713 #define TSW_S2MM_DMA_SR_IRQ_MASK (0x8U)
2714 #define TSW_S2MM_DMA_SR_IRQ_SHIFT (3U)
2715 #define TSW_S2MM_DMA_SR_IRQ_SET(x) (((uint32_t)(x) << TSW_S2MM_DMA_SR_IRQ_SHIFT) & TSW_S2MM_DMA_SR_IRQ_MASK)
2716 #define TSW_S2MM_DMA_SR_IRQ_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_IRQ_MASK) >> TSW_S2MM_DMA_SR_IRQ_SHIFT)
2717 
2718 /*
2719  * RSET (RO)
2720  *
2721  * resetting status
2722  */
2723 #define TSW_S2MM_DMA_SR_RSET_MASK (0x4U)
2724 #define TSW_S2MM_DMA_SR_RSET_SHIFT (2U)
2725 #define TSW_S2MM_DMA_SR_RSET_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_RSET_MASK) >> TSW_S2MM_DMA_SR_RSET_SHIFT)
2726 
2727 /*
2728  * BUSY (RO)
2729  *
2730  * busy, issued command and outstanding response
2731  */
2732 #define TSW_S2MM_DMA_SR_BUSY_MASK (0x2U)
2733 #define TSW_S2MM_DMA_SR_BUSY_SHIFT (1U)
2734 #define TSW_S2MM_DMA_SR_BUSY_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_BUSY_MASK) >> TSW_S2MM_DMA_SR_BUSY_SHIFT)
2735 
2736 /*
2737  * STOP (RO)
2738  *
2739  * s2mm is stopped
2740  */
2741 #define TSW_S2MM_DMA_SR_STOP_MASK (0x1U)
2742 #define TSW_S2MM_DMA_SR_STOP_SHIFT (0U)
2743 #define TSW_S2MM_DMA_SR_STOP_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_SR_STOP_MASK) >> TSW_S2MM_DMA_SR_STOP_SHIFT)
2744 
2745 /* Bitfield definition for register: S2MM_DMA_FILL */
2746 /*
2747  * RFILL (RO)
2748  *
2749  * response buffer fill level
2750  */
2751 #define TSW_S2MM_DMA_FILL_RFILL_MASK (0xFFFF0000UL)
2752 #define TSW_S2MM_DMA_FILL_RFILL_SHIFT (16U)
2753 #define TSW_S2MM_DMA_FILL_RFILL_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_FILL_RFILL_MASK) >> TSW_S2MM_DMA_FILL_RFILL_SHIFT)
2754 
2755 /*
2756  * CFILL (RO)
2757  *
2758  * command buffer fill level
2759  */
2760 #define TSW_S2MM_DMA_FILL_CFILL_MASK (0xFFFFU)
2761 #define TSW_S2MM_DMA_FILL_CFILL_SHIFT (0U)
2762 #define TSW_S2MM_DMA_FILL_CFILL_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_FILL_CFILL_MASK) >> TSW_S2MM_DMA_FILL_CFILL_SHIFT)
2763 
2764 /* Bitfield definition for register: S2MM_DMA_CFG */
2765 /*
2766  * DBUFD (RO)
2767  *
2768  * data buffer depth
2769  */
2770 #define TSW_S2MM_DMA_CFG_DBUFD_MASK (0xF000000UL)
2771 #define TSW_S2MM_DMA_CFG_DBUFD_SHIFT (24U)
2772 #define TSW_S2MM_DMA_CFG_DBUFD_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_DBUFD_MASK) >> TSW_S2MM_DMA_CFG_DBUFD_SHIFT)
2773 
2774 /*
2775  * CBUFD (RO)
2776  *
2777  * command buffer depth
2778  */
2779 #define TSW_S2MM_DMA_CFG_CBUFD_MASK (0xF00000UL)
2780 #define TSW_S2MM_DMA_CFG_CBUFD_SHIFT (20U)
2781 #define TSW_S2MM_DMA_CFG_CBUFD_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_CBUFD_MASK) >> TSW_S2MM_DMA_CFG_CBUFD_SHIFT)
2782 
2783 /*
2784  * ENA64 (RO)
2785  *
2786  * enabled support for 64 bit
2787  */
2788 #define TSW_S2MM_DMA_CFG_ENA64_MASK (0x80000UL)
2789 #define TSW_S2MM_DMA_CFG_ENA64_SHIFT (19U)
2790 #define TSW_S2MM_DMA_CFG_ENA64_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ENA64_MASK) >> TSW_S2MM_DMA_CFG_ENA64_SHIFT)
2791 
2792 /*
2793  * ASIZE (RO)
2794  *
2795  * axi data bus width
2796  */
2797 #define TSW_S2MM_DMA_CFG_ASIZE_MASK (0x70000UL)
2798 #define TSW_S2MM_DMA_CFG_ASIZE_SHIFT (16U)
2799 #define TSW_S2MM_DMA_CFG_ASIZE_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_ASIZE_MASK) >> TSW_S2MM_DMA_CFG_ASIZE_SHIFT)
2800 
2801 /*
2802  * VER (RO)
2803  *
2804  * IP version
2805  */
2806 #define TSW_S2MM_DMA_CFG_VER_MASK (0xFFFFU)
2807 #define TSW_S2MM_DMA_CFG_VER_SHIFT (0U)
2808 #define TSW_S2MM_DMA_CFG_VER_GET(x) (((uint32_t)(x) & TSW_S2MM_DMA_CFG_VER_MASK) >> TSW_S2MM_DMA_CFG_VER_SHIFT)
2809 
2810 /* Bitfield definition for register: S2MM_ADDRLO */
2811 /*
2812  * ADDRLO (RW)
2813  *
2814  * axi address
2815  */
2816 #define TSW_S2MM_ADDRLO_ADDRLO_MASK (0xFFFFFFFFUL)
2817 #define TSW_S2MM_ADDRLO_ADDRLO_SHIFT (0U)
2818 #define TSW_S2MM_ADDRLO_ADDRLO_SET(x) (((uint32_t)(x) << TSW_S2MM_ADDRLO_ADDRLO_SHIFT) & TSW_S2MM_ADDRLO_ADDRLO_MASK)
2819 #define TSW_S2MM_ADDRLO_ADDRLO_GET(x) (((uint32_t)(x) & TSW_S2MM_ADDRLO_ADDRLO_MASK) >> TSW_S2MM_ADDRLO_ADDRLO_SHIFT)
2820 
2821 /* Bitfield definition for register: S2MM_LENGTH */
2822 /*
2823  * LENGTH (RW)
2824  *
2825  * transfer request length in bytes
2826  */
2827 #define TSW_S2MM_LENGTH_LENGTH_MASK (0xFFFFU)
2828 #define TSW_S2MM_LENGTH_LENGTH_SHIFT (0U)
2829 #define TSW_S2MM_LENGTH_LENGTH_SET(x) (((uint32_t)(x) << TSW_S2MM_LENGTH_LENGTH_SHIFT) & TSW_S2MM_LENGTH_LENGTH_MASK)
2830 #define TSW_S2MM_LENGTH_LENGTH_GET(x) (((uint32_t)(x) & TSW_S2MM_LENGTH_LENGTH_MASK) >> TSW_S2MM_LENGTH_LENGTH_SHIFT)
2831 
2832 /* Bitfield definition for register: S2MM_CTRL */
2833 /*
2834  * GO (WO)
2835  *
2836  * commit buffered descriptor to command queue
2837  */
2838 #define TSW_S2MM_CTRL_GO_MASK (0x80000000UL)
2839 #define TSW_S2MM_CTRL_GO_SHIFT (31U)
2840 #define TSW_S2MM_CTRL_GO_SET(x) (((uint32_t)(x) << TSW_S2MM_CTRL_GO_SHIFT) & TSW_S2MM_CTRL_GO_MASK)
2841 #define TSW_S2MM_CTRL_GO_GET(x) (((uint32_t)(x) & TSW_S2MM_CTRL_GO_MASK) >> TSW_S2MM_CTRL_GO_SHIFT)
2842 
2843 /*
2844  * ID (RW)
2845  *
2846  * command id
2847  */
2848 #define TSW_S2MM_CTRL_ID_MASK (0xFU)
2849 #define TSW_S2MM_CTRL_ID_SHIFT (0U)
2850 #define TSW_S2MM_CTRL_ID_SET(x) (((uint32_t)(x) << TSW_S2MM_CTRL_ID_SHIFT) & TSW_S2MM_CTRL_ID_MASK)
2851 #define TSW_S2MM_CTRL_ID_GET(x) (((uint32_t)(x) & TSW_S2MM_CTRL_ID_MASK) >> TSW_S2MM_CTRL_ID_SHIFT)
2852 
2853 /* Bitfield definition for register: S2MM_RESP */
2854 /*
2855  * LAST (RO)
2856  *
2857  * axi-stream with last
2858  */
2859 #define TSW_S2MM_RESP_LAST_MASK (0x40000000UL)
2860 #define TSW_S2MM_RESP_LAST_SHIFT (30U)
2861 #define TSW_S2MM_RESP_LAST_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_LAST_MASK) >> TSW_S2MM_RESP_LAST_SHIFT)
2862 
2863 /*
2864  * DECERR (RO)
2865  *
2866  * decode error
2867  */
2868 #define TSW_S2MM_RESP_DECERR_MASK (0x20000000UL)
2869 #define TSW_S2MM_RESP_DECERR_SHIFT (29U)
2870 #define TSW_S2MM_RESP_DECERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_DECERR_MASK) >> TSW_S2MM_RESP_DECERR_SHIFT)
2871 
2872 /*
2873  * SLVERR (RO)
2874  *
2875  * slave error
2876  */
2877 #define TSW_S2MM_RESP_SLVERR_MASK (0x10000000UL)
2878 #define TSW_S2MM_RESP_SLVERR_SHIFT (28U)
2879 #define TSW_S2MM_RESP_SLVERR_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_SLVERR_MASK) >> TSW_S2MM_RESP_SLVERR_SHIFT)
2880 
2881 /*
2882  * ID (RO)
2883  *
2884  * command ID feedback
2885  */
2886 #define TSW_S2MM_RESP_ID_MASK (0xF000000UL)
2887 #define TSW_S2MM_RESP_ID_SHIFT (24U)
2888 #define TSW_S2MM_RESP_ID_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_ID_MASK) >> TSW_S2MM_RESP_ID_SHIFT)
2889 
2890 /*
2891  * LENGTH (RO)
2892  *
2893  * received packet size when terminated by TLAST
2894  */
2895 #define TSW_S2MM_RESP_LENGTH_MASK (0xFFFFU)
2896 #define TSW_S2MM_RESP_LENGTH_SHIFT (0U)
2897 #define TSW_S2MM_RESP_LENGTH_GET(x) (((uint32_t)(x) & TSW_S2MM_RESP_LENGTH_MASK) >> TSW_S2MM_RESP_LENGTH_SHIFT)
2898 
2899 /* Bitfield definition for register: PTP_EVT_TS_CTL */
2900 /*
2901  * ATSEN (RW)
2902  *
2903  * auxiliay snapshot enable
2904  */
2905 #define TSW_PTP_EVT_TS_CTL_ATSEN_MASK (0x1E000000UL)
2906 #define TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT (25U)
2907 #define TSW_PTP_EVT_TS_CTL_ATSEN_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK)
2908 #define TSW_PTP_EVT_TS_CTL_ATSEN_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSEN_MASK) >> TSW_PTP_EVT_TS_CTL_ATSEN_SHIFT)
2909 
2910 /*
2911  * ATSFC (W1C)
2912  *
2913  * auxiliary snapshot fifo clear
2914  */
2915 #define TSW_PTP_EVT_TS_CTL_ATSFC_MASK (0x1000000UL)
2916 #define TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT (24U)
2917 #define TSW_PTP_EVT_TS_CTL_ATSFC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK)
2918 #define TSW_PTP_EVT_TS_CTL_ATSFC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_ATSFC_MASK) >> TSW_PTP_EVT_TS_CTL_ATSFC_SHIFT)
2919 
2920 /*
2921  * TSTIG (RW)
2922  *
2923  * timestamp interrupt trigger enable
2924  */
2925 #define TSW_PTP_EVT_TS_CTL_TSTIG_MASK (0x10U)
2926 #define TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT (4U)
2927 #define TSW_PTP_EVT_TS_CTL_TSTIG_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK)
2928 #define TSW_PTP_EVT_TS_CTL_TSTIG_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TS_CTL_TSTIG_MASK) >> TSW_PTP_EVT_TS_CTL_TSTIG_SHIFT)
2929 
2930 /* Bitfield definition for register: PTP_EVT_PPS_TOD_SEC */
2931 /*
2932  * PPS_TOD_SEC (RO)
2933  *
2934  * pps tod seconds
2935  */
2936 #define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK (0xFFFFFFFFUL)
2937 #define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT (0U)
2938 #define TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_MASK) >> TSW_PTP_EVT_PPS_TOD_SEC_PPS_TOD_SEC_SHIFT)
2939 
2940 /* Bitfield definition for register: PTP_EVT_PPS_TOD_NS */
2941 /*
2942  * PPS_TOD_NS (RO)
2943  *
2944  * pps tod sub seconds
2945  */
2946 #define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK (0x3FFFFFFFUL)
2947 #define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT (0U)
2948 #define TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_MASK) >> TSW_PTP_EVT_PPS_TOD_NS_PPS_TOD_NS_SHIFT)
2949 
2950 /* Bitfield definition for register: PTP_EVT_SCP_SEC0 */
2951 /*
2952  * SCP_SEC (RW)
2953  *
2954  * target time seconds
2955  */
2956 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK (0xFFFFFFFFUL)
2957 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT (0U)
2958 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK)
2959 #define TSW_PTP_EVT_SCP_SEC0_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC0_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC0_SCP_SEC_SHIFT)
2960 
2961 /* Bitfield definition for register: PTP_EVT_SCP_NS0 */
2962 /*
2963  * SCP_NS (RW)
2964  *
2965  * target time sub seconds
2966  */
2967 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK (0x3FFFFFFFUL)
2968 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT (0U)
2969 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK)
2970 #define TSW_PTP_EVT_SCP_NS0_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS0_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS0_SCP_NS_SHIFT)
2971 
2972 /* Bitfield definition for register: PTP_EVT_TMR_STS */
2973 /*
2974  * RD_CNT (RO)
2975  *
2976  * fifo valid count
2977  */
2978 #define TSW_PTP_EVT_TMR_STS_RD_CNT_MASK (0x3E000000UL)
2979 #define TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT (25U)
2980 #define TSW_PTP_EVT_TMR_STS_RD_CNT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_RD_CNT_MASK) >> TSW_PTP_EVT_TMR_STS_RD_CNT_SHIFT)
2981 
2982 /*
2983  * ATSSTM (RO)
2984  *
2985  * auxiliary fifo full error
2986  */
2987 #define TSW_PTP_EVT_TMR_STS_ATSSTM_MASK (0x1000000UL)
2988 #define TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT (24U)
2989 #define TSW_PTP_EVT_TMR_STS_ATSSTM_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATSSTM_MASK) >> TSW_PTP_EVT_TMR_STS_ATSSTM_SHIFT)
2990 
2991 /*
2992  * ATPORT (RO)
2993  *
2994  * auxiliary port
2995  */
2996 #define TSW_PTP_EVT_TMR_STS_ATPORT_MASK (0xF0000UL)
2997 #define TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT (16U)
2998 #define TSW_PTP_EVT_TMR_STS_ATPORT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_ATPORT_MASK) >> TSW_PTP_EVT_TMR_STS_ATPORT_SHIFT)
2999 
3000 /*
3001  * PPS_TOD_INTR (RC)
3002  *
3003  * pps tod intrrupt
3004  */
3005 #define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK (0x400U)
3006 #define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT (10U)
3007 #define TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PPS_TOD_INTR_SHIFT)
3008 
3009 /*
3010  * TARGET_TIME3_CFG_ERR (RO)
3011  *
3012  * target time3 configure error
3013  */
3014 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK (0x200U)
3015 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT (9U)
3016 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_CFG_ERR_SHIFT)
3017 
3018 /*
3019  * TARGET_TIME3_REACH_INTR (RC)
3020  *
3021  * target time3 reached
3022  */
3023 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK (0x100U)
3024 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT (8U)
3025 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME3_REACH_INTR_SHIFT)
3026 
3027 /*
3028  * TARGET_TIME2_CFG_ERR (RO)
3029  *
3030  * target time2 configure error
3031  */
3032 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK (0x80U)
3033 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT (7U)
3034 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_CFG_ERR_SHIFT)
3035 
3036 /*
3037  * TARGET_TIME2_REACH_INTR (RC)
3038  *
3039  * target time2 reached
3040  */
3041 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK (0x40U)
3042 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT (6U)
3043 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME2_REACH_INTR_SHIFT)
3044 
3045 /*
3046  * TARGET_TIME1_CFG_ERR (RO)
3047  *
3048  * target time1 configure error
3049  */
3050 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK (0x20U)
3051 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT (5U)
3052 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_CFG_ERR_SHIFT)
3053 
3054 /*
3055  * TARGET_TIME1_REACH_INTR (RC)
3056  *
3057  * target time1 reached
3058  */
3059 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK (0x10U)
3060 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT (4U)
3061 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME1_REACH_INTR_SHIFT)
3062 
3063 /*
3064  * TARGET_TIME0_CFG_ERR (RO)
3065  *
3066  * target time0 configure error
3067  */
3068 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK (0x8U)
3069 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT (3U)
3070 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_CFG_ERR_SHIFT)
3071 
3072 /*
3073  * PTP_FIFO_WR_INTR (RC)
3074  *
3075  * auxiliary timestamp trigger snapshot
3076  */
3077 #define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK (0x4U)
3078 #define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT (2U)
3079 #define TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_PTP_FIFO_WR_INTR_SHIFT)
3080 
3081 /*
3082  * TARGET_TIME0_REACH_INTR (RC)
3083  *
3084  * target time0 reached
3085  */
3086 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK (0x2U)
3087 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT (1U)
3088 #define TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_MASK) >> TSW_PTP_EVT_TMR_STS_TARGET_TIME0_REACH_INTR_SHIFT)
3089 
3090 /* Bitfield definition for register: PTP_EVT_PPS_CMD */
3091 /*
3092  * PPS_MODE3 (RW)
3093  *
3094  * Target Time Register Mode for PPS3 Output
3095  */
3096 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK (0x60000000UL)
3097 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT (29U)
3098 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK)
3099 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE3_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE3_SHIFT)
3100 
3101 /*
3102  * PPS_CMD3 (RW)
3103  *
3104  * pps3 command
3105  */
3106 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK (0x7000000UL)
3107 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT (24U)
3108 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK)
3109 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD3_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD3_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD3_SHIFT)
3110 
3111 /*
3112  * PPS_MODE2 (RW)
3113  *
3114  * Target Time Register Mode for PPS2 Output
3115  */
3116 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK (0x600000UL)
3117 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT (21U)
3118 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK)
3119 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE2_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE2_SHIFT)
3120 
3121 /*
3122  * PPS_CMD2 (RW)
3123  *
3124  * pps2 command
3125  */
3126 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK (0x70000UL)
3127 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT (16U)
3128 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK)
3129 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD2_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD2_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD2_SHIFT)
3130 
3131 /*
3132  * PPS_MODE1 (RW)
3133  *
3134  * Target Time Register Mode for PPS1 Output
3135  */
3136 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK (0x6000U)
3137 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT (13U)
3138 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK)
3139 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE1_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE1_SHIFT)
3140 
3141 /*
3142  * PPS_CMD1 (RW)
3143  *
3144  * pps1 command
3145  */
3146 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK (0x700U)
3147 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT (8U)
3148 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK)
3149 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD1_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD1_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD1_SHIFT)
3150 
3151 /*
3152  * PPS_MODE0 (RW)
3153  *
3154  * Target Time Register Mode for PPS0 Output
3155  */
3156 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK (0x60U)
3157 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT (5U)
3158 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK)
3159 #define TSW_PTP_EVT_PPS_CMD_PPS_MODE0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_MODE0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_MODE0_SHIFT)
3160 
3161 /*
3162  * PPS_EN0 (RW)
3163  *
3164  * flexible PPS0 output mode enable
3165  */
3166 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK (0x10U)
3167 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT (4U)
3168 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK)
3169 #define TSW_PTP_EVT_PPS_CMD_PPS_EN0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_EN0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_EN0_SHIFT)
3170 
3171 /*
3172  * PPS_CMD0 (RW)
3173  *
3174  * pps0 command
3175  */
3176 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK (0xFU)
3177 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT (0U)
3178 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK)
3179 #define TSW_PTP_EVT_PPS_CMD_PPS_CMD0_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CMD_PPS_CMD0_MASK) >> TSW_PTP_EVT_PPS_CMD_PPS_CMD0_SHIFT)
3180 
3181 /* Bitfield definition for register: PTP_EVT_ATSLO */
3182 /*
3183  * STSLO (RO)
3184  *
3185  * auxiliary fifo read sub seconds info
3186  */
3187 #define TSW_PTP_EVT_ATSLO_STSLO_MASK (0x7FFFFFFFUL)
3188 #define TSW_PTP_EVT_ATSLO_STSLO_SHIFT (0U)
3189 #define TSW_PTP_EVT_ATSLO_STSLO_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_ATSLO_STSLO_MASK) >> TSW_PTP_EVT_ATSLO_STSLO_SHIFT)
3190 
3191 /* Bitfield definition for register: PTP_EVT_ATSHI */
3192 /*
3193  * STSHI (RO)
3194  *
3195  * auxiliary fifo read seconds info
3196  */
3197 #define TSW_PTP_EVT_ATSHI_STSHI_MASK (0xFFFFFFFFUL)
3198 #define TSW_PTP_EVT_ATSHI_STSHI_SHIFT (0U)
3199 #define TSW_PTP_EVT_ATSHI_STSHI_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_ATSHI_STSHI_MASK) >> TSW_PTP_EVT_ATSHI_STSHI_SHIFT)
3200 
3201 /* Bitfield definition for register: PTP_EVT_PPS0_INTERVAL */
3202 /*
3203  * PPSINT (RW)
3204  *
3205  * PPS0 output signal interval
3206  */
3207 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3208 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT (0U)
3209 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK)
3210 #define TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS0_INTERVAL_PPSINT_SHIFT)
3211 
3212 /* Bitfield definition for register: PTP_EVT_PPS0_WIDTH */
3213 /*
3214  * PPS_WIDTH (RW)
3215  *
3216  * pps0 output signal width
3217  */
3218 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3219 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT (0U)
3220 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK)
3221 #define TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS0_WIDTH_PPS_WIDTH_SHIFT)
3222 
3223 /* Bitfield definition for register: PTP_EVT_SCP_SEC1 */
3224 /*
3225  * SCP_SEC (RW)
3226  *
3227  * target time seconds
3228  */
3229 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK (0xFFFFFFFFUL)
3230 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT (0U)
3231 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK)
3232 #define TSW_PTP_EVT_SCP_SEC1_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC1_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC1_SCP_SEC_SHIFT)
3233 
3234 /* Bitfield definition for register: PTP_EVT_SCP_NS1 */
3235 /*
3236  * SCP_NS (RW)
3237  *
3238  * target time sub seconds
3239  */
3240 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK (0x3FFFFFFFUL)
3241 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT (0U)
3242 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK)
3243 #define TSW_PTP_EVT_SCP_NS1_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS1_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS1_SCP_NS_SHIFT)
3244 
3245 /* Bitfield definition for register: PTP_EVT_PPS1_INTERVAL */
3246 /*
3247  * PPSINT (RW)
3248  *
3249  * PPS1 output signal interval
3250  */
3251 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3252 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT (0U)
3253 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK)
3254 #define TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS1_INTERVAL_PPSINT_SHIFT)
3255 
3256 /* Bitfield definition for register: PTP_EVT_PPS1_WIDTH */
3257 /*
3258  * PPS_WIDTH (RW)
3259  *
3260  * pps1 output signal width
3261  */
3262 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3263 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT (0U)
3264 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK)
3265 #define TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS1_WIDTH_PPS_WIDTH_SHIFT)
3266 
3267 /* Bitfield definition for register: PTP_EVT_SCP_SEC2 */
3268 /*
3269  * SCP_SEC (RW)
3270  *
3271  * target time seconds
3272  */
3273 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK (0xFFFFFFFFUL)
3274 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT (0U)
3275 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK)
3276 #define TSW_PTP_EVT_SCP_SEC2_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC2_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC2_SCP_SEC_SHIFT)
3277 
3278 /* Bitfield definition for register: PTP_EVT_SCP_NS2 */
3279 /*
3280  * SCP_NS (RW)
3281  *
3282  * target time sub seconds
3283  */
3284 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK (0x3FFFFFFFUL)
3285 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT (0U)
3286 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK)
3287 #define TSW_PTP_EVT_SCP_NS2_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS2_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS2_SCP_NS_SHIFT)
3288 
3289 /* Bitfield definition for register: PTP_EVT_PPS2_INTERVAL */
3290 /*
3291  * PPSINT (RW)
3292  *
3293  * PPS2 output signal interval
3294  */
3295 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3296 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT (0U)
3297 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK)
3298 #define TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS2_INTERVAL_PPSINT_SHIFT)
3299 
3300 /* Bitfield definition for register: PTP_EVT_PPS2_WIDTH */
3301 /*
3302  * PPS_WIDTH (RW)
3303  *
3304  * pps2 output signal width
3305  */
3306 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3307 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT (0U)
3308 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK)
3309 #define TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS2_WIDTH_PPS_WIDTH_SHIFT)
3310 
3311 /* Bitfield definition for register: PTP_EVT_SCP_SEC3 */
3312 /*
3313  * SCP_SEC (RW)
3314  *
3315  * target time seconds
3316  */
3317 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK (0xFFFFFFFFUL)
3318 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT (0U)
3319 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK)
3320 #define TSW_PTP_EVT_SCP_SEC3_SCP_SEC_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_SEC3_SCP_SEC_MASK) >> TSW_PTP_EVT_SCP_SEC3_SCP_SEC_SHIFT)
3321 
3322 /* Bitfield definition for register: PTP_EVT_SCP_NS3 */
3323 /*
3324  * SCP_NS (RW)
3325  *
3326  * target time sub seconds
3327  */
3328 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK (0x3FFFFFFFUL)
3329 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT (0U)
3330 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK)
3331 #define TSW_PTP_EVT_SCP_NS3_SCP_NS_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_SCP_NS3_SCP_NS_MASK) >> TSW_PTP_EVT_SCP_NS3_SCP_NS_SHIFT)
3332 
3333 /* Bitfield definition for register: PTP_EVT_PPS3_INTERVAL */
3334 /*
3335  * PPSINT (RW)
3336  *
3337  * PPS3 output signal interval
3338  */
3339 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK (0xFFFFFFFFUL)
3340 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT (0U)
3341 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK)
3342 #define TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_MASK) >> TSW_PTP_EVT_PPS3_INTERVAL_PPSINT_SHIFT)
3343 
3344 /* Bitfield definition for register: PTP_EVT_PPS3_WIDTH */
3345 /*
3346  * PPS_WIDTH (RW)
3347  *
3348  * pps3 output signal width
3349  */
3350 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK (0xFFFFFFFFUL)
3351 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT (0U)
3352 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK)
3353 #define TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_MASK) >> TSW_PTP_EVT_PPS3_WIDTH_PPS_WIDTH_SHIFT)
3354 
3355 /* Bitfield definition for register: PTP_EVT_PPS_CTRL0 */
3356 /*
3357  * PPS_TOD_INTR_MSK (RW)
3358  *
3359  * pps tod interrupt enable
3360  */
3361 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK (0x8U)
3362 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT (3U)
3363 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK)
3364 #define TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_PPS_TOD_INTR_MSK_SHIFT)
3365 
3366 /*
3367  * TARGET_RAC_INTR_MSK (RW)
3368  *
3369  * target timmer interrupt mask
3370  */
3371 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK (0x4U)
3372 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT (2U)
3373 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK)
3374 #define TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TARGET_RAC_INTR_MSK_SHIFT)
3375 
3376 /*
3377  * FIFO_WR_INTR_MSK (RW)
3378  *
3379  * auxiliary snapshot fifo write interrupt enable
3380  */
3381 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK (0x2U)
3382 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT (1U)
3383 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK)
3384 #define TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_MASK) >> TSW_PTP_EVT_PPS_CTRL0_FIFO_WR_INTR_MSK_SHIFT)
3385 
3386 /*
3387  * TIME_SEL (RW)
3388  *
3389  * timer selection
3390  */
3391 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK (0x1U)
3392 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT (0U)
3393 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK)
3394 #define TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_MASK) >> TSW_PTP_EVT_PPS_CTRL0_TIME_SEL_SHIFT)
3395 
3396 /* Bitfield definition for register: PTP_EVT_PPS_SEL */
3397 /*
3398  * PPS3_SEL (RW)
3399  *
3400  * pps selection for pps3
3401  */
3402 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK (0x1F000000UL)
3403 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT (24U)
3404 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK)
3405 #define TSW_PTP_EVT_PPS_SEL_PPS3_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS3_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS3_SEL_SHIFT)
3406 
3407 /*
3408  * PPS2_SEL (RW)
3409  *
3410  * pps selection for pps2
3411  */
3412 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK (0x1F0000UL)
3413 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT (16U)
3414 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK)
3415 #define TSW_PTP_EVT_PPS_SEL_PPS2_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS2_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS2_SEL_SHIFT)
3416 
3417 /*
3418  * PPS1_SEL (RW)
3419  *
3420  * pps selection for pps1
3421  */
3422 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK (0x1F00U)
3423 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT (8U)
3424 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK)
3425 #define TSW_PTP_EVT_PPS_SEL_PPS1_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS1_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS1_SEL_SHIFT)
3426 
3427 /*
3428  * PPS0_SEL (RW)
3429  *
3430  * pps selection for pps0
3431  */
3432 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK (0x1FU)
3433 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT (0U)
3434 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SET(x) (((uint32_t)(x) << TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK)
3435 #define TSW_PTP_EVT_PPS_SEL_PPS0_SEL_GET(x) (((uint32_t)(x) & TSW_PTP_EVT_PPS_SEL_PPS0_SEL_MASK) >> TSW_PTP_EVT_PPS_SEL_PPS0_SEL_SHIFT)
3436 
3437 /* Bitfield definition for register: SOFT_RST_CTRL */
3438 /*
3439  * TSN_CORE_RST (RW)
3440  *
3441  * tsn core reset control
3442  */
3443 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK (0x800U)
3444 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT (11U)
3445 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK)
3446 #define TSW_SOFT_RST_CTRL_TSN_CORE_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_TSN_CORE_RST_MASK) >> TSW_SOFT_RST_CTRL_TSN_CORE_RST_SHIFT)
3447 
3448 /*
3449  * PTP_EVT_RST (RW)
3450  *
3451  * ptp event module reset control
3452  */
3453 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK (0x400U)
3454 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT (10U)
3455 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK)
3456 #define TSW_SOFT_RST_CTRL_PTP_EVT_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PTP_EVT_RST_MASK) >> TSW_SOFT_RST_CTRL_PTP_EVT_RST_SHIFT)
3457 
3458 /*
3459  * DMA0_RST (RW)
3460  *
3461  * dma0 reset control
3462  */
3463 #define TSW_SOFT_RST_CTRL_DMA0_RST_MASK (0x100U)
3464 #define TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT (8U)
3465 #define TSW_SOFT_RST_CTRL_DMA0_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK)
3466 #define TSW_SOFT_RST_CTRL_DMA0_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_DMA0_RST_MASK) >> TSW_SOFT_RST_CTRL_DMA0_RST_SHIFT)
3467 
3468 /*
3469  * PORT3_RX_RST (RW)
3470  *
3471  * port3 rx reset control
3472  */
3473 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK (0x20U)
3474 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT (5U)
3475 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK)
3476 #define TSW_SOFT_RST_CTRL_PORT3_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_RX_RST_SHIFT)
3477 
3478 /*
3479  * PORT3_TX_RST (RW)
3480  *
3481  * port3 tx reset control
3482  */
3483 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK (0x10U)
3484 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT (4U)
3485 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK)
3486 #define TSW_SOFT_RST_CTRL_PORT3_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT3_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT3_TX_RST_SHIFT)
3487 
3488 /*
3489  * PORT2_RX_RST (RW)
3490  *
3491  * port2 rx reset control
3492  */
3493 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK (0x8U)
3494 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT (3U)
3495 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK)
3496 #define TSW_SOFT_RST_CTRL_PORT2_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_RX_RST_SHIFT)
3497 
3498 /*
3499  * PORT2_TX_RST (RW)
3500  *
3501  * port2 tx reset control
3502  */
3503 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK (0x4U)
3504 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT (2U)
3505 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK)
3506 #define TSW_SOFT_RST_CTRL_PORT2_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT2_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT2_TX_RST_SHIFT)
3507 
3508 /*
3509  * PORT1_RX_RST (RW)
3510  *
3511  * port1 rx reset control
3512  */
3513 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK (0x2U)
3514 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT (1U)
3515 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK)
3516 #define TSW_SOFT_RST_CTRL_PORT1_RX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_RX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_RX_RST_SHIFT)
3517 
3518 /*
3519  * PORT1_TX_RST (RW)
3520  *
3521  * port1 tx reset control
3522  */
3523 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK (0x1U)
3524 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT (0U)
3525 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_SET(x) (((uint32_t)(x) << TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK)
3526 #define TSW_SOFT_RST_CTRL_PORT1_TX_RST_GET(x) (((uint32_t)(x) & TSW_SOFT_RST_CTRL_PORT1_TX_RST_MASK) >> TSW_SOFT_RST_CTRL_PORT1_TX_RST_SHIFT)
3527 
3528 /* Bitfield definition for register: CPU_PORT_PORT_MAIN_TAGGING */
3529 /*
3530  * FORCE (R/W)
3531  *
3532  * The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports
3533  */
3534 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK (0x20000UL)
3535 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT (17U)
3536 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK)
3537 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_FORCE_SHIFT)
3538 
3539 /*
3540  * ACCESS (R/W)
3541  *
3542  * Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged
3543  */
3544 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK (0x10000UL)
3545 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT (16U)
3546 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK)
3547 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_ACCESS_SHIFT)
3548 
3549 /*
3550  * PCP (R/W)
3551  *
3552  * VLAN-TCI: Priority Code Point, used when tagged.
3553  */
3554 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK (0xE000U)
3555 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT (13U)
3556 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK)
3557 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PCP_SHIFT)
3558 
3559 /*
3560  * DEI (R/W)
3561  *
3562  * VLAN-TCI: Drop Eligible Indicator, used when tagged.
3563  */
3564 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK (0x1000U)
3565 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT (12U)
3566 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK)
3567 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_DEI_SHIFT)
3568 
3569 /*
3570  * PVID (R/W)
3571  *
3572  * Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1.
3573  */
3574 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK (0xFFFU)
3575 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT (0U)
3576 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK)
3577 #define TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_CPU_PORT_PORT_MAIN_TAGGING_PVID_SHIFT)
3578 
3579 /* Bitfield definition for register: CPU_PORT_PORT_MAIN_ENNABLE */
3580 /*
3581  * EN_SF (R/W)
3582  *
3583  * only applicable for CPU-Port at egress: '1' to use S&F FIFO and '0' disable S&F FIFO. Changing during frame operation can lead to frame corruption
3584  */
3585 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK (0x2U)
3586 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT (1U)
3587 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK)
3588 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_SF_SHIFT)
3589 
3590 /*
3591  * EN_QCI (R/W)
3592  *
3593  * if QCI is present at selected egress port, '1' to use QCI and '0' disable QCI. Changing during frame operation can lead to frame corruption.
3594  */
3595 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK (0x1U)
3596 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT (0U)
3597 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK)
3598 #define TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_CPU_PORT_PORT_MAIN_ENNABLE_EN_QCI_SHIFT)
3599 
3600 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_ESELECT */
3601 /*
3602  * ESEL (RW)
3603  *
3604  * Select entry. Selected entry mapped to 0x40 – 0x5C.
3605  */
3606 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK (0xFFU)
3607 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT (0U)
3608 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK)
3609 #define TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_ESELECT_ESEL_SHIFT)
3610 
3611 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_CONTROL */
3612 /*
3613  * SID (R/W)
3614  *
3615  * Stream ID – inserted to header on match
3616  */
3617 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK (0xFF00U)
3618 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT (8U)
3619 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK)
3620 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SID_SHIFT)
3621 
3622 /*
3623  * SEQGEN (R/W)
3624  *
3625  * Sequence number generation enable
3626  */
3627 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK (0x80U)
3628 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT (7U)
3629 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK)
3630 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SEQGEN_SHIFT)
3631 
3632 /*
3633  * ACTCTL (R/W)
3634  *
3635  * Active Destination MAC – control. See Table 6-6.
3636  */
3637 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK (0x30U)
3638 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT (4U)
3639 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK)
3640 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_ACTCTL_SHIFT)
3641 
3642 /*
3643  * SMAC (R/W)
3644  *
3645  * 0: Lookup by Destination MAC 1: Lookup by Source MAC
3646  */
3647 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK (0x8U)
3648 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT (3U)
3649 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK)
3650 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_SMAC_SHIFT)
3651 
3652 /*
3653  * MODE (R/W)
3654  *
3655  * Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged
3656  */
3657 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK (0x6U)
3658 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT (1U)
3659 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK)
3660 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_MODE_SHIFT)
3661 
3662 /*
3663  * EN (R/W)
3664  *
3665  * Enable entry
3666  */
3667 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK (0x1U)
3668 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT (0U)
3669 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK)
3670 #define TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_EGRESS_STMID_CONTROL_EN_SHIFT)
3671 
3672 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_SEQNO */
3673 /*
3674  * SEQNO (R/WC)
3675  *
3676  * Sequence number – next number when generating,any write access to clear.
3677  */
3678 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK (0xFFFFU)
3679 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT (0U)
3680 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK)
3681 #define TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_EGRESS_STMID_SEQNO_SEQNO_SHIFT)
3682 
3683 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MATCHCNT */
3684 /*
3685  * MATCH (R/WC)
3686  *
3687  * Entry match counter – any write access to clear.
3688  */
3689 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK (0xFFFFFFFFUL)
3690 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT (0U)
3691 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK)
3692 #define TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MATCHCNT_MATCH_SHIFT)
3693 
3694 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MACLO */
3695 /*
3696  * MACL (R/WC)
3697  *
3698  * MAC-Address [31:0] used by lookup.
3699  */
3700 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK (0xFFFFFFFFUL)
3701 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT (0U)
3702 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK)
3703 #define TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACLO_MACL_SHIFT)
3704 
3705 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_MACHI */
3706 /*
3707  * VID (R/W)
3708  *
3709  * VLAN ID used by lookup.
3710  */
3711 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK (0xFFF0000UL)
3712 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT (16U)
3713 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK)
3714 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_VID_SHIFT)
3715 
3716 /*
3717  * MATCH (R/W)
3718  *
3719  * MAC-Address [47:31] used by lookup.
3720  */
3721 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK (0xFFFFU)
3722 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT (0U)
3723 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK)
3724 #define TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_MACHI_MATCH_SHIFT)
3725 
3726 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_AMACLO */
3727 /*
3728  * AMACL (R/W)
3729  *
3730  * Active Destination MAC, MAC-Address [31:0]
3731  */
3732 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK (0xFFFFFFFFUL)
3733 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT (0U)
3734 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK)
3735 #define TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACLO_AMACL_SHIFT)
3736 
3737 /* Bitfield definition for register: CPU_PORT_EGRESS_STMID_AMACHI */
3738 /*
3739  * APCP (R/W)
3740  *
3741  * Active Destination MAC, PCP
3742  */
3743 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK (0xF0000000UL)
3744 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT (28U)
3745 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK)
3746 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_APCP_SHIFT)
3747 
3748 /*
3749  * AVID (R/W)
3750  *
3751  * Active Destination MAC, VLAN ID
3752  */
3753 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK (0xFFF0000UL)
3754 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT (16U)
3755 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK)
3756 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AVID_SHIFT)
3757 
3758 /*
3759  * AMACH (R/W)
3760  *
3761  * Active Destination MAC, MAC-Address [47:32]
3762  */
3763 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK (0xFFFFU)
3764 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT (0U)
3765 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK)
3766 #define TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_EGRESS_STMID_AMACHI_AMACH_SHIFT)
3767 
3768 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_CONTROL */
3769 /*
3770  * LATER (R/WC)
3771  *
3772  * Latent error flag – write 1 to clear
3773  */
3774 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK (0x2U)
3775 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT (1U)
3776 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK)
3777 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_LATER_SHIFT)
3778 
3779 /*
3780  * RTENC (R/W)
3781  *
3782  * R-TAG encoding enable.
3783  */
3784 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK (0x1U)
3785 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT (0U)
3786 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK)
3787 #define TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_EGRESS_FRER_CONTROL_RTENC_SHIFT)
3788 
3789 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_SIDSEL */
3790 /*
3791  * SID (R/W)
3792  *
3793  * Stream ID selection for host access to IRFUNC and SRFUNC.
3794  */
3795 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK (0xFFU)
3796 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT (0U)
3797 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK)
3798 #define TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SIDSEL_SID_SHIFT)
3799 
3800 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_IRFUNC */
3801 /*
3802  * FEN (R/W)
3803  *
3804  * Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
3805  */
3806 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK (0x80000000UL)
3807 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT (31U)
3808 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK)
3809 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FEN_SHIFT)
3810 
3811 /*
3812  * FIDX (R/W)
3813  *
3814  */
3815 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK (0xFFU)
3816 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT (0U)
3817 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK)
3818 #define TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_IRFUNC_FIDX_SHIFT)
3819 
3820 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_SRFUNC */
3821 /*
3822  * FEN (R/W)
3823  *
3824  * Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
3825  */
3826 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK (0x80000000UL)
3827 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT (31U)
3828 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK)
3829 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FEN_SHIFT)
3830 
3831 /*
3832  * FIDX (R/W)
3833  *
3834  */
3835 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK (0xFFU)
3836 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT (0U)
3837 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK)
3838 #define TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_SRFUNC_FIDX_SHIFT)
3839 
3840 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_FSELECT */
3841 /*
3842  * FIDX (R/W)
3843  *
3844  * Recovery function selection for host access at offset 0x140+
3845  */
3846 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK (0xFFU)
3847 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT (0U)
3848 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK)
3849 #define TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FSELECT_FIDX_SHIFT)
3850 
3851 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_FCTRL */
3852 /*
3853  * FRSET (WO)
3854  *
3855  * Reset recovery function – self-resetting to 0
3856  */
3857 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK (0x80000000UL)
3858 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT (31U)
3859 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK)
3860 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_FRSET_SHIFT)
3861 
3862 /*
3863  * PATHS (R/W)
3864  *
3865  * Number of paths (used by latent error detection)
3866  */
3867 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK (0xFF0000UL)
3868 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT (16U)
3869 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK)
3870 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_PATHS_SHIFT)
3871 
3872 /*
3873  * HLEN (R/W)
3874  *
3875  * History length (used by Vector recovery algorithm)
3876  */
3877 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK (0x1F00U)
3878 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT (8U)
3879 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK)
3880 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_HLEN_SHIFT)
3881 
3882 /*
3883  * ALGO (R/W)
3884  *
3885  * Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm
3886  */
3887 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK (0x10U)
3888 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT (4U)
3889 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK)
3890 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_ALGO_SHIFT)
3891 
3892 /*
3893  * LATEN (R/W)
3894  *
3895  * Latent error detection enable
3896  */
3897 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK (0x8U)
3898 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT (3U)
3899 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK)
3900 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_LATEN_SHIFT)
3901 
3902 /*
3903  * IND (R/W)
3904  *
3905  * Individual function (802.1CB 10.4.1.10)
3906  */
3907 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK (0x4U)
3908 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT (2U)
3909 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK)
3910 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_IND_SHIFT)
3911 
3912 /*
3913  * TNS (R/W)
3914  *
3915  * TakeNoSequence (802.1CB 10.4.1.9)
3916  */
3917 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK (0x2U)
3918 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT (1U)
3919 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK)
3920 #define TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_FCTRL_TNS_SHIFT)
3921 
3922 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_RESETMSEC */
3923 /*
3924  * FSRMS (R/W)
3925  *
3926  * frerSeqRcvyResetMSec (802.1CB 10.4.1.7)
3927  */
3928 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK (0xFFFFFFUL)
3929 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT (0U)
3930 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK)
3931 #define TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_EGRESS_FRER_RESETMSEC_FSRMS_SHIFT)
3932 
3933 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATRSPERIOD */
3934 /*
3935  * FLATR (R/W)
3936  *
3937  * frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4)
3938  */
3939 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK (0xFFFFFFUL)
3940 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT (0U)
3941 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK)
3942 #define TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)
3943 
3944 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATTESTPERIOD */
3945 /*
3946  * FLATT (R/W)
3947  *
3948  * frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2)
3949  */
3950 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK (0xFFFFFFUL)
3951 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT (0U)
3952 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK)
3953 #define TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)
3954 
3955 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATERRDIFFALW */
3956 /*
3957  * FDIFF (R/W)
3958  *
3959  * frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1)
3960  */
3961 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK (0xFFFFFFFFUL)
3962 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT (0U)
3963 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)
3964 #define TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)
3965 
3966 /* Bitfield definition for register: CPU_PORT_EGRESS_FRER_LATERRCNT */
3967 /*
3968  * LATERR (R/WC)
3969  *
3970  * Counter – latent error detect. Write any value to clear
3971  */
3972 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK (0xFFFFFFFFUL)
3973 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT (0U)
3974 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK)
3975 #define TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_EGRESS_FRER_LATERRCNT_LATERR_SHIFT)
3976 
3977 /* Bitfield definition for register array: EGFRCNT */
3978 /*
3979  * VALUE (RO)
3980  *
3981  * Frame counters
3982  */
3983 #define TSW_EGFRCNT_VALUE_MASK (0xFFFFFFFFUL)
3984 #define TSW_EGFRCNT_VALUE_SHIFT (0U)
3985 #define TSW_EGFRCNT_VALUE_GET(x) (((uint32_t)(x) & TSW_EGFRCNT_VALUE_MASK) >> TSW_EGFRCNT_VALUE_SHIFT)
3986 
3987 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE */
3988 /*
3989  * FDMEM_CNT_BYTE (RO)
3990  *
3991  * Number of bytes stored in frame drop FIFO
3992  */
3993 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK (0xFFFFFFFFUL)
3994 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT (0U)
3995 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)
3996 
3997 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS */
3998 /*
3999  * WAIT_FOR_LU (RO)
4000  *
4001  * FD FIFO waits for LookUp information.
4002  */
4003 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK (0x800U)
4004 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT (11U)
4005 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_LU_SHIFT)
4006 
4007 /*
4008  * WAIT_FOR_FRAME (RO)
4009  *
4010  * FD FIFO waits for more frame data.
4011  */
4012 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK (0x400U)
4013 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT (10U)
4014 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)
4015 
4016 /*
4017  * BUSY (RO)
4018  *
4019  * FD FIFO processes data.
4020  */
4021 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK (0x200U)
4022 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT (9U)
4023 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_BUSY_SHIFT)
4024 
4025 /*
4026  * READY (RO)
4027  *
4028  * FD FIFO ready to work or working.
4029  */
4030 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK (0x100U)
4031 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT (8U)
4032 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_READY_SHIFT)
4033 
4034 /*
4035  * FULL (RO)
4036  *
4037  * FD FIFO full
4038  */
4039 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK (0x8U)
4040 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT (3U)
4041 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_FULL_SHIFT)
4042 
4043 /*
4044  * AMST_FULL (RO)
4045  *
4046  * FD FIFO almost full. Less than 1600 Byte left.
4047  */
4048 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK (0x4U)
4049 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT (2U)
4050 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_FULL_SHIFT)
4051 
4052 /*
4053  * AMST_EMPTY (RO)
4054  *
4055  * FD FIFO almost empty. Few bytes in FIFO.
4056  */
4057 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK (0x2U)
4058 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT (1U)
4059 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_AMST_EMPTY_SHIFT)
4060 
4061 /*
4062  * EMPTY (RO)
4063  *
4064  * FD FIFO empty
4065  */
4066 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK (0x1U)
4067 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT (0U)
4068 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_FDMEM_STS_EMPTY_SHIFT)
4069 
4070 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG */
4071 /*
4072  * LU_DESC_ERR (R/W1C)
4073  *
4074  * LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset.
4075  */
4076 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK (0x40U)
4077 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT (6U)
4078 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK)
4079 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_LU_DESC_ERR_SHIFT)
4080 
4081 /*
4082  * WRFAIL_FULL (R/W1C)
4083  *
4084  * Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set.
4085  */
4086 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK (0x20U)
4087 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT (5U)
4088 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK)
4089 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_WRFAIL_FULL_SHIFT)
4090 
4091 /*
4092  * DROP_NRDY (R/W1C)
4093  *
4094  * Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO
4095  */
4096 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK (0x10U)
4097 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT (4U)
4098 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK)
4099 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_NRDY_SHIFT)
4100 
4101 /*
4102  * DROP_FULL_DESC (R/W1C)
4103  *
4104  * Frame was dropped because the internal descriptor FIFO is full. Full by too many frames.
4105  */
4106 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK (0x8U)
4107 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT (3U)
4108 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK)
4109 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_DESC_SHIFT)
4110 
4111 /*
4112  * DROP_FULL_MEM (R/W1C)
4113  *
4114  * Frame was dropped because the FIFO is full. Full by too much data.
4115  */
4116 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK (0x4U)
4117 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT (2U)
4118 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK)
4119 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DROP_FULL_MEM_SHIFT)
4120 
4121 /*
4122  * DESC_NRDY_ERR (R/W1C)
4123  *
4124  * FD FIFO failure. Descriptor not received correctly.
4125  */
4126 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK (0x2U)
4127 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT (1U)
4128 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK)
4129 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)
4130 
4131 /*
4132  * DESC_SEQ_ERR (R/W1C)
4133  *
4134  * FD FIFO failure. Internal controller lost synchronization.
4135  */
4136 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK (0x1U)
4137 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT (0U)
4138 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK)
4139 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)
4140 
4141 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG */
4142 /*
4143  * IE (R/W)
4144  *
4145  * Interrupt enable of ERROR_FLAG.
4146  */
4147 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK (0x7FU)
4148 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT (0U)
4149 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK)
4150 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IE_ERROR_FLAG_IE_SHIFT)
4151 
4152 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG */
4153 /*
4154  * NOCUT_ERROR (R/W)
4155  *
4156  * FD_FIFO does not shorten frames which contain an error.
4157  */
4158 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK (0x1U)
4159 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT (0U)
4160 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK)
4161 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_IN_CONFIG_NOCUT_ERROR_SHIFT)
4162 
4163 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG */
4164 /*
4165  * DROP_DEST (R/W)
4166  *
4167  * Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0].
4168  */
4169 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK (0xFFFF0000UL)
4170 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT (16U)
4171 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK)
4172 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_DEST_SHIFT)
4173 
4174 /*
4175  * MIRROR_TX_EN (R/W)
4176  *
4177  * Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX.
4178  */
4179 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK (0x200U)
4180 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT (9U)
4181 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK)
4182 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TX_EN_SHIFT)
4183 
4184 /*
4185  * MIRROR_RX_EN (R/W)
4186  *
4187  * Incoming frames of this port will be mirrored to the given destination in MIRROR_RX.
4188  */
4189 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK (0x100U)
4190 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT (8U)
4191 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK)
4192 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_RX_EN_SHIFT)
4193 
4194 /*
4195  * CT_FPE_OVRD (R/W)
4196  *
4197  * If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F.
4198  */
4199 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK (0x40U)
4200 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT (6U)
4201 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK)
4202 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_CT_FPE_OVRD_SHIFT)
4203 
4204 /*
4205  * DISABLE (R/W)
4206  *
4207  * Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL.
4208  */
4209 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK (0x20U)
4210 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT (5U)
4211 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK)
4212 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DISABLE_SHIFT)
4213 
4214 /*
4215  * DROP_ALL (R/W)
4216  *
4217  * Route all frames to DROP_DEST.
4218  */
4219 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK (0x10U)
4220 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT (4U)
4221 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK)
4222 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_DROP_ALL_SHIFT)
4223 
4224 /*
4225  * ERROR_TO_CPU (R/W)
4226  *
4227  * Send error frames to CPU.
4228  */
4229 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK (0x8U)
4230 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT (3U)
4231 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK)
4232 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_ERROR_TO_CPU_SHIFT)
4233 
4234 /*
4235  * MIRROR_TO_CPU (R/W)
4236  *
4237  * Duplicate frames to CPU.
4238  */
4239 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK (0x4U)
4240 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT (2U)
4241 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK)
4242 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)
4243 
4244 /*
4245  * NODROP_ERROR (R/W)
4246  *
4247  * Do not drop frame errors.
4248  */
4249 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK (0x2U)
4250 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT (1U)
4251 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK)
4252 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_NODROP_ERROR_SHIFT)
4253 
4254 /*
4255  * MODE_STORE_FW (R/W)
4256  *
4257  * Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward
4258  */
4259 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK (0x1U)
4260 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT (0U)
4261 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK)
4262 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_OUT_CONFIG_MODE_STORE_FW_SHIFT)
4263 
4264 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_RESET */
4265 /*
4266  * SOFTRS (W)
4267  *
4268  * Write 1 to reset FD controller and memory pointers. Register Map content remains untouched
4269  */
4270 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK (0x1U)
4271 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT (0U)
4272 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK)
4273 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_RESET_SOFTRS_SHIFT)
4274 
4275 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_PARAM */
4276 /*
4277  * LU_FIFO_DEPTH (RO)
4278  *
4279  * Number of MAC lookup descriptors the FIFO can store.
4280  */
4281 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK (0xFF000000UL)
4282 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT (24U)
4283 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_LU_FIFO_DEPTH_SHIFT)
4284 
4285 /*
4286  * FD_DESC_FIFO_DESC (RO)
4287  *
4288  * Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame.
4289  */
4290 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK (0xFF0000UL)
4291 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT (16U)
4292 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_DESC_FIFO_DESC_SHIFT)
4293 
4294 /*
4295  * FD_FIFO_DESC (RO)
4296  *
4297  * Number of words (4byte) the Frame Drop FIFO can store.
4298  */
4299 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK (0xFFFFU)
4300 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT (0U)
4301 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PARAM_FD_FIFO_DESC_SHIFT)
4302 
4303 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_STRFWD */
4304 /*
4305  * PORT (R/W)
4306  *
4307  * If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port,
4308  * bit 1 - Port 1, …
4309  */
4310 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK (0x1FFFFFFUL)
4311 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT (0U)
4312 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK)
4313 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_STRFWD_PORT_SHIFT)
4314 
4315 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK */
4316 /*
4317  * PORT (R/W)
4318  *
4319  * Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports).
4320  * bit 0 - CPU-Port,
4321  * bit 1 - Port 1, …
4322  */
4323 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK (0x1FFFFFFUL)
4324 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT (0U)
4325 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK)
4326 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_PORTMASK_PORT_SHIFT)
4327 
4328 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_MIRROR */
4329 /*
4330  * PORT (R/W)
4331  *
4332  * Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port.
4333  * bit 0 - CPU-Port,
4334  * bit 1 - Port 1, …
4335  */
4336 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK (0x1FFFFFFUL)
4337 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT (0U)
4338 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK)
4339 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_PORT_SHIFT)
4340 
4341 /* Bitfield definition for register: CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX */
4342 /*
4343  * PORT (R/W)
4344  *
4345  * Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic.
4346  * bit 0 - CPU-Port,
4347  * bit 1 - Port 1, …
4348  */
4349 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK (0x1FFFFFFUL)
4350 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT (0U)
4351 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK)
4352 #define TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_MASK) >> TSW_CPU_PORT_IGRESS_RX_FDFIFO_MIRROR_TX_PORT_SHIFT)
4353 
4354 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_ESELECT */
4355 /*
4356  * ESEL (RW)
4357  *
4358  * Select entry. Selected entry mapped to 0x40 – 0x5C.
4359  */
4360 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK (0xFFU)
4361 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT (0U)
4362 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK)
4363 #define TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_ESELECT_ESEL_SHIFT)
4364 
4365 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_CONTROL */
4366 /*
4367  * SID (RW)
4368  *
4369  * Stream ID – inserted to header on match
4370  */
4371 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK (0xFF00U)
4372 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT (8U)
4373 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK)
4374 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SID_SHIFT)
4375 
4376 /*
4377  * SEQGEN (RW)
4378  *
4379  * Sequence number generation enable
4380  */
4381 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK (0x80U)
4382 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT (7U)
4383 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK)
4384 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SEQGEN_SHIFT)
4385 
4386 /*
4387  * ACTCTL (RW)
4388  *
4389  * Active Destination MAC – control. See Table 6-6.
4390  */
4391 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK (0x30U)
4392 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT (4U)
4393 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK)
4394 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_ACTCTL_SHIFT)
4395 
4396 /*
4397  * SMAC (RW)
4398  *
4399  * 0: Lookup by Destination MAC 1: Lookup by Source MAC
4400  */
4401 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK (0x8U)
4402 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT (3U)
4403 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK)
4404 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_SMAC_SHIFT)
4405 
4406 /*
4407  * MODE (RW)
4408  *
4409  * Lookup mode. 1:Priority – a frame must be untagged or priority tagged ; 2:Tagged – a frame must have a VLAN tag ; 3:All – a frame can be tagged or untagged
4410  */
4411 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK (0x6U)
4412 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT (1U)
4413 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK)
4414 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_MODE_SHIFT)
4415 
4416 /*
4417  * EN (RW)
4418  *
4419  * Enable entry
4420  */
4421 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK (0x1U)
4422 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT (0U)
4423 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK)
4424 #define TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_MASK) >> TSW_CPU_PORT_IGRESS_STMID_CONTROL_EN_SHIFT)
4425 
4426 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_SEQNO */
4427 /*
4428  * SEQNO (RWC)
4429  *
4430  * Sequence number – next number when generating,any write access to clear.
4431  */
4432 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK (0xFFFFU)
4433 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT (0U)
4434 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK)
4435 #define TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_MASK) >> TSW_CPU_PORT_IGRESS_STMID_SEQNO_SEQNO_SHIFT)
4436 
4437 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MATCHCNT */
4438 /*
4439  * MATCH (RWC)
4440  *
4441  * Entry match counter – any write access to clear.
4442  */
4443 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK (0xFFFFFFFFUL)
4444 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT (0U)
4445 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK)
4446 #define TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MATCHCNT_MATCH_SHIFT)
4447 
4448 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MACLO */
4449 /*
4450  * MACL (RWC)
4451  *
4452  * MAC-Address [31:0] used by lookup.
4453  */
4454 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK (0xFFFFFFFFUL)
4455 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT (0U)
4456 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK)
4457 #define TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACLO_MACL_SHIFT)
4458 
4459 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_MACHI */
4460 /*
4461  * VID (RW)
4462  *
4463  * VLAN ID used by lookup.
4464  */
4465 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK (0xFFF0000UL)
4466 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT (16U)
4467 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK)
4468 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_VID_SHIFT)
4469 
4470 /*
4471  * MATCH (RW)
4472  *
4473  * MAC-Address [47:31] used by lookup.
4474  */
4475 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK (0xFFFFU)
4476 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT (0U)
4477 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK)
4478 #define TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_MACHI_MATCH_SHIFT)
4479 
4480 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_AMACLO */
4481 /*
4482  * AMACL (RW)
4483  *
4484  * Active Destination MAC, MAC-Address [31:0]
4485  */
4486 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK (0xFFFFFFFFUL)
4487 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT (0U)
4488 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK)
4489 #define TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACLO_AMACL_SHIFT)
4490 
4491 /* Bitfield definition for register: CPU_PORT_IGRESS_STMID_AMACHI */
4492 /*
4493  * APCP (RW)
4494  *
4495  * Active Destination MAC, PCP
4496  */
4497 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK (0xF0000000UL)
4498 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT (28U)
4499 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK)
4500 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_APCP_SHIFT)
4501 
4502 /*
4503  * AVID (RW)
4504  *
4505  * Active Destination MAC, VLAN ID
4506  */
4507 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK (0xFFF0000UL)
4508 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT (16U)
4509 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK)
4510 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AVID_SHIFT)
4511 
4512 /*
4513  * AMACH (RW)
4514  *
4515  * Active Destination MAC, MAC-Address [47:32]
4516  */
4517 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK (0xFFFFU)
4518 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT (0U)
4519 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK)
4520 #define TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_MASK) >> TSW_CPU_PORT_IGRESS_STMID_AMACHI_AMACH_SHIFT)
4521 
4522 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_CONTROL */
4523 /*
4524  * LATER (RWC)
4525  *
4526  * Latent error flag – write 1 to clear
4527  */
4528 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK (0x2U)
4529 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT (1U)
4530 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK)
4531 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_LATER_SHIFT)
4532 
4533 /*
4534  * RTENC (RW)
4535  *
4536  * R-TAG encoding enable.
4537  */
4538 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK (0x1U)
4539 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT (0U)
4540 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK)
4541 #define TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_MASK) >> TSW_CPU_PORT_IGRESS_FRER_CONTROL_RTENC_SHIFT)
4542 
4543 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_SIDSEL */
4544 /*
4545  * SID (RW)
4546  *
4547  * Stream ID selection for host access to IRFUNC and SRFUNC.
4548  */
4549 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK (0xFFU)
4550 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT (0U)
4551 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK)
4552 #define TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SIDSEL_SID_SHIFT)
4553 
4554 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_IRFUNC */
4555 /*
4556  * FEN (RW)
4557  *
4558  * Individual recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
4559  */
4560 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK (0x80000000UL)
4561 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT (31U)
4562 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK)
4563 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FEN_SHIFT)
4564 
4565 /*
4566  * FIDX (RW)
4567  *
4568  */
4569 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK (0xFFU)
4570 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT (0U)
4571 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK)
4572 #define TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_IRFUNC_FIDX_SHIFT)
4573 
4574 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_SRFUNC */
4575 /*
4576  * FEN (RW)
4577  *
4578  * Sequence recovery function: FEN – enable function for stream SIDSEL.SID. FIDX – function index for stream SIDSEL.SID If function does not exists (FIDX >= 2**FD), FEN will be set to 0.
4579  */
4580 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK (0x80000000UL)
4581 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT (31U)
4582 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK)
4583 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FEN_SHIFT)
4584 
4585 /*
4586  * FIDX (RW)
4587  *
4588  */
4589 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK (0xFFU)
4590 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT (0U)
4591 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK)
4592 #define TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_SRFUNC_FIDX_SHIFT)
4593 
4594 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_FSELECT */
4595 /*
4596  * FIDX (RW)
4597  *
4598  * Recovery function selection for host access at offset 0x140+
4599  */
4600 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK (0xFFU)
4601 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT (0U)
4602 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK)
4603 #define TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FSELECT_FIDX_SHIFT)
4604 
4605 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_FCTRL */
4606 /*
4607  * FRSET (WO)
4608  *
4609  * Reset recovery function – self-resetting to 0
4610  */
4611 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK (0x80000000UL)
4612 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT (31U)
4613 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK)
4614 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_FRSET_SHIFT)
4615 
4616 /*
4617  * PATHS (RW)
4618  *
4619  * Number of paths (used by latent error detection)
4620  */
4621 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK (0xFF0000UL)
4622 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT (16U)
4623 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK)
4624 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_PATHS_SHIFT)
4625 
4626 /*
4627  * HLEN (RW)
4628  *
4629  * History length (used by Vector recovery algorithm)
4630  */
4631 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK (0x1F00U)
4632 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT (8U)
4633 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK)
4634 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_HLEN_SHIFT)
4635 
4636 /*
4637  * ALGO (RW)
4638  *
4639  * Recovery function algorithm: 0 – Vector recovery algorithm 1 – Match recovery algorithm
4640  */
4641 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK (0x10U)
4642 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT (4U)
4643 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK)
4644 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_ALGO_SHIFT)
4645 
4646 /*
4647  * LATEN (RW)
4648  *
4649  * Latent error detection enable
4650  */
4651 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK (0x8U)
4652 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT (3U)
4653 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK)
4654 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_LATEN_SHIFT)
4655 
4656 /*
4657  * IND (RW)
4658  *
4659  * Individual function (802.1CB 10.4.1.10)
4660  */
4661 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK (0x4U)
4662 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT (2U)
4663 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK)
4664 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_IND_SHIFT)
4665 
4666 /*
4667  * TNS (RW)
4668  *
4669  * TakeNoSequence (802.1CB 10.4.1.9)
4670  */
4671 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK (0x2U)
4672 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT (1U)
4673 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK)
4674 #define TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_FCTRL_TNS_SHIFT)
4675 
4676 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_RESETMSEC */
4677 /*
4678  * FSRMS (RW)
4679  *
4680  * frerSeqRcvyResetMSec (802.1CB 10.4.1.7)
4681  */
4682 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK (0xFFFFFFUL)
4683 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT (0U)
4684 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK)
4685 #define TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_MASK) >> TSW_CPU_PORT_IGRESS_FRER_RESETMSEC_FSRMS_SHIFT)
4686 
4687 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATRSPERIOD */
4688 /*
4689  * FLATR (RW)
4690  *
4691  * frerSeqRcvyLatentResetPeriod (802.1CB 10.4.1.12.4)
4692  */
4693 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK (0xFFFFFFUL)
4694 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT (0U)
4695 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK)
4696 #define TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATRSPERIOD_FLATR_SHIFT)
4697 
4698 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATTESTPERIOD */
4699 /*
4700  * FLATT (RW)
4701  *
4702  * frerSeqRcvyLatentErrorPeriod (802.1CB 10.4.1.12.2)
4703  */
4704 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK (0xFFFFFFUL)
4705 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT (0U)
4706 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK)
4707 #define TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATTESTPERIOD_FLATT_SHIFT)
4708 
4709 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATERRDIFFALW */
4710 /*
4711  * FDIFF (RW)
4712  *
4713  * frerSeqRcvyLatentErrorDifference (802.1CB 10.4.1.12.1)
4714  */
4715 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK (0xFFFFFFFFUL)
4716 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT (0U)
4717 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK)
4718 #define TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRDIFFALW_FDIFF_SHIFT)
4719 
4720 /* Bitfield definition for register: CPU_PORT_IGRESS_FRER_LATERRCNT */
4721 /*
4722  * LATERR (RWC)
4723  *
4724  * Counter – latent error detect. Write any value to clear
4725  */
4726 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK (0xFFFFFFFFUL)
4727 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT (0U)
4728 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK)
4729 #define TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_MASK) >> TSW_CPU_PORT_IGRESS_FRER_LATERRCNT_LATERR_SHIFT)
4730 
4731 /* Bitfield definition for register array: IGFRCNT */
4732 /*
4733  * VALUE (RO)
4734  *
4735  * Frame counters
4736  */
4737 #define TSW_IGFRCNT_VALUE_MASK (0xFFFFFFFFUL)
4738 #define TSW_IGFRCNT_VALUE_SHIFT (0U)
4739 #define TSW_IGFRCNT_VALUE_GET(x) (((uint32_t)(x) & TSW_IGFRCNT_VALUE_MASK) >> TSW_IGFRCNT_VALUE_SHIFT)
4740 
4741 /* Bitfield definition for register: CPU_PORT_MONITOR_CTRL */
4742 /*
4743  * EN (R/W)
4744  *
4745  * Enables counter. If deasserted the counter process stops and the counters hold their value.
4746  */
4747 #define TSW_CPU_PORT_MONITOR_CTRL_EN_MASK (0x1U)
4748 #define TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT (0U)
4749 #define TSW_CPU_PORT_MONITOR_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK)
4750 #define TSW_CPU_PORT_MONITOR_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_CTRL_EN_MASK) >> TSW_CPU_PORT_MONITOR_CTRL_EN_SHIFT)
4751 
4752 /* Bitfield definition for register: CPU_PORT_MONITOR_RESET */
4753 /*
4754  * RSRX (WO)
4755  *
4756  * Write '1' to reset all RX counters.
4757  */
4758 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK (0x4U)
4759 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT (2U)
4760 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK)
4761 #define TSW_CPU_PORT_MONITOR_RESET_RSRX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSRX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSRX_SHIFT)
4762 
4763 /*
4764  * RSTX (WO)
4765  *
4766  * Write '1' to reset all TX counters
4767  */
4768 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK (0x2U)
4769 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT (1U)
4770 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK)
4771 #define TSW_CPU_PORT_MONITOR_RESET_RSTX_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSTX_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSTX_SHIFT)
4772 
4773 /*
4774  * RSALL (WO)
4775  *
4776  * Write '1' to reset all TX&RX counters.
4777  */
4778 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK (0x1U)
4779 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT (0U)
4780 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_SET(x) (((uint32_t)(x) << TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK)
4781 #define TSW_CPU_PORT_MONITOR_RESET_RSALL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RESET_RSALL_MASK) >> TSW_CPU_PORT_MONITOR_RESET_RSALL_SHIFT)
4782 
4783 /* Bitfield definition for register: CPU_PORT_MONITOR_PARAM */
4784 /*
4785  * RX_CNT_EN_VEC (RO)
4786  *
4787  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
4788  */
4789 #define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK (0xFFFF0000UL)
4790 #define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT (16U)
4791 #define TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)
4792 
4793 /*
4794  * TX_CNT_EN_VEC (RO)
4795  *
4796  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
4797  */
4798 #define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK (0xFF00U)
4799 #define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT (8U)
4800 #define TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)
4801 
4802 /*
4803  * CNTW (RO)
4804  *
4805  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter
4806  * are available.
4807  */
4808 #define TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK (0x7FU)
4809 #define TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT (0U)
4810 #define TSW_CPU_PORT_MONITOR_PARAM_CNTW_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_PARAM_CNTW_MASK) >> TSW_CPU_PORT_MONITOR_PARAM_CNTW_SHIFT)
4811 
4812 /* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD */
4813 /*
4814  * TX_FGOOD (RO)
4815  *
4816  * Good transmitted Frames to TX TSN-EP.
4817  */
4818 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK (0xFFFFFFFFUL)
4819 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT (0U)
4820 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)
4821 
4822 /* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR */
4823 /*
4824  * TX_FERROR (RO)
4825  *
4826  * Transmitted Frames with Error to TX TSN-EP.
4827  */
4828 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK (0xFFFFFFFFUL)
4829 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT (0U)
4830 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)
4831 
4832 /* Bitfield definition for register: CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL */
4833 /*
4834  * TX_DROP_OVFL (RO)
4835  *
4836  * Dropped frames by full queue of TSN-EP.
4837  */
4838 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK (0xFFFFFFFFUL)
4839 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT (0U)
4840 #define TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)
4841 
4842 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD */
4843 /*
4844  * RX_FGOOD (RO)
4845  *
4846  * Good received frame by ingress buffer.
4847  */
4848 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK (0xFFFFFFFFUL)
4849 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT (0U)
4850 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)
4851 
4852 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR */
4853 /*
4854  * RX_FERROR (RO)
4855  *
4856  * Bad received frame by ingress buffer.
4857  */
4858 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK (0xFFFFFFFFUL)
4859 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT (0U)
4860 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)
4861 
4862 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN */
4863 /*
4864  * RX_KNOWN (RO)
4865  *
4866  * Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames.
4867  */
4868 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK (0xFFFFFFFFUL)
4869 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT (0U)
4870 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)
4871 
4872 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN */
4873 /*
4874  * RX_UNKNOWN (RO)
4875  *
4876  * Number of frames passed ingress without hit by MAC table.
4877  */
4878 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK (0xFFFFFFFFUL)
4879 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT (0U)
4880 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)
4881 
4882 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_UC */
4883 /*
4884  * RX_UC (RO)
4885  *
4886  * Number of unicast frames
4887  */
4888 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK (0xFFFFFFFFUL)
4889 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT (0U)
4890 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)
4891 
4892 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN */
4893 /*
4894  * RX_INTERN (RO)
4895  *
4896  * Number of non-relay frames
4897  */
4898 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK (0xFFFFFFFFUL)
4899 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT (0U)
4900 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)
4901 
4902 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_BC */
4903 /*
4904  * RX_BC (RO)
4905  *
4906  * Number of Broadcast frames
4907  */
4908 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK (0xFFFFFFFFUL)
4909 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT (0U)
4910 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)
4911 
4912 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI */
4913 /*
4914  * RX_MULTI (RO)
4915  *
4916  * Number of Multicast frames
4917  */
4918 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK (0xFFFFFFFFUL)
4919 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT (0U)
4920 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)
4921 
4922 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN */
4923 /*
4924  * RX_VLAN (RO)
4925  *
4926  * Number of VLAN tagged frames
4927  */
4928 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK (0xFFFFFFFFUL)
4929 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT (0U)
4930 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)
4931 
4932 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL */
4933 /*
4934  * RX_DROP_OVFL (RO)
4935  *
4936  * Dropped frames by ingress overflow.
4937  */
4938 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK (0xFFFFFFFFUL)
4939 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT (0U)
4940 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)
4941 
4942 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU */
4943 /*
4944  * RX_DROP_LU (RO)
4945  *
4946  * Dropped frames by LookUp decision.
4947  */
4948 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK (0xFFFFFFFFUL)
4949 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT (0U)
4950 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)
4951 
4952 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR */
4953 /*
4954  * RX_DROP_ERR (RO)
4955  *
4956  * Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress.
4957  */
4958 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK (0xFFFFFFFFUL)
4959 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT (0U)
4960 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)
4961 
4962 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN */
4963 /*
4964  * RX_DROP_VLAN (RO)
4965  *
4966  * Dropped frames by incompatible VLAN.
4967  */
4968 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK (0xFFFFFFFFUL)
4969 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT (0U)
4970 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)
4971 
4972 /* Bitfield definition for register: CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD */
4973 /*
4974  * RX_FPE_FGOOD (RO)
4975  *
4976  * Number of preemptable frames. Subset of RX_FGOOD
4977  */
4978 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK (0xFFFFFFFFUL)
4979 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT (0U)
4980 #define TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x) (((uint32_t)(x) & TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_CPU_PORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)
4981 
4982 /* Bitfield definition for register of struct array TSNPORT: MAC_VER */
4983 /*
4984  * VER_H (R)
4985  *
4986  * Major version number (higher part of the version)
4987  */
4988 #define TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK (0xFFFF0000UL)
4989 #define TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT (16U)
4990 #define TSW_TSNPORT_MAC_MAC_VER_VER_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_H_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_H_SHIFT)
4991 
4992 /*
4993  * VER_L (R)
4994  *
4995  * Minor version number (lower part of the version)
4996  */
4997 #define TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK (0xFFFFU)
4998 #define TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT (0U)
4999 #define TSW_TSNPORT_MAC_MAC_VER_VER_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_VER_VER_L_MASK) >> TSW_TSNPORT_MAC_MAC_VER_VER_L_SHIFT)
5000 
5001 /* Bitfield definition for register of struct array TSNPORT: MAC_MACADDR_L */
5002 /*
5003  * MACADDR (R/W)
5004  *
5005  * MAC address
5006  * Lower bits of MAC address (31:0).
5007  * MACADDR only be modified if TX_EN=0 and RX_EN=0.
5008  */
5009 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK (0xFFFFFFFFUL)
5010 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT (0U)
5011 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK)
5012 #define TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_L_MACADDR_SHIFT)
5013 
5014 /* Bitfield definition for register of struct array TSNPORT: MAC_MACADDR_H */
5015 /*
5016  * PROMISC (R/W)
5017  *
5018  * 0 – disabled
5019  * 1 – enabled
5020  * If promiscuous mode is enabled, then reception of all frames independent from the
5021  * Ethernet destination address is enabled.
5022  * PROMISC can be changed at any time.
5023  */
5024 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK (0x10000UL)
5025 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT (16U)
5026 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK)
5027 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_PROMISC_SHIFT)
5028 
5029 /*
5030  * MACADDR (R/W)
5031  *
5032  * MAC address (see Chapter 4.1)
5033  * Upper bits of MAC address (47:32).
5034  * MACADDR can only be modified if TX_EN=0 and RX_EN=0.
5035  */
5036 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK (0xFFFFU)
5037 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT (0U)
5038 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK)
5039 #define TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_MASK) >> TSW_TSNPORT_MAC_MAC_MACADDR_H_MACADDR_SHIFT)
5040 
5041 /* Bitfield definition for register of struct array TSNPORT: MAC_MAC_CTRL */
5042 /*
5043  * FSTIM (R/W)
5044  *
5045  * Fault Stimulation
5046  * See Chapter 11.3, Table 11-1 for details.
5047  * FSTIM is write-locked if CSA=1.
5048  */
5049 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK (0x1F000000UL)
5050 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT (24U)
5051 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK)
5052 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_FSTIM_SHIFT)
5053 
5054 /*
5055  * RCA (R)
5056  *
5057  * <ref_clk> active
5058  * 0 – not active
5059  * 1 – active
5060  * See chapter 11.2.3 for details.
5061  */
5062 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK (0x100000UL)
5063 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT (20U)
5064 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCA_SHIFT)
5065 
5066 /*
5067  * MCA (R)
5068  *
5069  * <mii_clk> active
5070  * 0 – not active
5071  * 1 – active
5072  * See chapter 11.2.3 for details.
5073  */
5074 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK (0x80000UL)
5075 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT (19U)
5076 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCA_SHIFT)
5077 
5078 /*
5079  * SEN (R/W)
5080  *
5081  * Safety Enable
5082  * 0 – disabled
5083  * 1 – enabled
5084  * If enabled, then two instances of the logic core of LLEMAC-1G are compared at
5085  * runtime to each other.
5086  * SEN can only be changed if RX_EN and TX_EN can be read as 0. Deactivation delays
5087  * of RX_EN and TX_EN have to be considered. It is possible to change SEN together
5088  * with the activation of RX_EN and TX_EN.
5089  */
5090 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK (0x10000UL)
5091 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT (16U)
5092 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK)
5093 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_SEN_SHIFT)
5094 
5095 /*
5096  * CSA (R)
5097  *
5098  * Clock switching active (<tx_clk>)
5099  * 0 – not active
5100  * 1 – active
5101  * Switching of <tx_clk> is commanded if CLKSEL or FSTIM (see Table 11-1) are
5102  * written. Clock switching takes a few clock cycles and this is signaled with CSA=1.
5103  * When CSA=1 then CLKSEL and FSTIM are write-locked and cannot be changed.
5104  */
5105 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK (0x2000U)
5106 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT (13U)
5107 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CSA_SHIFT)
5108 
5109 /*
5110  * RCE (R/W)
5111  *
5112  * <ref_clk> enable
5113  * 0 – disabled
5114  * 1 – enabled
5115  * RCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details.
5116  */
5117 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK (0x1000U)
5118 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT (12U)
5119 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK)
5120 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RCE_SHIFT)
5121 
5122 /*
5123  * MCE (R/W)
5124  *
5125  * <mii_clk> enable
5126  * 0 – disabled
5127  * 1 – enabled
5128  * MCE can only be modified if CLKSEL=111. See Chapter 7.3.3 for further details.
5129  */
5130 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK (0x800U)
5131 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT (11U)
5132 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK)
5133 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_MCE_SHIFT)
5134 
5135 /*
5136  * CLKSEL (R/W)
5137  *
5138  * TX path clock selector
5139  * 000 – <mii_clk>
5140  * 001 – <ref_clk> (recommended setting for this selection)
5141  * 010 – <ref_clk> divided by 5
5142  * 011 – <ref_clk> divided by 10
5143  * 100 – <ref_clk> divided by 50
5144  * 111 – <ref_clk> and enables modification of RCE and MCE
5145  * others – <ref_clk>
5146  * See Chapter 7 for further details.
5147  * CLKSEL is write-locked if CSA=1.
5148  */
5149 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK (0x700U)
5150 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT (8U)
5151 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK)
5152 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_CLKSEL_SHIFT)
5153 
5154 /*
5155  * PHYSEL (R/W)
5156  *
5157  * Selection of the PHY (See Chapter 4.6.)
5158  * 00 – MII
5159  * 01 – GMII
5160  * 10 – RGMII
5161  * 11 – reserved
5162  * PHYSEL can only be changed if RX_EN=0 and TX_EN=0. Deactivation delays of
5163  * RX_EN and TX_EN have to be considered. PHYSEL can only be changed, if these
5164  * register bits can be read as 0. It is possible to change PHYSEL together with the
5165  * activation of RX_EN and TX_EN.
5166  * PHYSEL drives the output <rx_physel>.
5167  */
5168 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK (0x60U)
5169 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT (5U)
5170 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK)
5171 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_PHYSEL_SHIFT)
5172 
5173 /*
5174  * GMIIMODE (R/W)
5175  *
5176  * GMII mode / Ethernet speed selection (See Chapter 4.5.)
5177  * 0 – MII: 10Mbit/s or 100Mbit/s
5178  * 1 – GMII: 1GBit/s
5179  * GMIIMODE can only be changed if RX_EN=0 and TX_EN=0. Deactivation delays of
5180  * RX_EN and TX_EN have to be considered. GMIIMODE can only be changed, if these
5181  * register bits can be read as 0. It is possible to change GMIIMODE together with the
5182  * activation of RX_EN and TX_EN.
5183  * GMIIMODE drives the outputs <tx_gmiimode> and <rx_gmiimode>.
5184  */
5185 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK (0x10U)
5186 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT (4U)
5187 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK)
5188 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_GMIIMODE_SHIFT)
5189 
5190 /*
5191  * JUMBO (R/W)
5192  *
5193  * Jumbo frame support
5194  * 0 – jumbo frames not supported
5195  * 1 – jumbo frame supported (not recommended)
5196  * Jumbo frames are non-standard Ethernet frames with a size bigger than envelope
5197  * frames (which contain 1982 payload bytes). If jumbo frames are not supported, then
5198  * LLEMAC-1G generates the appropriate error signals (<tx_gmii_er> for the TX path
5199  * and <rx_avst_err> for the RX path).
5200  * Although jumbo frames typically contain up to 9000 bytes, the LLEMAC-1G can handle
5201  * an infinite frame size. The problem of jumbo frames is the necessary storage space in
5202  * transmission and reception buffers. LLEMAC-1G does not include storage buffers.
5203  * JUMBO can be activated or deactivated at any time. The new setting becomes valid
5204  * immediately after clock domain crossing.
5205  */
5206 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK (0x8U)
5207 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT (3U)
5208 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK)
5209 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_JUMBO_SHIFT)
5210 
5211 /*
5212  * TX_EN (R/W)
5213  *
5214  * TX path enable
5215  * 0 – transmission disabled - Avalon-ST READY for the TX path will be set to 0.
5216  * 1 – transmission enabled
5217  * TX_EN can be activated or deactivated at any time. Deactivation may take some time.
5218  * If during deactivation there is a frame in transmission, then this frame will be
5219  * completed fist. Afterwards bit TX_EN can be read as 0.
5220  * After the transmission is disabled there may be pending frames left, waiting at the TX
5221  * stream interface.
5222  */
5223 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK (0x4U)
5224 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT (2U)
5225 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK)
5226 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_TX_EN_SHIFT)
5227 
5228 /*
5229  * RX_EN (R/W)
5230  *
5231  * RX path enable
5232  * 0 – reception disabled – no frames fed to Avalon-ST RX path
5233  * 1 – reception enabled
5234  * RX_EN can be activated or deactivated at any time. Deactivation may take some time.
5235  * If during deactivation there is a frame in reception, then this frame will be completed
5236  * first. Afterwards bit RX_EN can be read as 0.
5237  */
5238 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK (0x2U)
5239 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT (1U)
5240 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK)
5241 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RX_EN_SHIFT)
5242 
5243 /*
5244  * RESSTAT (R/W)
5245  *
5246  * Software reset of the statistic counters (see Table 3-8)
5247  * 0 – no reset
5248  * 1 – reset active
5249  * RESSTAT will be automatically set to 0 after the counters have been reset
5250  */
5251 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK (0x1U)
5252 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT (0U)
5253 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK)
5254 #define TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_MASK) >> TSW_TSNPORT_MAC_MAC_MAC_CTRL_RESSTAT_SHIFT)
5255 
5256 /* Bitfield definition for register of struct array TSNPORT: MAC_TX_FRAMES */
5257 /*
5258  * TX_FRAMES (R)
5259  *
5260  * Number of successfully transmitted frames.
5261  */
5262 #define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK (0xFFFFFFFFUL)
5263 #define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT (0U)
5264 #define TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_TX_FRAMES_TX_FRAMES_SHIFT)
5265 
5266 /* Bitfield definition for register of struct array TSNPORT: MAC_RX_FRAMES */
5267 /*
5268  * RX_FRAMES (R)
5269  *
5270  * Number of successfully received frames.
5271  */
5272 #define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK (0xFFFFFFFFUL)
5273 #define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT (0U)
5274 #define TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_MASK) >> TSW_TSNPORT_MAC_MAC_RX_FRAMES_RX_FRAMES_SHIFT)
5275 
5276 /* Bitfield definition for register of struct array TSNPORT: MAC_TX_OCTETS */
5277 /*
5278  * TX_OCTETS (R)
5279  *
5280  * Number of successfully transmitted payload and padding octets.
5281  */
5282 #define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK (0xFFFFFFFFUL)
5283 #define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT (0U)
5284 #define TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_TX_OCTETS_TX_OCTETS_SHIFT)
5285 
5286 /* Bitfield definition for register of struct array TSNPORT: MAC_RX_OCTETS */
5287 /*
5288  * RX_OCTETS (R)
5289  *
5290  * Number of successfully received payload and padding octets.
5291  */
5292 #define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK (0xFFFFFFFFUL)
5293 #define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT (0U)
5294 #define TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_MASK) >> TSW_TSNPORT_MAC_MAC_RX_OCTETS_RX_OCTETS_SHIFT)
5295 
5296 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_CFG */
5297 /*
5298  * NPRE (R/W)
5299  *
5300  * No Preamble
5301  * With NPRE=1 the preamble generation is suppressed and frames are initiated with
5302  * Start of Frame pattern directly. Suitable in case that all connected PHYs accept
5303  * management frames without a preamble pattern. Recommended to be used if only
5304  * one PHY is connected.
5305  */
5306 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK (0x8000U)
5307 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT (15U)
5308 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK)
5309 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_NPRE_SHIFT)
5310 
5311 /*
5312  * ENABLE (R/W)
5313  *
5314  * Enable the MDIO controller. If the controller is enabled then MDC will be toggled.
5315  * ENABLE can only be read as 1 if a valid MDC_CLKDIV value is set.
5316  */
5317 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK (0x100U)
5318 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT (8U)
5319 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK)
5320 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_ENABLE_SHIFT)
5321 
5322 /*
5323  * MDC_CLKDIV (R/W)
5324  *
5325  * Clock Divider to configure MDC clock frequency. Refer to 10.1 Clock Divider for more
5326  * details.
5327  */
5328 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK (0xFFU)
5329 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT (0U)
5330 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK)
5331 #define TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CFG_MDC_CLKDIV_SHIFT)
5332 
5333 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_CTRL */
5334 /*
5335  * OP (R/W)
5336  *
5337  * Opcode to determine transfer type
5338  * 01 – Write Access
5339  * 10 – Read Access
5340  */
5341 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK (0xC0000000UL)
5342 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT (30U)
5343 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK)
5344 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_OP_SHIFT)
5345 
5346 /*
5347  * PHYAD (R/W)
5348  *
5349  * Management Frame PHY Address.
5350  */
5351 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK (0x1F000000UL)
5352 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT (24U)
5353 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK)
5354 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_PHYAD_SHIFT)
5355 
5356 /*
5357  * REGAD (R/W)
5358  *
5359  * Management Frame Register Address.
5360  */
5361 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK (0x1F0000UL)
5362 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT (16U)
5363 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK)
5364 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_REGAD_SHIFT)
5365 
5366 /*
5367  * INIT (R/W)
5368  *
5369  * INIT=1 results in a MDIO write/read transfer if READY=1. If READY=0 while a
5370  * transfer is already pending or if ENABLE=0 then settings INIT=1 has no effect and
5371  * the current transaction is withdrawn.
5372  */
5373 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK (0x100U)
5374 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT (8U)
5375 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK)
5376 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_INIT_SHIFT)
5377 
5378 /*
5379  * READY (R)
5380  *
5381  * READY=1 indicates a finished transfer and also shows that the controller is ready for a
5382  * new transfer. READY=1 is only possible if ENABLE=1.
5383  * If READY=1 is signaled after a read transfer, then RD_DATA is valid until a new
5384  * transfer is started.
5385  */
5386 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK (0x1U)
5387 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT (0U)
5388 #define TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_CTRL_READY_SHIFT)
5389 
5390 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_RD_DATA */
5391 /*
5392  * RD_DATA (R)
5393  *
5394  * Read Data is available if READY=1 after a transfer has been started. RD_DATA represents the content of the management data field of the read transfer.
5395  */
5396 #define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK (0xFFFFU)
5397 #define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT (0U)
5398 #define TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_RD_DATA_RD_DATA_SHIFT)
5399 
5400 /* Bitfield definition for register of struct array TSNPORT: MAC_MDIO_WR_DATA */
5401 /*
5402  * WR_DATA (R/W)
5403  *
5404  * Data is used for the management data field after a write transfer has been started
5405  */
5406 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK (0xFFFFU)
5407 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT (0U)
5408 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK)
5409 #define TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_MASK) >> TSW_TSNPORT_MAC_MAC_MDIO_WR_DATA_WR_DATA_SHIFT)
5410 
5411 /* Bitfield definition for register of struct array TSNPORT: MAC_IRQ_CTRL */
5412 /*
5413  * CAIF (R/W)
5414  *
5415  * Clock activity interrupt flag
5416  * 0 – no interrupt
5417  * 1 – interrupt pending
5418  * See Chapter 11.2.3 for details.
5419  */
5420 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK (0x800U)
5421 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT (11U)
5422 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK)
5423 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIF_SHIFT)
5424 
5425 /*
5426  * SWIF (R/W)
5427  *
5428  * Safety warning interrupt flag
5429  * 0 – no interrupt
5430  * 1 – interrupt pending
5431  * See Chapter 11.2.2 for details
5432  */
5433 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK (0x400U)
5434 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT (10U)
5435 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK)
5436 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIF_SHIFT)
5437 
5438 /*
5439  * SEIF (R/W)
5440  *
5441  * Safety Error Interrupt Flag
5442  * 0 – no interrupt
5443  * 1 – interrupt pending
5444  * If SEN=1 and if there is a mismatch between both instances of the logic core of
5445  * LLEMAC-1G then this results in SEIF=1, TX_EN=0 and RX_EN=0.
5446  */
5447 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK (0x200U)
5448 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT (9U)
5449 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK)
5450 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SEIF_SHIFT)
5451 
5452 /*
5453  * MDIF (R/W)
5454  *
5455  * MDIO Interrupt Flag
5456  * 1 – A transfer has been finished
5457  * 0 – No transfer done
5458  */
5459 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK (0x100U)
5460 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT (8U)
5461 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK)
5462 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIF_SHIFT)
5463 
5464 /*
5465  * CAIE (R/W)
5466  *
5467  * Clock activity interrupt enable
5468  * 0 – CAIF disabled
5469  * 1 – CAIF enabled
5470  */
5471 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK (0x8U)
5472 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT (3U)
5473 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK)
5474 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_CAIE_SHIFT)
5475 
5476 /*
5477  * SWIE (R/W)
5478  *
5479  * Safety warning interrupt enable
5480  * 0 – SWIF disabled
5481  * 1 – SWIF enabled
5482  */
5483 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK (0x4U)
5484 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT (2U)
5485 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK)
5486 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_SWIE_SHIFT)
5487 
5488 /*
5489  * MDIE (R/W)
5490  *
5491  * MDIO Interrupt Enable
5492  * 0 – Disabled
5493  * 1 – Enabled
5494  */
5495 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK (0x1U)
5496 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT (0U)
5497 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK)
5498 #define TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_MASK) >> TSW_TSNPORT_MAC_MAC_IRQ_CTRL_MDIE_SHIFT)
5499 
5500 /* Bitfield definition for register of struct array TSNPORT: RTC_CR */
5501 /*
5502  * TAIE (R/W)
5503  *
5504  * Timer A interrupt enable: interrupt enabled when 1
5505  */
5506 #define TSW_TSNPORT_RTC_CR_TAIE_MASK (0x8U)
5507 #define TSW_TSNPORT_RTC_CR_TAIE_SHIFT (3U)
5508 #define TSW_TSNPORT_RTC_CR_TAIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAIE_SHIFT) & TSW_TSNPORT_RTC_CR_TAIE_MASK)
5509 #define TSW_TSNPORT_RTC_CR_TAIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAIE_MASK) >> TSW_TSNPORT_RTC_CR_TAIE_SHIFT)
5510 
5511 /*
5512  * TAEN (R/W)
5513  *
5514  * Timer A enable: timer enabled when 1
5515  */
5516 #define TSW_TSNPORT_RTC_CR_TAEN_MASK (0x4U)
5517 #define TSW_TSNPORT_RTC_CR_TAEN_SHIFT (2U)
5518 #define TSW_TSNPORT_RTC_CR_TAEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_TAEN_SHIFT) & TSW_TSNPORT_RTC_CR_TAEN_MASK)
5519 #define TSW_TSNPORT_RTC_CR_TAEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_TAEN_MASK) >> TSW_TSNPORT_RTC_CR_TAEN_SHIFT)
5520 
5521 /*
5522  * ALIE (R/W)
5523  *
5524  * Alarm interrupt enable: alarm interrupt enabled when 1
5525  */
5526 #define TSW_TSNPORT_RTC_CR_ALIE_MASK (0x2U)
5527 #define TSW_TSNPORT_RTC_CR_ALIE_SHIFT (1U)
5528 #define TSW_TSNPORT_RTC_CR_ALIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CR_ALIE_SHIFT) & TSW_TSNPORT_RTC_CR_ALIE_MASK)
5529 #define TSW_TSNPORT_RTC_CR_ALIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CR_ALIE_MASK) >> TSW_TSNPORT_RTC_CR_ALIE_SHIFT)
5530 
5531 /* Bitfield definition for register of struct array TSNPORT: RTC_SR */
5532 /*
5533  * TAIS (R/WC)
5534  *
5535  * Timer A Interrupt Status: set at rising edge of “timer_clk_a”, write 1 to clear
5536  */
5537 #define TSW_TSNPORT_RTC_SR_TAIS_MASK (0x8U)
5538 #define TSW_TSNPORT_RTC_SR_TAIS_SHIFT (3U)
5539 #define TSW_TSNPORT_RTC_SR_TAIS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_SR_TAIS_SHIFT) & TSW_TSNPORT_RTC_SR_TAIS_MASK)
5540 #define TSW_TSNPORT_RTC_SR_TAIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_TAIS_MASK) >> TSW_TSNPORT_RTC_SR_TAIS_SHIFT)
5541 
5542 /*
5543  * ALIS (RO)
5544  *
5545  * ALIS ro Alarm Interrupt Status: Always set while RTC-Time >= Alarm-Time
5546  */
5547 #define TSW_TSNPORT_RTC_SR_ALIS_MASK (0x2U)
5548 #define TSW_TSNPORT_RTC_SR_ALIS_SHIFT (1U)
5549 #define TSW_TSNPORT_RTC_SR_ALIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_SR_ALIS_MASK) >> TSW_TSNPORT_RTC_SR_ALIS_SHIFT)
5550 
5551 /* Bitfield definition for register of struct array TSNPORT: RTC_CT_CURTIME_NS */
5552 /*
5553  * CT_NS (RO/WU)
5554  *
5555  * Local Time (nanosecond part): Update can be triggered by write access to this register. Value range from 0 – 999999999.
5556  */
5557 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK (0x3FFFFFFFUL)
5558 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT (0U)
5559 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK)
5560 #define TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_NS_CT_NS_SHIFT)
5561 
5562 /* Bitfield definition for register of struct array TSNPORT: RTC_CT_CURTIME_SEC */
5563 /*
5564  * CT_SEC (RO)
5565  *
5566  * Current Time (second part): Update can be triggered by write access to register CURTIME_NS.
5567  */
5568 #define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK (0xFFFFFFFFUL)
5569 #define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT (0U)
5570 #define TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_MASK) >> TSW_TSNPORT_RTC_CT_CURTIME_SEC_CT_SEC_SHIFT)
5571 
5572 /* Bitfield definition for register of struct array TSNPORT: RTC_CT_TIMER_INCR */
5573 /*
5574  * NS (RW)
5575  *
5576  * Local time increment – nanoseconds (integer)
5577  */
5578 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK (0xFF000000UL)
5579 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT (24U)
5580 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK)
5581 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_NS_SHIFT)
5582 
5583 /*
5584  * FNS (RW)
5585  *
5586  * Local time increment – fractional ns, unsigned, in (1 / 2^24) n
5587  */
5588 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK (0xFFFFFFUL)
5589 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT (0U)
5590 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK)
5591 #define TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_MASK) >> TSW_TSNPORT_RTC_CT_TIMER_INCR_FNS_SHIFT)
5592 
5593 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_NS */
5594 /*
5595  * OFS_NS (R/W)
5596  *
5597  * Real Time Offset (nanoseconds part). Valid value range from 0 – 999999999.
5598  */
5599 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK (0x3FFFFFFFUL)
5600 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT (0U)
5601 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK)
5602 #define TSW_TSNPORT_RTC_OFS_NS_OFS_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_NS_OFS_NS_MASK) >> TSW_TSNPORT_RTC_OFS_NS_OFS_NS_SHIFT)
5603 
5604 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_SL */
5605 /*
5606  * OFS_SL (R/W)
5607  *
5608  * 48 Bit Real Time Offset (seconds lo part)
5609  */
5610 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK (0xFFFFFFFFUL)
5611 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT (0U)
5612 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK)
5613 #define TSW_TSNPORT_RTC_OFS_SL_OFS_SL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SL_OFS_SL_MASK) >> TSW_TSNPORT_RTC_OFS_SL_OFS_SL_SHIFT)
5614 
5615 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_SH */
5616 /*
5617  * OFS_SH (R/W)
5618  *
5619  * 48 Bit Real Time Offset (seconds hi part)
5620  */
5621 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK (0xFFFFU)
5622 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT (0U)
5623 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK)
5624 #define TSW_TSNPORT_RTC_OFS_SH_OFS_SH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_SH_OFS_SH_MASK) >> TSW_TSNPORT_RTC_OFS_SH_OFS_SH_SHIFT)
5625 
5626 /* Bitfield definition for register of struct array TSNPORT: RTC_OFS_CH */
5627 /*
5628  * SEXT (RO)
5629  *
5630  * Real Time Offset Change – sign extension of SFNS (Bit 23)
5631  */
5632 #define TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK (0xFF000000UL)
5633 #define TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT (24U)
5634 #define TSW_TSNPORT_RTC_OFS_CH_SEXT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SEXT_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SEXT_SHIFT)
5635 
5636 /*
5637  * SFNS (R/W)
5638  *
5639  * Real Time Offset Change in fractional nanoseconds, signed value; value range from -2^23 / 2^24 to (2^23-1) / 2^24 nanoseconds.
5640  */
5641 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK (0xFFFFFFUL)
5642 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT (0U)
5643 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK)
5644 #define TSW_TSNPORT_RTC_OFS_CH_SFNS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_OFS_CH_SFNS_MASK) >> TSW_TSNPORT_RTC_OFS_CH_SFNS_SHIFT)
5645 
5646 /* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_NS */
5647 /*
5648  * AL_NS (R/W)
5649  *
5650  * Alarm Time (nanoseconds part). Valid value range from 0 – 999999999.
5651  */
5652 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK (0x3FFFFFFFUL)
5653 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT (0U)
5654 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK)
5655 #define TSW_TSNPORT_RTC_ALARM_NS_AL_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_NS_AL_NS_MASK) >> TSW_TSNPORT_RTC_ALARM_NS_AL_NS_SHIFT)
5656 
5657 /* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_SL */
5658 /*
5659  * AL_SL (R/W)
5660  *
5661  * Alarm Time (seconds lo part)
5662  */
5663 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK (0xFFFFFFFFUL)
5664 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT (0U)
5665 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK)
5666 #define TSW_TSNPORT_RTC_ALARM_SL_AL_SL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SL_AL_SL_MASK) >> TSW_TSNPORT_RTC_ALARM_SL_AL_SL_SHIFT)
5667 
5668 /* Bitfield definition for register of struct array TSNPORT: RTC_ALARM_SH */
5669 /*
5670  * AL_SH (R/W)
5671  *
5672  * Alarm Time (seconds hi part)
5673  */
5674 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK (0xFFFFU)
5675 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT (0U)
5676 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK)
5677 #define TSW_TSNPORT_RTC_ALARM_SH_AL_SH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_ALARM_SH_AL_SH_MASK) >> TSW_TSNPORT_RTC_ALARM_SH_AL_SH_SHIFT)
5678 
5679 /* Bitfield definition for register of struct array TSNPORT: RTC_TIMER_A_PERIOD */
5680 /*
5681  * PERIOD_NS (R/W)
5682  *
5683  * Timer A Period in ns. This is the period of the timer until the next event, but the half-period of the signal “timer_a_clk”.
5684  */
5685 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK (0x1FFFFFFFUL)
5686 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT (0U)
5687 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK)
5688 #define TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_MASK) >> TSW_TSNPORT_RTC_TIMER_A_PERIOD_PERIOD_NS_SHIFT)
5689 
5690 /* Bitfield definition for register of struct array TSNPORT: TSYN_CR */
5691 /*
5692  * TMR_ALD (R/W)
5693  *
5694  * Timer Auto Load: automatic reloading of timer when reaching 0. Done flag stays set after countdown. Used for periodic events, when following event shall not be delayed by host interaction.
5695  */
5696 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK (0x1F0000UL)
5697 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT (16U)
5698 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK)
5699 #define TSW_TSNPORT_TSYN_CR_TMR_ALD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_ALD_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_ALD_SHIFT)
5700 
5701 /*
5702  * TMR_EN (R/W)
5703  *
5704  * Timer Enable: every bit corresponds to Timer 0 – 4
5705  */
5706 #define TSW_TSNPORT_TSYN_CR_TMR_EN_MASK (0x1F00U)
5707 #define TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT (8U)
5708 #define TSW_TSNPORT_TSYN_CR_TMR_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK)
5709 #define TSW_TSNPORT_TSYN_CR_TMR_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMR_EN_MASK) >> TSW_TSNPORT_TSYN_CR_TMR_EN_SHIFT)
5710 
5711 /*
5712  * TMRIE (R/W)
5713  *
5714  * Timer Interrupt Enable
5715  */
5716 #define TSW_TSNPORT_TSYN_CR_TMRIE_MASK (0x4U)
5717 #define TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT (2U)
5718 #define TSW_TSNPORT_TSYN_CR_TMRIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK)
5719 #define TSW_TSNPORT_TSYN_CR_TMRIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TMRIE_MASK) >> TSW_TSNPORT_TSYN_CR_TMRIE_SHIFT)
5720 
5721 /*
5722  * RXIE (R/W)
5723  *
5724  * Rx Interrupt Enable
5725  */
5726 #define TSW_TSNPORT_TSYN_CR_RXIE_MASK (0x2U)
5727 #define TSW_TSNPORT_TSYN_CR_RXIE_SHIFT (1U)
5728 #define TSW_TSNPORT_TSYN_CR_RXIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_RXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_RXIE_MASK)
5729 #define TSW_TSNPORT_TSYN_CR_RXIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_RXIE_MASK) >> TSW_TSNPORT_TSYN_CR_RXIE_SHIFT)
5730 
5731 /*
5732  * TXIE (R/W)
5733  *
5734  * Tx Interrupt Enable
5735  */
5736 #define TSW_TSNPORT_TSYN_CR_TXIE_MASK (0x1U)
5737 #define TSW_TSNPORT_TSYN_CR_TXIE_SHIFT (0U)
5738 #define TSW_TSNPORT_TSYN_CR_TXIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_CR_TXIE_SHIFT) & TSW_TSNPORT_TSYN_CR_TXIE_MASK)
5739 #define TSW_TSNPORT_TSYN_CR_TXIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_CR_TXIE_MASK) >> TSW_TSNPORT_TSYN_CR_TXIE_SHIFT)
5740 
5741 /* Bitfield definition for register of struct array TSNPORT: TSYN_SR */
5742 /*
5743  * TMR_DN (R/WC)
5744  *
5745  * Timer Done: 1 when timer reached 0
5746  */
5747 #define TSW_TSNPORT_TSYN_SR_TMR_DN_MASK (0x1F00U)
5748 #define TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT (8U)
5749 #define TSW_TSNPORT_TSYN_SR_TMR_DN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK)
5750 #define TSW_TSNPORT_TSYN_SR_TMR_DN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMR_DN_MASK) >> TSW_TSNPORT_TSYN_SR_TMR_DN_SHIFT)
5751 
5752 /*
5753  * TMRIS (RO)
5754  *
5755  * Timer Interrupt Status: OR’ed (TMR_DN AND TMR_EN) flags. 1 when timer is enabled and countdown is done
5756  */
5757 #define TSW_TSNPORT_TSYN_SR_TMRIS_MASK (0x4U)
5758 #define TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT (2U)
5759 #define TSW_TSNPORT_TSYN_SR_TMRIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TMRIS_MASK) >> TSW_TSNPORT_TSYN_SR_TMRIS_SHIFT)
5760 
5761 /*
5762  * RXIS (RO)
5763  *
5764  * Rx Interrupt Status, RX buffer data available equal to PTP_RX_STS.AV)
5765  */
5766 #define TSW_TSNPORT_TSYN_SR_RXIS_MASK (0x2U)
5767 #define TSW_TSNPORT_TSYN_SR_RXIS_SHIFT (1U)
5768 #define TSW_TSNPORT_TSYN_SR_RXIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_RXIS_MASK) >> TSW_TSNPORT_TSYN_SR_RXIS_SHIFT)
5769 
5770 /*
5771  * TXIS (RO)
5772  *
5773  * Tx Done Interrupt Status: OR’ed PTP_TX_DONE
5774  */
5775 #define TSW_TSNPORT_TSYN_SR_TXIS_MASK (0x1U)
5776 #define TSW_TSNPORT_TSYN_SR_TXIS_SHIFT (0U)
5777 #define TSW_TSNPORT_TSYN_SR_TXIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_SR_TXIS_MASK) >> TSW_TSNPORT_TSYN_SR_TXIS_SHIFT)
5778 
5779 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_STS */
5780 /*
5781  * STS (RO)
5782  *
5783  * Transmission status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission pending
5784  */
5785 #define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK (0xFFU)
5786 #define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT (0U)
5787 #define TSW_TSNPORT_TSYN_PTP_TX_STS_STS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_STS_STS_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_STS_STS_SHIFT)
5788 
5789 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_DONE */
5790 /*
5791  * DONE (R/WC)
5792  *
5793  * Transmission done status of PTP TX bin n (bit 0 – 7 correspond to tx bin 0 – 7). 1: transmission done.
5794  * Writing a ‘1’ clears corresponding bit..
5795  */
5796 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK (0xFFU)
5797 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT (0U)
5798 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK)
5799 #define TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_DONE_DONE_SHIFT)
5800 
5801 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_TX_TRIG */
5802 /*
5803  * TRIG (WO)
5804  *
5805  * Trigger PTP TX bin n (bit 0 – 7 correspond to tx bin 0 –7). Writing ‘1’ will trigger transmission. Corresponding bit PTP_TX_STS.STS(n) will be set immediately.
5806  */
5807 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK (0xFFU)
5808 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT (0U)
5809 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK)
5810 #define TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_MASK) >> TSW_TSNPORT_TSYN_PTP_TX_TRIG_TRIG_SHIFT)
5811 
5812 /* Bitfield definition for register of struct array TSNPORT: TSYN_PTP_RX_STS */
5813 /*
5814  * OV (R/WC)
5815  *
5816  * FIFO overflow flag. PTP frame has been received and there was no free buffer available. Data has been lost.
5817  */
5818 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK (0x80000000UL)
5819 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT (31U)
5820 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK)
5821 #define TSW_TSNPORT_TSYN_PTP_RX_STS_OV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_OV_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_OV_SHIFT)
5822 
5823 /*
5824  * AV_NXT (R/W)
5825  *
5826  * Read access: buffer data available – reading data from RX_BUF is valid.
5827  * Write access: switch to next RX buffer – shall only be done when buffer not empty (AV=1). Use field RX_SEL as indication when rx buffer switch has been done.
5828  */
5829 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK (0x40000000UL)
5830 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT (30U)
5831 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK)
5832 #define TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_AV_NXT_SHIFT)
5833 
5834 /*
5835  * RX_SEL (RO)
5836  *
5837  * Current selected RX buffer for reading (0-7). Can be used to determine when RX buffer has been switched after setting PTP_RX_STS.NXT
5838  */
5839 #define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK (0x7U)
5840 #define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT (0U)
5841 #define TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_MASK) >> TSW_TSNPORT_TSYN_PTP_RX_STS_RX_SEL_SHIFT)
5842 
5843 /* Bitfield definition for register of struct array TSNPORT: TSYN_TMR0 */
5844 /*
5845  * PERIOD (R/W)
5846  *
5847  * Period in ticks, ticks based on register HCLKDIV and host clock <sys_clk>.
5848  */
5849 #define TSW_TSNPORT_TSYNTMR_PERIOD_MASK (0xFFFFFUL)
5850 #define TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT (0U)
5851 #define TSW_TSNPORT_TSYNTMR_PERIOD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK)
5852 #define TSW_TSNPORT_TSYNTMR_PERIOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYNTMR_PERIOD_MASK) >> TSW_TSNPORT_TSYNTMR_PERIOD_SHIFT)
5853 
5854 /* Bitfield definition for register of struct array TSNPORT: TSYN_HCLKDIV */
5855 /*
5856  * PERIOD (R/W)
5857  *
5858  * Period in host clocks <sys_clk>. Host clock shall be scaled to ticks of 1/1024th second. Ticks are used by timer TMR0 – TMR4.
5859  */
5860 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK (0xFFFFFUL)
5861 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT (0U)
5862 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK)
5863 #define TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_MASK) >> TSW_TSNPORT_TSYN_HCLKDIV_PERIOD_SHIFT)
5864 
5865 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_FRAME_LENGTH_BYTES */
5866 /*
5867  * RX_FRAME_LENGTH_BYTES (RO)
5868  *
5869  * RX frame length bytes [11:0]
5870  */
5871 #define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK (0xFFFU)
5872 #define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT (0U)
5873 #define TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_FRAME_LENGTH_BYTES_RX_FRAME_LENGTH_BYTES_SHIFT)
5874 
5875 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_TIME_STAMP_L */
5876 /*
5877  * RX_TIMESTAMP_LOW (RO)
5878  *
5879  * RX Timestamp [31:0]
5880  */
5881 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK (0xFFFFFFFFUL)
5882 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT (0U)
5883 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_L_RX_TIMESTAMP_LOW_SHIFT)
5884 
5885 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_RX_TIME_STAMP_H */
5886 /*
5887  * RX_TIMESTAMP_HIGH (RO)
5888  *
5889  * RX Timestamp [63:32]
5890  */
5891 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK (0xFFFFFFFFUL)
5892 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT (0U)
5893 #define TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_MASK) >> TSW_TSNPORT_TSYN_RXBUF_RX_TIME_STAMP_H_RX_TIMESTAMP_HIGH_SHIFT)
5894 
5895 /* Bitfield definition for register of struct array TSNPORT: TSYN_RXBUF_DATA_WORD0 */
5896 /*
5897  * RXBUF_DATA_WORD (RO)
5898  *
5899  * RXBUF_DATA_WORD
5900  */
5901 #define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK (0xFFFFFFFFUL)
5902 #define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT (0U)
5903 #define TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_MASK) >> TSW_TSNPORT_RXDATA_RXBUF_DATA_WORD_SHIFT)
5904 
5905 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_BIN0_DATA_WORD0 */
5906 /*
5907  * TXBUF_DATA (WO)
5908  *
5909  * TXBUF_DATA
5910  */
5911 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK (0xFFFFFFFFUL)
5912 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT (0U)
5913 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK)
5914 #define TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_MASK) >> TSW_TSNPORT_BIN_TXDATA_TXBUF_DATA_SHIFT)
5915 
5916 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_TQUE_AND_TX_LEN */
5917 /*
5918  * TXBUF_TQUE (WO)
5919  *
5920  * TXBUF_TQUE
5921  */
5922 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK (0x7000000UL)
5923 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT (24U)
5924 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK)
5925 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TQUE_SHIFT)
5926 
5927 /*
5928  * TXBUF_TX_LEN (WO)
5929  *
5930  * TXBUF_TX_LEN
5931  */
5932 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK (0xFFU)
5933 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT (0U)
5934 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK)
5935 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TQUE_AND_TX_LEN_TXBUF_TX_LEN_SHIFT)
5936 
5937 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_TX_TIMESTAMP_L */
5938 /*
5939  * TXBUF_TX_TIMESTAMP_L (RO)
5940  *
5941  * TXBUF_TX_TIMESTAMP_L
5942  */
5943 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK (0xFFFFFFFFUL)
5944 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT (0U)
5945 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_L_TXBUF_TX_TIMESTAMP_L_SHIFT)
5946 
5947 /* Bitfield definition for register of struct array TSNPORT: TSYN_TXBUF_TX_TIMESTAMP_H */
5948 /*
5949  * TXBUF_TX_TIMESTAMP_H (RO)
5950  *
5951  * TXBUF_TX_TIMESTAMP_H
5952  */
5953 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK (0xFFFFFFFFUL)
5954 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT (0U)
5955 #define TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_MASK) >> TSW_TSNPORT_BIN_TSYN_TXBUF_TX_TIMESTAMP_H_TXBUF_TX_TIMESTAMP_H_SHIFT)
5956 
5957 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_HWCFG1 */
5958 /*
5959  * LWIDTH (RO)
5960  *
5961  * Scheduler list address width (IP core parameter LWIDTH)
5962  */
5963 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK (0xFF000000UL)
5964 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT (24U)
5965 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_LWIDTH_SHIFT)
5966 
5967 /*
5968  * TQC (RO)
5969  *
5970  * Traffic queue count (IP core parameter TQC)
5971  */
5972 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK (0xFF0000UL)
5973 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT (16U)
5974 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQC_SHIFT)
5975 
5976 /*
5977  * TQD (RO)
5978  *
5979  * Traffic queue depth (IP core parameter TQD)
5980  */
5981 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK (0xFF00U)
5982 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT (8U)
5983 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_TQD_SHIFT)
5984 
5985 /*
5986  * DW (RO)
5987  *
5988  * Traffic queue data width (Bytes); fixed to value 4 within
5989  * IP core
5990  */
5991 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK (0xFFU)
5992 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT (0U)
5993 #define TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_MASK) >> TSW_TSNPORT_TSN_SHAPER_HWCFG1_DW_SHIFT)
5994 
5995 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TQAV */
5996 /*
5997  * AVIE (R/W)
5998  *
5999  * Traffic queue interrupt enable on buffer space available,
6000  * one bit per traffic queue
6001  * Bit[i] = 0: no interrupt
6002  * Bit[i] = 1: interrupt, when AVAIL[i]=1
6003  */
6004 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK (0xFF00U)
6005 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT (8U)
6006 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK)
6007 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVIE_SHIFT)
6008 
6009 /*
6010  * AVAIL (RO)
6011  *
6012  * Traffic queue buffer space available for complete packet of size MaxSDU (register MXSDUi)
6013  * Bit[i] = 1: space available
6014  * Bit[i] = 0: no space available or TQ not implemented (I >= TQC)
6015  */
6016 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK (0xFFU)
6017 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT (0U)
6018 #define TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQAV_AVAIL_SHIFT)
6019 
6020 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TQEM */
6021 /*
6022  * EMPTY (RO)
6023  *
6024  * Traffic queue empty
6025  * Bit[i] = 1: traffic queue i is empty
6026  */
6027 #define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK (0xFFU)
6028 #define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT (0U)
6029 #define TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_MASK) >> TSW_TSNPORT_TSN_SHAPER_TQEM_EMPTY_SHIFT)
6030 
6031 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_FPST */
6032 /*
6033  * TABLE (R/W)
6034  *
6035  * Frame Preemption Status Table,
6036  * Bit[i] = 1: Preemptable traffic in TQ[i], otherwise
6037  * Express traffic (default)
6038  */
6039 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK (0xFFU)
6040 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT (0U)
6041 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK)
6042 #define TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_MASK) >> TSW_TSNPORT_TSN_SHAPER_FPST_TABLE_SHIFT)
6043 
6044 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MMCT */
6045 /*
6046  * RQREL (R/W)
6047  *
6048  * Request HOLD-Signal release operation. Will be automatically set to <0>
6049  */
6050 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK (0x2U)
6051 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT (1U)
6052 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK)
6053 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQREL_SHIFT)
6054 
6055 /*
6056  * RQHLD (R/W)
6057  *
6058  * Request HOLD-Signal hold operation. Will be automatically set to <0>.
6059  */
6060 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK (0x1U)
6061 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT (0U)
6062 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK)
6063 #define TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_MASK) >> TSW_TSNPORT_TSN_SHAPER_MMCT_RQHLD_SHIFT)
6064 
6065 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_HOLDADV */
6066 /*
6067  * VALUE (R/W)
6068  *
6069  * holdAdvance time for TAS operation Set-And-Hold-MAC in <sys_clk> cycles
6070  */
6071 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK (0xFFFFU)
6072 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT (0U)
6073 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK)
6074 #define TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_MASK) >> TSW_TSNPORT_TSN_SHAPER_HOLDADV_VALUE_SHIFT)
6075 
6076 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MXSDU0 */
6077 /*
6078  * SDU (R/W)
6079  *
6080  * Maximum SDU size for traffic queue n (n = 0 – 7)Returns 0 when n > TQC. Value is size in words (32 bit word size).
6081  */
6082 #define TSW_TSNPORT_MXSDU_SDU_MASK (0xFFFFU)
6083 #define TSW_TSNPORT_MXSDU_SDU_SHIFT (0U)
6084 #define TSW_TSNPORT_MXSDU_SDU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MXSDU_SDU_SHIFT) & TSW_TSNPORT_MXSDU_SDU_MASK)
6085 #define TSW_TSNPORT_MXSDU_SDU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MXSDU_SDU_MASK) >> TSW_TSNPORT_MXSDU_SDU_SHIFT)
6086 
6087 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TXSEL0 */
6088 /*
6089  * CBS_EN (R/W)
6090  *
6091  * CBS enable traffic queue n (n = 0 – 7). Returns 0 when n > TQC. Must be 0 when changing register IDSLPi.
6092  */
6093 #define TSW_TSNPORT_TXSEL_CBS_EN_MASK (0x1U)
6094 #define TSW_TSNPORT_TXSEL_CBS_EN_SHIFT (0U)
6095 #define TSW_TSNPORT_TXSEL_CBS_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TXSEL_CBS_EN_SHIFT) & TSW_TSNPORT_TXSEL_CBS_EN_MASK)
6096 #define TSW_TSNPORT_TXSEL_CBS_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TXSEL_CBS_EN_MASK) >> TSW_TSNPORT_TXSEL_CBS_EN_SHIFT)
6097 
6098 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_IDSEL0 */
6099 /*
6100  * INT (R/W)
6101  *
6102  * CBS idle slope for traffic queue n (n = 0 – 7). Returns
6103  * 0 when n > TQC. The register must only be written
6104  * when TXSELi.CBE_EN=0.
6105  * The idle slope value is defined as (INT + FRACT /
6106  * 65536). The idle slope is set in bits per tick related to
6107  * <tx_clk>.
6108  */
6109 #define TSW_TSNPORT_IDSEL_INT_MASK (0xF0000UL)
6110 #define TSW_TSNPORT_IDSEL_INT_SHIFT (16U)
6111 #define TSW_TSNPORT_IDSEL_INT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_IDSEL_INT_SHIFT) & TSW_TSNPORT_IDSEL_INT_MASK)
6112 #define TSW_TSNPORT_IDSEL_INT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_IDSEL_INT_MASK) >> TSW_TSNPORT_IDSEL_INT_SHIFT)
6113 
6114 /*
6115  * FRACT (R/W)
6116  *
6117  */
6118 #define TSW_TSNPORT_IDSEL_FRACT_MASK (0xFFFFU)
6119 #define TSW_TSNPORT_IDSEL_FRACT_SHIFT (0U)
6120 #define TSW_TSNPORT_IDSEL_FRACT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_IDSEL_FRACT_SHIFT) & TSW_TSNPORT_IDSEL_FRACT_MASK)
6121 #define TSW_TSNPORT_IDSEL_FRACT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_IDSEL_FRACT_MASK) >> TSW_TSNPORT_IDSEL_FRACT_SHIFT)
6122 
6123 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH0_CFG */
6124 /*
6125  * CQF_IN_ERR (WC)
6126  *
6127  * qch queue in error
6128  */
6129 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK (0x100000UL)
6130 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT (20U)
6131 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK)
6132 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_IN_ERR_SHIFT)
6133 
6134 /*
6135  * CQF_NUM (R/W)
6136  *
6137  * qch queue destination buffer select
6138  */
6139 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK (0x70000UL)
6140 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT (16U)
6141 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK)
6142 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_NUM_SHIFT)
6143 
6144 /*
6145  * TAS_GPIO_SEL (R/W)
6146  *
6147  * tas_gpio select
6148  */
6149 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6150 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT (12U)
6151 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK)
6152 #define TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_TAS_GPIO_SEL_SHIFT)
6153 
6154 /*
6155  * AXIS_QCH_EN (R/W)
6156  *
6157  * qch queue in select
6158  */
6159 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6160 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT (4U)
6161 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK)
6162 #define TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_AXIS_QCH_EN_SHIFT)
6163 
6164 /*
6165  * CQF_EN (R/W)
6166  *
6167  * qch enable
6168  */
6169 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK (0x1U)
6170 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT (0U)
6171 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK)
6172 #define TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH0_CFG_CQF_EN_SHIFT)
6173 
6174 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH1_CFG */
6175 /*
6176  * CQF_IN_ERR (WC)
6177  *
6178  * qch queue in error
6179  */
6180 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK (0x100000UL)
6181 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT (20U)
6182 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK)
6183 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_IN_ERR_SHIFT)
6184 
6185 /*
6186  * CQF_NUM (R/W)
6187  *
6188  * qch queue destination buffer select
6189  */
6190 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK (0x70000UL)
6191 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT (16U)
6192 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK)
6193 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_NUM_SHIFT)
6194 
6195 /*
6196  * TAS_GPIO_SEL (R/W)
6197  *
6198  * tas_gpio select
6199  */
6200 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6201 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT (12U)
6202 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK)
6203 #define TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_TAS_GPIO_SEL_SHIFT)
6204 
6205 /*
6206  * AXIS_QCH_EN (R/W)
6207  *
6208  * qch queue in select
6209  */
6210 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6211 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT (4U)
6212 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK)
6213 #define TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_AXIS_QCH_EN_SHIFT)
6214 
6215 /*
6216  * CQF_EN (R/W)
6217  *
6218  * qch enable
6219  */
6220 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK (0x1U)
6221 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT (0U)
6222 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK)
6223 #define TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH1_CFG_CQF_EN_SHIFT)
6224 
6225 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH2_CFG */
6226 /*
6227  * CQF_IN_ERR (WC)
6228  *
6229  * qch queue in error
6230  */
6231 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK (0x100000UL)
6232 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT (20U)
6233 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK)
6234 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_IN_ERR_SHIFT)
6235 
6236 /*
6237  * CQF_NUM (R/W)
6238  *
6239  * qch queue destination buffer select
6240  */
6241 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK (0x70000UL)
6242 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT (16U)
6243 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK)
6244 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_NUM_SHIFT)
6245 
6246 /*
6247  * TAS_GPIO_SEL (R/W)
6248  *
6249  * tas_gpio select
6250  */
6251 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6252 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT (12U)
6253 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK)
6254 #define TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_TAS_GPIO_SEL_SHIFT)
6255 
6256 /*
6257  * AXIS_QCH_EN (R/W)
6258  *
6259  * qch queue in select
6260  */
6261 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6262 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT (4U)
6263 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK)
6264 #define TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_AXIS_QCH_EN_SHIFT)
6265 
6266 /*
6267  * CQF_EN (R/W)
6268  *
6269  * qch enable
6270  */
6271 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK (0x1U)
6272 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT (0U)
6273 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK)
6274 #define TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH2_CFG_CQF_EN_SHIFT)
6275 
6276 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH3_CFG */
6277 /*
6278  * CQF_IN_ERR (WC)
6279  *
6280  * qch queue in error
6281  */
6282 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK (0x100000UL)
6283 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT (20U)
6284 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK)
6285 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_IN_ERR_SHIFT)
6286 
6287 /*
6288  * CQF_NUM (R/W)
6289  *
6290  * qch queue destination buffer select
6291  */
6292 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK (0x70000UL)
6293 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT (16U)
6294 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK)
6295 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_NUM_SHIFT)
6296 
6297 /*
6298  * TAS_GPIO_SEL (R/W)
6299  *
6300  * tas_gpio select
6301  */
6302 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK (0x7000U)
6303 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT (12U)
6304 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK)
6305 #define TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_TAS_GPIO_SEL_SHIFT)
6306 
6307 /*
6308  * AXIS_QCH_EN (R/W)
6309  *
6310  * qch queue in select
6311  */
6312 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK (0xFF0U)
6313 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT (4U)
6314 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK)
6315 #define TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_AXIS_QCH_EN_SHIFT)
6316 
6317 /*
6318  * CQF_EN (R/W)
6319  *
6320  * qch enable
6321  */
6322 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK (0x1U)
6323 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT (0U)
6324 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK)
6325 #define TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_MASK) >> TSW_TSNPORT_PORT1_QCH3_CFG_CQF_EN_SHIFT)
6326 
6327 /* Bitfield definition for register of struct array TSNPORT: PORT1_QCH_ERR_CFG */
6328 /*
6329  * CQF_QUE_ERR (WC)
6330  *
6331  * que gate error for each cqf
6332  */
6333 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK (0xFF00U)
6334 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT (8U)
6335 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK)
6336 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_QUE_ERR_SHIFT)
6337 
6338 /*
6339  * CQF_NUM_CFG_ERR (RO)
6340  *
6341  * cqf_num config error
6342  */
6343 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK (0x4U)
6344 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT (2U)
6345 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_NUM_CFG_ERR_SHIFT)
6346 
6347 /*
6348  * AXIS_QCH_CFG_ERR (RO)
6349  *
6350  * axis_qch_en config error
6351  */
6352 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK (0x2U)
6353 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT (1U)
6354 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_AXIS_QCH_CFG_ERR_SHIFT)
6355 
6356 /*
6357  * CQF_CLR_CTRL (R/W)
6358  *
6359  * enable cqf buffer auto clear when error
6360  */
6361 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK (0x1U)
6362 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT (0U)
6363 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK)
6364 #define TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_MASK) >> TSW_TSNPORT_PORT1_QCH_ERR_CFG_CQF_CLR_CTRL_SHIFT)
6365 
6366 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_CRSR */
6367 /*
6368  * ADMINGS (RO)
6369  *
6370  * Admin gate states, fixed 0xFF. Gate states when TAS is disabled.
6371  */
6372 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK (0xFF000000UL)
6373 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT (24U)
6374 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_ADMINGS_SHIFT)
6375 
6376 /*
6377  * OPERGS (RO)
6378  *
6379  * Operational gate states of TQ[i] (i = 0 – TQC-1)
6380  * Bit[i]=0 – Gate is closed; no start of frame TX possible
6381  * Bit[i]=1 – Gate is open
6382  */
6383 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK (0xFF0000UL)
6384 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT (16U)
6385 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_OPERGS_SHIFT)
6386 
6387 /*
6388  * TAS_GPIO_STA (RO)
6389  *
6390  * operational tas gpio gate status of TQ[i]
6391  */
6392 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK (0xFF00U)
6393 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT (8U)
6394 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_TAS_GPIO_STA_SHIFT)
6395 
6396 /*
6397  * CFGPEND (RO)
6398  *
6399  * Configuration change is pending – Admin basetime not yet reached.
6400  */
6401 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK (0x8U)
6402 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT (3U)
6403 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGPEND_SHIFT)
6404 
6405 /*
6406  * CFGERR (R/WC)
6407  *
6408  * Configuration error.
6409  */
6410 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK (0x4U)
6411 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT (2U)
6412 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK)
6413 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGERR_SHIFT)
6414 
6415 /*
6416  * CFGCHG (R/W)
6417  *
6418  * Switch configuration; Bit is automatically reset to 0;
6419  * Setting Bit=1 triggers configuration change event.
6420  */
6421 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK (0x2U)
6422 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT (1U)
6423 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK)
6424 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_CFGCHG_SHIFT)
6425 
6426 /*
6427  * EN (R/W)
6428  *
6429  * Enable time aware scheduling.
6430  */
6431 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK (0x1U)
6432 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT (0U)
6433 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK)
6434 #define TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_CRSR_EN_SHIFT)
6435 
6436 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ACYCLETM */
6437 /*
6438  * CTIME (R/W)
6439  *
6440  * Admin cycletime in nanoseconds.
6441  */
6442 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK (0x3FFFFFFFUL)
6443 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT (0U)
6444 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK)
6445 #define TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ACYCLETM_CTIME_SHIFT)
6446 
6447 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ABASETM_L */
6448 /*
6449  * BASETM_L (R/W)
6450  *
6451  * Admin basetime – nanoseconds and seconds part.
6452  */
6453 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK (0x3FFFFFFFUL)
6454 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT (0U)
6455 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK)
6456 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_L_BASETM_L_SHIFT)
6457 
6458 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_ABASETM_H */
6459 /*
6460  * BASETM_H (R/W)
6461  *
6462  */
6463 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK (0xFFFFFFFFUL)
6464 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT (0U)
6465 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK)
6466 #define TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_ABASETM_H_BASETM_H_SHIFT)
6467 
6468 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_LISTLEN */
6469 /*
6470  * OLISTLEN (RO)
6471  *
6472  * Oper list length.
6473  */
6474 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK (0xFF0000UL)
6475 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT (16U)
6476 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_OLISTLEN_SHIFT)
6477 
6478 /*
6479  * ALISTLEN (R/W)
6480  *
6481  * Admin list length.
6482  */
6483 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK (0xFFU)
6484 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT (0U)
6485 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK)
6486 #define TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_LISTLEN_ALISTLEN_SHIFT)
6487 
6488 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OCYCLETM */
6489 /*
6490  * CTIME (RO)
6491  *
6492  * Operational cycletime in nanoseconds
6493  */
6494 #define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK (0x3FFFFFFFUL)
6495 #define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT (0U)
6496 #define TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OCYCLETM_CTIME_SHIFT)
6497 
6498 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OBASETM_L */
6499 /*
6500  * BASETM_L (RO)
6501  *
6502  * Operational basetime – nanoseconds and seconds part. The operational basetime might occasionally have a non-normalized value (ns >= 10^9) for one clock cycle.
6503  */
6504 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK (0xFFFFFFFFUL)
6505 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT (0U)
6506 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_L_BASETM_L_SHIFT)
6507 
6508 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TAS_OBASETM_H */
6509 /*
6510  * BASETM_H (RO)
6511  *
6512  */
6513 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK (0xFFFFFFFFUL)
6514 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT (0U)
6515 #define TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_MASK) >> TSW_TSNPORT_TSN_SHAPER_TAS_OBASETM_H_BASETM_H_SHIFT)
6516 
6517 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_MXTK0 */
6518 /*
6519  * TICK (R/W)
6520  *
6521  * Maximum SDU size in clock ticks. MXTKi is only supported when TQC > i, otherwise read-only with value 0
6522  */
6523 #define TSW_TSNPORT_MXTK_TICK_MASK (0xFFFFFFUL)
6524 #define TSW_TSNPORT_MXTK_TICK_SHIFT (0U)
6525 #define TSW_TSNPORT_MXTK_TICK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_MXTK_TICK_SHIFT) & TSW_TSNPORT_MXTK_TICK_MASK)
6526 #define TSW_TSNPORT_MXTK_TICK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MXTK_TICK_MASK) >> TSW_TSNPORT_MXTK_TICK_SHIFT)
6527 
6528 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_TXOV0 */
6529 /*
6530  * VALUE (R/WC)
6531  *
6532  * Transmission overrun counter; increments on transmission when gate is closed; any write access will clear register to 0. TXOVi is only supported when TQC > i.
6533  */
6534 #define TSW_TSNPORT_TXOV_VALUE_MASK (0xFFFFFFFFUL)
6535 #define TSW_TSNPORT_TXOV_VALUE_SHIFT (0U)
6536 #define TSW_TSNPORT_TXOV_VALUE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TXOV_VALUE_SHIFT) & TSW_TSNPORT_TXOV_VALUE_MASK)
6537 #define TSW_TSNPORT_TXOV_VALUE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TXOV_VALUE_MASK) >> TSW_TSNPORT_TXOV_VALUE_SHIFT)
6538 
6539 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_ACLIST_ENTRY_L */
6540 /*
6541  * TAS_GPIO (R/W)
6542  *
6543  * gate states for qch and ptp event source
6544  */
6545 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK (0x3FC00UL)
6546 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT (10U)
6547 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK)
6548 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_TAS_GPIO_SHIFT)
6549 
6550 /*
6551  * OP (R/W)
6552  *
6553  * gate operation:
6554  * 0 – SetGateStates
6555  * 1 – Set-And-Hold-MAC
6556  * 2 – Set-And-Release-MAC
6557  * 3 – undefined
6558  */
6559 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK (0x300U)
6560 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT (8U)
6561 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK)
6562 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_OP_SHIFT)
6563 
6564 /*
6565  * STATE (R/W)
6566  *
6567  * gate state vector;
6568  * 1 – Gate is open
6569  */
6570 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK (0xFFU)
6571 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT (0U)
6572 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK)
6573 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_L_STATE_SHIFT)
6574 
6575 /* Bitfield definition for register of struct array TSNPORT: TSN_SHAPER_ACLIST_ENTRY_H */
6576 /*
6577  * TIME (R/W)
6578  *
6579  * Time interval, entry execution in in host clock ticks (<sys_clk>)
6580  */
6581 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK (0xFFFFFFFFUL)
6582 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT (0U)
6583 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK)
6584 #define TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_MASK) >> TSW_TSNPORT_SHACL_TSN_SHAPER_ACLIST_ENTRY_H_TIME_SHIFT)
6585 
6586 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_VER */
6587 /*
6588  * VER_HI (RO)
6589  *
6590  * major version number
6591  */
6592 #define TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK (0xFF000000UL)
6593 #define TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT (24U)
6594 #define TSW_TSNPORT_TSN_EP_VER_VER_HI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_HI_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_HI_SHIFT)
6595 
6596 /*
6597  * VER_LO (RO)
6598  *
6599  * minor version number
6600  */
6601 #define TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK (0xFF0000UL)
6602 #define TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT (16U)
6603 #define TSW_TSNPORT_TSN_EP_VER_VER_LO_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_LO_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_LO_SHIFT)
6604 
6605 /*
6606  * VER_REV (RO)
6607  *
6608  * revision number
6609  */
6610 #define TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK (0xFFU)
6611 #define TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT (0U)
6612 #define TSW_TSNPORT_TSN_EP_VER_VER_REV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_VER_VER_REV_MASK) >> TSW_TSNPORT_TSN_EP_VER_VER_REV_SHIFT)
6613 
6614 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_CTRL */
6615 /*
6616  * FILTDIS (R/W)
6617  *
6618  * Disable filtering of PTP frames (Ethertype = 0x88F7)
6619  */
6620 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK (0x80000000UL)
6621 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT (31U)
6622 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK)
6623 #define TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_FILTDIS_SHIFT)
6624 
6625 /*
6626  * PTP_1S_EN (R/W)
6627  *
6628  * Enable PTPv2 1-step synchronization suppor
6629  */
6630 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK (0x40000000UL)
6631 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT (30U)
6632 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK)
6633 #define TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_PTP_1S_EN_SHIFT)
6634 
6635 /*
6636  * IE_TSF (R/W)
6637  *
6638  * TxTimestampFifo interrupt enable; interrupt will be set when IE_TSF=<1> and TSF_SR.USED>0
6639  */
6640 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK (0x1U)
6641 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT (0U)
6642 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK)
6643 #define TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_MASK) >> TSW_TSNPORT_TSN_EP_CTRL_IE_TSF_SHIFT)
6644 
6645 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TXUF */
6646 /*
6647  * COUNTER (R/WC)
6648  *
6649  * TX buffer underflow counter; incremented when any MAC runs out of data during transmission. The counter is cleared at any write access. The counter is shared by pMAC and eMAC. If underflow event occurs at the same time for pMAC and eMAC, it will be counted as one event.
6650  */
6651 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK (0xFFFFFFFFUL)
6652 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT (0U)
6653 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK)
6654 #define TSW_TSNPORT_TSN_EP_TXUF_COUNTER_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TXUF_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_TXUF_COUNTER_SHIFT)
6655 
6656 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_IPCFG */
6657 /*
6658  * INCL_RTC (RO)
6659  *
6660  * IP core parameter “INCL_RTC”
6661  */
6662 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK (0x80000000UL)
6663 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT (31U)
6664 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_RTC_SHIFT)
6665 
6666 /*
6667  * INCL_SHAP (RO)
6668  *
6669  * IP core parameter “INCL_SHAPER”
6670  */
6671 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK (0x40000000UL)
6672 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT (30U)
6673 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_SHAP_SHIFT)
6674 
6675 /*
6676  * INCL_FPE (RO)
6677  *
6678  * IP core parameter “INCL_FPE”
6679  */
6680 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK (0x20000000UL)
6681 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT (29U)
6682 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_FPE_SHIFT)
6683 
6684 /*
6685  * INCL_TSF (RO)
6686  *
6687  * IP core parameter “INCL_TSF”
6688  */
6689 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK (0x10000000UL)
6690 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT (28U)
6691 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSF_SHIFT)
6692 
6693 /*
6694  * INCL_TSYNC (RO)
6695  *
6696  * IP core parameter “INCL_TSYNC”
6697  */
6698 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK (0x8000000UL)
6699 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT (27U)
6700 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_TSYNC_SHIFT)
6701 
6702 /*
6703  * INCL_1STEP (RO)
6704  *
6705  * IP core parameter “INCL_1STEP”
6706  */
6707 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK (0x4000000UL)
6708 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT (26U)
6709 #define TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_MASK) >> TSW_TSNPORT_TSN_EP_IPCFG_INCL_1STEP_SHIFT)
6710 
6711 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D0 */
6712 /*
6713  * TSF_NS (RO)
6714  *
6715  * Tx-Timestamp-Fifo, lower 32 bit part of local time (<curtime>) at the start of transmission of the packet. Usually nanoseconds part when used with included RTC.
6716  */
6717 #define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK (0xFFFFFFFFUL)
6718 #define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT (0U)
6719 #define TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D0_TSF_NS_SHIFT)
6720 
6721 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D1 */
6722 /*
6723  * TSF_SEC (RO)
6724  *
6725  * Tx-Timestamp-Fifo, upper 32 bit part of the local time (<curtime>) at the start of the transmission of the packet. Usually seconds part when used with included RTC.
6726  */
6727 #define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK (0xFFFFFFFFUL)
6728 #define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT (0U)
6729 #define TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D1_TSF_SEC_SHIFT)
6730 
6731 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_D2 */
6732 /*
6733  * TSF_TQ (RO)
6734  *
6735  * Tx-Timestamp-Fifo, traffic queue <tx_tqueue> of sent packet
6736  */
6737 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK (0xE0000000UL)
6738 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT (29U)
6739 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_TQ_SHIFT)
6740 
6741 /*
6742  * TSF_USR (RO)
6743  *
6744  * Tx-Timestamp-Fifo, user sideband <tx_tuser> of sent packet; Note: any read to register will remove actual value from FIFO
6745  */
6746 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK (0x7U)
6747 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT (0U)
6748 #define TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_MASK) >> TSW_TSNPORT_TSN_EP_TSF_D2_TSF_USR_SHIFT)
6749 
6750 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_TSF_SR */
6751 /*
6752  * TSF_OV (R/WC)
6753  *
6754  * Overflow of Tx-Timestamp-Fifo. At least one transmitted packet has been sent and timestamp was not stored; write bit to clear flag
6755  */
6756 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK (0x80000000UL)
6757 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT (31U)
6758 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK)
6759 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_OV_SHIFT)
6760 
6761 /*
6762  * TSF_USED (RO)
6763  *
6764  * Tx-Timestamp-Fifo currently used entries counter; reading of TSF_Dx is only valid if field value > 0. Any read from TSF_D2 will decrement counter (unless already 0).
6765  */
6766 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK (0xFFU)
6767 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT (0U)
6768 #define TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_MASK) >> TSW_TSNPORT_TSN_EP_TSF_SR_TSF_USED_SHIFT)
6769 
6770 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_CTRL */
6771 /*
6772  * STATSEL (R/W)
6773  *
6774  * MMS statistic counter selection, value can be read in register
6775  * MMS_STAT
6776  * <000>: Frame reassembly error counter (802.3br, 30.14.1.8)
6777  * <001>: Frames rejected due to wrong SMD (802.3br, 30.14.1.9)
6778  * <010>: Frame assembly ok counter (802.3br, 30.14.1.10)
6779  * <011>: Fragment rx counter (802.3br, 30.14.1.11)
6780  * <100>: Fragment tx counter (802.3br, 30.14.1.12)
6781  * <101>: Hold request counter (802.3br, 30.14.1.13)
6782  * otherwise: <0>
6783  */
6784 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK (0xE0U)
6785 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT (5U)
6786 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK)
6787 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_STATSEL_SHIFT)
6788 
6789 /*
6790  * FRAGSZ (R/W)
6791  *
6792  * Minimum non-final fragment size: 64 x (1 + FRAGSZ) – 4 octets
6793  */
6794 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK (0x18U)
6795 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT (3U)
6796 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK)
6797 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_FRAGSZ_SHIFT)
6798 
6799 /*
6800  * DISV (R/W)
6801  *
6802  * Disable verification
6803  */
6804 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK (0x4U)
6805 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT (2U)
6806 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK)
6807 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_DISV_SHIFT)
6808 
6809 /*
6810  * LINK (R/W)
6811  *
6812  * Link error
6813  */
6814 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK (0x2U)
6815 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT (1U)
6816 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK)
6817 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_LINK_SHIFT)
6818 
6819 /*
6820  * EN (R/W)
6821  *
6822  * Enable preemption
6823  */
6824 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK (0x1U)
6825 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT (0U)
6826 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK)
6827 #define TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_MASK) >> TSW_TSNPORT_TSN_EP_MMS_CTRL_EN_SHIFT)
6828 
6829 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_STS */
6830 /*
6831  * VFAIL (RO)
6832  *
6833  * 802.3br verification state failure; verification is done when any bit VFAIL or VOK is <1>
6834  */
6835 #define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK (0x4U)
6836 #define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT (2U)
6837 #define TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VFAIL_SHIFT)
6838 
6839 /*
6840  * VOK (RO)
6841  *
6842  * 802.3br verification state ok; verification is done when any bit VFAIL or VOK is <1>
6843  */
6844 #define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK (0x2U)
6845 #define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT (1U)
6846 #define TSW_TSNPORT_TSN_EP_MMS_STS_VOK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_VOK_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_VOK_SHIFT)
6847 
6848 /*
6849  * HLD (RO)
6850  *
6851  * HOLD-Signal
6852  */
6853 #define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK (0x1U)
6854 #define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT (0U)
6855 #define TSW_TSNPORT_TSN_EP_MMS_STS_HLD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STS_HLD_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STS_HLD_SHIFT)
6856 
6857 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_VTIME */
6858 /*
6859  * VTIME (R/W)
6860  *
6861  * 802.3br verification timeout counter in <sys_clk> cycles. Must be set by software in range of 1ms to 128ms.
6862  */
6863 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK (0xFFFFFFFFUL)
6864 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT (0U)
6865 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK)
6866 #define TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_MASK) >> TSW_TSNPORT_TSN_EP_MMS_VTIME_VTIME_SHIFT)
6867 
6868 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_MMS_STAT */
6869 /*
6870  * COUNTER (R/WC)
6871  *
6872  * Statistic counter of MMS, selected by MMS_CTRL.STATSEL,any write access will clear selected counter
6873  */
6874 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK (0xFFFFFFFFUL)
6875 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT (0U)
6876 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK)
6877 #define TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_MASK) >> TSW_TSNPORT_TSN_EP_MMS_STAT_COUNTER_SHIFT)
6878 
6879 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_UPTM_NS */
6880 /*
6881  * UPTM_NS (WO)
6882  *
6883  * PTP SYNC frame “upstreamTxTime” in format “seconds.nanoseconds” as potentially received by another TSN-EP port. The correction field of a transmitted PTP SYNC frame is modified by (egressTimestamp –upstreamTxTime), relative to the LocalClock. The “rateRatio” to the Grandmaster Clock is not taken into account.
6884  */
6885 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK (0xFFFFFFFFUL)
6886 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT (0U)
6887 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK)
6888 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_NS_UPTM_NS_SHIFT)
6889 
6890 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_UPTM_S */
6891 /*
6892  * UPTM_NS (WO)
6893  *
6894  */
6895 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK (0xFFFFFFFFUL)
6896 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT (0U)
6897 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK)
6898 #define TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_UPTM_S_UPTM_NS_SHIFT)
6899 
6900 /* Bitfield definition for register of struct array TSNPORT: TSN_EP_PTP_SR */
6901 /*
6902  * MEAS_NS (RO)
6903  *
6904  * Measured value of the deviation of the early timestamping for PTP frames. This value is informational only. The deviation is already included to the corrected “correctionField”.
6905  */
6906 #define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK (0xFFFFU)
6907 #define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT (0U)
6908 #define TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_MASK) >> TSW_TSNPORT_TSN_EP_PTP_SR_MEAS_NS_SHIFT)
6909 
6910 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_PORT_MAIN_TAGGING */
6911 /*
6912  * FORCE (R/W)
6913  *
6914  * The VLAN-TAG with PVID will be inserted in every frame from Host as their first VLAN-TAG. This can be used for double tagging of tagged/trunk ports
6915  */
6916 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK (0x20000UL)
6917 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT (17U)
6918 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK)
6919 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_FORCE_SHIFT)
6920 
6921 /*
6922  * ACCESS (R/W)
6923  *
6924  * Every tagged frame not matching PVID is filtered out. Every untagged ingress frame will be tagged with PVID. Every egress frame with PVID will be untagged
6925  */
6926 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK (0x10000UL)
6927 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT (16U)
6928 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK)
6929 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_ACCESS_SHIFT)
6930 
6931 /*
6932  * PCP (R/W)
6933  *
6934  * VLAN-TCI: Priority Code Point, used when tagged.
6935  */
6936 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK (0xE000U)
6937 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT (13U)
6938 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK)
6939 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PCP_SHIFT)
6940 
6941 /*
6942  * DEI (R/W)
6943  *
6944  * VLAN-TCI: Drop Eligible Indicator, used when tagged.
6945  */
6946 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK (0x1000U)
6947 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT (12U)
6948 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK)
6949 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_DEI_SHIFT)
6950 
6951 /*
6952  * PVID (R/W)
6953  *
6954  * Native VLAN of Port. Untagged traffic will be tagged with the native VLAN-ID By default the Port uses VLAN 1.
6955  */
6956 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK (0xFFFU)
6957 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT (0U)
6958 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK)
6959 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_TAGGING_PVID_SHIFT)
6960 
6961 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_PORT_MAIN_ENNABLE */
6962 /*
6963  * EN_SF (R/W)
6964  *
6965  * only applicable for CPU-Port at egress: '1' to use S&F FIFO and '0' disable S&F FIFO. Changing during frame operation can lead to frame corruption
6966  */
6967 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK (0x2U)
6968 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT (1U)
6969 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK)
6970 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_SF_SHIFT)
6971 
6972 /*
6973  * EN_QCI (R/W)
6974  *
6975  * if QCI is present at selected egress port, '1' to use QCI and '0' disable QCI. Changing during frame operation can lead to frame corruption.
6976  */
6977 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK (0x1U)
6978 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT (0U)
6979 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK)
6980 #define TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_MASK) >> TSW_TSNPORT_SW_CTRL_PORT_MAIN_ENNABLE_EN_QCI_SHIFT)
6981 
6982 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_EGRESS_ECSR_QDROP */
6983 /*
6984  * DIS_VEC (R/W)
6985  *
6986  * disable drop for each queue when queue not free
6987  */
6988 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK (0xFF000000UL)
6989 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT (24U)
6990 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK)
6991 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_DIS_VEC_SHIFT)
6992 
6993 /*
6994  * EN_VEC (R/W)
6995  *
6996  * Enable/Disable drop in egress when TSN queue not free.
6997  * 1 - drop enabled
6998  * 0 - drop disabled
6999  * TSN-SW:
7000  * bit[i] - from Port[i]
7001  */
7002 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK (0xFFFFFFUL)
7003 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT (0U)
7004 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK)
7005 #define TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_EGRESS_ECSR_QDROP_EN_VEC_SHIFT)
7006 
7007 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE */
7008 /*
7009  * FDMEM_CNT_BYTE (RO)
7010  *
7011  * Number of bytes stored in frame drop FIFO
7012  */
7013 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK (0xFFFFFFFFUL)
7014 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT (0U)
7015 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_CNT_BYTE_FDMEM_CNT_BYTE_SHIFT)
7016 
7017 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS */
7018 /*
7019  * WAIT_FOR_LU (RO)
7020  *
7021  * FD FIFO waits for LookUp information.
7022  */
7023 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK (0x800U)
7024 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT (11U)
7025 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_LU_SHIFT)
7026 
7027 /*
7028  * WAIT_FOR_FRAME (RO)
7029  *
7030  * FD FIFO waits for more frame data.
7031  */
7032 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK (0x400U)
7033 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT (10U)
7034 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_WAIT_FOR_FRAME_SHIFT)
7035 
7036 /*
7037  * BUSY (RO)
7038  *
7039  * FD FIFO processes data.
7040  */
7041 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK (0x200U)
7042 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT (9U)
7043 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_BUSY_SHIFT)
7044 
7045 /*
7046  * READY (RO)
7047  *
7048  * FD FIFO ready to work or working.
7049  */
7050 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK (0x100U)
7051 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT (8U)
7052 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_READY_SHIFT)
7053 
7054 /*
7055  * FULL (RO)
7056  *
7057  * FD FIFO full
7058  */
7059 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK (0x8U)
7060 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT (3U)
7061 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_FULL_SHIFT)
7062 
7063 /*
7064  * AMST_FULL (RO)
7065  *
7066  * FD FIFO almost full. Less than 1600 Byte left.
7067  */
7068 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK (0x4U)
7069 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT (2U)
7070 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_FULL_SHIFT)
7071 
7072 /*
7073  * AMST_EMPTY (RO)
7074  *
7075  * FD FIFO almost empty. Few bytes in FIFO.
7076  */
7077 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK (0x2U)
7078 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT (1U)
7079 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_AMST_EMPTY_SHIFT)
7080 
7081 /*
7082  * EMPTY (RO)
7083  *
7084  * FD FIFO empty
7085  */
7086 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK (0x1U)
7087 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT (0U)
7088 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_FDMEM_STS_EMPTY_SHIFT)
7089 
7090 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG */
7091 /*
7092  * LU_DESC_ERR (R/W1C)
7093  *
7094  * LookUp Descriptor lost, because of unknown frame burst by MAC. If there is no MAC mailfunction then this flag will never be raised. FDFIFO requires reset.
7095  */
7096 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK (0x40U)
7097 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT (6U)
7098 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK)
7099 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_LU_DESC_ERR_SHIFT)
7100 
7101 /*
7102  * WRFAIL_FULL (R/W1C)
7103  *
7104  * Set if a frame is partially written into FIFO which had insufficient space. The frame is cut and frame error is set.
7105  */
7106 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK (0x20U)
7107 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT (5U)
7108 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK)
7109 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_WRFAIL_FULL_SHIFT)
7110 
7111 /*
7112  * DROP_NRDY (R/W1C)
7113  *
7114  * Frame was dropped because the FIFO was not ready. That can typically happen after a reset of the FIFO
7115  */
7116 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK (0x10U)
7117 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT (4U)
7118 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK)
7119 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_NRDY_SHIFT)
7120 
7121 /*
7122  * DROP_FULL_DESC (R/W1C)
7123  *
7124  * Frame was dropped because the internal descriptor FIFO is full. Full by too many frames.
7125  */
7126 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK (0x8U)
7127 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT (3U)
7128 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK)
7129 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_DESC_SHIFT)
7130 
7131 /*
7132  * DROP_FULL_MEM (R/W1C)
7133  *
7134  * Frame was dropped because the FIFO is full. Full by too much data.
7135  */
7136 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK (0x4U)
7137 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT (2U)
7138 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK)
7139 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DROP_FULL_MEM_SHIFT)
7140 
7141 /*
7142  * DESC_NRDY_ERR (R/W1C)
7143  *
7144  * FD FIFO failure. Descriptor not received correctly.
7145  */
7146 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK (0x2U)
7147 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT (1U)
7148 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK)
7149 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_NRDY_ERR_SHIFT)
7150 
7151 /*
7152  * DESC_SEQ_ERR (R/W1C)
7153  *
7154  * FD FIFO failure. Internal controller lost synchronization.
7155  */
7156 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK (0x1U)
7157 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT (0U)
7158 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK)
7159 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_ERROR_FLAG_DESC_SEQ_ERR_SHIFT)
7160 
7161 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG */
7162 /*
7163  * IE (R/W)
7164  *
7165  * Interrupt enable of ERROR_FLAG.
7166  */
7167 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK (0x7FU)
7168 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT (0U)
7169 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK)
7170 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IE_ERROR_FLAG_IE_SHIFT)
7171 
7172 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG */
7173 /*
7174  * NOCUT_ERROR (R/W)
7175  *
7176  * FD_FIFO does not shorten frames which contain an error.
7177  */
7178 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK (0x1U)
7179 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT (0U)
7180 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK)
7181 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_IN_CONFIG_NOCUT_ERROR_SHIFT)
7182 
7183 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG */
7184 /*
7185  * DROP_DEST (R/W)
7186  *
7187  * Bit mapped Destination for dropped frames. Typically, frames are cleared at destination 0. Use another value to stream frames for analysis. Supports only max range of port[15:0].
7188  */
7189 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK (0xFFFF0000UL)
7190 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT (16U)
7191 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK)
7192 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_DEST_SHIFT)
7193 
7194 /*
7195  * MIRROR_TX_EN (R/W)
7196  *
7197  * Incoming frames of this port will be mirrored to the given destination in MIRROR if their destination match with MIRROR_TX.
7198  */
7199 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK (0x200U)
7200 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT (9U)
7201 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK)
7202 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TX_EN_SHIFT)
7203 
7204 /*
7205  * MIRROR_RX_EN (R/W)
7206  *
7207  * Incoming frames of this port will be mirrored to the given destination in MIRROR_RX.
7208  */
7209 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK (0x100U)
7210 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT (8U)
7211 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK)
7212 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_RX_EN_SHIFT)
7213 
7214 /*
7215  * CT_FPE_OVRD (R/W)
7216  *
7217  * If any Store&Forward option in RX_FDFIFO is set then this flag will still force preemptable traffic to be forwarded in Cut-Through mode. This is a useful option to save latency by double buffering if the used MAC/TSN-EP already does S&F.
7218  */
7219 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK (0x40U)
7220 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT (6U)
7221 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK)
7222 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_CT_FPE_OVRD_SHIFT)
7223 
7224 /*
7225  * DISABLE (R/W)
7226  *
7227  * Disable input of FD FIFO. Take care that also descriptor generation of LookUp is disabled. Remaining frames should be cleared with DROP_ALL.
7228  */
7229 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK (0x20U)
7230 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT (5U)
7231 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK)
7232 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DISABLE_SHIFT)
7233 
7234 /*
7235  * DROP_ALL (R/W)
7236  *
7237  * Route all frames to DROP_DEST.
7238  */
7239 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK (0x10U)
7240 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT (4U)
7241 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK)
7242 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_DROP_ALL_SHIFT)
7243 
7244 /*
7245  * ERROR_TO_CPU (R/W)
7246  *
7247  * Send error frames to CPU.
7248  */
7249 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK (0x8U)
7250 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT (3U)
7251 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK)
7252 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_ERROR_TO_CPU_SHIFT)
7253 
7254 /*
7255  * MIRROR_TO_CPU (R/W)
7256  *
7257  * Duplicate frames to CPU.
7258  */
7259 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK (0x4U)
7260 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT (2U)
7261 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK)
7262 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MIRROR_TO_CPU_SHIFT)
7263 
7264 /*
7265  * NODROP_ERROR (R/W)
7266  *
7267  * Do not drop frame errors.
7268  */
7269 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK (0x2U)
7270 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT (1U)
7271 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK)
7272 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_NODROP_ERROR_SHIFT)
7273 
7274 /*
7275  * MODE_STORE_FW (R/W)
7276  *
7277  * Switch between Cut-Through and Store&Forward mode. 0 - Cut-Through 1 - Store&Forward
7278  */
7279 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK (0x1U)
7280 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT (0U)
7281 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK)
7282 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_OUT_CONFIG_MODE_STORE_FW_SHIFT)
7283 
7284 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_RESET */
7285 /*
7286  * SOFTRS (W)
7287  *
7288  * Write 1 to reset FD controller and memory pointers. Register Map content remains untouched
7289  */
7290 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK (0x1U)
7291 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT (0U)
7292 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK)
7293 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_RESET_SOFTRS_SHIFT)
7294 
7295 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM */
7296 /*
7297  * LU_FIFO_DEPTH (RO)
7298  *
7299  * Number of MAC lookup descriptors the FIFO can store.
7300  */
7301 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK (0xFF000000UL)
7302 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT (24U)
7303 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_LU_FIFO_DEPTH_SHIFT)
7304 
7305 /*
7306  * FD_DESC_FIFO_DESC (RO)
7307  *
7308  * Number of FD descriptors the FIFO can store. Two descriptors need to be stored per frame.
7309  */
7310 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK (0xFF0000UL)
7311 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT (16U)
7312 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_DESC_FIFO_DESC_SHIFT)
7313 
7314 /*
7315  * FD_FIFO_DESC (RO)
7316  *
7317  * Number of words (4byte) the Frame Drop FIFO can store.
7318  */
7319 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK (0xFFFFU)
7320 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT (0U)
7321 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PARAM_FD_FIFO_DESC_SHIFT)
7322 
7323 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD */
7324 /*
7325  * PORT (R/W)
7326  *
7327  * If selected port is set then the frame is transmitted in Store & Forward mode. This is necessary when the ingress rate of this port is slower than the egress rate of the transmitting port. In S&F, the ingress module is able to drop frames with bad CRC.bit 0 - CPU-Port,
7328  * bit 1 - Port 1, …
7329  */
7330 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK (0x1FFFFFFUL)
7331 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT (0U)
7332 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK)
7333 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_STRFWD_PORT_SHIFT)
7334 
7335 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK */
7336 /*
7337  * PORT (R/W)
7338  *
7339  * Port grouping via port mask. If the selected port is not set then the destination will be filtered out. This register allows the realization of port-based-VLAN (no VLAN tags required, only set it by ports).
7340  * bit 0 - CPU-Port,
7341  * bit 1 - Port 1, …
7342  */
7343 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK (0x1FFFFFFUL)
7344 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT (0U)
7345 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK)
7346 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_PORTMASK_PORT_SHIFT)
7347 
7348 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR */
7349 /*
7350  * PORT (R/W)
7351  *
7352  * Mirror Port. If port mirroring is enabled TX/RX traffic will also be forwarded to this port.
7353  * bit 0 - CPU-Port,
7354  * bit 1 - Port 1, …
7355  */
7356 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK (0x1FFFFFFUL)
7357 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT (0U)
7358 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK)
7359 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_PORT_SHIFT)
7360 
7361 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX */
7362 /*
7363  * PORT (R/W)
7364  *
7365  * Mirror Selection TX. The destination of the frame is compared with this vector. All matching TX probe ports will be mirrored to MIRROR. It is necessary to configure all ingress ports to mirror the complete TX traffic.
7366  * bit 0 - CPU-Port,
7367  * bit 1 - Port 1, …
7368  */
7369 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK (0x1FFFFFFUL)
7370 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT (0U)
7371 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SET(x) (((uint32_t)(x) << TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK)
7372 #define TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_GET(x) (((uint32_t)(x) & TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_MASK) >> TSW_TSNPORT_RXFIFO_SW_CTRL_IGRESS_RX_FDFIFO_E_MIRROR_TX_PORT_SHIFT)
7373 
7374 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_CTRL */
7375 /*
7376  * EN (R/W)
7377  *
7378  * Enables counter. If deasserted the counter process stops and the counters hold their value.
7379  */
7380 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK (0x1U)
7381 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT (0U)
7382 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK)
7383 #define TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_CTRL_EN_SHIFT)
7384 
7385 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_RESET */
7386 /*
7387  * RSRX (WO)
7388  *
7389  * Write '1' to reset all RX counters.
7390  */
7391 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK (0x4U)
7392 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT (2U)
7393 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK)
7394 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSRX_SHIFT)
7395 
7396 /*
7397  * RSTX (WO)
7398  *
7399  * Write '1' to reset all TX counters
7400  */
7401 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK (0x2U)
7402 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT (1U)
7403 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK)
7404 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSTX_SHIFT)
7405 
7406 /*
7407  * RSALL (WO)
7408  *
7409  * Write '1' to reset all TX&RX counters.
7410  */
7411 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK (0x1U)
7412 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT (0U)
7413 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK)
7414 #define TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_RESET_RSALL_SHIFT)
7415 
7416 /* Bitfield definition for register of struct array TSNPORT: SW_CTRL_MONITOR_PARAM */
7417 /*
7418  * RX_CNT_EN_VEC (RO)
7419  *
7420  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
7421  */
7422 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK (0xFFFF0000UL)
7423 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT (16U)
7424 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_RX_CNT_EN_VEC_SHIFT)
7425 
7426 /*
7427  * TX_CNT_EN_VEC (RO)
7428  *
7429  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter are available.
7430  */
7431 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK (0xFF00U)
7432 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT (8U)
7433 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_TX_CNT_EN_VEC_SHIFT)
7434 
7435 /*
7436  * CNTW (RO)
7437  *
7438  * Vector of implemented RX counters. E.g. 0x000F means only the first 4 RX counter
7439  * are available.
7440  */
7441 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK (0x7FU)
7442 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT (0U)
7443 #define TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_GET(x) (((uint32_t)(x) & TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_MASK) >> TSW_TSNPORT_SW_CTRL_MONITOR_PARAM_CNTW_SHIFT)
7444 
7445 /* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_FGOOD */
7446 /*
7447  * TX_FGOOD (RO)
7448  *
7449  * Good transmitted Frames to TX TSN-EP.
7450  */
7451 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK (0xFFFFFFFFUL)
7452 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT (0U)
7453 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FGOOD_TX_FGOOD_SHIFT)
7454 
7455 /* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_FERROR */
7456 /*
7457  * TX_FERROR (RO)
7458  *
7459  * Transmitted Frames with Error to TX TSN-EP.
7460  */
7461 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK (0xFFFFFFFFUL)
7462 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT (0U)
7463 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_FERROR_TX_FERROR_SHIFT)
7464 
7465 /* Bitfield definition for register of struct array TSNPORT: MONITOR_TX_COUNTER_TX_DROP_OVFL */
7466 /*
7467  * TX_DROP_OVFL (RO)
7468  *
7469  * Dropped frames by full queue of TSN-EP.
7470  */
7471 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK (0xFFFFFFFFUL)
7472 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT (0U)
7473 #define TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_TX_COUNTER_TX_DROP_OVFL_TX_DROP_OVFL_SHIFT)
7474 
7475 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FGOOD */
7476 /*
7477  * RX_FGOOD (RO)
7478  *
7479  * Good received frame by ingress buffer.
7480  */
7481 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK (0xFFFFFFFFUL)
7482 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT (0U)
7483 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FGOOD_RX_FGOOD_SHIFT)
7484 
7485 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FERROR */
7486 /*
7487  * RX_FERROR (RO)
7488  *
7489  * Bad received frame by ingress buffer.
7490  */
7491 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK (0xFFFFFFFFUL)
7492 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT (0U)
7493 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FERROR_RX_FERROR_SHIFT)
7494 
7495 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_KNOWN */
7496 /*
7497  * RX_KNOWN (RO)
7498  *
7499  * Number of frames passed ingress with hit by MAC Table. This includes Broadcast and non-relayed frames.
7500  */
7501 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK (0xFFFFFFFFUL)
7502 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT (0U)
7503 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_KNOWN_RX_KNOWN_SHIFT)
7504 
7505 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_UNKNOWN */
7506 /*
7507  * RX_UNKNOWN (RO)
7508  *
7509  * Number of frames passed ingress without hit by MAC table.
7510  */
7511 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK (0xFFFFFFFFUL)
7512 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT (0U)
7513 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UNKNOWN_RX_UNKNOWN_SHIFT)
7514 
7515 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_UC */
7516 /*
7517  * RX_UC (RO)
7518  *
7519  * Number of unicast frames
7520  */
7521 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK (0xFFFFFFFFUL)
7522 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT (0U)
7523 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_UC_RX_UC_SHIFT)
7524 
7525 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_INTERN */
7526 /*
7527  * RX_INTERN (RO)
7528  *
7529  * Number of non-relay frames
7530  */
7531 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK (0xFFFFFFFFUL)
7532 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT (0U)
7533 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_INTERN_RX_INTERN_SHIFT)
7534 
7535 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_BC */
7536 /*
7537  * RX_BC (RO)
7538  *
7539  * Number of Broadcast frames
7540  */
7541 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK (0xFFFFFFFFUL)
7542 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT (0U)
7543 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_BC_RX_BC_SHIFT)
7544 
7545 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_MULTI */
7546 /*
7547  * RX_MULTI (RO)
7548  *
7549  * Number of Multicast frames
7550  */
7551 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK (0xFFFFFFFFUL)
7552 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT (0U)
7553 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_MULTI_RX_MULTI_SHIFT)
7554 
7555 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_VLAN */
7556 /*
7557  * RX_VLAN (RO)
7558  *
7559  * Number of VLAN tagged frames
7560  */
7561 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK (0xFFFFFFFFUL)
7562 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT (0U)
7563 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_VLAN_RX_VLAN_SHIFT)
7564 
7565 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_OVFL */
7566 /*
7567  * RX_DROP_OVFL (RO)
7568  *
7569  * Dropped frames by ingress overflow.
7570  */
7571 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK (0xFFFFFFFFUL)
7572 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT (0U)
7573 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_OVFL_RX_DROP_OVFL_SHIFT)
7574 
7575 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_LU */
7576 /*
7577  * RX_DROP_LU (RO)
7578  *
7579  * Dropped frames by LookUp decision.
7580  */
7581 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK (0xFFFFFFFFUL)
7582 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT (0U)
7583 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_LU_RX_DROP_LU_SHIFT)
7584 
7585 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_ERR */
7586 /*
7587  * RX_DROP_ERR (RO)
7588  *
7589  * Dropped frames with error by ingress. Possible in S&F mode or when frame is queued in ingress.
7590  */
7591 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK (0xFFFFFFFFUL)
7592 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT (0U)
7593 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_ERR_RX_DROP_ERR_SHIFT)
7594 
7595 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_DROP_VLAN */
7596 /*
7597  * RX_DROP_VLAN (RO)
7598  *
7599  * Dropped frames by incompatible VLAN.
7600  */
7601 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK (0xFFFFFFFFUL)
7602 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT (0U)
7603 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_DROP_VLAN_RX_DROP_VLAN_SHIFT)
7604 
7605 /* Bitfield definition for register of struct array TSNPORT: MONITOR_RX_COUNTER_RX_FPE_FGOOD */
7606 /*
7607  * RX_FPE_FGOOD (RO)
7608  *
7609  * Number of preemptable frames. Subset of RX_FGOOD
7610  */
7611 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK (0xFFFFFFFFUL)
7612 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT (0U)
7613 #define TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_GET(x) (((uint32_t)(x) & TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_MASK) >> TSW_TSNPORT_MONITOR_RX_COUNTER_RX_FPE_FGOOD_RX_FPE_FGOOD_SHIFT)
7614 
7615 /* Bitfield definition for register of struct array TSNPORT: GPR_CTRL0 */
7616 /*
7617  * RXCLK_DLY_SEL (RW)
7618  *
7619  * delay value of rxclk_delay_chain
7620  */
7621 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK (0x3F00U)
7622 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT (8U)
7623 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK)
7624 #define TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_RXCLK_DLY_SEL_SHIFT)
7625 
7626 /*
7627  * TXCLK_DLY_SEL (RW)
7628  *
7629  * delay value of txclk_delay_chain
7630  */
7631 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK (0x3FU)
7632 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT (0U)
7633 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK)
7634 #define TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL0_TXCLK_DLY_SEL_SHIFT)
7635 
7636 /* Bitfield definition for register of struct array TSNPORT: GPR_CTRL2 */
7637 /*
7638  * MAC_SPEED (RW)
7639  *
7640  * mac speed
7641  * 00: 1000Mbps
7642  * 10: 10Mbps
7643  * 11: 100Mbps
7644  */
7645 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK (0x300000UL)
7646 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT (20U)
7647 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK)
7648 #define TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_MASK) >> TSW_TSNPORT_GPR_CTRL2_MAC_SPEED_SHIFT)
7649 
7650 /*
7651  * PAD_OE_ETH_REFCLK (RW)
7652  *
7653  * RMII REFCLK output enable
7654  * 0: Disable REFCLK output
7655  * 1: Enable EFCLK output
7656  */
7657 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK (0x80000UL)
7658 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT (19U)
7659 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK)
7660 #define TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_MASK) >> TSW_TSNPORT_GPR_CTRL2_PAD_OE_ETH_REFCLK_SHIFT)
7661 
7662 /*
7663  * PHY_INTF_SEL (RW)
7664  *
7665  * phy interface select
7666  * 000: MII
7667  * 001: RGMII
7668  * 100: RMII
7669  */
7670 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK (0xE000U)
7671 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT (13U)
7672 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK)
7673 #define TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_PHY_INTF_SEL_SHIFT)
7674 
7675 /*
7676  * RMII_TXCLK_SEL (RW)
7677  *
7678  * refclk select for RMII
7679  * 0: Use RXCLK PAD
7680  * 1: Use TXCLK PAD
7681  */
7682 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK (0x400U)
7683 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT (10U)
7684 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SET(x) (((uint32_t)(x) << TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK)
7685 #define TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_GET(x) (((uint32_t)(x) & TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_MASK) >> TSW_TSNPORT_GPR_CTRL2_RMII_TXCLK_SEL_SHIFT)
7686 
7687 
7688 
7689 /* HITMEM register group index macro definition */
7690 #define TSW_HITMEM_HITMEM_REG_1 (0UL)
7691 #define TSW_HITMEM_HITMEM_REG_2 (1UL)
7692 #define TSW_HITMEM_HITMEM_REG_3 (2UL)
7693 #define TSW_HITMEM_HITMEM_REG_4 (3UL)
7694 
7695 /* QCI_CNT register group index macro definition */
7696 #define TSW_QCI_CNT_CENTRAL_QCI_CNT0 (0UL)
7697 #define TSW_QCI_CNT_CENTRAL_QCI_CNT1 (1UL)
7698 #define TSW_QCI_CNT_CENTRAL_QCI_CNT2 (2UL)
7699 #define TSW_QCI_CNT_CENTRAL_QCI_CNT3 (3UL)
7700 #define TSW_QCI_CNT_CENTRAL_QCI_CNT4 (4UL)
7701 #define TSW_QCI_CNT_CENTRAL_QCI_CNT5 (5UL)
7702 
7703 /* EGFRCNT register group index macro definition */
7704 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT0 (0UL)
7705 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT1 (1UL)
7706 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT2 (2UL)
7707 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT3 (3UL)
7708 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT4 (4UL)
7709 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT5 (5UL)
7710 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT6 (6UL)
7711 #define TSW_EGFRCNT_CPU_PORT_EGRESS_FRER_CNT7 (7UL)
7712 
7713 /* IGFRCNT register group index macro definition */
7714 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT0 (0UL)
7715 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT1 (1UL)
7716 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT2 (2UL)
7717 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT3 (3UL)
7718 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT4 (4UL)
7719 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT5 (5UL)
7720 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT6 (6UL)
7721 #define TSW_IGFRCNT_CPU_PORT_IGRESS_FRER_CNT7 (7UL)
7722 
7723 /* MAC register group index macro definition */
7724 #define TSW_MAC_EM1 (0UL)
7725 #define TSW_MAC_PM1 (1UL)
7726 
7727 /* TSYNTMR register group index macro definition */
7728 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR0 (0UL)
7729 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR1 (1UL)
7730 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR2 (2UL)
7731 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR3 (3UL)
7732 #define TSW_TSNPORT_TSYNTMR_TSYN_TMR4 (4UL)
7733 
7734 /* RXDATA register group index macro definition */
7735 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD0 (0UL)
7736 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD1 (1UL)
7737 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD2 (2UL)
7738 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD3 (3UL)
7739 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD4 (4UL)
7740 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD5 (5UL)
7741 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD6 (6UL)
7742 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD7 (7UL)
7743 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD8 (8UL)
7744 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD9 (9UL)
7745 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD10 (10UL)
7746 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD11 (11UL)
7747 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD12 (12UL)
7748 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD13 (13UL)
7749 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD14 (14UL)
7750 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD15 (15UL)
7751 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD16 (16UL)
7752 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD17 (17UL)
7753 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD18 (18UL)
7754 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD19 (19UL)
7755 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD20 (20UL)
7756 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD21 (21UL)
7757 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD22 (22UL)
7758 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD23 (23UL)
7759 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD24 (24UL)
7760 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD25 (25UL)
7761 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD26 (26UL)
7762 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD27 (27UL)
7763 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD28 (28UL)
7764 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD29 (29UL)
7765 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD30 (30UL)
7766 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD31 (31UL)
7767 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD32 (32UL)
7768 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD33 (33UL)
7769 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD34 (34UL)
7770 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD35 (35UL)
7771 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD36 (36UL)
7772 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD37 (37UL)
7773 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD38 (38UL)
7774 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD39 (39UL)
7775 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD40 (40UL)
7776 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD41 (41UL)
7777 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD42 (42UL)
7778 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD43 (43UL)
7779 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD44 (44UL)
7780 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD45 (45UL)
7781 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD46 (46UL)
7782 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD47 (47UL)
7783 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD48 (48UL)
7784 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD49 (49UL)
7785 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD50 (50UL)
7786 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD51 (51UL)
7787 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD52 (52UL)
7788 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD53 (53UL)
7789 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD54 (54UL)
7790 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD55 (55UL)
7791 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD56 (56UL)
7792 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD57 (57UL)
7793 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD58 (58UL)
7794 #define TSW_TSNPORT_RXDATA_TSYN_RXBUF_DATA_WORD59 (59UL)
7795 
7796 /* TXDATA register group index macro definition */
7797 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD0 (0UL)
7798 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD1 (1UL)
7799 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD2 (2UL)
7800 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD3 (3UL)
7801 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD4 (4UL)
7802 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD5 (5UL)
7803 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD6 (6UL)
7804 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD7 (7UL)
7805 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD8 (8UL)
7806 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD9 (9UL)
7807 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD10 (10UL)
7808 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD11 (11UL)
7809 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD12 (12UL)
7810 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD13 (13UL)
7811 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD14 (14UL)
7812 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD15 (15UL)
7813 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD16 (16UL)
7814 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD17 (17UL)
7815 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD18 (18UL)
7816 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD19 (19UL)
7817 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD20 (20UL)
7818 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD21 (21UL)
7819 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD22 (22UL)
7820 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD23 (23UL)
7821 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD24 (24UL)
7822 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD25 (25UL)
7823 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD26 (26UL)
7824 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD27 (27UL)
7825 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD28 (28UL)
7826 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD29 (29UL)
7827 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD30 (30UL)
7828 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD31 (31UL)
7829 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD32 (32UL)
7830 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD33 (33UL)
7831 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD34 (34UL)
7832 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD35 (35UL)
7833 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD36 (36UL)
7834 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD37 (37UL)
7835 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD38 (38UL)
7836 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD39 (39UL)
7837 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD40 (40UL)
7838 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD41 (41UL)
7839 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD42 (42UL)
7840 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD43 (43UL)
7841 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD44 (44UL)
7842 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD45 (45UL)
7843 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD46 (46UL)
7844 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD47 (47UL)
7845 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD48 (48UL)
7846 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD49 (49UL)
7847 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD50 (50UL)
7848 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD51 (51UL)
7849 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD52 (52UL)
7850 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD53 (53UL)
7851 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD54 (54UL)
7852 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD55 (55UL)
7853 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD56 (56UL)
7854 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD57 (57UL)
7855 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD58 (58UL)
7856 #define TSW_TSNPORT_BIN_TXDATA_TSYN_TXBUF_BIN0_DATA_WORD59 (59UL)
7857 
7858 /* BIN register group index macro definition */
7859 #define TSW_BIN_TX0 (0UL)
7860 #define TSW_BIN_TX1 (1UL)
7861 #define TSW_BIN_TX2 (2UL)
7862 #define TSW_BIN_TX3 (3UL)
7863 #define TSW_BIN_TX4 (4UL)
7864 #define TSW_BIN_TX5 (5UL)
7865 #define TSW_BIN_TX6 (6UL)
7866 #define TSW_BIN_TX7 (7UL)
7867 
7868 /* MXSDU register group index macro definition */
7869 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU0 (0UL)
7870 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU1 (1UL)
7871 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU2 (2UL)
7872 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU3 (3UL)
7873 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU4 (4UL)
7874 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU5 (5UL)
7875 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU6 (6UL)
7876 #define TSW_TSNPORT_MXSDU_TSN_SHAPER_MXSDU7 (7UL)
7877 
7878 /* TXSEL register group index macro definition */
7879 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL0 (0UL)
7880 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL1 (1UL)
7881 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL2 (2UL)
7882 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL3 (3UL)
7883 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL4 (4UL)
7884 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL5 (5UL)
7885 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL6 (6UL)
7886 #define TSW_TSNPORT_TXSEL_TSN_SHAPER_TXSEL7 (7UL)
7887 
7888 /* IDSEL register group index macro definition */
7889 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL0 (0UL)
7890 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL1 (1UL)
7891 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL2 (2UL)
7892 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL3 (3UL)
7893 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL04 (4UL)
7894 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL5 (5UL)
7895 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL6 (6UL)
7896 #define TSW_TSNPORT_IDSEL_TSN_SHAPER_IDSEL7 (7UL)
7897 
7898 /* MXTK register group index macro definition */
7899 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK0 (0UL)
7900 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK1 (1UL)
7901 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK2 (2UL)
7902 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK3 (3UL)
7903 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK4 (4UL)
7904 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK5 (5UL)
7905 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK6 (6UL)
7906 #define TSW_TSNPORT_MXTK_TSN_SHAPER_MXTK7 (7UL)
7907 
7908 /* TXOV register group index macro definition */
7909 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV0 (0UL)
7910 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV1 (1UL)
7911 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV2 (2UL)
7912 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV3 (3UL)
7913 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV4 (4UL)
7914 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV5 (5UL)
7915 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV6 (6UL)
7916 #define TSW_TSNPORT_TXOV_TSN_SHAPER_TXOV7 (7UL)
7917 
7918 /* SHACL register group index macro definition */
7919 #define TSW_SHACL_ENT0 (0UL)
7920 #define TSW_SHACL_ENT1 (1UL)
7921 #define TSW_SHACL_ENT2 (2UL)
7922 #define TSW_SHACL_ENT3 (3UL)
7923 #define TSW_SHACL_ENT4 (4UL)
7924 #define TSW_SHACL_ENT5 (5UL)
7925 #define TSW_SHACL_ENT6 (6UL)
7926 #define TSW_SHACL_ENT7 (7UL)
7927 #define TSW_SHACL_ENT8 (8UL)
7928 #define TSW_SHACL_ENT9 (9UL)
7929 #define TSW_SHACL_ENT10 (10UL)
7930 #define TSW_SHACL_ENT11 (11UL)
7931 #define TSW_SHACL_ENT12 (12UL)
7932 #define TSW_SHACL_ENT13 (13UL)
7933 #define TSW_SHACL_ENT14 (14UL)
7934 #define TSW_SHACL_ENT15 (15UL)
7935 #define TSW_SHACL_ENT16 (16UL)
7936 #define TSW_SHACL_ENT17 (17UL)
7937 #define TSW_SHACL_ENT18 (18UL)
7938 #define TSW_SHACL_ENT19 (19UL)
7939 #define TSW_SHACL_ENT20 (20UL)
7940 #define TSW_SHACL_ENT21 (21UL)
7941 #define TSW_SHACL_ENT22 (22UL)
7942 #define TSW_SHACL_ENT23 (23UL)
7943 #define TSW_SHACL_ENT24 (24UL)
7944 #define TSW_SHACL_ENT25 (25UL)
7945 #define TSW_SHACL_ENT26 (26UL)
7946 #define TSW_SHACL_ENT27 (27UL)
7947 #define TSW_SHACL_ENT28 (28UL)
7948 #define TSW_SHACL_ENT29 (29UL)
7949 #define TSW_SHACL_ENT30 (30UL)
7950 #define TSW_SHACL_ENT31 (31UL)
7951 #define TSW_SHACL_ENT32 (32UL)
7952 #define TSW_SHACL_ENT33 (33UL)
7953 #define TSW_SHACL_ENT34 (34UL)
7954 #define TSW_SHACL_ENT35 (35UL)
7955 #define TSW_SHACL_ENT36 (36UL)
7956 #define TSW_SHACL_ENT37 (37UL)
7957 #define TSW_SHACL_ENT38 (38UL)
7958 #define TSW_SHACL_ENT39 (39UL)
7959 #define TSW_SHACL_ENT40 (40UL)
7960 #define TSW_SHACL_ENT41 (41UL)
7961 #define TSW_SHACL_ENT42 (42UL)
7962 #define TSW_SHACL_ENT43 (43UL)
7963 #define TSW_SHACL_ENT44 (44UL)
7964 #define TSW_SHACL_ENT45 (45UL)
7965 #define TSW_SHACL_ENT46 (46UL)
7966 #define TSW_SHACL_ENT47 (47UL)
7967 #define TSW_SHACL_ENT48 (48UL)
7968 #define TSW_SHACL_ENT49 (49UL)
7969 #define TSW_SHACL_ENT50 (50UL)
7970 #define TSW_SHACL_ENT51 (51UL)
7971 #define TSW_SHACL_ENT52 (52UL)
7972 #define TSW_SHACL_ENT53 (53UL)
7973 #define TSW_SHACL_ENT54 (54UL)
7974 #define TSW_SHACL_ENT55 (55UL)
7975 #define TSW_SHACL_ENT56 (56UL)
7976 #define TSW_SHACL_ENT57 (57UL)
7977 #define TSW_SHACL_ENT58 (58UL)
7978 #define TSW_SHACL_ENT59 (59UL)
7979 #define TSW_SHACL_ENT60 (60UL)
7980 #define TSW_SHACL_ENT61 (61UL)
7981 #define TSW_SHACL_ENT62 (62UL)
7982 #define TSW_SHACL_ENT63 (63UL)
7983 #define TSW_SHACL_ENT64 (64UL)
7984 #define TSW_SHACL_ENT65 (65UL)
7985 #define TSW_SHACL_ENT66 (66UL)
7986 #define TSW_SHACL_ENT67 (67UL)
7987 #define TSW_SHACL_ENT68 (68UL)
7988 #define TSW_SHACL_ENT69 (69UL)
7989 #define TSW_SHACL_ENT70 (70UL)
7990 #define TSW_SHACL_ENT71 (71UL)
7991 #define TSW_SHACL_ENT72 (72UL)
7992 #define TSW_SHACL_ENT73 (73UL)
7993 #define TSW_SHACL_ENT74 (74UL)
7994 #define TSW_SHACL_ENT75 (75UL)
7995 #define TSW_SHACL_ENT76 (76UL)
7996 #define TSW_SHACL_ENT77 (77UL)
7997 #define TSW_SHACL_ENT78 (78UL)
7998 #define TSW_SHACL_ENT79 (79UL)
7999 #define TSW_SHACL_ENT80 (80UL)
8000 #define TSW_SHACL_ENT81 (81UL)
8001 #define TSW_SHACL_ENT82 (82UL)
8002 #define TSW_SHACL_ENT83 (83UL)
8003 #define TSW_SHACL_ENT84 (84UL)
8004 #define TSW_SHACL_ENT85 (85UL)
8005 #define TSW_SHACL_ENT86 (86UL)
8006 #define TSW_SHACL_ENT87 (87UL)
8007 #define TSW_SHACL_ENT88 (88UL)
8008 #define TSW_SHACL_ENT89 (89UL)
8009 #define TSW_SHACL_ENT90 (90UL)
8010 #define TSW_SHACL_ENT91 (91UL)
8011 #define TSW_SHACL_ENT92 (92UL)
8012 #define TSW_SHACL_ENT93 (93UL)
8013 #define TSW_SHACL_ENT94 (94UL)
8014 #define TSW_SHACL_ENT95 (95UL)
8015 #define TSW_SHACL_ENT96 (96UL)
8016 #define TSW_SHACL_ENT97 (97UL)
8017 #define TSW_SHACL_ENT98 (98UL)
8018 #define TSW_SHACL_ENT99 (99UL)
8019 #define TSW_SHACL_ENT100 (100UL)
8020 #define TSW_SHACL_ENT101 (101UL)
8021 #define TSW_SHACL_ENT102 (102UL)
8022 #define TSW_SHACL_ENT103 (103UL)
8023 #define TSW_SHACL_ENT104 (104UL)
8024 #define TSW_SHACL_ENT105 (105UL)
8025 #define TSW_SHACL_ENT106 (106UL)
8026 #define TSW_SHACL_ENT107 (107UL)
8027 #define TSW_SHACL_ENT108 (108UL)
8028 #define TSW_SHACL_ENT109 (109UL)
8029 #define TSW_SHACL_ENT110 (110UL)
8030 #define TSW_SHACL_ENT111 (111UL)
8031 #define TSW_SHACL_ENT112 (112UL)
8032 #define TSW_SHACL_ENT113 (113UL)
8033 #define TSW_SHACL_ENT114 (114UL)
8034 #define TSW_SHACL_ENT115 (115UL)
8035 #define TSW_SHACL_ENT116 (116UL)
8036 #define TSW_SHACL_ENT117 (117UL)
8037 #define TSW_SHACL_ENT118 (118UL)
8038 #define TSW_SHACL_ENT119 (119UL)
8039 #define TSW_SHACL_ENT120 (120UL)
8040 #define TSW_SHACL_ENT121 (121UL)
8041 #define TSW_SHACL_ENT122 (122UL)
8042 #define TSW_SHACL_ENT123 (123UL)
8043 #define TSW_SHACL_ENT124 (124UL)
8044 #define TSW_SHACL_ENT125 (125UL)
8045 #define TSW_SHACL_ENT126 (126UL)
8046 #define TSW_SHACL_ENT127 (127UL)
8047 #define TSW_SHACL_ENT128 (128UL)
8048 #define TSW_SHACL_ENT129 (129UL)
8049 #define TSW_SHACL_ENT130 (130UL)
8050 #define TSW_SHACL_ENT131 (131UL)
8051 #define TSW_SHACL_ENT132 (132UL)
8052 #define TSW_SHACL_ENT133 (133UL)
8053 #define TSW_SHACL_ENT134 (134UL)
8054 #define TSW_SHACL_ENT135 (135UL)
8055 #define TSW_SHACL_ENT136 (136UL)
8056 #define TSW_SHACL_ENT137 (137UL)
8057 #define TSW_SHACL_ENT138 (138UL)
8058 #define TSW_SHACL_ENT139 (139UL)
8059 #define TSW_SHACL_ENT140 (140UL)
8060 #define TSW_SHACL_ENT141 (141UL)
8061 #define TSW_SHACL_ENT142 (142UL)
8062 #define TSW_SHACL_ENT143 (143UL)
8063 #define TSW_SHACL_ENT144 (144UL)
8064 #define TSW_SHACL_ENT145 (145UL)
8065 #define TSW_SHACL_ENT146 (146UL)
8066 #define TSW_SHACL_ENT147 (147UL)
8067 #define TSW_SHACL_ENT148 (148UL)
8068 #define TSW_SHACL_ENT149 (149UL)
8069 #define TSW_SHACL_ENT150 (150UL)
8070 #define TSW_SHACL_ENT151 (151UL)
8071 #define TSW_SHACL_ENT152 (152UL)
8072 #define TSW_SHACL_ENT153 (153UL)
8073 #define TSW_SHACL_ENT154 (154UL)
8074 #define TSW_SHACL_ENT155 (155UL)
8075 #define TSW_SHACL_ENT156 (156UL)
8076 #define TSW_SHACL_ENT157 (157UL)
8077 #define TSW_SHACL_ENT158 (158UL)
8078 #define TSW_SHACL_ENT159 (159UL)
8079 #define TSW_SHACL_ENT160 (160UL)
8080 #define TSW_SHACL_ENT161 (161UL)
8081 #define TSW_SHACL_ENT162 (162UL)
8082 #define TSW_SHACL_ENT163 (163UL)
8083 #define TSW_SHACL_ENT164 (164UL)
8084 #define TSW_SHACL_ENT165 (165UL)
8085 #define TSW_SHACL_ENT166 (166UL)
8086 #define TSW_SHACL_ENT167 (167UL)
8087 #define TSW_SHACL_ENT168 (168UL)
8088 #define TSW_SHACL_ENT169 (169UL)
8089 #define TSW_SHACL_ENT170 (170UL)
8090 #define TSW_SHACL_ENT171 (171UL)
8091 #define TSW_SHACL_ENT172 (172UL)
8092 #define TSW_SHACL_ENT173 (173UL)
8093 #define TSW_SHACL_ENT174 (174UL)
8094 #define TSW_SHACL_ENT175 (175UL)
8095 #define TSW_SHACL_ENT176 (176UL)
8096 #define TSW_SHACL_ENT177 (177UL)
8097 #define TSW_SHACL_ENT178 (178UL)
8098 #define TSW_SHACL_ENT179 (179UL)
8099 #define TSW_SHACL_ENT180 (180UL)
8100 #define TSW_SHACL_ENT181 (181UL)
8101 #define TSW_SHACL_ENT182 (182UL)
8102 #define TSW_SHACL_ENT183 (183UL)
8103 #define TSW_SHACL_ENT184 (184UL)
8104 #define TSW_SHACL_ENT185 (185UL)
8105 #define TSW_SHACL_ENT186 (186UL)
8106 #define TSW_SHACL_ENT187 (187UL)
8107 #define TSW_SHACL_ENT188 (188UL)
8108 #define TSW_SHACL_ENT189 (189UL)
8109 #define TSW_SHACL_ENT190 (190UL)
8110 #define TSW_SHACL_ENT191 (191UL)
8111 #define TSW_SHACL_ENT192 (192UL)
8112 #define TSW_SHACL_ENT193 (193UL)
8113 #define TSW_SHACL_ENT194 (194UL)
8114 #define TSW_SHACL_ENT195 (195UL)
8115 #define TSW_SHACL_ENT196 (196UL)
8116 #define TSW_SHACL_ENT197 (197UL)
8117 #define TSW_SHACL_ENT198 (198UL)
8118 #define TSW_SHACL_ENT199 (199UL)
8119 #define TSW_SHACL_ENT200 (200UL)
8120 #define TSW_SHACL_ENT201 (201UL)
8121 #define TSW_SHACL_ENT202 (202UL)
8122 #define TSW_SHACL_ENT203 (203UL)
8123 #define TSW_SHACL_ENT204 (204UL)
8124 #define TSW_SHACL_ENT205 (205UL)
8125 #define TSW_SHACL_ENT206 (206UL)
8126 #define TSW_SHACL_ENT207 (207UL)
8127 #define TSW_SHACL_ENT208 (208UL)
8128 #define TSW_SHACL_ENT209 (209UL)
8129 #define TSW_SHACL_ENT210 (210UL)
8130 #define TSW_SHACL_ENT211 (211UL)
8131 #define TSW_SHACL_ENT212 (212UL)
8132 #define TSW_SHACL_ENT213 (213UL)
8133 #define TSW_SHACL_ENT214 (214UL)
8134 #define TSW_SHACL_ENT215 (215UL)
8135 #define TSW_SHACL_ENT216 (216UL)
8136 #define TSW_SHACL_ENT217 (217UL)
8137 #define TSW_SHACL_ENT218 (218UL)
8138 #define TSW_SHACL_ENT219 (219UL)
8139 #define TSW_SHACL_ENT220 (220UL)
8140 #define TSW_SHACL_ENT221 (221UL)
8141 #define TSW_SHACL_ENT222 (222UL)
8142 #define TSW_SHACL_ENT223 (223UL)
8143 #define TSW_SHACL_ENT224 (224UL)
8144 #define TSW_SHACL_ENT225 (225UL)
8145 #define TSW_SHACL_ENT226 (226UL)
8146 #define TSW_SHACL_ENT227 (227UL)
8147 #define TSW_SHACL_ENT228 (228UL)
8148 #define TSW_SHACL_ENT229 (229UL)
8149 #define TSW_SHACL_ENT230 (230UL)
8150 #define TSW_SHACL_ENT231 (231UL)
8151 #define TSW_SHACL_ENT232 (232UL)
8152 #define TSW_SHACL_ENT233 (233UL)
8153 #define TSW_SHACL_ENT234 (234UL)
8154 #define TSW_SHACL_ENT235 (235UL)
8155 #define TSW_SHACL_ENT236 (236UL)
8156 #define TSW_SHACL_ENT237 (237UL)
8157 #define TSW_SHACL_ENT238 (238UL)
8158 #define TSW_SHACL_ENT239 (239UL)
8159 #define TSW_SHACL_ENT240 (240UL)
8160 #define TSW_SHACL_ENT241 (241UL)
8161 #define TSW_SHACL_ENT242 (242UL)
8162 #define TSW_SHACL_ENT243 (243UL)
8163 #define TSW_SHACL_ENT244 (244UL)
8164 #define TSW_SHACL_ENT245 (245UL)
8165 #define TSW_SHACL_ENT246 (246UL)
8166 #define TSW_SHACL_ENT247 (247UL)
8167 #define TSW_SHACL_ENT248 (248UL)
8168 #define TSW_SHACL_ENT249 (249UL)
8169 #define TSW_SHACL_ENT250 (250UL)
8170 #define TSW_SHACL_ENT251 (251UL)
8171 #define TSW_SHACL_ENT252 (252UL)
8172 #define TSW_SHACL_ENT253 (253UL)
8173 #define TSW_SHACL_ENT254 (254UL)
8174 #define TSW_SHACL_ENT255 (255UL)
8175 
8176 /* RXFIFO register group index macro definition */
8177 #define TSW_RXFIFO_E1 (0UL)
8178 #define TSW_RXFIFO_P1 (1UL)
8179 
8180 /* TSNPORT register group index macro definition */
8181 #define TSW_TSNPORT_PORT1 (0UL)
8182 #define TSW_TSNPORT_PORT2 (1UL)
8183 #define TSW_TSNPORT_PORT3 (2UL)
8184 
8185 
8186 #endif /* HPM_TSW_H */
TSW_Type
Definition: hpm_tsw_regs.h:12