HPM SDK
HPMicro Software Development Kit
hpm_wm8978_regs.h
Go to the documentation of this file.
1
/*
2
* Copyright (c) 2024 HPMicro
3
*
4
* SPDX-License-Identifier: BSD-3-Clause
5
*
6
*/
7
8
#ifndef _HPM_WM8978_REG_H_
9
#define _HPM_WM8978_REG_H_
10
11
/* Define the register address of WM8978 */
12
#define WM8978_RESET 0x00U
/* software reset */
13
#define WM8978_POWER_MANAGET_1 0x01U
/* power managet 1 */
14
#define WM8978_POWER_MANAGET_2 0x02U
/* power managet 2 */
15
#define WM8978_POWER_MANAGET_3 0x03U
/* power managet 3 */
16
#define WM8978_AUDIO_INTERFACE 0x04U
/* audio interface */
17
#define WM8978_CLOCK_GEN_CTRL 0x06U
/* clock gen ctrl */
18
#define WM8978_GPIO_CTRL 0x08U
/* GPIO ctrl */
19
#define WM8978_DAC_CTRL 0x0AU
/* DAC ctrl */
20
#define WM8978_LEFT_DAC_VOL 0x0BU
/* Left DAC digital vol */
21
#define WM8978_RIGHT_DAC_VOL 0x0CU
/* Right DAC digital vol */
22
#define WM8978_ADC_CONTROL 0x0EU
/* ADC control */
23
#define WM8978_LEFT_ADC_VOL 0x0FU
/* Left ADC digital vol */
24
#define WM8978_RIGHT_ADC_VOL 0x10U
/* Right ADC digital vol */
25
#define WM8978_NOTCH_FILTER1 0x1BU
/* notch filter1 */
26
#define WM8978_NOTCH_FILTER2 0x1CU
/* notch filter2 */
27
#define WM8978_NOTCH_FILTER3 0x1DU
/* notch filter3 */
28
#define WM8978_NOTCH_FILTER4 0x1EU
/* notch filter4 */
29
#define WM8978_ALC_CONTROL1 0x20U
/* ALC control1 */
30
#define WM8978_ALC_CONTROL2 0x21U
/* ALC control2 */
31
#define WM8978_ALC_CONTROL3 0x22U
/* ALC control3 */
32
#define WM8978_NOISE_GATE 0x23U
/* noise Gate */
33
#define WM8978_BEEP_CONTROL 0x2BU
/* beep control */
34
#define WM8978_INPUT_CTRL 0x2CU
/* input ctrl */
35
#define WM8978_LOUT1_VOLUME_CTRL 0x34U
/* LOUT1 (HP)volume ctrl */
36
#define WM8978_ROUT1_VOLUME_CTRL 0x35U
/* ROUT1 (HP)volume ctrl */
37
#define WM8978_LOUT2_VOLUME_CTRL 0x36U
/* LOUT2 (SPK)volume ctrl */
38
#define WM8978_ROUT2_VOLUME_CTRL 0x37U
/* ROUT2 (SPK)volume ctrl */
39
#define WM8978_LINP_PGA_GAIM_CTRL 0x2DU
/* Left INP PGA gain ctrl */
40
#define WM8978_RINP_PGA_GAIM_CTRL 0x2EU
/* Right INP PGA gain ctrl */
41
#define WM8978_LADC_BOOST_CTRL 0x2FU
/* Left INP PGA gain ctrl */
42
#define WM8978_RADC_BOOST_CTRL 0x30U
/* Right INP PGA gain ctrl */
43
#define WM8978_OUTPUT_CTRL 0x31U
/* Output ctrl */
44
#define WM8978_LEFT_MIXER_CTRL 0x32U
/* left mixer ctrl */
45
#define WM8978_RIGHT_MIXER_CTRL 0x33U
/* right mixer ctrl */
46
#define WM8978_OUT3_MIXER_CTRL 0x38U
/* out3 mixer ctrl */
47
#define WM8978_OUT4_MIXER_CTRL 0x39U
/* out4 mixer ctrl */
48
49
/*
50
* BUFDCOPEN (RW)
51
* Dedicated buffer for DC level shifting output stages when in 1.5x gain boost configuration
52
*/
53
#define WM8978_BUFDCOPEN_R1_MASK (0x100U)
54
#define WM8978_BUFDCOPEN_R1_SHIFT (8U)
55
#define WM8978_BUFDCOPEN_R1_SET(x) (((uint16_t)(x) << WM8978_BUFDCOPEN_R1_SHIFT) & WM8978_BUFDCOPEN_R1_MASK)
56
#define WM8978_BUFDCOPEN_R1_GET(x) (((uint16_t)(x) & WM8978_BUFDCOPEN_R1_MASK) >> WM8978_BUFDCOPEN_R1_SHIFT)
57
58
/*
59
* OUT4MIXEN (RW)
60
* OUT4 mixer enable
61
*/
62
#define WM8978_OUT4MIXEN_R1_MASK (0x80U)
63
#define WM8978_OUT4MIXEN_R1_SHIFT (7U)
64
#define WM8978_OUT4MIXEN_R1_SET(x) (((uint16_t)(x) << WM8978_OUT4MIXEN_R1_SHIFT) & WM8978_OUT4MIXEN_R1_MASK)
65
#define WM8978_OUT4MIXEN_R1_GET(x) (((uint16_t)(x) & WM8978_OUT4MIXEN_R1_MASK) >> WM8978_OUT4MIXEN_R1_SHIFT)
66
67
/*
68
* OUT3MIXEN (RW)
69
* OUT3 mixer enable
70
*/
71
#define WM8978_OUT3MIXEN_R1_MASK (0x40U)
72
#define WM8978_OUT3MIXEN_R1_SHIFT (6U)
73
#define WM8978_OUT3MIXEN_R1_SET(x) (((uint16_t)(x) << WM8978_OUT3MIXEN_R1_SHIFT) & WM8978_OUT3MIXEN_R1_MASK)
74
#define WM8978_OUT3MIXEN_R1_GET(x) (((uint16_t)(x) & WM8978_OUT3MIXEN_R1_MASK) >> WM8978_OUT3MIXEN_R1_SHIFT)
75
76
/*
77
* PLLEN (RW)
78
* PLL enable
79
*/
80
#define WM8978_PLLEN_R1_MASK (0x20U)
81
#define WM8978_PLLEN_R1_SHIFT (5U)
82
#define WM8978_PLLEN_R1_SET(x) (((uint16_t)(x) << WM8978_PLLEN_R1_SHIFT) & WM8978_PLLEN_R1_MASK)
83
#define WM8978_PLLEN_R1_GET(x) (((uint16_t)(x) & WM8978_PLLEN_R1_MASK) >> WM8978_PLLEN_R1_SHIFT)
84
85
/*
86
* MICBEN (RW)
87
* Microphone Bias Enable
88
*/
89
#define WM8978_MICBEN_R1_MASK (0x10U)
90
#define WM8978_MICBEN_R1_SHIFT (4U)
91
#define WM8978_MICBEN_R1_SET(x) (((uint16_t)(x) << WM8978_MICBEN_R1_SHIFT) & WM8978_MICBEN_R1_MASK)
92
#define WM8978_MICBEN_R1_GET(x) (((uint16_t)(x) & WM8978_MICBEN_R1_MASK) >> WM8978_MICBEN_R1_SHIFT)
93
94
/*
95
* BIASEN (RW)
96
* Analogue amplifier bias control
97
*/
98
#define WM8978_BIASEN_R1_MASK (0x08U)
99
#define WM8978_BIASEN_R1_SHIFT (3U)
100
#define WM8978_BIASEN_R1_SET(x) (((uint16_t)(x) << WM8978_BIASEN_R1_SHIFT) & WM8978_BIASEN_R1_MASK)
101
#define WM8978_BIASEN_R1_GET(x) (((uint16_t)(x) & WM8978_BIASEN_R1_MASK) >> WM8978_BIASEN_R1_SHIFT)
102
103
104
/*
105
* BUFIOEN (RW)
106
* Unused input/output tie off buffer enable
107
*/
108
#define WM8978_BUFIOEN_R1_MASK (0x04U)
109
#define WM8978_BUFIOEN_R1_SHIFT (2U)
110
#define WM8978_BUFIOEN_R1_SET(x) (((uint16_t)(x) << WM8978_BUFIOEN_R1_SHIFT) & WM8978_BUFIOEN_R1_MASK)
111
#define WM8978_BUFIOEN_R1_GET(x) (((uint16_t)(x) & WM8978_BUFIOEN_R1_MASK) >> WM8978_BUFIOEN_R1_SHIFT)
112
113
/*
114
* VMIDSEL (RW)
115
* Reference string impedance to VMID pin
116
*/
117
#define WM8978_VMIDSEL_R1_MASK (0x03U)
118
#define WM8978_VMIDSEL_R1_SHIFT (0U)
119
#define WM8978_VMIDSEL_R1_SET(x) (((uint16_t)(x) << WM8978_VMIDSEL_R1_SHIFT) & WM8978_VMIDSEL_R1_MASK)
120
#define WM8978_VMIDSEL_R1_GET(x) (((uint16_t)(x) & WM8978_VMIDSEL_R1_MASK) >> WM8978_VMIDSEL_R1_SHIFT)
121
122
/*
123
* ROUT1EN (RW)
124
* ROUT1 output enable
125
*/
126
#define WM8978_ROUT1EN_R2_MASK (0x100U)
127
#define WM8978_ROUT1EN_R2_SHIFT (8U)
128
#define WM8978_ROUT1EN_R2_SET(x) (((uint16_t)(x) << WM8978_ROUT1EN_R2_SHIFT) & WM8978_ROUT1EN_R2_MASK)
129
#define WM8978_ROUT1EN_R2_GET(x) (((uint16_t)(x) & WM8978_ROUT1EN_R2_MASK) >> WM8978_ROUT1EN_R2_SHIFT)
130
131
/*
132
* LOUT1EN (RW)
133
* LOUT1 output enable
134
*/
135
#define WM8978_LOUT1EN_R2_MASK (0x80U)
136
#define WM8978_LOUT1EN_R2_SHIFT (7U)
137
#define WM8978_LOUT1EN_R2_SET(x) (((uint16_t)(x) << WM8978_LOUT1EN_R2_SHIFT) & WM8978_LOUT1EN_R2_MASK)
138
#define WM8978_LOUT1EN_R2_GET(x) (((uint16_t)(x) & WM8978_LOUT1EN_R2_MASK) >> WM8978_LOUT1EN_R2_SHIFT)
139
140
/*
141
* SLEEP (RW)
142
* residual current reduced in device standby mode if 1
143
*/
144
#define WM8978_SLEEP_R2_MASK (0x40U)
145
#define WM8978_SLEEP_R2_SHIFT (6U)
146
#define WM8978_SLEEP_R2_SET(x) (((uint16_t)(x) << WM8978_SLEEP_R2_SHIFT) & WM8978_SLEEP_R2_MASK)
147
#define WM8978_SLEEP_R2_GET(x) (((uint16_t)(x) & WM8978_SLEEP_R2_MASK) >> WM8978_SLEEP_R2_SHIFT)
148
149
/*
150
* BOOSTENR (RW)
151
* Right channel Input BOOST enable
152
*/
153
#define WM8978_BOOSTENR_R2_MASK (0x20U)
154
#define WM8978_BOOSTENR_R2_SHIFT (5U)
155
#define WM8978_BOOSTENR_R2_SET(x) (((uint16_t)(x) << WM8978_BOOSTENR_R2_SHIFT) & WM8978_BOOSTENR_R2_MASK)
156
#define WM8978_BOOSTENR_R2_GET(x) (((uint16_t)(x) & WM8978_BOOSTENR_R2_MASK) >> WM8978_BOOSTENR_R2_SHIFT)
157
158
/*
159
* BOOSTENL (RW)
160
* Left channel Input BOOST enable
161
*/
162
#define WM8978_BOOSTENL_R2_MASK (0x10U)
163
#define WM8978_BOOSTENL_R2_SHIFT (4U)
164
#define WM8978_BOOSTENL_R2_SET(x) (((uint16_t)(x) << WM8978_BOOSTENL_R2_SHIFT) & WM8978_BOOSTENL_R2_MASK)
165
#define WM8978_BOOSTENL_R2_GET(x) (((uint16_t)(x) & WM8978_BOOSTENL_R2_MASK) >> WM8978_BOOSTENL_R2_SHIFT)
166
167
/*
168
* INPPGAENR (RW)
169
* Right channel input PGA enable
170
*/
171
#define WM8978_INPPGAENR_R2_MASK (0x08U)
172
#define WM8978_INPPGAENR_R2_SHIFT (3U)
173
#define WM8978_INPPGAENR_R2_SET(x) (((uint16_t)(x) << WM8978_INPPGAENR_R2_SHIFT) & WM8978_INPPGAENR_R2_MASK)
174
#define WM8978_INPPGAENR_R2_GET(x) (((uint16_t)(x) & WM8978_INPPGAENR_R2_MASK) >> WM8978_INPPGAENR_R2_SHIFT)
175
176
177
/*
178
* INPPGAENL (RW)
179
* Left channel input PGA enable
180
*/
181
#define WM8978_INPPGAENL_R2_MASK (0x04U)
182
#define WM8978_INPPGAENL_R2_SHIFT (2U)
183
#define WM8978_INPPGAENL_R2_SET(x) (((uint16_t)(x) << WM8978_INPPGAENL_R2_SHIFT) & WM8978_INPPGAENL_R2_MASK)
184
#define WM8978_INPPGAENL_R2_GET(x) (((uint16_t)(x) & WM8978_INPPGAENL_R2_MASK) >> WM8978_INPPGAENL_R2_SHIFT)
185
186
/*
187
* ADCENR (RW)
188
* Enable ADC right channel
189
*/
190
#define WM8978_ADCENR_R2_MASK (0x02U)
191
#define WM8978_ADCENR_R2_SHIFT (1U)
192
#define WM8978_ADCENR_R2_SET(x) (((uint16_t)(x) << WM8978_ADCENR_R2_SHIFT) & WM8978_ADCENR_R2_MASK)
193
#define WM8978_ADCENR_R2_GET(x) (((uint16_t)(x) & WM8978_ADCENR_R2_MASK) >> WM8978_ADCENR_R2_SHIFT)
194
195
/*
196
* ADCENL (RW)
197
* Enable ADC left channel
198
*/
199
#define WM8978_ADCENL_R2_MASK (0x01U)
200
#define WM8978_ADCENL_R2_SHIFT (0U)
201
#define WM8978_ADCENL_R2_SET(x) (((uint16_t)(x) << WM8978_ADCENL_R2_SHIFT) & WM8978_ADCENL_R2_MASK)
202
#define WM8978_ADCENL_R2_GET(x) (((uint16_t)(x) & WM8978_ADCENL_R2_MASK) >> WM8978_ADCENL_R2_SHIFT)
203
204
/*
205
* MBVSEL (RW)
206
* Microphone Bias Voltage Control
207
*/
208
#define WM8978_OUT4EN_R3_MASK (0x100U)
209
#define WM8978_OUT4EN_R3_SHIFT (8U)
210
#define WM8978_OUT4EN_R3_SET(x) (((uint16_t)(x) << WM8978_OUT4EN_R3_SHIFT) & WM8978_OUT4EN_R3_MASK)
211
#define WM8978_OUT4EN_R3_GET(x) (((uint16_t)(x) & WM8978_OUT4EN_R3_MASK) >> WM8978_OUT4EN_R3_SHIFT)
212
213
/*
214
* OUT3EN (RW)
215
* OUT3 enable
216
*/
217
#define WM8978_OUT3EN_R3_MASK (0x80U)
218
#define WM8978_OUT3EN_R3_SHIFT (7U)
219
#define WM8978_OUT3EN_R3_SET(x) (((uint16_t)(x) << WM8978_OUT3EN_R3_SHIFT) & WM8978_OUT3EN_R3_MASK)
220
#define WM8978_OUT3EN_R3_GET(x) (((uint16_t)(x) & WM8978_OUT3EN_R3_MASK) >> WM8978_OUT3EN_R3_SHIFT)
221
222
/*
223
* LOUT2EN (RW)
224
* LOUT2 enable
225
*/
226
#define WM8978_LOUT2EN_R3_MASK (0x40U)
227
#define WM8978_LOUT2EN_R3_SHIFT (6U)
228
#define WM8978_LOUT2EN_R3_SET(x) (((uint16_t)(x) << WM8978_LOUT2EN_R3_SHIFT) & WM8978_LOUT2EN_R3_MASK)
229
#define WM8978_LOUT2EN_R3_GET(x) (((uint16_t)(x) & WM8978_LOUT2EN_R3_MASK) >> WM8978_LOUT2EN_R3_SHIFT)
230
231
/*
232
* ROUT2EN (RW)
233
* ROUT2 enable
234
*/
235
#define WM8978_ROUT2EN_R3_MASK (0x20U)
236
#define WM8978_ROUT2EN_R3_SHIFT (5U)
237
#define WM8978_ROUT2EN_R3_SET(x) (((uint16_t)(x) << WM8978_ROUT2EN_R3_SHIFT) & WM8978_ROUT2EN_R3_MASK)
238
#define WM8978_ROUT2EN_R3_GET(x) (((uint16_t)(x) & WM8978_ROUT2EN_R3_MASK) >> WM8978_ROUT2EN_R3_SHIFT)
239
240
/*
241
* RMIXEN (RW)
242
* Right output channel mixer enable
243
*/
244
#define WM8978_RMIXEN_R3_MASK (0x08U)
245
#define WM8978_RMIXEN_R3_SHIFT (3U)
246
#define WM8978_RMIXEN_R3_SET(x) (((uint16_t)(x) << WM8978_RMIXEN_R3_SHIFT) & WM8978_RMIXEN_R3_MASK)
247
#define WM8978_RMIXEN_R3_GET(x) (((uint16_t)(x) & WM8978_RMIXEN_R3_MASK) >> WM8978_RMIXEN_R3_SHIFT)
248
249
/*
250
* LMIXEN (RW)
251
* Left output channel mixer enable
252
*/
253
#define WM8978_LMIXEN_R3_MASK (0x04U)
254
#define WM8978_LMIXEN_R3_SHIFT (2U)
255
#define WM8978_LMIXEN_R3_SET(x) (((uint16_t)(x) << WM8978_LMIXEN_R3_SHIFT) & WM8978_LMIXEN_R3_MASK)
256
#define WM8978_LMIXEN_R3_GET(x) (((uint16_t)(x) & WM8978_LMIXEN_R3_MASK) >> WM8978_LMIXEN_R3_SHIFT)
257
258
/*
259
* DACENR (RW)
260
* Right channel DAC enable
261
*/
262
#define WM8978_DACENR_R3_MASK (0x02U)
263
#define WM8978_DACENR_R3_SHIFT (1U)
264
#define WM8978_DACENR_R3_SET(x) (((uint16_t)(x) << WM8978_DACENR_R3_SHIFT) & WM8978_DACENR_R3_MASK)
265
#define WM8978_DACENR_R3_GET(x) (((uint16_t)(x) & WM8978_DACENR_R3_MASK) >> WM8978_DACENR_R3_SHIFT)
266
267
/*
268
* DACENL (RW)
269
* Left channel DAC enable
270
*/
271
#define WM8978_DACENL_R3_MASK (0x01U)
272
#define WM8978_DACENL_R3_SHIFT (0U)
273
#define WM8978_DACENL_R3_SET(x) (((uint16_t)(x) << WM8978_DACENL_R3_SHIFT) & WM8978_DACENL_R3_MASK)
274
#define WM8978_DACENL_R3_GET(x) (((uint16_t)(x) & WM8978_DACENL_R3_MASK) >> WM8978_DACENL_R3_SHIFT)
275
276
/*
277
* HPFEN (RW)
278
* High Pass Filter Enable
279
*/
280
#define WM8978_HPFEN_R14_MASK (0x100U)
281
#define WM8978_HPFEN_R14_SHIFT (8U)
282
#define WM8978_HPFEN_R14_SET(x) (((uint16_t)(x) << WM8978_HPFEN_R14_SHIFT) & WM8978_HPFEN_R14_MASK)
283
#define WM8978_HPFEN_R14_GET(x) (((uint16_t)(x) & WM8978_HPFEN_R14_MASK) >> WM8978_HPFEN_R14_SHIFT)
284
285
/*
286
* ADCOSR128 (RW)
287
* ADC oversample rate select
288
*/
289
#define WM8978_ADCOSR128_R14_MASK (0x08U)
290
#define WM8978_ADCOSR128_R14_SHIFT (3U)
291
#define WM8978_ADCOSR128_R14_SET(x) (((uint16_t)(x) << WM8978_ADCOSR128_R14_SHIFT) & WM8978_ADCOSR128_R14_MASK)
292
#define WM8978_ADCOSR128_R14_GET(x) (((uint16_t)(x) & WM8978_ADCOSR128_R14_MASK) >> WM8978_ADCOSR128_R14_SHIFT)
293
294
/*
295
* ADCRPOL (RW)
296
* ADC right channel polarity adjust
297
*/
298
#define WM8978_ADCRPOL_R14_MASK (0x02U)
299
#define WM8978_ADCRPOL_R14_SHIFT (1U)
300
#define WM8978_ADCRPOL_R14_SET(x) (((uint16_t)(x) << WM8978_ADCRPOL_R14_SHIFT) & WM8978_ADCRPOL_R14_MASK)
301
#define WM8978_ADCRPOL_R14_GET(x) (((uint16_t)(x) & WM8978_ADCRPOL_R14_MASK) >> WM8978_ADCRPOL_R14_SHIFT)
302
303
/*
304
* ADCLPOL (RW)
305
* ADC left channel polarity adjust
306
*/
307
#define WM8978_ADCLPOL_R14_MASK (0x01U)
308
#define WM8978_ADCLPOL_R14_SHIFT (0U)
309
#define WM8978_ADCLPOL_R14_SET(x) (((uint16_t)(x) << WM8978_ADCLPOL_R14_SHIFT) & WM8978_ADCLPOL_R14_MASK)
310
#define WM8978_ADCLPOL_R14_GET(x) (((uint16_t)(x) & WM8978_ADCLPOL_R14_MASK) >> WM8978_ADCLPOL_R14_SHIFT)
311
312
/*
313
* MBVSEL (RW)
314
* Microphone Bias Voltage Control
315
*/
316
#define WM8978_MBVSEL_R44_MASK (0x100U)
317
#define WM8978_MBVSEL_R44_SHIFT (8U)
318
#define WM8978_MBVSEL_R44_SET(x) (((uint16_t)(x) << WM8978_MBVSEL_R44_SHIFT) & WM8978_MBVSEL_R44_MASK)
319
#define WM8978_MBVSEL_R44_GET(x) (((uint16_t)(x) & WM8978_MBVSEL_R44_MASK) >> WM8978_MBVSEL_R44_SHIFT)
320
321
/*
322
* R2_2INPPGA (RW)
323
* Connect R2 pin to right channel input PGA positive terminal
324
*/
325
#define WM8978_R2_2INPPGA_R44_MASK (0x40U)
326
#define WM8978_R2_2INPPGA_R44_SHIFT (6U)
327
#define WM8978_R2_2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_R2_2INPPGA_R44_SHIFT) & WM8978_R2_2INPPGA_R44_MASK)
328
#define WM8978_R2_2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_R2_2INPPGA_R44_MASK) >> WM8978_R2_2INPPGA_R44_SHIFT)
329
330
/*
331
* RIN2INPPGA (RW)
332
* Connect RIN pin to right channel input PGA negative terminaL
333
*/
334
#define WM8978_RIN2INPPGA_R44_MASK (0x20U)
335
#define WM8978_RIN2INPPGA_R44_SHIFT (5U)
336
#define WM8978_RIN2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_RIN2INPPGA_R44_SHIFT) & WM8978_RIN2INPPGA_R44_MASK)
337
#define WM8978_RIN2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_RIN2INPPGA_R44_MASK) >> WM8978_RIN2INPPGA_R44_SHIFT)
338
339
/*
340
* RIP2INPPGA (RW)
341
* Connect RIP pin to right channel input PGA amplifier positive terminal
342
*/
343
#define WM8978_RIP2INPPGA_R44_MASK (0x10U)
344
#define WM8978_RIP2INPPGA_R44_SHIFT (4U)
345
#define WM8978_RIP2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_RIP2INPPGA_R44_SHIFT) & WM8978_RIP2INPPGA_R44_MASK)
346
#define WM8978_RIP2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_RIP2INPPGA_R44_MASK) >> WM8978_RIP2INPPGA_R44_SHIFT)
347
348
/*
349
* L2_2INPPGA (RW)
350
* Connect L2 pin to left channel input PGA positive terminal
351
*/
352
#define WM8978_L2_2INPPGA_R44_MASK (0x04U)
353
#define WM8978_L2_2INPPGA_R44_SHIFT (2U)
354
#define WM8978_L2_2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_L2_2INPPGA_R44_SHIFT) & WM8978_L2_2INPPGA_R44_MASK)
355
#define WM8978_L2_2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_L2_2INPPGA_R44_MASK) >> WM8978_L2_2INPPGA_R44_SHIFT)
356
357
/*
358
* LIN2INPPGA (RW)
359
* Connect LIN pin to left channel input PGA negative terminal
360
*/
361
#define WM8978_LIN2INPPGA_R44_MASK (0x02U)
362
#define WM8978_LIN2INPPGA_R44_SHIFT (1U)
363
#define WM8978_LIN2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_LIN2INPPGA_R44_SHIFT) & WM8978_LIN2INPPGA_R44_MASK)
364
#define WM8978_LIN2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_LIN2INPPGA_R44_MASK) >> WM8978_LIN2INPPGA_R44_SHIFT)
365
366
/*
367
* DACENL (RW)
368
* Connect LIP pin to left channel input PGA amplifier positive terminal
369
*/
370
#define WM8978_LIP2INPPGA_R44_MASK (0x01U)
371
#define WM8978_LIP2INPPGA_R44_SHIFT (0U)
372
#define WM8978_LIP2INPPGA_R44_SET(x) (((uint16_t)(x) << WM8978_LIP2INPPGA_R44_SHIFT) & WM8978_LIP2INPPGA_R44_MASK)
373
#define WM8978_LIP2INPPGA_R44_GET(x) (((uint16_t)(x) & WM8978_LIP2INPPGA_R44_MASK) >> WM8978_LIP2INPPGA_R44_SHIFT)
374
375
/*
376
* BCP (RW)
377
* BCLK polarity
378
* for 0x04 reg
379
*/
380
#define WM8978_BCP_MASK (0x100U)
381
#define WM8978_BCP_SHIFT (8U)
382
#define WM8978_BCP_SET(x) (((uint16_t)(x) << WM8978_BCP_SHIFT) & WM8978_BCP_MASK)
383
#define WM8978_BCP_GET(x) (((uint16_t)(x) & WM8978_BCP_MASK) >> WM8978_BCP_SHIFT)
384
385
/*
386
* LRP (RW)
387
* LRC clock polarity
388
* for 0x04 reg
389
*/
390
#define WM8978_LRP_MASK (0x80U)
391
#define WM8978_LRP_SHIFT (7U)
392
#define WM8978_LRP_SET(x) (((uint16_t)(x) << WM8978_LRP_SHIFT) & WM8978_LRP_MASK)
393
#define WM8978_LRP_GET(x) (((uint16_t)(x) & WM8978_LRP_MASK) >> WM8978_LRP_SHIFT)
394
395
/*
396
* WL (RW)
397
* word length
398
* for 0x04 reg
399
*/
400
#define WM8978_WL_MASK (0x60U)
401
#define WM8978_WL_SHIFT (5U)
402
#define WM8978_WL_SET(x) (((uint16_t)(x) << WM8978_WL_SHIFT) & WM8978_WL_MASK)
403
#define WM8978_WL_GET(x) (((uint16_t)(x) & WM8978_WL_MASK) >> WM8978_WL_SHIFT)
404
405
/*
406
* FMT (RW)
407
* addio interface data format select
408
* for 0x04 reg
409
*/
410
#define WM8978_FMT_MASK (0x18U)
411
#define WM8978_FMT_SHIFT (3U)
412
#define WM8978_FMT_SET(x) (((uint16_t)(x) << WM8978_FMT_SHIFT) & WM8978_FMT_MASK)
413
#define WM8978_FMT_GET(x) (((uint16_t)(x) & WM8978_FMT_MASK) >> WM8978_FMT_SHIFT)
414
415
/*
416
* DACLRSWAP (RW)
417
* Controls whether DAC data appears in 'right'orleft’ phases of LRC clock
418
* for 0x04 reg
419
*/
420
#define WM8978_DACLRSWAP_MASK (0x04U)
421
#define WM8978_DACLRSWAP_SHIFT (2U)
422
#define WM8978_DACLRSWAP_SET(x) (((uint16_t)(x) << WM8978_DACLRSWAP_SHIFT) & WM8978_DACLRSWAP_MASK)
423
#define WM8978_DACLRSWAP_GET(x) (((uint16_t)(x) & WM8978_DACLRSWAP_MASK) >> WM8978_DACLRSWAP_SHIFT)
424
425
/*
426
* ADCLRSWAP (RW)
427
* Controls whether ADC data appears in 'right' orleft’ phases of LRC clock
428
* for 0x04 reg
429
*/
430
#define WM8978_ADCLRSWAP_MASK (0x02U)
431
#define WM8978_ADCLRSWAP_SHIFT (1U)
432
#define WM8978_ADCLRSWAP_SET(x) (((uint16_t)(x) << WM8978_ADCLRSWAP_SHIFT) & WM8978_ADCLRSWAP_MASK)
433
#define WM8978_ADCLRSWAP_GET(x) (((uint16_t)(x) & WM8978_ADCLRSWAP_MASK) >> WM8978_ADCLRSWAP_SHIFT)
434
435
/*
436
* MONO (RW)
437
* Selects between stereo and mono deviceoperation
438
* for 0x04 reg
439
*/
440
#define WM8978_MONO_MASK (0x01U)
441
#define WM8978_MONO_SHIFT (0U)
442
#define WM8978_MONO_SET(x) (((uint16_t)(x) << WM8978_MONO_SHIFT) & WM8978_MONO_MASK)
443
#define WM8978_MONO_GET(x) (((uint16_t)(x) & WM8978_MONO_MASK) >> WM8978_MONO_SHIFT)
444
445
/*
446
* ROUTVOL (RW)
447
*
448
* OUT Volume
449
* 000000 = -57dB
450
* 111001 = 0dB
451
* 111111 = 6dB
452
* for 0x34/0x35/0x36/0x37 regs
453
*/
454
#define WM8978_OUT_VOLUME_MASK (0x7FU)
455
#define WM8978_OUT_VOLUME_SHIFT (0U)
456
#define WM8978_OUT_VOLUME_SET(x) (((uint16_t)(x) << WM8978_OUT_VOLUME_SHIFT) & WM8978_OUT_VOLUME_MASK)
457
#define WM8978_OUT_VOLUME_GET(x) (((uint16_t)(x) & WM8978_OUT_VOLUME_MASK) >> WM8978_OUT_VOLUME_SHIFT)
458
459
/*
460
* OUT_SPKVU (RW)
461
* LOUT1/2 and ROUT1/2 volumes do not update untila 1 is written to SPKkVU
462
* for 0x34/0x35/0x36/0x37 regs
463
*/
464
#define WM8978_OUT_SPKVU_MASK (0x100U)
465
#define WM8978_OUT_SPKVU_SHIFT (8U)
466
#define WM8978_OUT_SPKVU_SET(x) (((uint16_t)(x) << WM8978_OUT_SPKVU_SHIFT) & WM8978_OUT_SPKVU_MASK)
467
#define WM8978_OUT_SPKVU_GET(x) (((uint16_t)(x) & WM8978_OUT_SPKVU_MASK) >> WM8978_OUT_SPKVU_SHIFT)
468
469
/*
470
* OUT_MUTE (RW)
471
* LOUT1/2 and ROUT1/2 headphone output mute
472
* for 0x34/0x35/0x36/0x37 regs
473
*/
474
#define WM8978_OUT_MUTE_MASK (0x40U)
475
#define WM8978_OUT_MUTE_SHIFT (6U)
476
#define WM8978_OUT_MUTE_SET(x) (((uint16_t)(x) << WM8978_OUT_MUTE_SHIFT) & WM8978_OUT_MUTE_MASK)
477
#define WM8978_OUT_MUTE_GET(x) (((uint16_t)(x) & WM8978_OUT_MUTE_MASK) >> WM8978_OUT_MUTE_SHIFT)
478
479
/*
480
* INPGA_UPDATE (RW)
481
* inpga update
482
* for 0x45/0x46 regs
483
*/
484
#define WM8978_INPGA_UPDATE_MASK (0x100U)
485
#define WM8978_INPGA_UPDATE_SHIFT (8U)
486
#define WM8978_INPGA_UPDATE_SET(x) (((uint16_t)(x) << WM8978_INPGA_UPDATE_SHIFT) & WM8978_INPGA_UPDATE_MASK)
487
#define WM8978_INPGA_UPDATE_GET(x) (((uint16_t)(x) & WM8978_INPGA_UPDATE_MASK) >> WM8978_INPGA_UPDATE_SHIFT)
488
489
/*
490
* NPPGAZCR/L (RW)
491
* Left/Right channel input PGA zero cross enable
492
* for 0x45/0x46 regs
493
*/
494
#define WM8978_NP_PGA_ZC_MASK (0x80U)
495
#define WM8978_NP_PGA_ZC_SHIFT (7U)
496
#define WM8978_NP_PGA_ZC_SET(x) (((uint16_t)(x) << WM8978_NP_PGA_ZC_SHIFT) & WM8978_NP_PGA_ZC_MASK)
497
#define WM8978_NP_PGA_ZC_GET(x) (((uint16_t)(x) & WM8978_NP_PGA_ZC_MASK) >> WM8978_NP_PGA_ZC_SHIFT)
498
499
/*
500
* NPPGA_MUTEL (RW)
501
* Mute control for left/right channel input PGA
502
* for 0x45/0x46 regs
503
*/
504
#define WM8978_INPPGA_MUTEL_MASK (0x40U)
505
#define WM8978_INPPGA_MUTEL_SHIFT (6U)
506
#define WM8978_INPPGA_MUTEL_SET(x) (((uint16_t)(x) << WM8978_INPPGA_MUTEL_SHIFT) & WM8978_INPPGA_MUTEL_MASK)
507
#define WM8978_INPPGA_MUTEL_GET(x) (((uint16_t)(x) & WM8978_INPPGA_MUTEL_MASK) >> WM8978_INPPGA_MUTEL_SHIFT)
508
509
/*
510
* INPPGA_VOL (RW)
511
* Left/Right channel input PGA volume
512
* for 0x2d/0x2e regs
513
*/
514
#define WM8978_INPPGA_VOL_MASK (0x3FU)
515
#define WM8978_INPPGA_VOL_SHIFT (0U)
516
#define WM8978_INPPGA_VOL_SET(x) (((uint16_t)(x) << WM8978_INPPGA_VOL_SHIFT) & WM8978_INPPGA_VOL_MASK)
517
#define WM8978_INPPGA_VOL_GET(x) (((uint16_t)(x) & WM8978_INPPGA_VOL_MASK) >> WM8978_INPPGA_VOL_SHIFT)
518
519
/*
520
* PGABOOST (RW)
521
* Boost enable for left/right channel input PGA
522
* for 0x2f/0x30 regs
523
*/
524
#define WM8978_PGABOOST_MASK (0x100U)
525
#define WM8978_PGABOOST_SHIFT (8U)
526
#define WM8978_PGABOOST_SET(x) (((uint16_t)(x) << WM8978_PGABOOST_SHIFT) & WM8978_PGABOOST_MASK)
527
#define WM8978_PGABOOST_GET(x) (((uint16_t)(x) & WM8978_PGABOOST_MASK) >> WM8978_PGABOOST_SHIFT)
528
529
/*
530
* LR2_2BOOSTVOL (RW)
531
* Controls the L2 pin to the left/right channel input
532
* for 0x2f/0x30 regs
533
*/
534
#define WM8978_2_2_BOOSTVOL_MASK (0x70U)
535
#define WM8978_2_2_BOOSTVOL_SHIFT (4U)
536
#define WM8978_2_2_BOOSTVOL_SET(x) (((uint16_t)(x) << WM8978_2_2_BOOSTVOL_SHIFT) & WM8978_2_2_BOOSTVOL_MASK)
537
#define WM8978_2_2_BOOSTVOL_GET(x) (((uint16_t)(x) & WM8978_2_2_BOOSTVOL_MASK) >> WM8978_2_2_BOOSTVOL_SHIFT)
538
539
/*
540
* AUXL2BOOSTVOL (RW)
541
* Controls the auxiliary amplifer to the left/right channelinput boost stage
542
* for 0x2f/0x30 regs
543
*/
544
#define WM8978_AUXL2BOOSTVOL_MASK (0x07U)
545
#define WM8978_AUXL2BOOSTVOL_SHIFT (0U)
546
#define WM8978_AUXL2BOOSTVOL_SET(x) (((uint16_t)(x) << WM8978_AUXL2BOOSTVOL_SHIFT) & WM8978_AUXL2BOOSTVOL_MASK)
547
#define WM8978_AUXL2BOOSTVOL_GET(x) (((uint16_t)(x) & WM8978_AUXL2BOOSTVOL_MASK) >> WM8978_AUXL2BOOSTVOL_SHIFT)
548
#endif
549
components
codec
wm8978
hpm_wm8978_regs.h
Generated on Tue Dec 31 2024 02:57:16 for HPM SDK by
1.9.1
1.9.1