7 #ifndef HPM_ENET_SOC_DRV_H
8 #define HPM_ENET_SOC_DRV_H
12 #if defined __cplusplus
76 if (
internal ==
true) {
104 #if defined __cplusplus
static hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal)
Definition: hpm_enet_soc_drv.h:70
static hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr)
Definition: hpm_enet_soc_drv.h:43
static hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type)
Definition: hpm_enet_soc_drv.h:16
static hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay)
Definition: hpm_enet_soc_drv.h:56
static hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr)
Definition: hpm_enet_soc_drv.h:90
static hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr)
Definition: hpm_enet_soc_drv.h:30
#define HPM_ENET0
Definition: hpm_soc_ip.h:374
#define ENET_CTRL2_ENET0_REFCLK_OE_MASK
Definition: hpm_enet_regs.h:5489
#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x)
Definition: hpm_enet_regs.h:5460
#define ENET_CTRL2_ENET0_PHY_INF_SEL_SET(x)
Definition: hpm_enet_regs.h:5503
#define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK
Definition: hpm_enet_regs.h:5501
#define ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK
Definition: hpm_enet_regs.h:5478
#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x)
Definition: hpm_enet_regs.h:5469
#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK
Definition: hpm_enet_regs.h:5467
#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK
Definition: hpm_enet_regs.h:5524
#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK
Definition: hpm_enet_regs.h:5458
uint32_t hpm_stat_t
Definition: hpm_common.h:135
@ status_invalid_argument
Definition: hpm_common.h:191
@ status_success
Definition: hpm_common.h:189
Definition: hpm_enet_regs.h:12
__RW uint32_t CTRL2
Definition: hpm_enet_regs.h:134
__RW uint32_t CTRL0
Definition: hpm_enet_regs.h:132