HPM SDK
HPMicro Software Development Kit
Data Fields
ENET_Type Struct Reference

#include <hpm_enet_regs.h>

Data Fields

__RW uint32_t MACCFG
 
__RW uint32_t MACFF
 
__RW uint32_t HASH_H
 
__RW uint32_t HASH_L
 
__RW uint32_t GMII_ADDR
 
__RW uint32_t GMII_DATA
 
__RW uint32_t FLOWCTRL
 
__RW uint32_t VLAN_TAG
 
__R uint8_t RESERVED0 [8]
 
__RW uint32_t RWKFRMFILT
 
__RW uint32_t PMT_CSR
 
__RW uint32_t LPI_CSR
 
__RW uint32_t LPI_TCR
 
__R uint32_t INTR_STATUS
 
__RW uint32_t INTR_MASK
 
__RW uint32_t MAC_ADDR_0_HIGH
 
__RW uint32_t MAC_ADDR_0_LOW
 
struct {
   __RW uint32_t   HIGH
 
   __RW uint32_t   LOW
 
} MAC_ADDR [4]
 
__R uint8_t RESERVED1 [112]
 
__RW uint32_t XMII_CSR
 
__RW uint32_t WDOG_WTO
 
__R uint8_t RESERVED2 [32]
 
__RW uint32_t MMC_CNTRL
 
__RW uint32_t MMC_INTR_RX
 
__RW uint32_t MMC_INTR_TX
 
__RW uint32_t MMC_INTR_MASK_RX
 
__RW uint32_t MMC_INTR_MASK_TX
 
__R uint8_t RESERVED3 [16]
 
__RW uint32_t TX64OCTETS_GB
 
__RW uint32_t TX65TO127OCTETS_GB
 
__RW uint32_t TX128TO255OCTETS_GB
 
__RW uint32_t TX256TO511OCTETS_GB
 
__RW uint32_t TX512TO1023OCTETS_GB
 
__RW uint32_t TX1024TOMAXOCTETS_GB
 
__R uint8_t RESERVED4 [68]
 
__RW uint32_t RXFRAMECOUNT_GB
 
__R uint8_t RESERVED5 [124]
 
__RW uint32_t MMC_IPC_INTR_MASK_RX
 
__R uint8_t RESERVED6 [4]
 
__RW uint32_t MMC_IPC_INTR_RX
 
__R uint8_t RESERVED7 [4]
 
__RW uint32_t RXIPV4_GD_FMS
 
__R uint8_t RESERVED8 [492]
 
struct {
   __RW uint32_t   L3_L4_CTRL
 
   __RW uint32_t   L4_ADDR
 
   __R uint8_t   RESERVED0 [8]
 
   __RW uint32_t   L3_ADDR_0
 
   __RW uint32_t   L3_ADDR_1
 
   __RW uint32_t   L3_ADDR_2
 
   __RW uint32_t   L3_ADDR_3
 
} L3_L4_CFG [1]
 
__R uint8_t RESERVED9 [356]
 
__RW uint32_t VLAN_TAG_INC_RPL
 
__RW uint32_t VLAN_HASH
 
__R uint8_t RESERVED10 [372]
 
__RW uint32_t TS_CTRL
 
__RW uint32_t SUB_SEC_INCR
 
__R uint32_t SYST_SEC
 
__R uint32_t SYST_NSEC
 
__RW uint32_t SYST_SEC_UPD
 
__RW uint32_t SYST_NSEC_UPD
 
__RW uint32_t TS_ADDEND
 
__RW uint32_t TGTTM_SEC
 
__RW uint32_t TGTTM_NSEC
 
__RW uint32_t SYSTM_H_SEC
 
__R uint32_t TS_STATUS
 
__RW uint32_t PPS_CTRL
 
__R uint32_t AUX_TS_NSEC
 
__R uint32_t AUX_TS_SEC
 
__R uint8_t RESERVED11 [40]
 
__RW uint32_t PPS0_INTERVAL
 
__RW uint32_t PPS0_WIDTH
 
__R uint8_t RESERVED12 [24]
 
struct {
   __RW uint32_t   TGTTM_SEC
 
   __RW uint32_t   TGTTM_NSEC
 
   __RW uint32_t   INTERVAL
 
   __RW uint32_t   WIDTH
 
   __R uint8_t   RESERVED0 [16]
 
} PPS [3]
 
__R uint8_t RESERVED13 [2080]
 
__RW uint32_t DMA_BUS_MODE
 
__RW uint32_t DMA_TX_POLL_DEMAND
 
__RW uint32_t DMA_RX_POLL_DEMAND
 
__RW uint32_t DMA_RX_DESC_LIST_ADDR
 
__RW uint32_t DMA_TX_DESC_LIST_ADDR
 
__RW uint32_t DMA_STATUS
 
__RW uint32_t DMA_OP_MODE
 
__RW uint32_t DMA_INTR_EN
 
__RW uint32_t DMA_MISS_OVF_CNT
 
__RW uint32_t DMA_RX_INTR_WDOG
 
__RW uint32_t DMA_AXI_MODE
 
__RW uint32_t DMA_BUS_STATUS
 
__R uint8_t RESERVED14 [24]
 
__RW uint32_t DMA_CURR_HOST_TX_DESC
 
__RW uint32_t DMA_CURR_HOST_RX_DESC
 
__RW uint32_t DMA_CURR_HOST_TX_BUF
 
__RW uint32_t DMA_CURR_HOST_RX_BUF
 
__R uint8_t RESERVED15 [8104]
 
__RW uint32_t CTRL0
 
__R uint8_t RESERVED16 [4]
 
__RW uint32_t CTRL2
 
__R uint8_t RESERVED17 [28]
 
struct {
   __RW uint32_t   HIGH
 
   __RW uint32_t   LOW
 
} MAC_ADDR [4]
 
struct {
   __RW uint32_t   L3_L4_CTRL
 
   __RW uint32_t   L4_ADDR
 
   __R uint8_t   RESERVED0 [8]
 
   __RW uint32_t   L3_ADDR_0
 
   __RW uint32_t   L3_ADDR_1
 
   __RW uint32_t   L3_ADDR_2
 
   __RW uint32_t   L3_ADDR_3
 
} L3_L4_CFG [1]
 
struct {
   __RW uint32_t   TGTTM_SEC
 
   __RW uint32_t   TGTTM_NSEC
 
   __RW uint32_t   INTERVAL
 
   __RW uint32_t   WIDTH
 
   __R uint8_t   RESERVED0 [16]
 
} PPS [3]
 
struct {
   __RW uint32_t   HIGH
 
   __RW uint32_t   LOW
 
} MAC_ADDR [4]
 
struct {
   __RW uint32_t   L3_L4_CTRL
 
   __RW uint32_t   L4_ADDR
 
   __R uint8_t   RESERVED0 [8]
 
   __RW uint32_t   L3_ADDR_0
 
   __RW uint32_t   L3_ADDR_1
 
   __RW uint32_t   L3_ADDR_2
 
   __RW uint32_t   L3_ADDR_3
 
} L3_L4_CFG [1]
 
struct {
   __RW uint32_t   TGTTM_SEC
 
   __RW uint32_t   TGTTM_NSEC
 
   __RW uint32_t   INTERVAL
 
   __RW uint32_t   WIDTH
 
   __R uint8_t   RESERVED0 [16]
 
} PPS [3]
 
struct {
   __RW uint32_t   HIGH
 
   __RW uint32_t   LOW
 
} MAC_ADDR [4]
 
struct {
   __RW uint32_t   L3_L4_CTRL
 
   __RW uint32_t   L4_ADDR
 
   __R uint8_t   RESERVED0 [8]
 
   __RW uint32_t   L3_ADDR_0
 
   __RW uint32_t   L3_ADDR_1
 
   __RW uint32_t   L3_ADDR_2
 
   __RW uint32_t   L3_ADDR_3
 
} L3_L4_CFG [1]
 
struct {
   __RW uint32_t   TGTTM_SEC
 
   __RW uint32_t   TGTTM_NSEC
 
   __RW uint32_t   INTERVAL
 
   __RW uint32_t   WIDTH
 
   __R uint8_t   RESERVED0 [16]
 
} PPS [3]
 
struct {
   __RW uint32_t   HIGH
 
   __RW uint32_t   LOW
 
} MAC_ADDR [4]
 
struct {
   __RW uint32_t   L3_L4_CTRL
 
   __RW uint32_t   L4_ADDR
 
   __R uint8_t   RESERVED0 [8]
 
   __RW uint32_t   L3_ADDR_0
 
   __RW uint32_t   L3_ADDR_1
 
   __RW uint32_t   L3_ADDR_2
 
   __RW uint32_t   L3_ADDR_3
 
} L3_L4_CFG [1]
 
struct {
   __RW uint32_t   TGTTM_SEC
 
   __RW uint32_t   TGTTM_NSEC
 
   __RW uint32_t   INTERVAL
 
   __RW uint32_t   WIDTH
 
   __R uint8_t   RESERVED0 [16]
 
} PPS [3]
 
struct {
   __RW uint32_t   HIGH
 
   __RW uint32_t   LOW
 
} MAC_ADDR [4]
 
struct {
   __RW uint32_t   L3_L4_CTRL
 
   __RW uint32_t   L4_ADDR
 
   __R uint8_t   RESERVED0 [8]
 
   __RW uint32_t   L3_ADDR_0
 
   __RW uint32_t   L3_ADDR_1
 
   __RW uint32_t   L3_ADDR_2
 
   __RW uint32_t   L3_ADDR_3
 
} L3_L4_CFG [1]
 
struct {
   __RW uint32_t   TGTTM_SEC
 
   __RW uint32_t   TGTTM_NSEC
 
   __RW uint32_t   INTERVAL
 
   __RW uint32_t   WIDTH
 
   __R uint8_t   RESERVED0 [16]
 
} PPS [3]
 

Field Documentation

◆ AUX_TS_NSEC

__R uint32_t ENET_Type::AUX_TS_NSEC

◆ AUX_TS_SEC

__R uint32_t ENET_Type::AUX_TS_SEC

◆ CTRL0

__RW uint32_t ENET_Type::CTRL0

◆ CTRL2

__RW uint32_t ENET_Type::CTRL2

◆ DMA_AXI_MODE

__RW uint32_t ENET_Type::DMA_AXI_MODE

◆ DMA_BUS_MODE

__RW uint32_t ENET_Type::DMA_BUS_MODE

◆ DMA_BUS_STATUS

__RW uint32_t ENET_Type::DMA_BUS_STATUS

◆ DMA_CURR_HOST_RX_BUF

__RW uint32_t ENET_Type::DMA_CURR_HOST_RX_BUF

◆ DMA_CURR_HOST_RX_DESC

__RW uint32_t ENET_Type::DMA_CURR_HOST_RX_DESC

◆ DMA_CURR_HOST_TX_BUF

__RW uint32_t ENET_Type::DMA_CURR_HOST_TX_BUF

◆ DMA_CURR_HOST_TX_DESC

__RW uint32_t ENET_Type::DMA_CURR_HOST_TX_DESC

◆ DMA_INTR_EN

__RW uint32_t ENET_Type::DMA_INTR_EN

◆ DMA_MISS_OVF_CNT

__RW uint32_t ENET_Type::DMA_MISS_OVF_CNT

◆ DMA_OP_MODE

__RW uint32_t ENET_Type::DMA_OP_MODE

◆ DMA_RX_DESC_LIST_ADDR

__RW uint32_t ENET_Type::DMA_RX_DESC_LIST_ADDR

◆ DMA_RX_INTR_WDOG

__RW uint32_t ENET_Type::DMA_RX_INTR_WDOG

◆ DMA_RX_POLL_DEMAND

__RW uint32_t ENET_Type::DMA_RX_POLL_DEMAND

◆ DMA_STATUS

__RW uint32_t ENET_Type::DMA_STATUS

◆ DMA_TX_DESC_LIST_ADDR

__RW uint32_t ENET_Type::DMA_TX_DESC_LIST_ADDR

◆ DMA_TX_POLL_DEMAND

__RW uint32_t ENET_Type::DMA_TX_POLL_DEMAND

◆ FLOWCTRL

__RW uint32_t ENET_Type::FLOWCTRL

◆ GMII_ADDR

__RW uint32_t ENET_Type::GMII_ADDR

◆ GMII_DATA

__RW uint32_t ENET_Type::GMII_DATA

◆ HASH_H

__RW uint32_t ENET_Type::HASH_H

◆ HASH_L

__RW uint32_t ENET_Type::HASH_L

◆ HIGH

__RW uint32_t ENET_Type::HIGH

◆ INTERVAL

__RW uint32_t ENET_Type::INTERVAL

◆ INTR_MASK

__RW uint32_t ENET_Type::INTR_MASK

◆ INTR_STATUS

__R uint32_t ENET_Type::INTR_STATUS

◆ L3_ADDR_0

__RW uint32_t ENET_Type::L3_ADDR_0

◆ L3_ADDR_1

__RW uint32_t ENET_Type::L3_ADDR_1

◆ L3_ADDR_2

__RW uint32_t ENET_Type::L3_ADDR_2

◆ L3_ADDR_3

__RW uint32_t ENET_Type::L3_ADDR_3

◆  [1/6]

struct { ... } ENET_Type::L3_L4_CFG[1]

◆  [2/6]

struct { ... } ENET_Type::L3_L4_CFG[1]

◆  [3/6]

struct { ... } ENET_Type::L3_L4_CFG[1]

◆  [4/6]

struct { ... } ENET_Type::L3_L4_CFG[1]

◆  [5/6]

struct { ... } ENET_Type::L3_L4_CFG[1]

◆  [6/6]

struct { ... } ENET_Type::L3_L4_CFG[1]

◆ L3_L4_CTRL

__RW uint32_t ENET_Type::L3_L4_CTRL

◆ L4_ADDR

__RW uint32_t ENET_Type::L4_ADDR

◆ LOW

__RW uint32_t ENET_Type::LOW

◆ LPI_CSR

__RW uint32_t ENET_Type::LPI_CSR

◆ LPI_TCR

__RW uint32_t ENET_Type::LPI_TCR

◆  [1/6]

struct { ... } ENET_Type::MAC_ADDR[4]

◆  [2/6]

struct { ... } ENET_Type::MAC_ADDR[4]

◆  [3/6]

struct { ... } ENET_Type::MAC_ADDR[4]

◆  [4/6]

struct { ... } ENET_Type::MAC_ADDR[4]

◆  [5/6]

struct { ... } ENET_Type::MAC_ADDR[4]

◆  [6/6]

struct { ... } ENET_Type::MAC_ADDR[4]

◆ MAC_ADDR_0_HIGH

__RW uint32_t ENET_Type::MAC_ADDR_0_HIGH

◆ MAC_ADDR_0_LOW

__RW uint32_t ENET_Type::MAC_ADDR_0_LOW

◆ MACCFG

__RW uint32_t ENET_Type::MACCFG

◆ MACFF

__RW uint32_t ENET_Type::MACFF

◆ MMC_CNTRL

__RW uint32_t ENET_Type::MMC_CNTRL

◆ MMC_INTR_MASK_RX

__RW uint32_t ENET_Type::MMC_INTR_MASK_RX

◆ MMC_INTR_MASK_TX

__RW uint32_t ENET_Type::MMC_INTR_MASK_TX

◆ MMC_INTR_RX

__RW uint32_t ENET_Type::MMC_INTR_RX

◆ MMC_INTR_TX

__RW uint32_t ENET_Type::MMC_INTR_TX

◆ MMC_IPC_INTR_MASK_RX

__RW uint32_t ENET_Type::MMC_IPC_INTR_MASK_RX

◆ MMC_IPC_INTR_RX

__RW uint32_t ENET_Type::MMC_IPC_INTR_RX

◆ PMT_CSR

__RW uint32_t ENET_Type::PMT_CSR

◆  [1/6]

struct { ... } ENET_Type::PPS[3]

◆  [2/6]

struct { ... } ENET_Type::PPS[3]

◆  [3/6]

struct { ... } ENET_Type::PPS[3]

◆  [4/6]

struct { ... } ENET_Type::PPS[3]

◆  [5/6]

struct { ... } ENET_Type::PPS[3]

◆  [6/6]

struct { ... } ENET_Type::PPS[3]

◆ PPS0_INTERVAL

__RW uint32_t ENET_Type::PPS0_INTERVAL

◆ PPS0_WIDTH

__RW uint32_t ENET_Type::PPS0_WIDTH

◆ PPS_CTRL

__RW uint32_t ENET_Type::PPS_CTRL

◆ RESERVED0

__R uint8_t ENET_Type::RESERVED0

◆ RESERVED1

__R uint8_t ENET_Type::RESERVED1

◆ RESERVED10

__R uint8_t ENET_Type::RESERVED10

◆ RESERVED11

__R uint8_t ENET_Type::RESERVED11

◆ RESERVED12

__R uint8_t ENET_Type::RESERVED12

◆ RESERVED13

__R uint8_t ENET_Type::RESERVED13

◆ RESERVED14

__R uint8_t ENET_Type::RESERVED14

◆ RESERVED15

__R uint8_t ENET_Type::RESERVED15

◆ RESERVED16

__R uint8_t ENET_Type::RESERVED16

◆ RESERVED17

__R uint8_t ENET_Type::RESERVED17

◆ RESERVED2

__R uint8_t ENET_Type::RESERVED2

◆ RESERVED3

__R uint8_t ENET_Type::RESERVED3

◆ RESERVED4

__R uint8_t ENET_Type::RESERVED4

◆ RESERVED5

__R uint8_t ENET_Type::RESERVED5

◆ RESERVED6

__R uint8_t ENET_Type::RESERVED6

◆ RESERVED7

__R uint8_t ENET_Type::RESERVED7

◆ RESERVED8

__R uint8_t ENET_Type::RESERVED8

◆ RESERVED9

__R uint8_t ENET_Type::RESERVED9

◆ RWKFRMFILT

__RW uint32_t ENET_Type::RWKFRMFILT

◆ RXFRAMECOUNT_GB

__RW uint32_t ENET_Type::RXFRAMECOUNT_GB

◆ RXIPV4_GD_FMS

__RW uint32_t ENET_Type::RXIPV4_GD_FMS

◆ SUB_SEC_INCR

__RW uint32_t ENET_Type::SUB_SEC_INCR

◆ SYST_NSEC

__R uint32_t ENET_Type::SYST_NSEC

◆ SYST_NSEC_UPD

__RW uint32_t ENET_Type::SYST_NSEC_UPD

◆ SYST_SEC

__R uint32_t ENET_Type::SYST_SEC

◆ SYST_SEC_UPD

__RW uint32_t ENET_Type::SYST_SEC_UPD

◆ SYSTM_H_SEC

__RW uint32_t ENET_Type::SYSTM_H_SEC

◆ TGTTM_NSEC

__RW uint32_t ENET_Type::TGTTM_NSEC

◆ TGTTM_SEC

__RW uint32_t ENET_Type::TGTTM_SEC

◆ TS_ADDEND

__RW uint32_t ENET_Type::TS_ADDEND

◆ TS_CTRL

__RW uint32_t ENET_Type::TS_CTRL

◆ TS_STATUS

__R uint32_t ENET_Type::TS_STATUS

◆ TX1024TOMAXOCTETS_GB

__RW uint32_t ENET_Type::TX1024TOMAXOCTETS_GB

◆ TX128TO255OCTETS_GB

__RW uint32_t ENET_Type::TX128TO255OCTETS_GB

◆ TX256TO511OCTETS_GB

__RW uint32_t ENET_Type::TX256TO511OCTETS_GB

◆ TX512TO1023OCTETS_GB

__RW uint32_t ENET_Type::TX512TO1023OCTETS_GB

◆ TX64OCTETS_GB

__RW uint32_t ENET_Type::TX64OCTETS_GB

◆ TX65TO127OCTETS_GB

__RW uint32_t ENET_Type::TX65TO127OCTETS_GB

◆ VLAN_HASH

__RW uint32_t ENET_Type::VLAN_HASH

◆ VLAN_TAG

__RW uint32_t ENET_Type::VLAN_TAG

◆ VLAN_TAG_INC_RPL

__RW uint32_t ENET_Type::VLAN_TAG_INC_RPL

◆ WDOG_WTO

__RW uint32_t ENET_Type::WDOG_WTO

◆ WIDTH

__RW uint32_t ENET_Type::WIDTH

◆ XMII_CSR

__RW uint32_t ENET_Type::XMII_CSR
The documentation for this struct was generated from the following file: