HPM SDK
HPMicro Software Development Kit
hpm_lobs_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_LOBS_H
10 #define HPM_LOBS_H
11 
12 typedef struct {
13  __RW uint32_t CTRL; /* 0x0: Control Register */
14  __RW uint32_t IRQ_EN; /* 0x4: Interrupt Enable Register */
15  __RW uint32_t IRQ_STS; /* 0x8: Interrupt Status Register */
16  __RW uint32_t STREAMCTRL; /* 0xC: Stream Control Register */
17  __RW uint32_t PTACTION; /* 0x10: Pre-trigger Action Register */
18  __RW uint32_t STARTADDR; /* 0x14: Start Address Register */
19  __RW uint32_t ENDADDR; /* 0x18: End Address Register */
20  __R uint8_t RESERVED0[4]; /* 0x1C - 0x1F: Reserved */
21  __R uint32_t CTSR; /* 0x20: Current Trigger State Register */
22  __R uint32_t CCVR; /* 0x24: Current Counter Value Register */
23  __R uint32_t CAVR; /* 0x28: Current Action Value Register */
24  __R uint8_t RESERVED1[4]; /* 0x2C - 0x2F: Reserved */
25  __R uint32_t FIFOSTATE; /* 0x30: Fifo State Register */
26  __RW uint32_t FINALADDR; /* 0x34: Final Address Register */
27  __R uint8_t RESERVED2[8]; /* 0x38 - 0x3F: Reserved */
28  __RW uint32_t TRIGADDR1; /* 0x40: Trigger Address1 */
29  __RW uint32_t TRIGADDR2; /* 0x44: Trigger Address1 */
30  __RW uint32_t TRIGADDR3; /* 0x48: Trigger Address1 */
31  __RW uint32_t TRIGADDR4; /* 0x4C: Trigger Address1 */
32  __RW uint32_t GRPSELA; /* 0x50: Group Select Register */
33  __RW uint32_t GRPENA; /* 0x54: Group Enable Register */
34  __RW uint32_t SIGSELA1; /* 0x58: Signal Select1 Register */
35  __R uint8_t RESERVED3[4]; /* 0x5C - 0x5F: Reserved */
36  __RW uint32_t SIGSELA2; /* 0x60: Signal Select2 Register */
37  __R uint8_t RESERVED4[52]; /* 0x64 - 0x97: Reserved */
38  __RW uint32_t SIGENA; /* 0x98: Signal Enable Register */
39  __R uint8_t RESERVED5[100]; /* 0x9C - 0xFF: Reserved */
40  struct {
41  __RW uint32_t SIGSEL; /* 0x100: Signal Select Register */
42  __RW uint32_t TRIGCTRL; /* 0x104: Trigger Control Register */
43  __RW uint32_t NEXTSTATE; /* 0x108: Next State Register */
44  __RW uint32_t ACTION; /* 0x10C: Action Register */
45  __R uint8_t RESERVED0[16]; /* 0x110 - 0x11F: Reserved */
46  __RW uint32_t COUNTCOMP; /* 0x120: Counter Compare Register */
47  __R uint8_t RESERVED1[12]; /* 0x124 - 0x12F: Reserved */
48  __RW uint32_t EXTMASK; /* 0x130: External Mask Register */
49  __RW uint32_t EXTCOMP; /* 0x134: External Compare Register */
50  __R uint8_t RESERVED2[8]; /* 0x138 - 0x13F: Reserved */
51  __RW uint32_t SIGMASK; /* 0x140: Signal Mask Register */
52  __RW uint32_t COMPEN; /* 0x144: Compare Enable register */
53  __R uint8_t RESERVED3[56]; /* 0x148 - 0x17F: Reserved */
54  __RW uint32_t SIGCOMP0; /* 0x180: Signal Compare Register0 */
55  __RW uint32_t SIGCOMP1; /* 0x184: Signal Compare Register1 */
56  __RW uint32_t SIGCOMP2; /* 0x188: Signal Compare Register2 */
57  __RW uint32_t SIGCOMP3; /* 0x18C: Signal Compare Register3 */
58  __R uint8_t RESERVED4[112]; /* 0x190 - 0x1FF: Reserved */
59  } STATE[5];
60  __R uint8_t RESERVED6[2480]; /* 0x600 - 0xFAF: Reserved */
61  __RW uint32_t LAR; /* 0xFB0: Lock Access Register */
62 } LOBS_Type;
63 
64 
65 /* Bitfield definition for register: CTRL */
66 /*
67  * RUN (RW)
68  *
69  * Run control.
70  * 0 LOBS disabled. Register programming permitted.
71  * 1 LOBS enabled
72  */
73 #define LOBS_CTRL_RUN_MASK (0x1U)
74 #define LOBS_CTRL_RUN_SHIFT (0U)
75 #define LOBS_CTRL_RUN_SET(x) (((uint32_t)(x) << LOBS_CTRL_RUN_SHIFT) & LOBS_CTRL_RUN_MASK)
76 #define LOBS_CTRL_RUN_GET(x) (((uint32_t)(x) & LOBS_CTRL_RUN_MASK) >> LOBS_CTRL_RUN_SHIFT)
77 
78 /* Bitfield definition for register: IRQ_EN */
79 /*
80  * FULL_EN (RW)
81  *
82  * FIFO overflow status interrupt enable
83  */
84 #define LOBS_IRQ_EN_FULL_EN_MASK (0x2U)
85 #define LOBS_IRQ_EN_FULL_EN_SHIFT (1U)
86 #define LOBS_IRQ_EN_FULL_EN_SET(x) (((uint32_t)(x) << LOBS_IRQ_EN_FULL_EN_SHIFT) & LOBS_IRQ_EN_FULL_EN_MASK)
87 #define LOBS_IRQ_EN_FULL_EN_GET(x) (((uint32_t)(x) & LOBS_IRQ_EN_FULL_EN_MASK) >> LOBS_IRQ_EN_FULL_EN_SHIFT)
88 
89 /*
90  * FINAL_EN (RW)
91  *
92  * final status interrupt enable
93  */
94 #define LOBS_IRQ_EN_FINAL_EN_MASK (0x1U)
95 #define LOBS_IRQ_EN_FINAL_EN_SHIFT (0U)
96 #define LOBS_IRQ_EN_FINAL_EN_SET(x) (((uint32_t)(x) << LOBS_IRQ_EN_FINAL_EN_SHIFT) & LOBS_IRQ_EN_FINAL_EN_MASK)
97 #define LOBS_IRQ_EN_FINAL_EN_GET(x) (((uint32_t)(x) & LOBS_IRQ_EN_FINAL_EN_MASK) >> LOBS_IRQ_EN_FINAL_EN_SHIFT)
98 
99 /* Bitfield definition for register: IRQ_STS */
100 /*
101  * FULL_STS (W1C)
102  *
103  * FIFO overflow status interrupt status
104  */
105 #define LOBS_IRQ_STS_FULL_STS_MASK (0x2U)
106 #define LOBS_IRQ_STS_FULL_STS_SHIFT (1U)
107 #define LOBS_IRQ_STS_FULL_STS_SET(x) (((uint32_t)(x) << LOBS_IRQ_STS_FULL_STS_SHIFT) & LOBS_IRQ_STS_FULL_STS_MASK)
108 #define LOBS_IRQ_STS_FULL_STS_GET(x) (((uint32_t)(x) & LOBS_IRQ_STS_FULL_STS_MASK) >> LOBS_IRQ_STS_FULL_STS_SHIFT)
109 
110 /*
111  * FINAL_STS (W1C)
112  *
113  * final status interrupt status
114  */
115 #define LOBS_IRQ_STS_FINAL_STS_MASK (0x1U)
116 #define LOBS_IRQ_STS_FINAL_STS_SHIFT (0U)
117 #define LOBS_IRQ_STS_FINAL_STS_SET(x) (((uint32_t)(x) << LOBS_IRQ_STS_FINAL_STS_SHIFT) & LOBS_IRQ_STS_FINAL_STS_MASK)
118 #define LOBS_IRQ_STS_FINAL_STS_GET(x) (((uint32_t)(x) & LOBS_IRQ_STS_FINAL_STS_MASK) >> LOBS_IRQ_STS_FINAL_STS_SHIFT)
119 
120 /* Bitfield definition for register: STREAMCTRL */
121 /*
122  * SAMPLE_INCR (RW)
123  *
124  * Sample Rate high extension bits, the high 6 bits of the SAMPLE bit field, and the combined value with the SAMPLE bit field are as follows:
125  * 4 take one every 5
126  * 5 take one every 6
127  * 6 take one every 7
128  * 9 take one every 10
129  * 49 take one every 50
130  * 99 take one every 100
131  * 499 take one every 500
132  * 999 take one every 1000
133  * others not supported
134  */
135 #define LOBS_STREAMCTRL_SAMPLE_INCR_MASK (0x7E00U)
136 #define LOBS_STREAMCTRL_SAMPLE_INCR_SHIFT (9U)
137 #define LOBS_STREAMCTRL_SAMPLE_INCR_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_SAMPLE_INCR_SHIFT) & LOBS_STREAMCTRL_SAMPLE_INCR_MASK)
138 #define LOBS_STREAMCTRL_SAMPLE_INCR_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_SAMPLE_INCR_MASK) >> LOBS_STREAMCTRL_SAMPLE_INCR_SHIFT)
139 
140 /*
141  * SEL (RW)
142  *
143  * Signal Group Select
144  * 0 128bit from one group
145  * 1 from 2 groups, 4bit in each group
146  */
147 #define LOBS_STREAMCTRL_SEL_MASK (0x100U)
148 #define LOBS_STREAMCTRL_SEL_SHIFT (8U)
149 #define LOBS_STREAMCTRL_SEL_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_SEL_SHIFT) & LOBS_STREAMCTRL_SEL_MASK)
150 #define LOBS_STREAMCTRL_SEL_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_SEL_MASK) >> LOBS_STREAMCTRL_SEL_SHIFT)
151 
152 /*
153  * SAMPLE (RW)
154  *
155  * Sample Rate
156  * 4 take one every 5
157  * 5 take one every 6
158  * 6 take one every 7
159  */
160 #define LOBS_STREAMCTRL_SAMPLE_MASK (0x78U)
161 #define LOBS_STREAMCTRL_SAMPLE_SHIFT (3U)
162 #define LOBS_STREAMCTRL_SAMPLE_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_SAMPLE_SHIFT) & LOBS_STREAMCTRL_SAMPLE_MASK)
163 #define LOBS_STREAMCTRL_SAMPLE_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_SAMPLE_MASK) >> LOBS_STREAMCTRL_SAMPLE_SHIFT)
164 
165 /*
166  * BURST (RW)
167  *
168  * Burst Cfg
169  * 3b011 Incr4
170  * 3b101 Incr8
171  * 3b111 Incr16
172  */
173 #define LOBS_STREAMCTRL_BURST_MASK (0x7U)
174 #define LOBS_STREAMCTRL_BURST_SHIFT (0U)
175 #define LOBS_STREAMCTRL_BURST_SET(x) (((uint32_t)(x) << LOBS_STREAMCTRL_BURST_SHIFT) & LOBS_STREAMCTRL_BURST_MASK)
176 #define LOBS_STREAMCTRL_BURST_GET(x) (((uint32_t)(x) & LOBS_STREAMCTRL_BURST_MASK) >> LOBS_STREAMCTRL_BURST_SHIFT)
177 
178 /* Bitfield definition for register: PTACTION */
179 /*
180  * TRACE (RW)
181  *
182  * Enables trace
183  */
184 #define LOBS_PTACTION_TRACE_MASK (0x8U)
185 #define LOBS_PTACTION_TRACE_SHIFT (3U)
186 #define LOBS_PTACTION_TRACE_SET(x) (((uint32_t)(x) << LOBS_PTACTION_TRACE_SHIFT) & LOBS_PTACTION_TRACE_MASK)
187 #define LOBS_PTACTION_TRACE_GET(x) (((uint32_t)(x) & LOBS_PTACTION_TRACE_MASK) >> LOBS_PTACTION_TRACE_SHIFT)
188 
189 /* Bitfield definition for register: STARTADDR */
190 /*
191  * ADDR (RW)
192  *
193  * Start address
194  */
195 #define LOBS_STARTADDR_ADDR_MASK (0xFFFFFFFFUL)
196 #define LOBS_STARTADDR_ADDR_SHIFT (0U)
197 #define LOBS_STARTADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_STARTADDR_ADDR_SHIFT) & LOBS_STARTADDR_ADDR_MASK)
198 #define LOBS_STARTADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_STARTADDR_ADDR_MASK) >> LOBS_STARTADDR_ADDR_SHIFT)
199 
200 /* Bitfield definition for register: ENDADDR */
201 /*
202  * ADDR (RW)
203  *
204  * End address
205  */
206 #define LOBS_ENDADDR_ADDR_MASK (0xFFFFFFFFUL)
207 #define LOBS_ENDADDR_ADDR_SHIFT (0U)
208 #define LOBS_ENDADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_ENDADDR_ADDR_SHIFT) & LOBS_ENDADDR_ADDR_MASK)
209 #define LOBS_ENDADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_ENDADDR_ADDR_MASK) >> LOBS_ENDADDR_ADDR_SHIFT)
210 
211 /* Bitfield definition for register: CTSR */
212 /*
213  * FINALSTATE (RO)
214  *
215  * 0 LOBS is still tracing.
216  * 1 Indicates that the LOBS has stopped advancing Trigger States and stopped trace.
217  * FINALSTATE can be set by TRIGCTRL.COUNTBRK reaching the final loop count, or by programming NEXTSTATEto zero
218  */
219 #define LOBS_CTSR_FINALSTATE_MASK (0x80000000UL)
220 #define LOBS_CTSR_FINALSTATE_SHIFT (31U)
221 #define LOBS_CTSR_FINALSTATE_GET(x) (((uint32_t)(x) & LOBS_CTSR_FINALSTATE_MASK) >> LOBS_CTSR_FINALSTATE_SHIFT)
222 
223 /*
224  * CTSR (RO)
225  *
226  * Reads current Trigger State. This is a one-hot encoded field.
227  * When CTRL.RUN:
228  * 0 RAZ.
229  * 1 Returns current Trigger State.
230  * If FINALSTATE is 1, then the CTSR field gives the Trigger State when FINALSTATE became 1
231  */
232 #define LOBS_CTSR_CTSR_MASK (0x1FU)
233 #define LOBS_CTSR_CTSR_SHIFT (0U)
234 #define LOBS_CTSR_CTSR_GET(x) (((uint32_t)(x) & LOBS_CTSR_CTSR_MASK) >> LOBS_CTSR_CTSR_SHIFT)
235 
236 /* Bitfield definition for register: CCVR */
237 /*
238  * CCVR (RO)
239  *
240  * Returns the counter value when the CTSR was last read. If the CTSR has never been read, then the value in the CCVR is undefined
241  */
242 #define LOBS_CCVR_CCVR_MASK (0xFFFFFFFFUL)
243 #define LOBS_CCVR_CCVR_SHIFT (0U)
244 #define LOBS_CCVR_CCVR_GET(x) (((uint32_t)(x) & LOBS_CCVR_CCVR_MASK) >> LOBS_CCVR_CCVR_SHIFT)
245 
246 /* Bitfield definition for register: CAVR */
247 /*
248  * TRACE (RO)
249  *
250  * Trace active.
251  * 0b0 Trace is not active.
252  * 0b1 Trace is active.
253  */
254 #define LOBS_CAVR_TRACE_MASK (0x8U)
255 #define LOBS_CAVR_TRACE_SHIFT (3U)
256 #define LOBS_CAVR_TRACE_GET(x) (((uint32_t)(x) & LOBS_CAVR_TRACE_MASK) >> LOBS_CAVR_TRACE_SHIFT)
257 
258 /* Bitfield definition for register: FIFOSTATE */
259 /*
260  * FULL (RO)
261  *
262  * FIFO full
263  */
264 #define LOBS_FIFOSTATE_FULL_MASK (0x2U)
265 #define LOBS_FIFOSTATE_FULL_SHIFT (1U)
266 #define LOBS_FIFOSTATE_FULL_GET(x) (((uint32_t)(x) & LOBS_FIFOSTATE_FULL_MASK) >> LOBS_FIFOSTATE_FULL_SHIFT)
267 
268 /*
269  * EMPTY (RO)
270  *
271  * FIFO empty
272  */
273 #define LOBS_FIFOSTATE_EMPTY_MASK (0x1U)
274 #define LOBS_FIFOSTATE_EMPTY_SHIFT (0U)
275 #define LOBS_FIFOSTATE_EMPTY_GET(x) (((uint32_t)(x) & LOBS_FIFOSTATE_EMPTY_MASK) >> LOBS_FIFOSTATE_EMPTY_SHIFT)
276 
277 /* Bitfield definition for register: FINALADDR */
278 /*
279  * ADDR (RW)
280  *
281  * Final address
282  */
283 #define LOBS_FINALADDR_ADDR_MASK (0xFFFFFFFFUL)
284 #define LOBS_FINALADDR_ADDR_SHIFT (0U)
285 #define LOBS_FINALADDR_ADDR_SET(x) (((uint32_t)(x) << LOBS_FINALADDR_ADDR_SHIFT) & LOBS_FINALADDR_ADDR_MASK)
286 #define LOBS_FINALADDR_ADDR_GET(x) (((uint32_t)(x) & LOBS_FINALADDR_ADDR_MASK) >> LOBS_FINALADDR_ADDR_SHIFT)
287 
288 /* Bitfield definition for register: TRIGADDR1 */
289 /*
290  * ADDR (RW)
291  *
292  * Trigger address1
293  */
294 #define LOBS_TRIGADDR1_ADDR_MASK (0xFFFFFFFFUL)
295 #define LOBS_TRIGADDR1_ADDR_SHIFT (0U)
296 #define LOBS_TRIGADDR1_ADDR_SET(x) (((uint32_t)(x) << LOBS_TRIGADDR1_ADDR_SHIFT) & LOBS_TRIGADDR1_ADDR_MASK)
297 #define LOBS_TRIGADDR1_ADDR_GET(x) (((uint32_t)(x) & LOBS_TRIGADDR1_ADDR_MASK) >> LOBS_TRIGADDR1_ADDR_SHIFT)
298 
299 /* Bitfield definition for register: TRIGADDR2 */
300 /*
301  * ADDR (RW)
302  *
303  * Trigger address2
304  */
305 #define LOBS_TRIGADDR2_ADDR_MASK (0xFFFFFFFFUL)
306 #define LOBS_TRIGADDR2_ADDR_SHIFT (0U)
307 #define LOBS_TRIGADDR2_ADDR_SET(x) (((uint32_t)(x) << LOBS_TRIGADDR2_ADDR_SHIFT) & LOBS_TRIGADDR2_ADDR_MASK)
308 #define LOBS_TRIGADDR2_ADDR_GET(x) (((uint32_t)(x) & LOBS_TRIGADDR2_ADDR_MASK) >> LOBS_TRIGADDR2_ADDR_SHIFT)
309 
310 /* Bitfield definition for register: TRIGADDR3 */
311 /*
312  * ADDR (RW)
313  *
314  * Trigger address3
315  */
316 #define LOBS_TRIGADDR3_ADDR_MASK (0xFFFFFFFFUL)
317 #define LOBS_TRIGADDR3_ADDR_SHIFT (0U)
318 #define LOBS_TRIGADDR3_ADDR_SET(x) (((uint32_t)(x) << LOBS_TRIGADDR3_ADDR_SHIFT) & LOBS_TRIGADDR3_ADDR_MASK)
319 #define LOBS_TRIGADDR3_ADDR_GET(x) (((uint32_t)(x) & LOBS_TRIGADDR3_ADDR_MASK) >> LOBS_TRIGADDR3_ADDR_SHIFT)
320 
321 /* Bitfield definition for register: TRIGADDR4 */
322 /*
323  * ADDR (RW)
324  *
325  * Trigger address4
326  */
327 #define LOBS_TRIGADDR4_ADDR_MASK (0xFFFFFFFFUL)
328 #define LOBS_TRIGADDR4_ADDR_SHIFT (0U)
329 #define LOBS_TRIGADDR4_ADDR_SET(x) (((uint32_t)(x) << LOBS_TRIGADDR4_ADDR_SHIFT) & LOBS_TRIGADDR4_ADDR_MASK)
330 #define LOBS_TRIGADDR4_ADDR_GET(x) (((uint32_t)(x) & LOBS_TRIGADDR4_ADDR_MASK) >> LOBS_TRIGADDR4_ADDR_SHIFT)
331 
332 /* Bitfield definition for register: GRPSELA */
333 /*
334  * NUM2 (RW)
335  *
336  * Select sample group number2
337  */
338 #define LOBS_GRPSELA_NUM2_MASK (0xF0U)
339 #define LOBS_GRPSELA_NUM2_SHIFT (4U)
340 #define LOBS_GRPSELA_NUM2_SET(x) (((uint32_t)(x) << LOBS_GRPSELA_NUM2_SHIFT) & LOBS_GRPSELA_NUM2_MASK)
341 #define LOBS_GRPSELA_NUM2_GET(x) (((uint32_t)(x) & LOBS_GRPSELA_NUM2_MASK) >> LOBS_GRPSELA_NUM2_SHIFT)
342 
343 /*
344  * NUM1 (RW)
345  *
346  * Select sample group number1
347  */
348 #define LOBS_GRPSELA_NUM1_MASK (0xFU)
349 #define LOBS_GRPSELA_NUM1_SHIFT (0U)
350 #define LOBS_GRPSELA_NUM1_SET(x) (((uint32_t)(x) << LOBS_GRPSELA_NUM1_SHIFT) & LOBS_GRPSELA_NUM1_MASK)
351 #define LOBS_GRPSELA_NUM1_GET(x) (((uint32_t)(x) & LOBS_GRPSELA_NUM1_MASK) >> LOBS_GRPSELA_NUM1_SHIFT)
352 
353 /* Bitfield definition for register: GRPENA */
354 /*
355  * EN2 (RW)
356  *
357  * Enable sample group number2
358  */
359 #define LOBS_GRPENA_EN2_MASK (0x2U)
360 #define LOBS_GRPENA_EN2_SHIFT (1U)
361 #define LOBS_GRPENA_EN2_SET(x) (((uint32_t)(x) << LOBS_GRPENA_EN2_SHIFT) & LOBS_GRPENA_EN2_MASK)
362 #define LOBS_GRPENA_EN2_GET(x) (((uint32_t)(x) & LOBS_GRPENA_EN2_MASK) >> LOBS_GRPENA_EN2_SHIFT)
363 
364 /*
365  * EN1 (RW)
366  *
367  * Enable sample group number1
368  */
369 #define LOBS_GRPENA_EN1_MASK (0x1U)
370 #define LOBS_GRPENA_EN1_SHIFT (0U)
371 #define LOBS_GRPENA_EN1_SET(x) (((uint32_t)(x) << LOBS_GRPENA_EN1_SHIFT) & LOBS_GRPENA_EN1_MASK)
372 #define LOBS_GRPENA_EN1_GET(x) (((uint32_t)(x) & LOBS_GRPENA_EN1_MASK) >> LOBS_GRPENA_EN1_SHIFT)
373 
374 /* Bitfield definition for register: SIGSELA1 */
375 /*
376  * NUM4 (RW)
377  *
378  * Select sample signal bit number4 in first group
379  */
380 #define LOBS_SIGSELA1_NUM4_MASK (0xFF000000UL)
381 #define LOBS_SIGSELA1_NUM4_SHIFT (24U)
382 #define LOBS_SIGSELA1_NUM4_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM4_SHIFT) & LOBS_SIGSELA1_NUM4_MASK)
383 #define LOBS_SIGSELA1_NUM4_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM4_MASK) >> LOBS_SIGSELA1_NUM4_SHIFT)
384 
385 /*
386  * NUM3 (RW)
387  *
388  * Select sample signal bit number3 in first group
389  */
390 #define LOBS_SIGSELA1_NUM3_MASK (0xFF0000UL)
391 #define LOBS_SIGSELA1_NUM3_SHIFT (16U)
392 #define LOBS_SIGSELA1_NUM3_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM3_SHIFT) & LOBS_SIGSELA1_NUM3_MASK)
393 #define LOBS_SIGSELA1_NUM3_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM3_MASK) >> LOBS_SIGSELA1_NUM3_SHIFT)
394 
395 /*
396  * NUM2 (RW)
397  *
398  * Select sample signal bit number2 in first group
399  */
400 #define LOBS_SIGSELA1_NUM2_MASK (0xFF00U)
401 #define LOBS_SIGSELA1_NUM2_SHIFT (8U)
402 #define LOBS_SIGSELA1_NUM2_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM2_SHIFT) & LOBS_SIGSELA1_NUM2_MASK)
403 #define LOBS_SIGSELA1_NUM2_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM2_MASK) >> LOBS_SIGSELA1_NUM2_SHIFT)
404 
405 /*
406  * NUM1 (RW)
407  *
408  * Select sample signal bit number1 in first group
409  */
410 #define LOBS_SIGSELA1_NUM1_MASK (0xFFU)
411 #define LOBS_SIGSELA1_NUM1_SHIFT (0U)
412 #define LOBS_SIGSELA1_NUM1_SET(x) (((uint32_t)(x) << LOBS_SIGSELA1_NUM1_SHIFT) & LOBS_SIGSELA1_NUM1_MASK)
413 #define LOBS_SIGSELA1_NUM1_GET(x) (((uint32_t)(x) & LOBS_SIGSELA1_NUM1_MASK) >> LOBS_SIGSELA1_NUM1_SHIFT)
414 
415 /* Bitfield definition for register: SIGSELA2 */
416 /*
417  * NUM4 (RW)
418  *
419  * Select sample signal bit number4 in second group
420  */
421 #define LOBS_SIGSELA2_NUM4_MASK (0xFF000000UL)
422 #define LOBS_SIGSELA2_NUM4_SHIFT (24U)
423 #define LOBS_SIGSELA2_NUM4_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM4_SHIFT) & LOBS_SIGSELA2_NUM4_MASK)
424 #define LOBS_SIGSELA2_NUM4_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM4_MASK) >> LOBS_SIGSELA2_NUM4_SHIFT)
425 
426 /*
427  * NUM3 (RW)
428  *
429  * Select sample signal bit number3 in second group
430  */
431 #define LOBS_SIGSELA2_NUM3_MASK (0xFF0000UL)
432 #define LOBS_SIGSELA2_NUM3_SHIFT (16U)
433 #define LOBS_SIGSELA2_NUM3_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM3_SHIFT) & LOBS_SIGSELA2_NUM3_MASK)
434 #define LOBS_SIGSELA2_NUM3_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM3_MASK) >> LOBS_SIGSELA2_NUM3_SHIFT)
435 
436 /*
437  * NUM2 (RW)
438  *
439  * Select sample signal bit number2 in second group
440  */
441 #define LOBS_SIGSELA2_NUM2_MASK (0xFF00U)
442 #define LOBS_SIGSELA2_NUM2_SHIFT (8U)
443 #define LOBS_SIGSELA2_NUM2_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM2_SHIFT) & LOBS_SIGSELA2_NUM2_MASK)
444 #define LOBS_SIGSELA2_NUM2_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM2_MASK) >> LOBS_SIGSELA2_NUM2_SHIFT)
445 
446 /*
447  * NUM1 (RW)
448  *
449  * Select sample signal bit number1 in second group
450  */
451 #define LOBS_SIGSELA2_NUM1_MASK (0xFFU)
452 #define LOBS_SIGSELA2_NUM1_SHIFT (0U)
453 #define LOBS_SIGSELA2_NUM1_SET(x) (((uint32_t)(x) << LOBS_SIGSELA2_NUM1_SHIFT) & LOBS_SIGSELA2_NUM1_MASK)
454 #define LOBS_SIGSELA2_NUM1_GET(x) (((uint32_t)(x) & LOBS_SIGSELA2_NUM1_MASK) >> LOBS_SIGSELA2_NUM1_SHIFT)
455 
456 /* Bitfield definition for register: SIGENA */
457 /*
458  * EN2 (RW)
459  *
460  * Enable sample signal number2
461  */
462 #define LOBS_SIGENA_EN2_MASK (0xF0U)
463 #define LOBS_SIGENA_EN2_SHIFT (4U)
464 #define LOBS_SIGENA_EN2_SET(x) (((uint32_t)(x) << LOBS_SIGENA_EN2_SHIFT) & LOBS_SIGENA_EN2_MASK)
465 #define LOBS_SIGENA_EN2_GET(x) (((uint32_t)(x) & LOBS_SIGENA_EN2_MASK) >> LOBS_SIGENA_EN2_SHIFT)
466 
467 /*
468  * EN1 (RW)
469  *
470  * Enable sample signal number1
471  */
472 #define LOBS_SIGENA_EN1_MASK (0xFU)
473 #define LOBS_SIGENA_EN1_SHIFT (0U)
474 #define LOBS_SIGENA_EN1_SET(x) (((uint32_t)(x) << LOBS_SIGENA_EN1_SHIFT) & LOBS_SIGENA_EN1_MASK)
475 #define LOBS_SIGENA_EN1_GET(x) (((uint32_t)(x) & LOBS_SIGENA_EN1_MASK) >> LOBS_SIGENA_EN1_SHIFT)
476 
477 /* Bitfield definition for register of struct array STATE: SIGSEL */
478 /*
479  * EN (RW)
480  *
481  * Selects Signal Group.
482  * 0x1 Selects Signal Group 0.
483  * 0x2 Selects Signal Group 1.
484  * 0x4 Selects Signal Group 2.
485  * 0x8 Selects Signal Group 3.
486  * 0x10 Selects Signal Group 4.
487  * 0x20 Selects Signal Group 5.
488  * 0x40 Selects Signal Group 6.
489  * 0x80 Selects Signal Group 7.
490  * 0x100 Selects Signal Group 8.
491  * 0x200 Selects Signal Group 9.
492  * 0x400 Selects Signal Group 10.
493  * 0x800 Selects Signal Group 11.
494  */
495 #define LOBS_STATE_SIGSEL_EN_MASK (0xFFFU)
496 #define LOBS_STATE_SIGSEL_EN_SHIFT (0U)
497 #define LOBS_STATE_SIGSEL_EN_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGSEL_EN_SHIFT) & LOBS_STATE_SIGSEL_EN_MASK)
498 #define LOBS_STATE_SIGSEL_EN_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGSEL_EN_MASK) >> LOBS_STATE_SIGSEL_EN_SHIFT)
499 
500 /* Bitfield definition for register of struct array STATE: TRIGCTRL */
501 /*
502  * TRACE (RW)
503  *
504  * Trace capture control.
505  * 0b10 Trace is captured every ELACLK cycle.
506  * others Reserved.
507  */
508 #define LOBS_STATE_TRIGCTRL_TRACE_MASK (0xC0U)
509 #define LOBS_STATE_TRIGCTRL_TRACE_SHIFT (6U)
510 #define LOBS_STATE_TRIGCTRL_TRACE_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_TRACE_SHIFT) & LOBS_STATE_TRIGCTRL_TRACE_MASK)
511 #define LOBS_STATE_TRIGCTRL_TRACE_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_TRACE_MASK) >> LOBS_STATE_TRIGCTRL_TRACE_SHIFT)
512 
513 /*
514  * COMPSEL (RW)
515  *
516  * Comparison mode. Acts as both a counter enable and a select for the comparison mode.
517  * 0b0 Disable counters and select Trigger Signal Comparison mode.
518  * 0b1 Enable counters and select Trigger Counter Comparison mode.
519  */
520 #define LOBS_STATE_TRIGCTRL_COMPSEL_MASK (0x8U)
521 #define LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT (3U)
522 #define LOBS_STATE_TRIGCTRL_COMPSEL_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT) & LOBS_STATE_TRIGCTRL_COMPSEL_MASK)
523 #define LOBS_STATE_TRIGCTRL_COMPSEL_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_COMPSEL_MASK) >> LOBS_STATE_TRIGCTRL_COMPSEL_SHIFT)
524 
525 /*
526  * COMP (RW)
527  *
528  * Trigger Signal Comparison type select.
529  * 0b000 Trigger Signal Comparisons disabled. The enabled counters count clocks immediately after the Trigger State has been entered and generate a programmable Output Action and transition to the next Trigger State when the Counter Compare Register count is reached, that is when a Trigger Counter Comparison match occurs.
530  * 0b001 Compare type is equal (==).
531  * 0b010 Compare type is greater than (>).
532  * 0b011 Compare type is greater than or equal (>=).
533  * 0b101 Compare type is not equal (!=).
534  * 0b110 Compare type is less than (<).
535  * 0b111 Compare type is less than or equal (<=).
536  */
537 #define LOBS_STATE_TRIGCTRL_COMP_MASK (0x7U)
538 #define LOBS_STATE_TRIGCTRL_COMP_SHIFT (0U)
539 #define LOBS_STATE_TRIGCTRL_COMP_SET(x) (((uint32_t)(x) << LOBS_STATE_TRIGCTRL_COMP_SHIFT) & LOBS_STATE_TRIGCTRL_COMP_MASK)
540 #define LOBS_STATE_TRIGCTRL_COMP_GET(x) (((uint32_t)(x) & LOBS_STATE_TRIGCTRL_COMP_MASK) >> LOBS_STATE_TRIGCTRL_COMP_SHIFT)
541 
542 /* Bitfield definition for register of struct array STATE: NEXTSTATE */
543 /*
544  * NEXTSTATE (RW)
545  *
546  * Selects the next state to move to after the Trigger Condition has been met in the current state.
547  * 0x0 Do not change state. This is the final Trigger State.
548  * 0x1 Selects Trigger State 0.
549  * 0x2 Selects Trigger State 1.
550  * 0x4 Selects Trigger State 2.
551  * 0x8 Selects Trigger State 3.
552  * 0x10 Selects Trigger State 4.
553  */
554 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK (0x1FU)
555 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT (0U)
556 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_SET(x) (((uint32_t)(x) << LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT) & LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK)
557 #define LOBS_STATE_NEXTSTATE_NEXTSTATE_GET(x) (((uint32_t)(x) & LOBS_STATE_NEXTSTATE_NEXTSTATE_MASK) >> LOBS_STATE_NEXTSTATE_NEXTSTATE_SHIFT)
558 
559 /* Bitfield definition for register of struct array STATE: ACTION */
560 /*
561  * TRACE (RW)
562  *
563  * Trace active.
564  * 0b0 Trace disable.
565  * 0b1 Trace enable.
566  */
567 #define LOBS_STATE_ACTION_TRACE_MASK (0x8U)
568 #define LOBS_STATE_ACTION_TRACE_SHIFT (3U)
569 #define LOBS_STATE_ACTION_TRACE_SET(x) (((uint32_t)(x) << LOBS_STATE_ACTION_TRACE_SHIFT) & LOBS_STATE_ACTION_TRACE_MASK)
570 #define LOBS_STATE_ACTION_TRACE_GET(x) (((uint32_t)(x) & LOBS_STATE_ACTION_TRACE_MASK) >> LOBS_STATE_ACTION_TRACE_SHIFT)
571 
572 /* Bitfield definition for register of struct array STATE: COUNTCOMP */
573 /*
574  * VALUE (RW)
575  *
576  * A value that, when reached in the associated up-counter for this Trigger State, causes a Trigger Counter Comparison match to occur.
577  */
578 #define LOBS_STATE_COUNTCOMP_VALUE_MASK (0xFFFFFFFFUL)
579 #define LOBS_STATE_COUNTCOMP_VALUE_SHIFT (0U)
580 #define LOBS_STATE_COUNTCOMP_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_COUNTCOMP_VALUE_SHIFT) & LOBS_STATE_COUNTCOMP_VALUE_MASK)
581 #define LOBS_STATE_COUNTCOMP_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_COUNTCOMP_VALUE_MASK) >> LOBS_STATE_COUNTCOMP_VALUE_SHIFT)
582 
583 /* Bitfield definition for register of struct array STATE: EXTMASK */
584 /*
585  * VALUE (RW)
586  *
587  * External Mask
588  */
589 #define LOBS_STATE_EXTMASK_VALUE_MASK (0xFFFFFFFFUL)
590 #define LOBS_STATE_EXTMASK_VALUE_SHIFT (0U)
591 #define LOBS_STATE_EXTMASK_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_EXTMASK_VALUE_SHIFT) & LOBS_STATE_EXTMASK_VALUE_MASK)
592 #define LOBS_STATE_EXTMASK_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_EXTMASK_VALUE_MASK) >> LOBS_STATE_EXTMASK_VALUE_SHIFT)
593 
594 /* Bitfield definition for register of struct array STATE: EXTCOMP */
595 /*
596  * VALUE (RW)
597  *
598  * External Compare
599  */
600 #define LOBS_STATE_EXTCOMP_VALUE_MASK (0xFFFFFFFFUL)
601 #define LOBS_STATE_EXTCOMP_VALUE_SHIFT (0U)
602 #define LOBS_STATE_EXTCOMP_VALUE_SET(x) (((uint32_t)(x) << LOBS_STATE_EXTCOMP_VALUE_SHIFT) & LOBS_STATE_EXTCOMP_VALUE_MASK)
603 #define LOBS_STATE_EXTCOMP_VALUE_GET(x) (((uint32_t)(x) & LOBS_STATE_EXTCOMP_VALUE_MASK) >> LOBS_STATE_EXTCOMP_VALUE_SHIFT)
604 
605 /* Bitfield definition for register of struct array STATE: SIGMASK */
606 /*
607  * NUM3 (RW)
608  *
609  * Select compare signal number3
610  */
611 #define LOBS_STATE_SIGMASK_NUM3_MASK (0xFF000000UL)
612 #define LOBS_STATE_SIGMASK_NUM3_SHIFT (24U)
613 #define LOBS_STATE_SIGMASK_NUM3_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM3_SHIFT) & LOBS_STATE_SIGMASK_NUM3_MASK)
614 #define LOBS_STATE_SIGMASK_NUM3_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM3_MASK) >> LOBS_STATE_SIGMASK_NUM3_SHIFT)
615 
616 /*
617  * NUM2 (RW)
618  *
619  * Select compare signal number2
620  */
621 #define LOBS_STATE_SIGMASK_NUM2_MASK (0xFF0000UL)
622 #define LOBS_STATE_SIGMASK_NUM2_SHIFT (16U)
623 #define LOBS_STATE_SIGMASK_NUM2_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM2_SHIFT) & LOBS_STATE_SIGMASK_NUM2_MASK)
624 #define LOBS_STATE_SIGMASK_NUM2_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM2_MASK) >> LOBS_STATE_SIGMASK_NUM2_SHIFT)
625 
626 /*
627  * NUM1 (RW)
628  *
629  * Select compare signal number1
630  */
631 #define LOBS_STATE_SIGMASK_NUM1_MASK (0xFF00U)
632 #define LOBS_STATE_SIGMASK_NUM1_SHIFT (8U)
633 #define LOBS_STATE_SIGMASK_NUM1_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM1_SHIFT) & LOBS_STATE_SIGMASK_NUM1_MASK)
634 #define LOBS_STATE_SIGMASK_NUM1_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM1_MASK) >> LOBS_STATE_SIGMASK_NUM1_SHIFT)
635 
636 /*
637  * NUM0 (RW)
638  *
639  * Select compare signal number0
640  */
641 #define LOBS_STATE_SIGMASK_NUM0_MASK (0xFFU)
642 #define LOBS_STATE_SIGMASK_NUM0_SHIFT (0U)
643 #define LOBS_STATE_SIGMASK_NUM0_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGMASK_NUM0_SHIFT) & LOBS_STATE_SIGMASK_NUM0_MASK)
644 #define LOBS_STATE_SIGMASK_NUM0_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGMASK_NUM0_MASK) >> LOBS_STATE_SIGMASK_NUM0_SHIFT)
645 
646 /* Bitfield definition for register of struct array STATE: COMPEN */
647 /*
648  * COMPLOGIC (RW)
649  *
650  * compare logic
651  * 0 and : compare signals must match simultaneously,then trigger
652  * 1 or : compare signals only need 1 signal match,then trigger
653  */
654 #define LOBS_STATE_COMPEN_COMPLOGIC_MASK (0x10U)
655 #define LOBS_STATE_COMPEN_COMPLOGIC_SHIFT (4U)
656 #define LOBS_STATE_COMPEN_COMPLOGIC_SET(x) (((uint32_t)(x) << LOBS_STATE_COMPEN_COMPLOGIC_SHIFT) & LOBS_STATE_COMPEN_COMPLOGIC_MASK)
657 #define LOBS_STATE_COMPEN_COMPLOGIC_GET(x) (((uint32_t)(x) & LOBS_STATE_COMPEN_COMPLOGIC_MASK) >> LOBS_STATE_COMPEN_COMPLOGIC_SHIFT)
658 
659 /*
660  * EN (RW)
661  *
662  * Select compare signal number0-3
663  */
664 #define LOBS_STATE_COMPEN_EN_MASK (0xFU)
665 #define LOBS_STATE_COMPEN_EN_SHIFT (0U)
666 #define LOBS_STATE_COMPEN_EN_SET(x) (((uint32_t)(x) << LOBS_STATE_COMPEN_EN_SHIFT) & LOBS_STATE_COMPEN_EN_MASK)
667 #define LOBS_STATE_COMPEN_EN_GET(x) (((uint32_t)(x) & LOBS_STATE_COMPEN_EN_MASK) >> LOBS_STATE_COMPEN_EN_SHIFT)
668 
669 /* Bitfield definition for register of struct array STATE: SIGCOMP0 */
670 /*
671  * VALUE0 (RW)
672  *
673  * Compare golden value for Signal Group signals[31:0].
674  */
675 #define LOBS_STATE_SIGCOMP0_VALUE0_MASK (0xFFFFFFFFUL)
676 #define LOBS_STATE_SIGCOMP0_VALUE0_SHIFT (0U)
677 #define LOBS_STATE_SIGCOMP0_VALUE0_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP0_VALUE0_SHIFT) & LOBS_STATE_SIGCOMP0_VALUE0_MASK)
678 #define LOBS_STATE_SIGCOMP0_VALUE0_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP0_VALUE0_MASK) >> LOBS_STATE_SIGCOMP0_VALUE0_SHIFT)
679 
680 /* Bitfield definition for register of struct array STATE: SIGCOMP1 */
681 /*
682  * VALUE1 (RW)
683  *
684  * Compare golden value for Signal Group signals[63:32].
685  */
686 #define LOBS_STATE_SIGCOMP1_VALUE1_MASK (0xFFFFFFFFUL)
687 #define LOBS_STATE_SIGCOMP1_VALUE1_SHIFT (0U)
688 #define LOBS_STATE_SIGCOMP1_VALUE1_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP1_VALUE1_SHIFT) & LOBS_STATE_SIGCOMP1_VALUE1_MASK)
689 #define LOBS_STATE_SIGCOMP1_VALUE1_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP1_VALUE1_MASK) >> LOBS_STATE_SIGCOMP1_VALUE1_SHIFT)
690 
691 /* Bitfield definition for register of struct array STATE: SIGCOMP2 */
692 /*
693  * VALUE2 (RW)
694  *
695  * Compare golden value for Signal Group signals[95:64].
696  */
697 #define LOBS_STATE_SIGCOMP2_VALUE2_MASK (0xFFFFFFFFUL)
698 #define LOBS_STATE_SIGCOMP2_VALUE2_SHIFT (0U)
699 #define LOBS_STATE_SIGCOMP2_VALUE2_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP2_VALUE2_SHIFT) & LOBS_STATE_SIGCOMP2_VALUE2_MASK)
700 #define LOBS_STATE_SIGCOMP2_VALUE2_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP2_VALUE2_MASK) >> LOBS_STATE_SIGCOMP2_VALUE2_SHIFT)
701 
702 /* Bitfield definition for register of struct array STATE: SIGCOMP3 */
703 /*
704  * VALUE3 (RW)
705  *
706  * Compare golden value for Signal Group signals[127:96].
707  */
708 #define LOBS_STATE_SIGCOMP3_VALUE3_MASK (0xFFFFFFFFUL)
709 #define LOBS_STATE_SIGCOMP3_VALUE3_SHIFT (0U)
710 #define LOBS_STATE_SIGCOMP3_VALUE3_SET(x) (((uint32_t)(x) << LOBS_STATE_SIGCOMP3_VALUE3_SHIFT) & LOBS_STATE_SIGCOMP3_VALUE3_MASK)
711 #define LOBS_STATE_SIGCOMP3_VALUE3_GET(x) (((uint32_t)(x) & LOBS_STATE_SIGCOMP3_VALUE3_MASK) >> LOBS_STATE_SIGCOMP3_VALUE3_SHIFT)
712 
713 /* Bitfield definition for register: LAR */
714 /*
715  * VALUE (RW)
716  *
717  * Lock Access Value
718  */
719 #define LOBS_LAR_VALUE_MASK (0xFFFFFFFFUL)
720 #define LOBS_LAR_VALUE_SHIFT (0U)
721 #define LOBS_LAR_VALUE_SET(x) (((uint32_t)(x) << LOBS_LAR_VALUE_SHIFT) & LOBS_LAR_VALUE_MASK)
722 #define LOBS_LAR_VALUE_GET(x) (((uint32_t)(x) & LOBS_LAR_VALUE_MASK) >> LOBS_LAR_VALUE_SHIFT)
723 
724 
725 
726 /* STATE register group index macro definition */
727 #define LOBS_STATE_0 (0UL)
728 #define LOBS_STATE_1 (1UL)
729 #define LOBS_STATE_2 (2UL)
730 #define LOBS_STATE_3 (3UL)
731 #define LOBS_STATE_4 (4UL)
732 
733 
734 #endif /* HPM_LOBS_H */
LOBS_Type
Definition: hpm_lobs_regs.h:12