LOBS_Type Struct Reference

#include <hpm_lobs_regs.h>

Data Fields
__RW uint32_t	CTRL
__RW uint32_t	IRQ_EN
__RW uint32_t	IRQ_STS
__RW uint32_t	STREAMCTRL
__RW uint32_t	PTACTION
__RW uint32_t	STARTADDR
__RW uint32_t	ENDADDR
__R uint8_t	RESERVED0 [4]
__R uint32_t	CTSR
__R uint32_t	CCVR
__R uint32_t	CAVR
__R uint8_t	RESERVED1 [4]
__R uint32_t	FIFOSTATE
__RW uint32_t	FINALADDR
__R uint8_t	RESERVED2 [8]
__RW uint32_t	TRIGADDR1
__RW uint32_t	TRIGADDR2
__RW uint32_t	TRIGADDR3
__RW uint32_t	TRIGADDR4
__RW uint32_t	GRPSELA
__RW uint32_t	GRPENA
__RW uint32_t	SIGSELA1
__R uint8_t	RESERVED3 [4]
__RW uint32_t	SIGSELA2
__R uint8_t	RESERVED4 [52]
__RW uint32_t	SIGENA
__R uint8_t	RESERVED5 [100]
struct {
__RW uint32_t   SIGSEL
__RW uint32_t   TRIGCTRL
__RW uint32_t   NEXTSTATE
__RW uint32_t   ACTION
__R uint8_t   RESERVED0 [16]
__RW uint32_t   COUNTCOMP
__R uint8_t   RESERVED1 [12]
__RW uint32_t   EXTMASK
__RW uint32_t   EXTCOMP
__R uint8_t   RESERVED2 [8]
__RW uint32_t   SIGMASK
__RW uint32_t   COMPEN
__R uint8_t   RESERVED3 [56]
__RW uint32_t   SIGCOMP0
__RW uint32_t   SIGCOMP1
__RW uint32_t   SIGCOMP2
__RW uint32_t   SIGCOMP3
__R uint8_t   RESERVED4 [112]
}	STATE [5]
__R uint8_t	RESERVED6 [2480]
__RW uint32_t	LAR
struct {
__RW uint32_t   SIGSEL
__RW uint32_t   TRIGCTRL
__RW uint32_t   NEXTSTATE
__RW uint32_t   ACTION
__R uint8_t   RESERVED0 [16]
__RW uint32_t   COUNTCOMP
__R uint8_t   RESERVED1 [12]
__RW uint32_t   EXTMASK
__RW uint32_t   EXTCOMP
__R uint8_t   RESERVED2 [8]
__RW uint32_t   SIGMASK
__RW uint32_t   COMPEN
__R uint8_t   RESERVED3 [56]
__RW uint32_t   SIGCOMP0
__RW uint32_t   SIGCOMP1
__RW uint32_t   SIGCOMP2
__RW uint32_t   SIGCOMP3
__R uint8_t   RESERVED4 [112]
}	STATE [5]
__R uint8_t	RESERVED7 [2480]
struct {
__RW uint32_t   SIGSEL
__RW uint32_t   TRIGCTRL
__RW uint32_t   NEXTSTATE
__RW uint32_t   ACTION
__R uint8_t   RESERVED0 [16]
__RW uint32_t   COUNTCOMP
__R uint8_t   RESERVED1 [12]
__RW uint32_t   EXTMASK
__RW uint32_t   EXTCOMP
__R uint8_t   RESERVED2 [8]
__RW uint32_t   SIGMASK
__RW uint32_t   COMPEN
__R uint8_t   RESERVED3 [56]
__RW uint32_t   SIGCOMP0
__RW uint32_t   SIGCOMP1
__RW uint32_t   SIGCOMP2
__RW uint32_t   SIGCOMP3
__R uint8_t   RESERVED4 [112]
}	STATE [5]

Field Documentation

ACTION

__RW uint32_t LOBS_Type::ACTION

CAVR

__R uint32_t LOBS_Type::CAVR

CCVR

__R uint32_t LOBS_Type::CCVR

COMPEN

__RW uint32_t LOBS_Type::COMPEN

COUNTCOMP

__RW uint32_t LOBS_Type::COUNTCOMP

CTRL

__RW uint32_t LOBS_Type::CTRL

CTSR

__R uint32_t LOBS_Type::CTSR

ENDADDR

__RW uint32_t LOBS_Type::ENDADDR

EXTCOMP

__RW uint32_t LOBS_Type::EXTCOMP

EXTMASK

__RW uint32_t LOBS_Type::EXTMASK

FIFOSTATE

__R uint32_t LOBS_Type::FIFOSTATE

FINALADDR

__RW uint32_t LOBS_Type::FINALADDR

GRPENA

__RW uint32_t LOBS_Type::GRPENA

GRPSELA

__RW uint32_t LOBS_Type::GRPSELA

IRQ_EN

__RW uint32_t LOBS_Type::IRQ_EN

IRQ_STS

__RW uint32_t LOBS_Type::IRQ_STS

LAR

__RW uint32_t LOBS_Type::LAR

NEXTSTATE

__RW uint32_t LOBS_Type::NEXTSTATE

PTACTION

__RW uint32_t LOBS_Type::PTACTION

RESERVED0

__R uint8_t LOBS_Type::RESERVED0

RESERVED1

__R uint8_t LOBS_Type::RESERVED1

RESERVED2

__R uint8_t LOBS_Type::RESERVED2

RESERVED3

__R uint8_t LOBS_Type::RESERVED3

RESERVED4

__R uint8_t LOBS_Type::RESERVED4

RESERVED5

__R uint8_t LOBS_Type::RESERVED5

RESERVED6

__R uint8_t LOBS_Type::RESERVED6

RESERVED7

__R uint8_t LOBS_Type::RESERVED7

SIGCOMP0

__RW uint32_t LOBS_Type::SIGCOMP0

SIGCOMP1

__RW uint32_t LOBS_Type::SIGCOMP1

SIGCOMP2

__RW uint32_t LOBS_Type::SIGCOMP2

SIGCOMP3

__RW uint32_t LOBS_Type::SIGCOMP3

SIGENA

__RW uint32_t LOBS_Type::SIGENA

SIGMASK

__RW uint32_t LOBS_Type::SIGMASK

SIGSEL

__RW uint32_t LOBS_Type::SIGSEL

SIGSELA1

__RW uint32_t LOBS_Type::SIGSELA1

SIGSELA2

__RW uint32_t LOBS_Type::SIGSELA2

STARTADDR

__RW uint32_t LOBS_Type::STARTADDR

[1/3]

struct { ... } LOBS_Type::STATE[5]

[2/3]

struct { ... } LOBS_Type::STATE[5]

[3/3]

struct { ... } LOBS_Type::STATE[5]

STREAMCTRL

__RW uint32_t LOBS_Type::STREAMCTRL

TRIGADDR1

__RW uint32_t LOBS_Type::TRIGADDR1

TRIGADDR2

__RW uint32_t LOBS_Type::TRIGADDR2

TRIGADDR3

__RW uint32_t LOBS_Type::TRIGADDR3

TRIGADDR4

__RW uint32_t LOBS_Type::TRIGADDR4

TRIGCTRL

__RW uint32_t LOBS_Type::TRIGCTRL

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The documentation for this struct was generated from the following file:

• /home/docs/checkouts/readthedocs.org/user_builds/hpm-sdk/checkouts/latest/soc/HPM5E00/ip/hpm_lobs_regs.h