HPM SDK
HPMicro Software Development Kit
hpm_qeiv2_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_QEIV2_H
10 #define HPM_QEIV2_H
11 
12 typedef struct {
13  __RW uint32_t CR; /* 0x0: Control register */
14  __RW uint32_t PHCFG; /* 0x4: Phase configure register */
15  __RW uint32_t WDGCFG; /* 0x8: Watchdog configure register */
16  __RW uint32_t PHIDX; /* 0xC: Phase index register */
17  __RW uint32_t TRGOEN; /* 0x10: Tigger output enable register */
18  __RW uint32_t READEN; /* 0x14: Read event enable register */
19  __RW uint32_t ZCMP; /* 0x18: Z comparator */
20  __RW uint32_t PHCMP; /* 0x1C: Phase comparator */
21  __RW uint32_t SPDCMP; /* 0x20: Speed comparator */
22  __RW uint32_t DMAEN; /* 0x24: DMA request enable register */
23  __RW uint32_t SR; /* 0x28: Status register */
24  __RW uint32_t IRQEN; /* 0x2C: Interrupt request register */
25  struct {
26  __RW uint32_t Z; /* 0x30: Z counter */
27  __R uint32_t PH; /* 0x34: Phase counter */
28  __RW uint32_t SPD; /* 0x38: Speed counter */
29  __R uint32_t TMR; /* 0x3C: Timer counter */
30  } COUNT[4];
31  __R uint8_t RESERVED0[16]; /* 0x70 - 0x7F: Reserved */
32  __RW uint32_t ZCMP2; /* 0x80: Z comparator */
33  __RW uint32_t PHCMP2; /* 0x84: Phase comparator */
34  __RW uint32_t SPDCMP2; /* 0x88: Speed comparator */
35  __RW uint32_t MATCH_CFG; /* 0x8C: */
36  __RW uint32_t FILT_CFG[6]; /* 0x90 - 0xA4: A signal filter config */
37  __R uint8_t RESERVED1[88]; /* 0xA8 - 0xFF: Reserved */
38  __RW uint32_t QEI_CFG; /* 0x100: qei config register */
39  __R uint8_t RESERVED2[12]; /* 0x104 - 0x10F: Reserved */
40  __RW uint32_t PULSE0_NUM; /* 0x110: pulse0_num */
41  __RW uint32_t PULSE1_NUM; /* 0x114: pulse1_num */
42  __R uint32_t CYCLE0_CNT; /* 0x118: cycle0_cnt */
43  __R uint32_t CYCLE0PULSE_CNT; /* 0x11C: cycle0pulse_cnt */
44  __R uint32_t CYCLE1_CNT; /* 0x120: cycle1_cnt */
45  __R uint32_t CYCLE1PULSE_CNT; /* 0x124: cycle1pulse_cnt */
46  __R uint32_t CYCLE0_SNAP0; /* 0x128: cycle0_snap0 */
47  __R uint32_t CYCLE0_SNAP1; /* 0x12C: cycle0_snap1 */
48  __R uint32_t CYCLE1_SNAP0; /* 0x130: cycle1_snap0 */
49  __R uint32_t CYCLE1_SNAP1; /* 0x134: cycle1_snap1 */
50  __R uint8_t RESERVED3[8]; /* 0x138 - 0x13F: Reserved */
51  __RW uint32_t CYCLE0_NUM; /* 0x140: cycle0_num */
52  __RW uint32_t CYCLE1_NUM; /* 0x144: cycle1_num */
53  __R uint32_t PULSE0_CNT; /* 0x148: pulse0_cnt */
54  __R uint32_t PULSE0CYCLE_CNT; /* 0x14C: pulse0cycle_cnt */
55  __R uint32_t PULSE1_CNT; /* 0x150: pulse1_cnt */
56  __R uint32_t PULSE1CYCLE_CNT; /* 0x154: pulse1cycle_cnt */
57  __R uint32_t PULSE0_SNAP0; /* 0x158: pulse0_snap0 */
58  __R uint32_t PULSE0CYCLE_SNAP0; /* 0x15C: pulse0cycle_snap0 */
59  __R uint32_t PULSE0_SNAP1; /* 0x160: pulse0_snap1 */
60  __R uint32_t PULSE0CYCLE_SNAP1; /* 0x164: pulse0cycle_snap1 */
61  __R uint32_t PULSE1_SNAP0; /* 0x168: pulse1_snap0 */
62  __R uint32_t PULSE1CYCLE_SNAP0; /* 0x16C: pulse1cycle_snap0 */
63  __R uint32_t PULSE1_SNAP1; /* 0x170: pulse1_snap1 */
64  __R uint32_t PULSE1CYCLE_SNAP1; /* 0x174: pulse1cycle_snap1 */
65  __R uint8_t RESERVED4[104]; /* 0x178 - 0x1DF: Reserved */
66  __R uint32_t TIMESTAMP; /* 0x1E0: timestamp */
67  __R uint8_t RESERVED5[12]; /* 0x1E4 - 0x1EF: Reserved */
68  __RW uint32_t ADC_THRESHOLD; /* 0x1F0: adc_threshold */
69  __R uint8_t RESERVED6[12]; /* 0x1F4 - 0x1FF: Reserved */
70  __RW uint32_t ADCX_CFG0; /* 0x200: adcx_cfg0 */
71  __RW uint32_t ADCX_CFG1; /* 0x204: adcx_cfg1 */
72  __RW uint32_t ADCX_CFG2; /* 0x208: adcx_cfg2 */
73  __RW uint32_t ADCX_VAL_SW; /* 0x20C: adcx_val_sw */
74  __RW uint32_t ADCY_CFG0; /* 0x210: adcy_cfg0 */
75  __RW uint32_t ADCY_CFG1; /* 0x214: adcy_cfg1 */
76  __RW uint32_t ADCY_CFG2; /* 0x218: adcy_cfg2 */
77  __RW uint32_t ADCY_VAL_SW; /* 0x21C: adcy_val_sw */
78  __RW uint32_t CAL_CFG; /* 0x220: cal_cfg */
79  __RW uint32_t ADC_INJECT_CTRL; /* 0x224: adc_inject_ctrl */
80  __R uint8_t RESERVED7[8]; /* 0x228 - 0x22F: Reserved */
81  __RW uint32_t PHASE_PARAM; /* 0x230: phase_param */
82  __RW uint32_t POS_ADJ; /* 0x234: pos_adj */
83  __RW uint32_t POS_THRESHOLD; /* 0x238: pos_threshold */
84  __R uint8_t RESERVED8[4]; /* 0x23C - 0x23F: Reserved */
85  __RW uint32_t UVW_POS[6]; /* 0x240 - 0x254: uvw_pos0 */
86  __RW uint32_t UVW_POS_CFG[6]; /* 0x258 - 0x26C: uvw_pos0_cfg */
87  __R uint8_t RESERVED9[16]; /* 0x270 - 0x27F: Reserved */
88  __RW uint32_t PHASE_CNT; /* 0x280: phase_cnt */
89  __W uint32_t PHASE_UPDATE; /* 0x284: phase_update */
90  __RW uint32_t POSITION; /* 0x288: position */
91  __W uint32_t POSITION_UPDATE; /* 0x28C: position_update */
92  __R uint32_t ANGLE; /* 0x290: angle */
93  __RW uint32_t POS_TIMEOUT; /* 0x294: pos_timeout */
94  __R uint8_t RESERVED10[8]; /* 0x298 - 0x29F: Reserved */
95  __R uint32_t CALC_STATE; /* 0x2A0: calc_state */
96  __R uint8_t RESERVED11[28]; /* 0x2A4 - 0x2BF: Reserved */
97  __RW uint32_t TOGI_CFG0; /* 0x2C0: togi_cfg0 */
98  __RW uint32_t TOGI_CFG1; /* 0x2C4: togi_cfg1 */
99  __R uint8_t RESERVED12[8]; /* 0x2C8 - 0x2CF: Reserved */
100  __R uint32_t SINP_ACC; /* 0x2D0: sinp_acc */
101  __R uint32_t SINN_ACC; /* 0x2D4: sinn_acc */
102  __R uint32_t COSP_ACC; /* 0x2D8: cosp_acc */
103  __R uint32_t COSN_ACC; /* 0x2DC: cosn_acc */
104 } QEIV2_Type;
105 
106 
107 /* Bitfield definition for register: CR */
108 /*
109  * READ (WO)
110  *
111  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their read registers. Hardware auto-clear; read as 0
112  */
113 #define QEIV2_CR_READ_MASK (0x80000000UL)
114 #define QEIV2_CR_READ_SHIFT (31U)
115 #define QEIV2_CR_READ_SET(x) (((uint32_t)(x) << QEIV2_CR_READ_SHIFT) & QEIV2_CR_READ_MASK)
116 #define QEIV2_CR_READ_GET(x) (((uint32_t)(x) & QEIV2_CR_READ_MASK) >> QEIV2_CR_READ_SHIFT)
117 
118 /*
119  * ZCNTCFG (RW)
120  *
121  * 1- zcnt will increment when phcnt upcount to phmax, decrement when phcnt downcount to 0
122  * 0- zcnt will increment or decrement when Z input assert
123  */
124 #define QEIV2_CR_ZCNTCFG_MASK (0x400000UL)
125 #define QEIV2_CR_ZCNTCFG_SHIFT (22U)
126 #define QEIV2_CR_ZCNTCFG_SET(x) (((uint32_t)(x) << QEIV2_CR_ZCNTCFG_SHIFT) & QEIV2_CR_ZCNTCFG_MASK)
127 #define QEIV2_CR_ZCNTCFG_GET(x) (((uint32_t)(x) & QEIV2_CR_ZCNTCFG_MASK) >> QEIV2_CR_ZCNTCFG_SHIFT)
128 
129 /*
130  * PHCALIZ (RW)
131  *
132  * 1- phcnt will set to phidx when Z input assert(for abz digital signsl)
133  */
134 #define QEIV2_CR_PHCALIZ_MASK (0x200000UL)
135 #define QEIV2_CR_PHCALIZ_SHIFT (21U)
136 #define QEIV2_CR_PHCALIZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PHCALIZ_SHIFT) & QEIV2_CR_PHCALIZ_MASK)
137 #define QEIV2_CR_PHCALIZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PHCALIZ_MASK) >> QEIV2_CR_PHCALIZ_SHIFT)
138 
139 /*
140  * Z_ONLY_EN (RW)
141  *
142  * 1- phcnt will set to phidx when Z input assert(only using z phase, ignore ab phase signals)
143  */
144 #define QEIV2_CR_Z_ONLY_EN_MASK (0x100000UL)
145 #define QEIV2_CR_Z_ONLY_EN_SHIFT (20U)
146 #define QEIV2_CR_Z_ONLY_EN_SET(x) (((uint32_t)(x) << QEIV2_CR_Z_ONLY_EN_SHIFT) & QEIV2_CR_Z_ONLY_EN_MASK)
147 #define QEIV2_CR_Z_ONLY_EN_GET(x) (((uint32_t)(x) & QEIV2_CR_Z_ONLY_EN_MASK) >> QEIV2_CR_Z_ONLY_EN_SHIFT)
148 
149 /*
150  * H2FDIR0 (RW)
151  *
152  */
153 #define QEIV2_CR_H2FDIR0_MASK (0x80000UL)
154 #define QEIV2_CR_H2FDIR0_SHIFT (19U)
155 #define QEIV2_CR_H2FDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR0_SHIFT) & QEIV2_CR_H2FDIR0_MASK)
156 #define QEIV2_CR_H2FDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR0_MASK) >> QEIV2_CR_H2FDIR0_SHIFT)
157 
158 /*
159  * H2FDIR1 (RW)
160  *
161  */
162 #define QEIV2_CR_H2FDIR1_MASK (0x40000UL)
163 #define QEIV2_CR_H2FDIR1_SHIFT (18U)
164 #define QEIV2_CR_H2FDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2FDIR1_SHIFT) & QEIV2_CR_H2FDIR1_MASK)
165 #define QEIV2_CR_H2FDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2FDIR1_MASK) >> QEIV2_CR_H2FDIR1_SHIFT)
166 
167 /*
168  * H2RDIR0 (RW)
169  *
170  */
171 #define QEIV2_CR_H2RDIR0_MASK (0x20000UL)
172 #define QEIV2_CR_H2RDIR0_SHIFT (17U)
173 #define QEIV2_CR_H2RDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR0_SHIFT) & QEIV2_CR_H2RDIR0_MASK)
174 #define QEIV2_CR_H2RDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR0_MASK) >> QEIV2_CR_H2RDIR0_SHIFT)
175 
176 /*
177  * H2RDIR1 (RW)
178  *
179  */
180 #define QEIV2_CR_H2RDIR1_MASK (0x10000UL)
181 #define QEIV2_CR_H2RDIR1_SHIFT (16U)
182 #define QEIV2_CR_H2RDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_H2RDIR1_SHIFT) & QEIV2_CR_H2RDIR1_MASK)
183 #define QEIV2_CR_H2RDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_H2RDIR1_MASK) >> QEIV2_CR_H2RDIR1_SHIFT)
184 
185 /*
186  * PAUSEPOS (RW)
187  *
188  * 1- pause position output valid when PAUSE assert
189  */
190 #define QEIV2_CR_PAUSEPOS_MASK (0x8000U)
191 #define QEIV2_CR_PAUSEPOS_SHIFT (15U)
192 #define QEIV2_CR_PAUSEPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPOS_SHIFT) & QEIV2_CR_PAUSEPOS_MASK)
193 #define QEIV2_CR_PAUSEPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPOS_MASK) >> QEIV2_CR_PAUSEPOS_SHIFT)
194 
195 /*
196  * PAUSESPD (RW)
197  *
198  * 1- pause spdcnt when PAUSE assert
199  */
200 #define QEIV2_CR_PAUSESPD_MASK (0x4000U)
201 #define QEIV2_CR_PAUSESPD_SHIFT (14U)
202 #define QEIV2_CR_PAUSESPD_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSESPD_SHIFT) & QEIV2_CR_PAUSESPD_MASK)
203 #define QEIV2_CR_PAUSESPD_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSESPD_MASK) >> QEIV2_CR_PAUSESPD_SHIFT)
204 
205 /*
206  * PAUSEPH (RW)
207  *
208  * 1- pause phcnt when PAUSE assert
209  */
210 #define QEIV2_CR_PAUSEPH_MASK (0x2000U)
211 #define QEIV2_CR_PAUSEPH_SHIFT (13U)
212 #define QEIV2_CR_PAUSEPH_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEPH_SHIFT) & QEIV2_CR_PAUSEPH_MASK)
213 #define QEIV2_CR_PAUSEPH_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEPH_MASK) >> QEIV2_CR_PAUSEPH_SHIFT)
214 
215 /*
216  * PAUSEZ (RW)
217  *
218  * 1- pause zcnt when PAUSE assert
219  */
220 #define QEIV2_CR_PAUSEZ_MASK (0x1000U)
221 #define QEIV2_CR_PAUSEZ_SHIFT (12U)
222 #define QEIV2_CR_PAUSEZ_SET(x) (((uint32_t)(x) << QEIV2_CR_PAUSEZ_SHIFT) & QEIV2_CR_PAUSEZ_MASK)
223 #define QEIV2_CR_PAUSEZ_GET(x) (((uint32_t)(x) & QEIV2_CR_PAUSEZ_MASK) >> QEIV2_CR_PAUSEZ_SHIFT)
224 
225 /*
226  * HFDIR0 (RW)
227  *
228  * 1- HOMEF will set at H rising edge when dir == 1 (negative rotation direction)
229  */
230 #define QEIV2_CR_HFDIR0_MASK (0x800U)
231 #define QEIV2_CR_HFDIR0_SHIFT (11U)
232 #define QEIV2_CR_HFDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR0_SHIFT) & QEIV2_CR_HFDIR0_MASK)
233 #define QEIV2_CR_HFDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR0_MASK) >> QEIV2_CR_HFDIR0_SHIFT)
234 
235 /*
236  * HFDIR1 (RW)
237  *
238  * 1- HOMEF will set at H rising edge when dir == 0 (positive rotation direction)
239  */
240 #define QEIV2_CR_HFDIR1_MASK (0x400U)
241 #define QEIV2_CR_HFDIR1_SHIFT (10U)
242 #define QEIV2_CR_HFDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HFDIR1_SHIFT) & QEIV2_CR_HFDIR1_MASK)
243 #define QEIV2_CR_HFDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HFDIR1_MASK) >> QEIV2_CR_HFDIR1_SHIFT)
244 
245 /*
246  * HRDIR0 (RW)
247  *
248  * 1- HOMEF will set at H falling edge when dir == 1 (negative rotation direction)
249  */
250 #define QEIV2_CR_HRDIR0_MASK (0x200U)
251 #define QEIV2_CR_HRDIR0_SHIFT (9U)
252 #define QEIV2_CR_HRDIR0_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR0_SHIFT) & QEIV2_CR_HRDIR0_MASK)
253 #define QEIV2_CR_HRDIR0_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR0_MASK) >> QEIV2_CR_HRDIR0_SHIFT)
254 
255 /*
256  * HRDIR1 (RW)
257  *
258  * 1- HOMEF will set at H falling edge when dir == 1 (positive rotation direction)
259  */
260 #define QEIV2_CR_HRDIR1_MASK (0x100U)
261 #define QEIV2_CR_HRDIR1_SHIFT (8U)
262 #define QEIV2_CR_HRDIR1_SET(x) (((uint32_t)(x) << QEIV2_CR_HRDIR1_SHIFT) & QEIV2_CR_HRDIR1_MASK)
263 #define QEIV2_CR_HRDIR1_GET(x) (((uint32_t)(x) & QEIV2_CR_HRDIR1_MASK) >> QEIV2_CR_HRDIR1_SHIFT)
264 
265 /*
266  * FAULTPOS (RW)
267  *
268  */
269 #define QEIV2_CR_FAULTPOS_MASK (0x40U)
270 #define QEIV2_CR_FAULTPOS_SHIFT (6U)
271 #define QEIV2_CR_FAULTPOS_SET(x) (((uint32_t)(x) << QEIV2_CR_FAULTPOS_SHIFT) & QEIV2_CR_FAULTPOS_MASK)
272 #define QEIV2_CR_FAULTPOS_GET(x) (((uint32_t)(x) & QEIV2_CR_FAULTPOS_MASK) >> QEIV2_CR_FAULTPOS_SHIFT)
273 
274 /*
275  * SNAPEN (RW)
276  *
277  * 1- load phcnt, zcnt, spdcnt and tmrcnt into their snap registers when snapi input assert
278  */
279 #define QEIV2_CR_SNAPEN_MASK (0x20U)
280 #define QEIV2_CR_SNAPEN_SHIFT (5U)
281 #define QEIV2_CR_SNAPEN_SET(x) (((uint32_t)(x) << QEIV2_CR_SNAPEN_SHIFT) & QEIV2_CR_SNAPEN_MASK)
282 #define QEIV2_CR_SNAPEN_GET(x) (((uint32_t)(x) & QEIV2_CR_SNAPEN_MASK) >> QEIV2_CR_SNAPEN_SHIFT)
283 
284 /*
285  * RSTCNT (RW)
286  *
287  * 1- reset zcnt, spdcnt and tmrcnt to 0. reset phcnt to phidx
288  */
289 #define QEIV2_CR_RSTCNT_MASK (0x10U)
290 #define QEIV2_CR_RSTCNT_SHIFT (4U)
291 #define QEIV2_CR_RSTCNT_SET(x) (((uint32_t)(x) << QEIV2_CR_RSTCNT_SHIFT) & QEIV2_CR_RSTCNT_MASK)
292 #define QEIV2_CR_RSTCNT_GET(x) (((uint32_t)(x) & QEIV2_CR_RSTCNT_MASK) >> QEIV2_CR_RSTCNT_SHIFT)
293 
294 /*
295  * RD_SEL (RW)
296  *
297  * define the width/counter value(affect width_match, width_match2, width_cur, timer_cur, width_read, timer_read,
298  * width_snap0,width_snap1, timer_snap0, timer_snap1)
299  * 0 : same as hpm1000/500/500s;
300  * 1: use width for position; use timer for angle
301  */
302 #define QEIV2_CR_RD_SEL_MASK (0x8U)
303 #define QEIV2_CR_RD_SEL_SHIFT (3U)
304 #define QEIV2_CR_RD_SEL_SET(x) (((uint32_t)(x) << QEIV2_CR_RD_SEL_SHIFT) & QEIV2_CR_RD_SEL_MASK)
305 #define QEIV2_CR_RD_SEL_GET(x) (((uint32_t)(x) & QEIV2_CR_RD_SEL_MASK) >> QEIV2_CR_RD_SEL_SHIFT)
306 
307 /*
308  * ENCTYP (RW)
309  *
310  * 000-abz; 001-pd; 010-ud; 011-UVW(hal)
311  * 100-single A; 101-single sin; 110: sin&cos
312  */
313 #define QEIV2_CR_ENCTYP_MASK (0x7U)
314 #define QEIV2_CR_ENCTYP_SHIFT (0U)
315 #define QEIV2_CR_ENCTYP_SET(x) (((uint32_t)(x) << QEIV2_CR_ENCTYP_SHIFT) & QEIV2_CR_ENCTYP_MASK)
316 #define QEIV2_CR_ENCTYP_GET(x) (((uint32_t)(x) & QEIV2_CR_ENCTYP_MASK) >> QEIV2_CR_ENCTYP_SHIFT)
317 
318 /* Bitfield definition for register: PHCFG */
319 /*
320  * PHMAX (RW)
321  *
322  * maximum phcnt number, phcnt will rollover to 0 when it upcount to phmax
323  */
324 #define QEIV2_PHCFG_PHMAX_MASK (0xFFFFFFFFUL)
325 #define QEIV2_PHCFG_PHMAX_SHIFT (0U)
326 #define QEIV2_PHCFG_PHMAX_SET(x) (((uint32_t)(x) << QEIV2_PHCFG_PHMAX_SHIFT) & QEIV2_PHCFG_PHMAX_MASK)
327 #define QEIV2_PHCFG_PHMAX_GET(x) (((uint32_t)(x) & QEIV2_PHCFG_PHMAX_MASK) >> QEIV2_PHCFG_PHMAX_SHIFT)
328 
329 /* Bitfield definition for register: WDGCFG */
330 /*
331  * WDGEN (RW)
332  *
333  * 1- enable wdog counter
334  */
335 #define QEIV2_WDGCFG_WDGEN_MASK (0x80000000UL)
336 #define QEIV2_WDGCFG_WDGEN_SHIFT (31U)
337 #define QEIV2_WDGCFG_WDGEN_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGEN_SHIFT) & QEIV2_WDGCFG_WDGEN_MASK)
338 #define QEIV2_WDGCFG_WDGEN_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGEN_MASK) >> QEIV2_WDGCFG_WDGEN_SHIFT)
339 
340 /*
341  * WDOG_CFG (RW)
342  *
343  * define as stop if phase_cnt change is less than it
344  * if 0, then each change of phase_cnt will clear wdog counter;
345  * if 2, then phase_cnt change larger than 2 will clear wdog counter
346  */
347 #define QEIV2_WDGCFG_WDOG_CFG_MASK (0x70000000UL)
348 #define QEIV2_WDGCFG_WDOG_CFG_SHIFT (28U)
349 #define QEIV2_WDGCFG_WDOG_CFG_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDOG_CFG_SHIFT) & QEIV2_WDGCFG_WDOG_CFG_MASK)
350 #define QEIV2_WDGCFG_WDOG_CFG_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDOG_CFG_MASK) >> QEIV2_WDGCFG_WDOG_CFG_SHIFT)
351 
352 /*
353  * WDGTO (RW)
354  *
355  * watch dog timeout value
356  */
357 #define QEIV2_WDGCFG_WDGTO_MASK (0xFFFFFFFUL)
358 #define QEIV2_WDGCFG_WDGTO_SHIFT (0U)
359 #define QEIV2_WDGCFG_WDGTO_SET(x) (((uint32_t)(x) << QEIV2_WDGCFG_WDGTO_SHIFT) & QEIV2_WDGCFG_WDGTO_MASK)
360 #define QEIV2_WDGCFG_WDGTO_GET(x) (((uint32_t)(x) & QEIV2_WDGCFG_WDGTO_MASK) >> QEIV2_WDGCFG_WDGTO_SHIFT)
361 
362 /* Bitfield definition for register: PHIDX */
363 /*
364  * PHIDX (RW)
365  *
366  * phcnt reset value, phcnt will reset to phidx when phcaliz set to 1
367  */
368 #define QEIV2_PHIDX_PHIDX_MASK (0xFFFFFFFFUL)
369 #define QEIV2_PHIDX_PHIDX_SHIFT (0U)
370 #define QEIV2_PHIDX_PHIDX_SET(x) (((uint32_t)(x) << QEIV2_PHIDX_PHIDX_SHIFT) & QEIV2_PHIDX_PHIDX_MASK)
371 #define QEIV2_PHIDX_PHIDX_GET(x) (((uint32_t)(x) & QEIV2_PHIDX_PHIDX_MASK) >> QEIV2_PHIDX_PHIDX_SHIFT)
372 
373 /* Bitfield definition for register: TRGOEN */
374 /*
375  * WDGFEN (RW)
376  *
377  * 1- enable trigger output when wdg flag set
378  */
379 #define QEIV2_TRGOEN_WDGFEN_MASK (0x80000000UL)
380 #define QEIV2_TRGOEN_WDGFEN_SHIFT (31U)
381 #define QEIV2_TRGOEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WDGFEN_SHIFT) & QEIV2_TRGOEN_WDGFEN_MASK)
382 #define QEIV2_TRGOEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WDGFEN_MASK) >> QEIV2_TRGOEN_WDGFEN_SHIFT)
383 
384 /*
385  * HOMEFEN (RW)
386  *
387  * 1- enable trigger output when homef flag set
388  */
389 #define QEIV2_TRGOEN_HOMEFEN_MASK (0x40000000UL)
390 #define QEIV2_TRGOEN_HOMEFEN_SHIFT (30U)
391 #define QEIV2_TRGOEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOMEFEN_SHIFT) & QEIV2_TRGOEN_HOMEFEN_MASK)
392 #define QEIV2_TRGOEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOMEFEN_MASK) >> QEIV2_TRGOEN_HOMEFEN_SHIFT)
393 
394 /*
395  * POSCMPFEN (RW)
396  *
397  * 1- enable trigger output when poscmpf flag set
398  */
399 #define QEIV2_TRGOEN_POSCMPFEN_MASK (0x20000000UL)
400 #define QEIV2_TRGOEN_POSCMPFEN_SHIFT (29U)
401 #define QEIV2_TRGOEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POSCMPFEN_SHIFT) & QEIV2_TRGOEN_POSCMPFEN_MASK)
402 #define QEIV2_TRGOEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POSCMPFEN_MASK) >> QEIV2_TRGOEN_POSCMPFEN_SHIFT)
403 
404 /*
405  * ZPHFEN (RW)
406  *
407  * 1- enable trigger output when zphf flag set
408  */
409 #define QEIV2_TRGOEN_ZPHFEN_MASK (0x10000000UL)
410 #define QEIV2_TRGOEN_ZPHFEN_SHIFT (28U)
411 #define QEIV2_TRGOEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZPHFEN_SHIFT) & QEIV2_TRGOEN_ZPHFEN_MASK)
412 #define QEIV2_TRGOEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZPHFEN_MASK) >> QEIV2_TRGOEN_ZPHFEN_SHIFT)
413 
414 /*
415  * ZMISSFEN (RW)
416  *
417  */
418 #define QEIV2_TRGOEN_ZMISSFEN_MASK (0x8000000UL)
419 #define QEIV2_TRGOEN_ZMISSFEN_SHIFT (27U)
420 #define QEIV2_TRGOEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_ZMISSFEN_SHIFT) & QEIV2_TRGOEN_ZMISSFEN_MASK)
421 #define QEIV2_TRGOEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_ZMISSFEN_MASK) >> QEIV2_TRGOEN_ZMISSFEN_SHIFT)
422 
423 /*
424  * WIDTHTMFEN (RW)
425  *
426  */
427 #define QEIV2_TRGOEN_WIDTHTMFEN_MASK (0x4000000UL)
428 #define QEIV2_TRGOEN_WIDTHTMFEN_SHIFT (26U)
429 #define QEIV2_TRGOEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_WIDTHTMFEN_SHIFT) & QEIV2_TRGOEN_WIDTHTMFEN_MASK)
430 #define QEIV2_TRGOEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_WIDTHTMFEN_MASK) >> QEIV2_TRGOEN_WIDTHTMFEN_SHIFT)
431 
432 /*
433  * POS2CMPFEN (RW)
434  *
435  */
436 #define QEIV2_TRGOEN_POS2CMPFEN_MASK (0x2000000UL)
437 #define QEIV2_TRGOEN_POS2CMPFEN_SHIFT (25U)
438 #define QEIV2_TRGOEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_POS2CMPFEN_SHIFT) & QEIV2_TRGOEN_POS2CMPFEN_MASK)
439 #define QEIV2_TRGOEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_POS2CMPFEN_MASK) >> QEIV2_TRGOEN_POS2CMPFEN_SHIFT)
440 
441 /*
442  * DIRCHGFEN (RW)
443  *
444  */
445 #define QEIV2_TRGOEN_DIRCHGFEN_MASK (0x1000000UL)
446 #define QEIV2_TRGOEN_DIRCHGFEN_SHIFT (24U)
447 #define QEIV2_TRGOEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_DIRCHGFEN_SHIFT) & QEIV2_TRGOEN_DIRCHGFEN_MASK)
448 #define QEIV2_TRGOEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_DIRCHGFEN_MASK) >> QEIV2_TRGOEN_DIRCHGFEN_SHIFT)
449 
450 /*
451  * CYCLE0FEN (RW)
452  *
453  */
454 #define QEIV2_TRGOEN_CYCLE0FEN_MASK (0x800000UL)
455 #define QEIV2_TRGOEN_CYCLE0FEN_SHIFT (23U)
456 #define QEIV2_TRGOEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE0FEN_SHIFT) & QEIV2_TRGOEN_CYCLE0FEN_MASK)
457 #define QEIV2_TRGOEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE0FEN_MASK) >> QEIV2_TRGOEN_CYCLE0FEN_SHIFT)
458 
459 /*
460  * CYCLE1FEN (RW)
461  *
462  */
463 #define QEIV2_TRGOEN_CYCLE1FEN_MASK (0x400000UL)
464 #define QEIV2_TRGOEN_CYCLE1FEN_SHIFT (22U)
465 #define QEIV2_TRGOEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_CYCLE1FEN_SHIFT) & QEIV2_TRGOEN_CYCLE1FEN_MASK)
466 #define QEIV2_TRGOEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_CYCLE1FEN_MASK) >> QEIV2_TRGOEN_CYCLE1FEN_SHIFT)
467 
468 /*
469  * PULSE0FEN (RW)
470  *
471  */
472 #define QEIV2_TRGOEN_PULSE0FEN_MASK (0x200000UL)
473 #define QEIV2_TRGOEN_PULSE0FEN_SHIFT (21U)
474 #define QEIV2_TRGOEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE0FEN_SHIFT) & QEIV2_TRGOEN_PULSE0FEN_MASK)
475 #define QEIV2_TRGOEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE0FEN_MASK) >> QEIV2_TRGOEN_PULSE0FEN_SHIFT)
476 
477 /*
478  * PULSE1FEN (RW)
479  *
480  */
481 #define QEIV2_TRGOEN_PULSE1FEN_MASK (0x100000UL)
482 #define QEIV2_TRGOEN_PULSE1FEN_SHIFT (20U)
483 #define QEIV2_TRGOEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_PULSE1FEN_SHIFT) & QEIV2_TRGOEN_PULSE1FEN_MASK)
484 #define QEIV2_TRGOEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_PULSE1FEN_MASK) >> QEIV2_TRGOEN_PULSE1FEN_SHIFT)
485 
486 /*
487  * HOME2FEN (RW)
488  *
489  */
490 #define QEIV2_TRGOEN_HOME2FEN_MASK (0x80000UL)
491 #define QEIV2_TRGOEN_HOME2FEN_SHIFT (19U)
492 #define QEIV2_TRGOEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_HOME2FEN_SHIFT) & QEIV2_TRGOEN_HOME2FEN_MASK)
493 #define QEIV2_TRGOEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_HOME2FEN_MASK) >> QEIV2_TRGOEN_HOME2FEN_SHIFT)
494 
495 /*
496  * FAULTFEN (RW)
497  *
498  */
499 #define QEIV2_TRGOEN_FAULTFEN_MASK (0x40000UL)
500 #define QEIV2_TRGOEN_FAULTFEN_SHIFT (18U)
501 #define QEIV2_TRGOEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_TRGOEN_FAULTFEN_SHIFT) & QEIV2_TRGOEN_FAULTFEN_MASK)
502 #define QEIV2_TRGOEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_TRGOEN_FAULTFEN_MASK) >> QEIV2_TRGOEN_FAULTFEN_SHIFT)
503 
504 /* Bitfield definition for register: READEN */
505 /*
506  * WDGFEN (RW)
507  *
508  * 1- load counters to their read registers when wdg flag set
509  */
510 #define QEIV2_READEN_WDGFEN_MASK (0x80000000UL)
511 #define QEIV2_READEN_WDGFEN_SHIFT (31U)
512 #define QEIV2_READEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WDGFEN_SHIFT) & QEIV2_READEN_WDGFEN_MASK)
513 #define QEIV2_READEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WDGFEN_MASK) >> QEIV2_READEN_WDGFEN_SHIFT)
514 
515 /*
516  * HOMEFEN (RW)
517  *
518  * 1- load counters to their read registers when homef flag set
519  */
520 #define QEIV2_READEN_HOMEFEN_MASK (0x40000000UL)
521 #define QEIV2_READEN_HOMEFEN_SHIFT (30U)
522 #define QEIV2_READEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOMEFEN_SHIFT) & QEIV2_READEN_HOMEFEN_MASK)
523 #define QEIV2_READEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOMEFEN_MASK) >> QEIV2_READEN_HOMEFEN_SHIFT)
524 
525 /*
526  * POSCMPFEN (RW)
527  *
528  * 1- load counters to their read registers when poscmpf flag set
529  */
530 #define QEIV2_READEN_POSCMPFEN_MASK (0x20000000UL)
531 #define QEIV2_READEN_POSCMPFEN_SHIFT (29U)
532 #define QEIV2_READEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POSCMPFEN_SHIFT) & QEIV2_READEN_POSCMPFEN_MASK)
533 #define QEIV2_READEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POSCMPFEN_MASK) >> QEIV2_READEN_POSCMPFEN_SHIFT)
534 
535 /*
536  * ZPHFEN (RW)
537  *
538  * 1- load counters to their read registers when zphf flag set
539  */
540 #define QEIV2_READEN_ZPHFEN_MASK (0x10000000UL)
541 #define QEIV2_READEN_ZPHFEN_SHIFT (28U)
542 #define QEIV2_READEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZPHFEN_SHIFT) & QEIV2_READEN_ZPHFEN_MASK)
543 #define QEIV2_READEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZPHFEN_MASK) >> QEIV2_READEN_ZPHFEN_SHIFT)
544 
545 /*
546  * ZMISSFEN (RW)
547  *
548  */
549 #define QEIV2_READEN_ZMISSFEN_MASK (0x8000000UL)
550 #define QEIV2_READEN_ZMISSFEN_SHIFT (27U)
551 #define QEIV2_READEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_ZMISSFEN_SHIFT) & QEIV2_READEN_ZMISSFEN_MASK)
552 #define QEIV2_READEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_ZMISSFEN_MASK) >> QEIV2_READEN_ZMISSFEN_SHIFT)
553 
554 /*
555  * WIDTHTMFEN (RW)
556  *
557  */
558 #define QEIV2_READEN_WIDTHTMFEN_MASK (0x4000000UL)
559 #define QEIV2_READEN_WIDTHTMFEN_SHIFT (26U)
560 #define QEIV2_READEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_WIDTHTMFEN_SHIFT) & QEIV2_READEN_WIDTHTMFEN_MASK)
561 #define QEIV2_READEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_WIDTHTMFEN_MASK) >> QEIV2_READEN_WIDTHTMFEN_SHIFT)
562 
563 /*
564  * POS2CMPFEN (RW)
565  *
566  */
567 #define QEIV2_READEN_POS2CMPFEN_MASK (0x2000000UL)
568 #define QEIV2_READEN_POS2CMPFEN_SHIFT (25U)
569 #define QEIV2_READEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_POS2CMPFEN_SHIFT) & QEIV2_READEN_POS2CMPFEN_MASK)
570 #define QEIV2_READEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_POS2CMPFEN_MASK) >> QEIV2_READEN_POS2CMPFEN_SHIFT)
571 
572 /*
573  * DIRCHGFEN (RW)
574  *
575  */
576 #define QEIV2_READEN_DIRCHGFEN_MASK (0x1000000UL)
577 #define QEIV2_READEN_DIRCHGFEN_SHIFT (24U)
578 #define QEIV2_READEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_DIRCHGFEN_SHIFT) & QEIV2_READEN_DIRCHGFEN_MASK)
579 #define QEIV2_READEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_DIRCHGFEN_MASK) >> QEIV2_READEN_DIRCHGFEN_SHIFT)
580 
581 /*
582  * CYCLE0FEN (RW)
583  *
584  */
585 #define QEIV2_READEN_CYCLE0FEN_MASK (0x800000UL)
586 #define QEIV2_READEN_CYCLE0FEN_SHIFT (23U)
587 #define QEIV2_READEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE0FEN_SHIFT) & QEIV2_READEN_CYCLE0FEN_MASK)
588 #define QEIV2_READEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE0FEN_MASK) >> QEIV2_READEN_CYCLE0FEN_SHIFT)
589 
590 /*
591  * CYCLE1FEN (RW)
592  *
593  */
594 #define QEIV2_READEN_CYCLE1FEN_MASK (0x400000UL)
595 #define QEIV2_READEN_CYCLE1FEN_SHIFT (22U)
596 #define QEIV2_READEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_CYCLE1FEN_SHIFT) & QEIV2_READEN_CYCLE1FEN_MASK)
597 #define QEIV2_READEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_CYCLE1FEN_MASK) >> QEIV2_READEN_CYCLE1FEN_SHIFT)
598 
599 /*
600  * PULSE0FEN (RW)
601  *
602  */
603 #define QEIV2_READEN_PULSE0FEN_MASK (0x200000UL)
604 #define QEIV2_READEN_PULSE0FEN_SHIFT (21U)
605 #define QEIV2_READEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE0FEN_SHIFT) & QEIV2_READEN_PULSE0FEN_MASK)
606 #define QEIV2_READEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE0FEN_MASK) >> QEIV2_READEN_PULSE0FEN_SHIFT)
607 
608 /*
609  * PULSE1FEN (RW)
610  *
611  */
612 #define QEIV2_READEN_PULSE1FEN_MASK (0x100000UL)
613 #define QEIV2_READEN_PULSE1FEN_SHIFT (20U)
614 #define QEIV2_READEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_PULSE1FEN_SHIFT) & QEIV2_READEN_PULSE1FEN_MASK)
615 #define QEIV2_READEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_PULSE1FEN_MASK) >> QEIV2_READEN_PULSE1FEN_SHIFT)
616 
617 /*
618  * HOME2FEN (RW)
619  *
620  */
621 #define QEIV2_READEN_HOME2FEN_MASK (0x80000UL)
622 #define QEIV2_READEN_HOME2FEN_SHIFT (19U)
623 #define QEIV2_READEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_HOME2FEN_SHIFT) & QEIV2_READEN_HOME2FEN_MASK)
624 #define QEIV2_READEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_HOME2FEN_MASK) >> QEIV2_READEN_HOME2FEN_SHIFT)
625 
626 /*
627  * FAULTFEN (RW)
628  *
629  */
630 #define QEIV2_READEN_FAULTFEN_MASK (0x40000UL)
631 #define QEIV2_READEN_FAULTFEN_SHIFT (18U)
632 #define QEIV2_READEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_READEN_FAULTFEN_SHIFT) & QEIV2_READEN_FAULTFEN_MASK)
633 #define QEIV2_READEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_READEN_FAULTFEN_MASK) >> QEIV2_READEN_FAULTFEN_SHIFT)
634 
635 /* Bitfield definition for register: ZCMP */
636 /*
637  * ZCMP (RW)
638  *
639  * zcnt postion compare value
640  */
641 #define QEIV2_ZCMP_ZCMP_MASK (0xFFFFFFFFUL)
642 #define QEIV2_ZCMP_ZCMP_SHIFT (0U)
643 #define QEIV2_ZCMP_ZCMP_SET(x) (((uint32_t)(x) << QEIV2_ZCMP_ZCMP_SHIFT) & QEIV2_ZCMP_ZCMP_MASK)
644 #define QEIV2_ZCMP_ZCMP_GET(x) (((uint32_t)(x) & QEIV2_ZCMP_ZCMP_MASK) >> QEIV2_ZCMP_ZCMP_SHIFT)
645 
646 /* Bitfield definition for register: PHCMP */
647 /*
648  * PHCMP (RW)
649  *
650  * phcnt position compare value
651  */
652 #define QEIV2_PHCMP_PHCMP_MASK (0xFFFFFFFFUL)
653 #define QEIV2_PHCMP_PHCMP_SHIFT (0U)
654 #define QEIV2_PHCMP_PHCMP_SET(x) (((uint32_t)(x) << QEIV2_PHCMP_PHCMP_SHIFT) & QEIV2_PHCMP_PHCMP_MASK)
655 #define QEIV2_PHCMP_PHCMP_GET(x) (((uint32_t)(x) & QEIV2_PHCMP_PHCMP_MASK) >> QEIV2_PHCMP_PHCMP_SHIFT)
656 
657 /* Bitfield definition for register: SPDCMP */
658 /*
659  * SPDCMP (RW)
660  *
661  * spdcnt position compare value
662  */
663 #define QEIV2_SPDCMP_SPDCMP_MASK (0xFFFFFFFFUL)
664 #define QEIV2_SPDCMP_SPDCMP_SHIFT (0U)
665 #define QEIV2_SPDCMP_SPDCMP_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP_SPDCMP_SHIFT) & QEIV2_SPDCMP_SPDCMP_MASK)
666 #define QEIV2_SPDCMP_SPDCMP_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP_SPDCMP_MASK) >> QEIV2_SPDCMP_SPDCMP_SHIFT)
667 
668 /* Bitfield definition for register: DMAEN */
669 /*
670  * WDGFEN (RW)
671  *
672  * 1- generate dma request when wdg flag set
673  */
674 #define QEIV2_DMAEN_WDGFEN_MASK (0x80000000UL)
675 #define QEIV2_DMAEN_WDGFEN_SHIFT (31U)
676 #define QEIV2_DMAEN_WDGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WDGFEN_SHIFT) & QEIV2_DMAEN_WDGFEN_MASK)
677 #define QEIV2_DMAEN_WDGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WDGFEN_MASK) >> QEIV2_DMAEN_WDGFEN_SHIFT)
678 
679 /*
680  * HOMEFEN (RW)
681  *
682  * 1- generate dma request when homef flag set
683  */
684 #define QEIV2_DMAEN_HOMEFEN_MASK (0x40000000UL)
685 #define QEIV2_DMAEN_HOMEFEN_SHIFT (30U)
686 #define QEIV2_DMAEN_HOMEFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOMEFEN_SHIFT) & QEIV2_DMAEN_HOMEFEN_MASK)
687 #define QEIV2_DMAEN_HOMEFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOMEFEN_MASK) >> QEIV2_DMAEN_HOMEFEN_SHIFT)
688 
689 /*
690  * POSCMPFEN (RW)
691  *
692  * 1- generate dma request when poscmpf flag set
693  */
694 #define QEIV2_DMAEN_POSCMPFEN_MASK (0x20000000UL)
695 #define QEIV2_DMAEN_POSCMPFEN_SHIFT (29U)
696 #define QEIV2_DMAEN_POSCMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POSCMPFEN_SHIFT) & QEIV2_DMAEN_POSCMPFEN_MASK)
697 #define QEIV2_DMAEN_POSCMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POSCMPFEN_MASK) >> QEIV2_DMAEN_POSCMPFEN_SHIFT)
698 
699 /*
700  * ZPHFEN (RW)
701  *
702  * 1- generate dma request when zphf flag set
703  */
704 #define QEIV2_DMAEN_ZPHFEN_MASK (0x10000000UL)
705 #define QEIV2_DMAEN_ZPHFEN_SHIFT (28U)
706 #define QEIV2_DMAEN_ZPHFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZPHFEN_SHIFT) & QEIV2_DMAEN_ZPHFEN_MASK)
707 #define QEIV2_DMAEN_ZPHFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZPHFEN_MASK) >> QEIV2_DMAEN_ZPHFEN_SHIFT)
708 
709 /*
710  * ZMISSFEN (RW)
711  *
712  */
713 #define QEIV2_DMAEN_ZMISSFEN_MASK (0x8000000UL)
714 #define QEIV2_DMAEN_ZMISSFEN_SHIFT (27U)
715 #define QEIV2_DMAEN_ZMISSFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_ZMISSFEN_SHIFT) & QEIV2_DMAEN_ZMISSFEN_MASK)
716 #define QEIV2_DMAEN_ZMISSFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_ZMISSFEN_MASK) >> QEIV2_DMAEN_ZMISSFEN_SHIFT)
717 
718 /*
719  * WIDTHTMFEN (RW)
720  *
721  */
722 #define QEIV2_DMAEN_WIDTHTMFEN_MASK (0x4000000UL)
723 #define QEIV2_DMAEN_WIDTHTMFEN_SHIFT (26U)
724 #define QEIV2_DMAEN_WIDTHTMFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_WIDTHTMFEN_SHIFT) & QEIV2_DMAEN_WIDTHTMFEN_MASK)
725 #define QEIV2_DMAEN_WIDTHTMFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_WIDTHTMFEN_MASK) >> QEIV2_DMAEN_WIDTHTMFEN_SHIFT)
726 
727 /*
728  * POS2CMPFEN (RW)
729  *
730  */
731 #define QEIV2_DMAEN_POS2CMPFEN_MASK (0x2000000UL)
732 #define QEIV2_DMAEN_POS2CMPFEN_SHIFT (25U)
733 #define QEIV2_DMAEN_POS2CMPFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_POS2CMPFEN_SHIFT) & QEIV2_DMAEN_POS2CMPFEN_MASK)
734 #define QEIV2_DMAEN_POS2CMPFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_POS2CMPFEN_MASK) >> QEIV2_DMAEN_POS2CMPFEN_SHIFT)
735 
736 /*
737  * DIRCHGFEN (RW)
738  *
739  */
740 #define QEIV2_DMAEN_DIRCHGFEN_MASK (0x1000000UL)
741 #define QEIV2_DMAEN_DIRCHGFEN_SHIFT (24U)
742 #define QEIV2_DMAEN_DIRCHGFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_DIRCHGFEN_SHIFT) & QEIV2_DMAEN_DIRCHGFEN_MASK)
743 #define QEIV2_DMAEN_DIRCHGFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_DIRCHGFEN_MASK) >> QEIV2_DMAEN_DIRCHGFEN_SHIFT)
744 
745 /*
746  * CYCLE0FEN (RW)
747  *
748  */
749 #define QEIV2_DMAEN_CYCLE0FEN_MASK (0x800000UL)
750 #define QEIV2_DMAEN_CYCLE0FEN_SHIFT (23U)
751 #define QEIV2_DMAEN_CYCLE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE0FEN_SHIFT) & QEIV2_DMAEN_CYCLE0FEN_MASK)
752 #define QEIV2_DMAEN_CYCLE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE0FEN_MASK) >> QEIV2_DMAEN_CYCLE0FEN_SHIFT)
753 
754 /*
755  * CYCLE1FEN (RW)
756  *
757  */
758 #define QEIV2_DMAEN_CYCLE1FEN_MASK (0x400000UL)
759 #define QEIV2_DMAEN_CYCLE1FEN_SHIFT (22U)
760 #define QEIV2_DMAEN_CYCLE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_CYCLE1FEN_SHIFT) & QEIV2_DMAEN_CYCLE1FEN_MASK)
761 #define QEIV2_DMAEN_CYCLE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_CYCLE1FEN_MASK) >> QEIV2_DMAEN_CYCLE1FEN_SHIFT)
762 
763 /*
764  * PULSE0FEN (RW)
765  *
766  */
767 #define QEIV2_DMAEN_PULSE0FEN_MASK (0x200000UL)
768 #define QEIV2_DMAEN_PULSE0FEN_SHIFT (21U)
769 #define QEIV2_DMAEN_PULSE0FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE0FEN_SHIFT) & QEIV2_DMAEN_PULSE0FEN_MASK)
770 #define QEIV2_DMAEN_PULSE0FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE0FEN_MASK) >> QEIV2_DMAEN_PULSE0FEN_SHIFT)
771 
772 /*
773  * PULSE1FEN (RW)
774  *
775  */
776 #define QEIV2_DMAEN_PULSE1FEN_MASK (0x100000UL)
777 #define QEIV2_DMAEN_PULSE1FEN_SHIFT (20U)
778 #define QEIV2_DMAEN_PULSE1FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_PULSE1FEN_SHIFT) & QEIV2_DMAEN_PULSE1FEN_MASK)
779 #define QEIV2_DMAEN_PULSE1FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_PULSE1FEN_MASK) >> QEIV2_DMAEN_PULSE1FEN_SHIFT)
780 
781 /*
782  * HOME2FEN (RW)
783  *
784  */
785 #define QEIV2_DMAEN_HOME2FEN_MASK (0x80000UL)
786 #define QEIV2_DMAEN_HOME2FEN_SHIFT (19U)
787 #define QEIV2_DMAEN_HOME2FEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_HOME2FEN_SHIFT) & QEIV2_DMAEN_HOME2FEN_MASK)
788 #define QEIV2_DMAEN_HOME2FEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_HOME2FEN_MASK) >> QEIV2_DMAEN_HOME2FEN_SHIFT)
789 
790 /*
791  * FAULTFEN (RW)
792  *
793  */
794 #define QEIV2_DMAEN_FAULTFEN_MASK (0x40000UL)
795 #define QEIV2_DMAEN_FAULTFEN_SHIFT (18U)
796 #define QEIV2_DMAEN_FAULTFEN_SET(x) (((uint32_t)(x) << QEIV2_DMAEN_FAULTFEN_SHIFT) & QEIV2_DMAEN_FAULTFEN_MASK)
797 #define QEIV2_DMAEN_FAULTFEN_GET(x) (((uint32_t)(x) & QEIV2_DMAEN_FAULTFEN_MASK) >> QEIV2_DMAEN_FAULTFEN_SHIFT)
798 
799 /* Bitfield definition for register: SR */
800 /*
801  * WDGF (RW)
802  *
803  * watchdog flag
804  */
805 #define QEIV2_SR_WDGF_MASK (0x80000000UL)
806 #define QEIV2_SR_WDGF_SHIFT (31U)
807 #define QEIV2_SR_WDGF_SET(x) (((uint32_t)(x) << QEIV2_SR_WDGF_SHIFT) & QEIV2_SR_WDGF_MASK)
808 #define QEIV2_SR_WDGF_GET(x) (((uint32_t)(x) & QEIV2_SR_WDGF_MASK) >> QEIV2_SR_WDGF_SHIFT)
809 
810 /*
811  * HOMEF (RW)
812  *
813  * home flag
814  */
815 #define QEIV2_SR_HOMEF_MASK (0x40000000UL)
816 #define QEIV2_SR_HOMEF_SHIFT (30U)
817 #define QEIV2_SR_HOMEF_SET(x) (((uint32_t)(x) << QEIV2_SR_HOMEF_SHIFT) & QEIV2_SR_HOMEF_MASK)
818 #define QEIV2_SR_HOMEF_GET(x) (((uint32_t)(x) & QEIV2_SR_HOMEF_MASK) >> QEIV2_SR_HOMEF_SHIFT)
819 
820 /*
821  * POSCMPF (RW)
822  *
823  * postion compare match flag
824  */
825 #define QEIV2_SR_POSCMPF_MASK (0x20000000UL)
826 #define QEIV2_SR_POSCMPF_SHIFT (29U)
827 #define QEIV2_SR_POSCMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POSCMPF_SHIFT) & QEIV2_SR_POSCMPF_MASK)
828 #define QEIV2_SR_POSCMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POSCMPF_MASK) >> QEIV2_SR_POSCMPF_SHIFT)
829 
830 /*
831  * ZPHF (RW)
832  *
833  * z input flag
834  */
835 #define QEIV2_SR_ZPHF_MASK (0x10000000UL)
836 #define QEIV2_SR_ZPHF_SHIFT (28U)
837 #define QEIV2_SR_ZPHF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZPHF_SHIFT) & QEIV2_SR_ZPHF_MASK)
838 #define QEIV2_SR_ZPHF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZPHF_MASK) >> QEIV2_SR_ZPHF_SHIFT)
839 
840 /*
841  * ZMISSF (RW)
842  *
843  */
844 #define QEIV2_SR_ZMISSF_MASK (0x8000000UL)
845 #define QEIV2_SR_ZMISSF_SHIFT (27U)
846 #define QEIV2_SR_ZMISSF_SET(x) (((uint32_t)(x) << QEIV2_SR_ZMISSF_SHIFT) & QEIV2_SR_ZMISSF_MASK)
847 #define QEIV2_SR_ZMISSF_GET(x) (((uint32_t)(x) & QEIV2_SR_ZMISSF_MASK) >> QEIV2_SR_ZMISSF_SHIFT)
848 
849 /*
850  * WIDTHTMF (RW)
851  *
852  */
853 #define QEIV2_SR_WIDTHTMF_MASK (0x4000000UL)
854 #define QEIV2_SR_WIDTHTMF_SHIFT (26U)
855 #define QEIV2_SR_WIDTHTMF_SET(x) (((uint32_t)(x) << QEIV2_SR_WIDTHTMF_SHIFT) & QEIV2_SR_WIDTHTMF_MASK)
856 #define QEIV2_SR_WIDTHTMF_GET(x) (((uint32_t)(x) & QEIV2_SR_WIDTHTMF_MASK) >> QEIV2_SR_WIDTHTMF_SHIFT)
857 
858 /*
859  * POS2CMPF (RW)
860  *
861  */
862 #define QEIV2_SR_POS2CMPF_MASK (0x2000000UL)
863 #define QEIV2_SR_POS2CMPF_SHIFT (25U)
864 #define QEIV2_SR_POS2CMPF_SET(x) (((uint32_t)(x) << QEIV2_SR_POS2CMPF_SHIFT) & QEIV2_SR_POS2CMPF_MASK)
865 #define QEIV2_SR_POS2CMPF_GET(x) (((uint32_t)(x) & QEIV2_SR_POS2CMPF_MASK) >> QEIV2_SR_POS2CMPF_SHIFT)
866 
867 /*
868  * DIRCHGF (RW)
869  *
870  */
871 #define QEIV2_SR_DIRCHGF_MASK (0x1000000UL)
872 #define QEIV2_SR_DIRCHGF_SHIFT (24U)
873 #define QEIV2_SR_DIRCHGF_SET(x) (((uint32_t)(x) << QEIV2_SR_DIRCHGF_SHIFT) & QEIV2_SR_DIRCHGF_MASK)
874 #define QEIV2_SR_DIRCHGF_GET(x) (((uint32_t)(x) & QEIV2_SR_DIRCHGF_MASK) >> QEIV2_SR_DIRCHGF_SHIFT)
875 
876 /*
877  * CYCLE0F (RW)
878  *
879  */
880 #define QEIV2_SR_CYCLE0F_MASK (0x800000UL)
881 #define QEIV2_SR_CYCLE0F_SHIFT (23U)
882 #define QEIV2_SR_CYCLE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE0F_SHIFT) & QEIV2_SR_CYCLE0F_MASK)
883 #define QEIV2_SR_CYCLE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE0F_MASK) >> QEIV2_SR_CYCLE0F_SHIFT)
884 
885 /*
886  * CYCLE1F (RW)
887  *
888  */
889 #define QEIV2_SR_CYCLE1F_MASK (0x400000UL)
890 #define QEIV2_SR_CYCLE1F_SHIFT (22U)
891 #define QEIV2_SR_CYCLE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_CYCLE1F_SHIFT) & QEIV2_SR_CYCLE1F_MASK)
892 #define QEIV2_SR_CYCLE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_CYCLE1F_MASK) >> QEIV2_SR_CYCLE1F_SHIFT)
893 
894 /*
895  * PULSE0F (RW)
896  *
897  */
898 #define QEIV2_SR_PULSE0F_MASK (0x200000UL)
899 #define QEIV2_SR_PULSE0F_SHIFT (21U)
900 #define QEIV2_SR_PULSE0F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE0F_SHIFT) & QEIV2_SR_PULSE0F_MASK)
901 #define QEIV2_SR_PULSE0F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE0F_MASK) >> QEIV2_SR_PULSE0F_SHIFT)
902 
903 /*
904  * PULSE1F (RW)
905  *
906  */
907 #define QEIV2_SR_PULSE1F_MASK (0x100000UL)
908 #define QEIV2_SR_PULSE1F_SHIFT (20U)
909 #define QEIV2_SR_PULSE1F_SET(x) (((uint32_t)(x) << QEIV2_SR_PULSE1F_SHIFT) & QEIV2_SR_PULSE1F_MASK)
910 #define QEIV2_SR_PULSE1F_GET(x) (((uint32_t)(x) & QEIV2_SR_PULSE1F_MASK) >> QEIV2_SR_PULSE1F_SHIFT)
911 
912 /*
913  * HOME2F (RW)
914  *
915  */
916 #define QEIV2_SR_HOME2F_MASK (0x80000UL)
917 #define QEIV2_SR_HOME2F_SHIFT (19U)
918 #define QEIV2_SR_HOME2F_SET(x) (((uint32_t)(x) << QEIV2_SR_HOME2F_SHIFT) & QEIV2_SR_HOME2F_MASK)
919 #define QEIV2_SR_HOME2F_GET(x) (((uint32_t)(x) & QEIV2_SR_HOME2F_MASK) >> QEIV2_SR_HOME2F_SHIFT)
920 
921 /*
922  * FAULTF (RW)
923  *
924  */
925 #define QEIV2_SR_FAULTF_MASK (0x40000UL)
926 #define QEIV2_SR_FAULTF_SHIFT (18U)
927 #define QEIV2_SR_FAULTF_SET(x) (((uint32_t)(x) << QEIV2_SR_FAULTF_SHIFT) & QEIV2_SR_FAULTF_MASK)
928 #define QEIV2_SR_FAULTF_GET(x) (((uint32_t)(x) & QEIV2_SR_FAULTF_MASK) >> QEIV2_SR_FAULTF_SHIFT)
929 
930 /* Bitfield definition for register: IRQEN */
931 /*
932  * WDGIE (RW)
933  *
934  * 1- generate interrupt when wdg flag set
935  */
936 #define QEIV2_IRQEN_WDGIE_MASK (0x80000000UL)
937 #define QEIV2_IRQEN_WDGIE_SHIFT (31U)
938 #define QEIV2_IRQEN_WDGIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WDGIE_SHIFT) & QEIV2_IRQEN_WDGIE_MASK)
939 #define QEIV2_IRQEN_WDGIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WDGIE_MASK) >> QEIV2_IRQEN_WDGIE_SHIFT)
940 
941 /*
942  * HOMEIE (RW)
943  *
944  * 1- generate interrupt when homef flag set
945  */
946 #define QEIV2_IRQEN_HOMEIE_MASK (0x40000000UL)
947 #define QEIV2_IRQEN_HOMEIE_SHIFT (30U)
948 #define QEIV2_IRQEN_HOMEIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOMEIE_SHIFT) & QEIV2_IRQEN_HOMEIE_MASK)
949 #define QEIV2_IRQEN_HOMEIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOMEIE_MASK) >> QEIV2_IRQEN_HOMEIE_SHIFT)
950 
951 /*
952  * POSCMPIE (RW)
953  *
954  * 1- generate interrupt when poscmpf flag set
955  */
956 #define QEIV2_IRQEN_POSCMPIE_MASK (0x20000000UL)
957 #define QEIV2_IRQEN_POSCMPIE_SHIFT (29U)
958 #define QEIV2_IRQEN_POSCMPIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POSCMPIE_SHIFT) & QEIV2_IRQEN_POSCMPIE_MASK)
959 #define QEIV2_IRQEN_POSCMPIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POSCMPIE_MASK) >> QEIV2_IRQEN_POSCMPIE_SHIFT)
960 
961 /*
962  * ZPHIE (RW)
963  *
964  * 1- generate interrupt when zphf flag set
965  */
966 #define QEIV2_IRQEN_ZPHIE_MASK (0x10000000UL)
967 #define QEIV2_IRQEN_ZPHIE_SHIFT (28U)
968 #define QEIV2_IRQEN_ZPHIE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZPHIE_SHIFT) & QEIV2_IRQEN_ZPHIE_MASK)
969 #define QEIV2_IRQEN_ZPHIE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZPHIE_MASK) >> QEIV2_IRQEN_ZPHIE_SHIFT)
970 
971 /*
972  * ZMISSE (RW)
973  *
974  */
975 #define QEIV2_IRQEN_ZMISSE_MASK (0x8000000UL)
976 #define QEIV2_IRQEN_ZMISSE_SHIFT (27U)
977 #define QEIV2_IRQEN_ZMISSE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_ZMISSE_SHIFT) & QEIV2_IRQEN_ZMISSE_MASK)
978 #define QEIV2_IRQEN_ZMISSE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_ZMISSE_MASK) >> QEIV2_IRQEN_ZMISSE_SHIFT)
979 
980 /*
981  * WIDTHTME (RW)
982  *
983  */
984 #define QEIV2_IRQEN_WIDTHTME_MASK (0x4000000UL)
985 #define QEIV2_IRQEN_WIDTHTME_SHIFT (26U)
986 #define QEIV2_IRQEN_WIDTHTME_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_WIDTHTME_SHIFT) & QEIV2_IRQEN_WIDTHTME_MASK)
987 #define QEIV2_IRQEN_WIDTHTME_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_WIDTHTME_MASK) >> QEIV2_IRQEN_WIDTHTME_SHIFT)
988 
989 /*
990  * POS2CMPE (RW)
991  *
992  */
993 #define QEIV2_IRQEN_POS2CMPE_MASK (0x2000000UL)
994 #define QEIV2_IRQEN_POS2CMPE_SHIFT (25U)
995 #define QEIV2_IRQEN_POS2CMPE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_POS2CMPE_SHIFT) & QEIV2_IRQEN_POS2CMPE_MASK)
996 #define QEIV2_IRQEN_POS2CMPE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_POS2CMPE_MASK) >> QEIV2_IRQEN_POS2CMPE_SHIFT)
997 
998 /*
999  * DIRCHGE (RW)
1000  *
1001  */
1002 #define QEIV2_IRQEN_DIRCHGE_MASK (0x1000000UL)
1003 #define QEIV2_IRQEN_DIRCHGE_SHIFT (24U)
1004 #define QEIV2_IRQEN_DIRCHGE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_DIRCHGE_SHIFT) & QEIV2_IRQEN_DIRCHGE_MASK)
1005 #define QEIV2_IRQEN_DIRCHGE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_DIRCHGE_MASK) >> QEIV2_IRQEN_DIRCHGE_SHIFT)
1006 
1007 /*
1008  * CYCLE0E (RW)
1009  *
1010  */
1011 #define QEIV2_IRQEN_CYCLE0E_MASK (0x800000UL)
1012 #define QEIV2_IRQEN_CYCLE0E_SHIFT (23U)
1013 #define QEIV2_IRQEN_CYCLE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE0E_SHIFT) & QEIV2_IRQEN_CYCLE0E_MASK)
1014 #define QEIV2_IRQEN_CYCLE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE0E_MASK) >> QEIV2_IRQEN_CYCLE0E_SHIFT)
1015 
1016 /*
1017  * CYCLE1E (RW)
1018  *
1019  */
1020 #define QEIV2_IRQEN_CYCLE1E_MASK (0x400000UL)
1021 #define QEIV2_IRQEN_CYCLE1E_SHIFT (22U)
1022 #define QEIV2_IRQEN_CYCLE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_CYCLE1E_SHIFT) & QEIV2_IRQEN_CYCLE1E_MASK)
1023 #define QEIV2_IRQEN_CYCLE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_CYCLE1E_MASK) >> QEIV2_IRQEN_CYCLE1E_SHIFT)
1024 
1025 /*
1026  * PULSE0E (RW)
1027  *
1028  */
1029 #define QEIV2_IRQEN_PULSE0E_MASK (0x200000UL)
1030 #define QEIV2_IRQEN_PULSE0E_SHIFT (21U)
1031 #define QEIV2_IRQEN_PULSE0E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE0E_SHIFT) & QEIV2_IRQEN_PULSE0E_MASK)
1032 #define QEIV2_IRQEN_PULSE0E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE0E_MASK) >> QEIV2_IRQEN_PULSE0E_SHIFT)
1033 
1034 /*
1035  * PULSE1E (RW)
1036  *
1037  */
1038 #define QEIV2_IRQEN_PULSE1E_MASK (0x100000UL)
1039 #define QEIV2_IRQEN_PULSE1E_SHIFT (20U)
1040 #define QEIV2_IRQEN_PULSE1E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_PULSE1E_SHIFT) & QEIV2_IRQEN_PULSE1E_MASK)
1041 #define QEIV2_IRQEN_PULSE1E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_PULSE1E_MASK) >> QEIV2_IRQEN_PULSE1E_SHIFT)
1042 
1043 /*
1044  * HOME2E (RW)
1045  *
1046  */
1047 #define QEIV2_IRQEN_HOME2E_MASK (0x80000UL)
1048 #define QEIV2_IRQEN_HOME2E_SHIFT (19U)
1049 #define QEIV2_IRQEN_HOME2E_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_HOME2E_SHIFT) & QEIV2_IRQEN_HOME2E_MASK)
1050 #define QEIV2_IRQEN_HOME2E_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_HOME2E_MASK) >> QEIV2_IRQEN_HOME2E_SHIFT)
1051 
1052 /*
1053  * FAULTE (RW)
1054  *
1055  */
1056 #define QEIV2_IRQEN_FAULTE_MASK (0x40000UL)
1057 #define QEIV2_IRQEN_FAULTE_SHIFT (18U)
1058 #define QEIV2_IRQEN_FAULTE_SET(x) (((uint32_t)(x) << QEIV2_IRQEN_FAULTE_SHIFT) & QEIV2_IRQEN_FAULTE_MASK)
1059 #define QEIV2_IRQEN_FAULTE_GET(x) (((uint32_t)(x) & QEIV2_IRQEN_FAULTE_MASK) >> QEIV2_IRQEN_FAULTE_SHIFT)
1060 
1061 /* Bitfield definition for register of struct array COUNT: Z */
1062 /*
1063  * ZCNT (RW)
1064  *
1065  * zcnt value
1066  */
1067 #define QEIV2_COUNT_Z_ZCNT_MASK (0xFFFFFFFFUL)
1068 #define QEIV2_COUNT_Z_ZCNT_SHIFT (0U)
1069 #define QEIV2_COUNT_Z_ZCNT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_Z_ZCNT_SHIFT) & QEIV2_COUNT_Z_ZCNT_MASK)
1070 #define QEIV2_COUNT_Z_ZCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_Z_ZCNT_MASK) >> QEIV2_COUNT_Z_ZCNT_SHIFT)
1071 
1072 /* Bitfield definition for register of struct array COUNT: PH */
1073 /*
1074  * DIR (RO)
1075  *
1076  * 1- reverse rotation
1077  * 0- forward rotation
1078  */
1079 #define QEIV2_COUNT_PH_DIR_MASK (0x40000000UL)
1080 #define QEIV2_COUNT_PH_DIR_SHIFT (30U)
1081 #define QEIV2_COUNT_PH_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_DIR_MASK) >> QEIV2_COUNT_PH_DIR_SHIFT)
1082 
1083 /*
1084  * ASTAT (RO)
1085  *
1086  * 1- a input is high
1087  * 0- a input is low
1088  */
1089 #define QEIV2_COUNT_PH_ASTAT_MASK (0x4000000UL)
1090 #define QEIV2_COUNT_PH_ASTAT_SHIFT (26U)
1091 #define QEIV2_COUNT_PH_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_ASTAT_MASK) >> QEIV2_COUNT_PH_ASTAT_SHIFT)
1092 
1093 /*
1094  * BSTAT (RO)
1095  *
1096  * 1- b input is high
1097  * 0- b input is low
1098  */
1099 #define QEIV2_COUNT_PH_BSTAT_MASK (0x2000000UL)
1100 #define QEIV2_COUNT_PH_BSTAT_SHIFT (25U)
1101 #define QEIV2_COUNT_PH_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_BSTAT_MASK) >> QEIV2_COUNT_PH_BSTAT_SHIFT)
1102 
1103 /*
1104  * PHCNT (RO)
1105  *
1106  * phcnt value
1107  */
1108 #define QEIV2_COUNT_PH_PHCNT_MASK (0x1FFFFFUL)
1109 #define QEIV2_COUNT_PH_PHCNT_SHIFT (0U)
1110 #define QEIV2_COUNT_PH_PHCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_PH_PHCNT_MASK) >> QEIV2_COUNT_PH_PHCNT_SHIFT)
1111 
1112 /* Bitfield definition for register of struct array COUNT: SPD */
1113 /*
1114  * DIR (RO)
1115  *
1116  * 1- reverse rotation
1117  * 0- forward rotation
1118  */
1119 #define QEIV2_COUNT_SPD_DIR_MASK (0x80000000UL)
1120 #define QEIV2_COUNT_SPD_DIR_SHIFT (31U)
1121 #define QEIV2_COUNT_SPD_DIR_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_DIR_MASK) >> QEIV2_COUNT_SPD_DIR_SHIFT)
1122 
1123 /*
1124  * ASTAT (RO)
1125  *
1126  * 1- a input is high
1127  * 0- a input is low
1128  */
1129 #define QEIV2_COUNT_SPD_ASTAT_MASK (0x40000000UL)
1130 #define QEIV2_COUNT_SPD_ASTAT_SHIFT (30U)
1131 #define QEIV2_COUNT_SPD_ASTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_ASTAT_MASK) >> QEIV2_COUNT_SPD_ASTAT_SHIFT)
1132 
1133 /*
1134  * BSTAT (RW)
1135  *
1136  * 1- b input is high
1137  * 0- b input is low
1138  */
1139 #define QEIV2_COUNT_SPD_BSTAT_MASK (0x20000000UL)
1140 #define QEIV2_COUNT_SPD_BSTAT_SHIFT (29U)
1141 #define QEIV2_COUNT_SPD_BSTAT_SET(x) (((uint32_t)(x) << QEIV2_COUNT_SPD_BSTAT_SHIFT) & QEIV2_COUNT_SPD_BSTAT_MASK)
1142 #define QEIV2_COUNT_SPD_BSTAT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_BSTAT_MASK) >> QEIV2_COUNT_SPD_BSTAT_SHIFT)
1143 
1144 /*
1145  * SPDCNT (RO)
1146  *
1147  * spdcnt value
1148  */
1149 #define QEIV2_COUNT_SPD_SPDCNT_MASK (0xFFFFFFFUL)
1150 #define QEIV2_COUNT_SPD_SPDCNT_SHIFT (0U)
1151 #define QEIV2_COUNT_SPD_SPDCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_SPD_SPDCNT_MASK) >> QEIV2_COUNT_SPD_SPDCNT_SHIFT)
1152 
1153 /* Bitfield definition for register of struct array COUNT: TMR */
1154 /*
1155  * TMRCNT (RO)
1156  *
1157  * 32 bit free run timer
1158  */
1159 #define QEIV2_COUNT_TMR_TMRCNT_MASK (0xFFFFFFFFUL)
1160 #define QEIV2_COUNT_TMR_TMRCNT_SHIFT (0U)
1161 #define QEIV2_COUNT_TMR_TMRCNT_GET(x) (((uint32_t)(x) & QEIV2_COUNT_TMR_TMRCNT_MASK) >> QEIV2_COUNT_TMR_TMRCNT_SHIFT)
1162 
1163 /* Bitfield definition for register: ZCMP2 */
1164 /*
1165  * ZCMP2 (RW)
1166  *
1167  */
1168 #define QEIV2_ZCMP2_ZCMP2_MASK (0xFFFFFFFFUL)
1169 #define QEIV2_ZCMP2_ZCMP2_SHIFT (0U)
1170 #define QEIV2_ZCMP2_ZCMP2_SET(x) (((uint32_t)(x) << QEIV2_ZCMP2_ZCMP2_SHIFT) & QEIV2_ZCMP2_ZCMP2_MASK)
1171 #define QEIV2_ZCMP2_ZCMP2_GET(x) (((uint32_t)(x) & QEIV2_ZCMP2_ZCMP2_MASK) >> QEIV2_ZCMP2_ZCMP2_SHIFT)
1172 
1173 /* Bitfield definition for register: PHCMP2 */
1174 /*
1175  * PHCMP2 (RW)
1176  *
1177  */
1178 #define QEIV2_PHCMP2_PHCMP2_MASK (0xFFFFFFFFUL)
1179 #define QEIV2_PHCMP2_PHCMP2_SHIFT (0U)
1180 #define QEIV2_PHCMP2_PHCMP2_SET(x) (((uint32_t)(x) << QEIV2_PHCMP2_PHCMP2_SHIFT) & QEIV2_PHCMP2_PHCMP2_MASK)
1181 #define QEIV2_PHCMP2_PHCMP2_GET(x) (((uint32_t)(x) & QEIV2_PHCMP2_PHCMP2_MASK) >> QEIV2_PHCMP2_PHCMP2_SHIFT)
1182 
1183 /* Bitfield definition for register: SPDCMP2 */
1184 /*
1185  * SPDCMP2 (RW)
1186  *
1187  */
1188 #define QEIV2_SPDCMP2_SPDCMP2_MASK (0xFFFFFFFFUL)
1189 #define QEIV2_SPDCMP2_SPDCMP2_SHIFT (0U)
1190 #define QEIV2_SPDCMP2_SPDCMP2_SET(x) (((uint32_t)(x) << QEIV2_SPDCMP2_SPDCMP2_SHIFT) & QEIV2_SPDCMP2_SPDCMP2_MASK)
1191 #define QEIV2_SPDCMP2_SPDCMP2_GET(x) (((uint32_t)(x) & QEIV2_SPDCMP2_SPDCMP2_MASK) >> QEIV2_SPDCMP2_SPDCMP2_SHIFT)
1192 
1193 /* Bitfield definition for register: MATCH_CFG */
1194 /*
1195  * ZCMPDIS (RW)
1196  *
1197  * 1- postion compare not include zcnt
1198  */
1199 #define QEIV2_MATCH_CFG_ZCMPDIS_MASK (0x80000000UL)
1200 #define QEIV2_MATCH_CFG_ZCMPDIS_SHIFT (31U)
1201 #define QEIV2_MATCH_CFG_ZCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMPDIS_SHIFT) & QEIV2_MATCH_CFG_ZCMPDIS_MASK)
1202 #define QEIV2_MATCH_CFG_ZCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMPDIS_MASK) >> QEIV2_MATCH_CFG_ZCMPDIS_SHIFT)
1203 
1204 /*
1205  * DIRCMPDIS (RW)
1206  *
1207  * 1- postion compare not include rotation direction
1208  */
1209 #define QEIV2_MATCH_CFG_DIRCMPDIS_MASK (0x40000000UL)
1210 #define QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT (30U)
1211 #define QEIV2_MATCH_CFG_DIRCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK)
1212 #define QEIV2_MATCH_CFG_DIRCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMPDIS_MASK) >> QEIV2_MATCH_CFG_DIRCMPDIS_SHIFT)
1213 
1214 /*
1215  * DIRCMP (RW)
1216  *
1217  * 0- position compare need positive rotation
1218  * 1- position compare need negative rotation
1219  */
1220 #define QEIV2_MATCH_CFG_DIRCMP_MASK (0x20000000UL)
1221 #define QEIV2_MATCH_CFG_DIRCMP_SHIFT (29U)
1222 #define QEIV2_MATCH_CFG_DIRCMP_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP_SHIFT) & QEIV2_MATCH_CFG_DIRCMP_MASK)
1223 #define QEIV2_MATCH_CFG_DIRCMP_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP_MASK) >> QEIV2_MATCH_CFG_DIRCMP_SHIFT)
1224 
1225 /*
1226  * SPDCMPDIS (RW)
1227  *
1228  */
1229 #define QEIV2_MATCH_CFG_SPDCMPDIS_MASK (0x10000000UL)
1230 #define QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT (28U)
1231 #define QEIV2_MATCH_CFG_SPDCMPDIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK)
1232 #define QEIV2_MATCH_CFG_SPDCMPDIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMPDIS_MASK) >> QEIV2_MATCH_CFG_SPDCMPDIS_SHIFT)
1233 
1234 /*
1235  * PHASE_MATCH_DIS (RW)
1236  *
1237  */
1238 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK (0x8000000UL)
1239 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT (27U)
1240 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK)
1241 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS_SHIFT)
1242 
1243 /*
1244  * POS_MATCH_DIR (RW)
1245  *
1246  */
1247 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK (0x4000000UL)
1248 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT (26U)
1249 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK)
1250 #define QEIV2_MATCH_CFG_POS_MATCH_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_DIR_SHIFT)
1251 
1252 /*
1253  * POS_MATCH_OPT (RW)
1254  *
1255  */
1256 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK (0x2000000UL)
1257 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT (25U)
1258 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK)
1259 #define QEIV2_MATCH_CFG_POS_MATCH_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH_OPT_SHIFT)
1260 
1261 /*
1262  * ZCMP2DIS (RW)
1263  *
1264  */
1265 #define QEIV2_MATCH_CFG_ZCMP2DIS_MASK (0x8000U)
1266 #define QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT (15U)
1267 #define QEIV2_MATCH_CFG_ZCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK)
1268 #define QEIV2_MATCH_CFG_ZCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_ZCMP2DIS_MASK) >> QEIV2_MATCH_CFG_ZCMP2DIS_SHIFT)
1269 
1270 /*
1271  * DIRCMP2DIS (RW)
1272  *
1273  */
1274 #define QEIV2_MATCH_CFG_DIRCMP2DIS_MASK (0x4000U)
1275 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT (14U)
1276 #define QEIV2_MATCH_CFG_DIRCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK)
1277 #define QEIV2_MATCH_CFG_DIRCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2DIS_MASK) >> QEIV2_MATCH_CFG_DIRCMP2DIS_SHIFT)
1278 
1279 /*
1280  * DIRCMP2 (RW)
1281  *
1282  */
1283 #define QEIV2_MATCH_CFG_DIRCMP2_MASK (0x2000U)
1284 #define QEIV2_MATCH_CFG_DIRCMP2_SHIFT (13U)
1285 #define QEIV2_MATCH_CFG_DIRCMP2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_DIRCMP2_SHIFT) & QEIV2_MATCH_CFG_DIRCMP2_MASK)
1286 #define QEIV2_MATCH_CFG_DIRCMP2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_DIRCMP2_MASK) >> QEIV2_MATCH_CFG_DIRCMP2_SHIFT)
1287 
1288 /*
1289  * SPDCMP2DIS (RW)
1290  *
1291  */
1292 #define QEIV2_MATCH_CFG_SPDCMP2DIS_MASK (0x1000U)
1293 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT (12U)
1294 #define QEIV2_MATCH_CFG_SPDCMP2DIS_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK)
1295 #define QEIV2_MATCH_CFG_SPDCMP2DIS_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_SPDCMP2DIS_MASK) >> QEIV2_MATCH_CFG_SPDCMP2DIS_SHIFT)
1296 
1297 /*
1298  * PHASE_MATCH_DIS2 (RW)
1299  *
1300  */
1301 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK (0x800U)
1302 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT (11U)
1303 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK)
1304 #define QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_MASK) >> QEIV2_MATCH_CFG_PHASE_MATCH_DIS2_SHIFT)
1305 
1306 /*
1307  * POS_MATCH2_DIR (RW)
1308  *
1309  */
1310 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK (0x400U)
1311 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT (10U)
1312 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK)
1313 #define QEIV2_MATCH_CFG_POS_MATCH2_DIR_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_DIR_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_DIR_SHIFT)
1314 
1315 /*
1316  * POS_MATCH2_OPT (RW)
1317  *
1318  */
1319 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK (0x200U)
1320 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT (9U)
1321 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_SET(x) (((uint32_t)(x) << QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK)
1322 #define QEIV2_MATCH_CFG_POS_MATCH2_OPT_GET(x) (((uint32_t)(x) & QEIV2_MATCH_CFG_POS_MATCH2_OPT_MASK) >> QEIV2_MATCH_CFG_POS_MATCH2_OPT_SHIFT)
1323 
1324 /* Bitfield definition for register array: FILT_CFG */
1325 /*
1326  * OUTINV (RW)
1327  *
1328  * 1- Filter will invert the output
1329  * 0- Filter will not invert the output
1330  */
1331 #define QEIV2_FILT_CFG_OUTINV_MASK (0x10000UL)
1332 #define QEIV2_FILT_CFG_OUTINV_SHIFT (16U)
1333 #define QEIV2_FILT_CFG_OUTINV_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_OUTINV_SHIFT) & QEIV2_FILT_CFG_OUTINV_MASK)
1334 #define QEIV2_FILT_CFG_OUTINV_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_OUTINV_MASK) >> QEIV2_FILT_CFG_OUTINV_SHIFT)
1335 
1336 /*
1337  * MODE (RW)
1338  *
1339  * This bitfields defines the filter mode
1340  * 000-bypass;
1341  * 100-rapid change mode;
1342  * 101-delay filter mode;
1343  * 110-stable low mode;
1344  * 111-stable high mode
1345  */
1346 #define QEIV2_FILT_CFG_MODE_MASK (0xE000U)
1347 #define QEIV2_FILT_CFG_MODE_SHIFT (13U)
1348 #define QEIV2_FILT_CFG_MODE_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_MODE_SHIFT) & QEIV2_FILT_CFG_MODE_MASK)
1349 #define QEIV2_FILT_CFG_MODE_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_MODE_MASK) >> QEIV2_FILT_CFG_MODE_SHIFT)
1350 
1351 /*
1352  * SYNCEN (RW)
1353  *
1354  * set to enable sychronization input signal with TRGM clock
1355  */
1356 #define QEIV2_FILT_CFG_SYNCEN_MASK (0x1000U)
1357 #define QEIV2_FILT_CFG_SYNCEN_SHIFT (12U)
1358 #define QEIV2_FILT_CFG_SYNCEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_SYNCEN_SHIFT) & QEIV2_FILT_CFG_SYNCEN_MASK)
1359 #define QEIV2_FILT_CFG_SYNCEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_SYNCEN_MASK) >> QEIV2_FILT_CFG_SYNCEN_SHIFT)
1360 
1361 /*
1362  * FILTLEN (RW)
1363  *
1364  * This bitfields defines the filter counter length.
1365  */
1366 #define QEIV2_FILT_CFG_FILTLEN_MASK (0xFFFU)
1367 #define QEIV2_FILT_CFG_FILTLEN_SHIFT (0U)
1368 #define QEIV2_FILT_CFG_FILTLEN_SET(x) (((uint32_t)(x) << QEIV2_FILT_CFG_FILTLEN_SHIFT) & QEIV2_FILT_CFG_FILTLEN_MASK)
1369 #define QEIV2_FILT_CFG_FILTLEN_GET(x) (((uint32_t)(x) & QEIV2_FILT_CFG_FILTLEN_MASK) >> QEIV2_FILT_CFG_FILTLEN_SHIFT)
1370 
1371 /* Bitfield definition for register: QEI_CFG */
1372 /*
1373  * SW_PULSE0_RESTART (RW)
1374  *
1375  * set to restart cycle counter for configed pulse_num. HW auto clear
1376  */
1377 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK (0x80000000UL)
1378 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT (31U)
1379 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK)
1380 #define QEIV2_QEI_CFG_SW_PULSE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE0_RESTART_SHIFT)
1381 
1382 /*
1383  * SW_PULSE1_RESTART (RW)
1384  *
1385  */
1386 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK (0x40000000UL)
1387 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT (30U)
1388 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK)
1389 #define QEIV2_QEI_CFG_SW_PULSE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_PULSE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_PULSE1_RESTART_SHIFT)
1390 
1391 /*
1392  * SW_CYCLE0_RESTART (RW)
1393  *
1394  * set to restart pulse counter for configed cycle_num. HW auto clear
1395  */
1396 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK (0x20000000UL)
1397 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT (29U)
1398 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK)
1399 #define QEIV2_QEI_CFG_SW_CYCLE0_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE0_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE0_RESTART_SHIFT)
1400 
1401 /*
1402  * SW_CYCLE1_RESTART (RW)
1403  *
1404  */
1405 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK (0x10000000UL)
1406 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT (28U)
1407 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK)
1408 #define QEIV2_QEI_CFG_SW_CYCLE1_RESTART_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SW_CYCLE1_RESTART_MASK) >> QEIV2_QEI_CFG_SW_CYCLE1_RESTART_SHIFT)
1409 
1410 /*
1411  * PULSE0_ONESHOT (RW)
1412  *
1413  * set to use oneshot mode for configed pulse_num
1414  */
1415 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK (0x80000UL)
1416 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT (19U)
1417 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK)
1418 #define QEIV2_QEI_CFG_PULSE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE0_ONESHOT_SHIFT)
1419 
1420 /*
1421  * PULSE1_ONESHOT (RW)
1422  *
1423  */
1424 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK (0x40000UL)
1425 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT (18U)
1426 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK)
1427 #define QEIV2_QEI_CFG_PULSE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_PULSE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_PULSE1_ONESHOT_SHIFT)
1428 
1429 /*
1430  * CYCLE0_ONESHOT (RW)
1431  *
1432  * set to use oneshot mode for configed cycle_num
1433  */
1434 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK (0x20000UL)
1435 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT (17U)
1436 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK)
1437 #define QEIV2_QEI_CFG_CYCLE0_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE0_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE0_ONESHOT_SHIFT)
1438 
1439 /*
1440  * CYCLE1_ONESHOT (RW)
1441  *
1442  */
1443 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK (0x10000UL)
1444 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT (16U)
1445 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK)
1446 #define QEIV2_QEI_CFG_CYCLE1_ONESHOT_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_CYCLE1_ONESHOT_MASK) >> QEIV2_QEI_CFG_CYCLE1_ONESHOT_SHIFT)
1447 
1448 /*
1449  * SPEED_DIR_CHG_EN (RW)
1450  *
1451  * clear counter if detect direction change
1452  */
1453 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK (0x1000U)
1454 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT (12U)
1455 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK)
1456 #define QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_MASK) >> QEIV2_QEI_CFG_SPEED_DIR_CHG_EN_SHIFT)
1457 
1458 /*
1459  * TRIG_PULSE0_EN (RW)
1460  *
1461  * set to enable trigger start cycle counter for configed pulse_num(from the selected edge)
1462  */
1463 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK (0x800U)
1464 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT (11U)
1465 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK)
1466 #define QEIV2_QEI_CFG_TRIG_PULSE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE0_EN_SHIFT)
1467 
1468 /*
1469  * TRIG_PULSE1_EN (RW)
1470  *
1471  */
1472 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK (0x400U)
1473 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT (10U)
1474 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK)
1475 #define QEIV2_QEI_CFG_TRIG_PULSE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_PULSE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_PULSE1_EN_SHIFT)
1476 
1477 /*
1478  * TRIG_CYCLE0_EN (RW)
1479  *
1480  * set to enable trigger start pulse counter for configed cycle_num
1481  */
1482 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK (0x200U)
1483 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT (9U)
1484 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK)
1485 #define QEIV2_QEI_CFG_TRIG_CYCLE0_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE0_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE0_EN_SHIFT)
1486 
1487 /*
1488  * TRIG_CYCLE1_EN (RW)
1489  *
1490  */
1491 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK (0x100U)
1492 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT (8U)
1493 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK)
1494 #define QEIV2_QEI_CFG_TRIG_CYCLE1_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_TRIG_CYCLE1_EN_MASK) >> QEIV2_QEI_CFG_TRIG_CYCLE1_EN_SHIFT)
1495 
1496 /*
1497  * UVW_POS_OPT0 (RW)
1498  *
1499  * set to output next area position for QEO use;
1500  * clr to output exact point position for MMC use
1501  */
1502 #define QEIV2_QEI_CFG_UVW_POS_OPT0_MASK (0x20U)
1503 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT (5U)
1504 #define QEIV2_QEI_CFG_UVW_POS_OPT0_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK)
1505 #define QEIV2_QEI_CFG_UVW_POS_OPT0_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_UVW_POS_OPT0_MASK) >> QEIV2_QEI_CFG_UVW_POS_OPT0_SHIFT)
1506 
1507 /*
1508  * NEGEDGE_EN (RW)
1509  *
1510  * bit4: negedge enable
1511  * bit3: posedge enable
1512  * bit2: W in hal enable
1513  * bit1: signal b(or V in hal) enable
1514  * bit0: signal a(or U in hal) enable
1515  * such as:
1516  * 01001: use posedge A
1517  * 11010: use both edge of signal B
1518  * 11111: use both edge of all HAL siganls
1519  */
1520 #define QEIV2_QEI_CFG_NEGEDGE_EN_MASK (0x10U)
1521 #define QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT (4U)
1522 #define QEIV2_QEI_CFG_NEGEDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK)
1523 #define QEIV2_QEI_CFG_NEGEDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_NEGEDGE_EN_MASK) >> QEIV2_QEI_CFG_NEGEDGE_EN_SHIFT)
1524 
1525 /*
1526  * POSIDGE_EN (RW)
1527  *
1528  */
1529 #define QEIV2_QEI_CFG_POSIDGE_EN_MASK (0x8U)
1530 #define QEIV2_QEI_CFG_POSIDGE_EN_SHIFT (3U)
1531 #define QEIV2_QEI_CFG_POSIDGE_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_POSIDGE_EN_SHIFT) & QEIV2_QEI_CFG_POSIDGE_EN_MASK)
1532 #define QEIV2_QEI_CFG_POSIDGE_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_POSIDGE_EN_MASK) >> QEIV2_QEI_CFG_POSIDGE_EN_SHIFT)
1533 
1534 /*
1535  * SIGZ_EN (RW)
1536  *
1537  */
1538 #define QEIV2_QEI_CFG_SIGZ_EN_MASK (0x4U)
1539 #define QEIV2_QEI_CFG_SIGZ_EN_SHIFT (2U)
1540 #define QEIV2_QEI_CFG_SIGZ_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGZ_EN_SHIFT) & QEIV2_QEI_CFG_SIGZ_EN_MASK)
1541 #define QEIV2_QEI_CFG_SIGZ_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGZ_EN_MASK) >> QEIV2_QEI_CFG_SIGZ_EN_SHIFT)
1542 
1543 /*
1544  * SIGB_EN (RW)
1545  *
1546  */
1547 #define QEIV2_QEI_CFG_SIGB_EN_MASK (0x2U)
1548 #define QEIV2_QEI_CFG_SIGB_EN_SHIFT (1U)
1549 #define QEIV2_QEI_CFG_SIGB_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGB_EN_SHIFT) & QEIV2_QEI_CFG_SIGB_EN_MASK)
1550 #define QEIV2_QEI_CFG_SIGB_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGB_EN_MASK) >> QEIV2_QEI_CFG_SIGB_EN_SHIFT)
1551 
1552 /*
1553  * SIGA_EN (RW)
1554  *
1555  */
1556 #define QEIV2_QEI_CFG_SIGA_EN_MASK (0x1U)
1557 #define QEIV2_QEI_CFG_SIGA_EN_SHIFT (0U)
1558 #define QEIV2_QEI_CFG_SIGA_EN_SET(x) (((uint32_t)(x) << QEIV2_QEI_CFG_SIGA_EN_SHIFT) & QEIV2_QEI_CFG_SIGA_EN_MASK)
1559 #define QEIV2_QEI_CFG_SIGA_EN_GET(x) (((uint32_t)(x) & QEIV2_QEI_CFG_SIGA_EN_MASK) >> QEIV2_QEI_CFG_SIGA_EN_SHIFT)
1560 
1561 /* Bitfield definition for register: PULSE0_NUM */
1562 /*
1563  * PULSE0_NUM (RW)
1564  *
1565  * for speed detection, will count the cycle number for configed pulse_num
1566  */
1567 #define QEIV2_PULSE0_NUM_PULSE0_NUM_MASK (0xFFFFFFFFUL)
1568 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT (0U)
1569 #define QEIV2_PULSE0_NUM_PULSE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK)
1570 #define QEIV2_PULSE0_NUM_PULSE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_NUM_PULSE0_NUM_MASK) >> QEIV2_PULSE0_NUM_PULSE0_NUM_SHIFT)
1571 
1572 /* Bitfield definition for register: PULSE1_NUM */
1573 /*
1574  * PULSE1_NUM (RW)
1575  *
1576  */
1577 #define QEIV2_PULSE1_NUM_PULSE1_NUM_MASK (0xFFFFFFFFUL)
1578 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT (0U)
1579 #define QEIV2_PULSE1_NUM_PULSE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK)
1580 #define QEIV2_PULSE1_NUM_PULSE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_NUM_PULSE1_NUM_MASK) >> QEIV2_PULSE1_NUM_PULSE1_NUM_SHIFT)
1581 
1582 /* Bitfield definition for register: CYCLE0_CNT */
1583 /*
1584  * CYCLE0_CNT (RO)
1585  *
1586  */
1587 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK (0xFFFFFFFFUL)
1588 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT (0U)
1589 #define QEIV2_CYCLE0_CNT_CYCLE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_CNT_CYCLE0_CNT_MASK) >> QEIV2_CYCLE0_CNT_CYCLE0_CNT_SHIFT)
1590 
1591 /* Bitfield definition for register: CYCLE0PULSE_CNT */
1592 /*
1593  * CYCLE0PULSE_CNT (RO)
1594  *
1595  */
1596 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK (0xFFFFFFFFUL)
1597 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT (0U)
1598 #define QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_MASK) >> QEIV2_CYCLE0PULSE_CNT_CYCLE0PULSE_CNT_SHIFT)
1599 
1600 /* Bitfield definition for register: CYCLE1_CNT */
1601 /*
1602  * CYCLE1_CNT (RO)
1603  *
1604  */
1605 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK (0xFFFFFFFFUL)
1606 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT (0U)
1607 #define QEIV2_CYCLE1_CNT_CYCLE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_CNT_CYCLE1_CNT_MASK) >> QEIV2_CYCLE1_CNT_CYCLE1_CNT_SHIFT)
1608 
1609 /* Bitfield definition for register: CYCLE1PULSE_CNT */
1610 /*
1611  * CYCLE1PULSE_CNT (RO)
1612  *
1613  */
1614 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK (0xFFFFFFFFUL)
1615 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT (0U)
1616 #define QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_MASK) >> QEIV2_CYCLE1PULSE_CNT_CYCLE1PULSE_CNT_SHIFT)
1617 
1618 /* Bitfield definition for register: CYCLE0_SNAP0 */
1619 /*
1620  * CYCLE0_SNAP0 (RO)
1621  *
1622  */
1623 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK (0xFFFFFFFFUL)
1624 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT (0U)
1625 #define QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_MASK) >> QEIV2_CYCLE0_SNAP0_CYCLE0_SNAP0_SHIFT)
1626 
1627 /* Bitfield definition for register: CYCLE0_SNAP1 */
1628 /*
1629  * CYCLE0_SNAP1 (RO)
1630  *
1631  */
1632 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK (0xFFFFFFFFUL)
1633 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT (0U)
1634 #define QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_MASK) >> QEIV2_CYCLE0_SNAP1_CYCLE0_SNAP1_SHIFT)
1635 
1636 /* Bitfield definition for register: CYCLE1_SNAP0 */
1637 /*
1638  * CYCLE1_SNAP0 (RO)
1639  *
1640  */
1641 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK (0xFFFFFFFFUL)
1642 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT (0U)
1643 #define QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_MASK) >> QEIV2_CYCLE1_SNAP0_CYCLE1_SNAP0_SHIFT)
1644 
1645 /* Bitfield definition for register: CYCLE1_SNAP1 */
1646 /*
1647  * CYCLE1_SNAP1 (RO)
1648  *
1649  */
1650 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK (0xFFFFFFFFUL)
1651 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT (0U)
1652 #define QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_MASK) >> QEIV2_CYCLE1_SNAP1_CYCLE1_SNAP1_SHIFT)
1653 
1654 /* Bitfield definition for register: CYCLE0_NUM */
1655 /*
1656  * CYCLE0_NUM (RW)
1657  *
1658  */
1659 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK (0xFFFFFFFFUL)
1660 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT (0U)
1661 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK)
1662 #define QEIV2_CYCLE0_NUM_CYCLE0_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE0_NUM_CYCLE0_NUM_MASK) >> QEIV2_CYCLE0_NUM_CYCLE0_NUM_SHIFT)
1663 
1664 /* Bitfield definition for register: CYCLE1_NUM */
1665 /*
1666  * CYCLE1_NUM (RW)
1667  *
1668  */
1669 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK (0xFFFFFFFFUL)
1670 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT (0U)
1671 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_SET(x) (((uint32_t)(x) << QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK)
1672 #define QEIV2_CYCLE1_NUM_CYCLE1_NUM_GET(x) (((uint32_t)(x) & QEIV2_CYCLE1_NUM_CYCLE1_NUM_MASK) >> QEIV2_CYCLE1_NUM_CYCLE1_NUM_SHIFT)
1673 
1674 /* Bitfield definition for register: PULSE0_CNT */
1675 /*
1676  * PULSE0_CNT (RO)
1677  *
1678  */
1679 #define QEIV2_PULSE0_CNT_PULSE0_CNT_MASK (0xFFFFFFFFUL)
1680 #define QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT (0U)
1681 #define QEIV2_PULSE0_CNT_PULSE0_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_CNT_PULSE0_CNT_MASK) >> QEIV2_PULSE0_CNT_PULSE0_CNT_SHIFT)
1682 
1683 /* Bitfield definition for register: PULSE0CYCLE_CNT */
1684 /*
1685  * PULSE0CYCLE_CNT (RO)
1686  *
1687  */
1688 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK (0xFFFFFFFFUL)
1689 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT (0U)
1690 #define QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_MASK) >> QEIV2_PULSE0CYCLE_CNT_PULSE0CYCLE_CNT_SHIFT)
1691 
1692 /* Bitfield definition for register: PULSE1_CNT */
1693 /*
1694  * PULSE1_CNT (RO)
1695  *
1696  */
1697 #define QEIV2_PULSE1_CNT_PULSE1_CNT_MASK (0xFFFFFFFFUL)
1698 #define QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT (0U)
1699 #define QEIV2_PULSE1_CNT_PULSE1_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_CNT_PULSE1_CNT_MASK) >> QEIV2_PULSE1_CNT_PULSE1_CNT_SHIFT)
1700 
1701 /* Bitfield definition for register: PULSE1CYCLE_CNT */
1702 /*
1703  * PULSE1CYCLE_CNT (RO)
1704  *
1705  */
1706 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK (0xFFFFFFFFUL)
1707 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT (0U)
1708 #define QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_MASK) >> QEIV2_PULSE1CYCLE_CNT_PULSE1CYCLE_CNT_SHIFT)
1709 
1710 /* Bitfield definition for register: PULSE0_SNAP0 */
1711 /*
1712  * PULSE0_SNAP0 (RO)
1713  *
1714  */
1715 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK (0xFFFFFFFFUL)
1716 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT (0U)
1717 #define QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_MASK) >> QEIV2_PULSE0_SNAP0_PULSE0_SNAP0_SHIFT)
1718 
1719 /* Bitfield definition for register: PULSE0CYCLE_SNAP0 */
1720 /*
1721  * PULSE0CYCLE_SNAP0 (RO)
1722  *
1723  */
1724 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1725 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT (0U)
1726 #define QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_MASK) >> QEIV2_PULSE0CYCLE_SNAP0_PULSE0CYCLE_SNAP0_SHIFT)
1727 
1728 /* Bitfield definition for register: PULSE0_SNAP1 */
1729 /*
1730  * PULSE0_SNAP1 (RO)
1731  *
1732  */
1733 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK (0xFFFFFFFFUL)
1734 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT (0U)
1735 #define QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_MASK) >> QEIV2_PULSE0_SNAP1_PULSE0_SNAP1_SHIFT)
1736 
1737 /* Bitfield definition for register: PULSE0CYCLE_SNAP1 */
1738 /*
1739  * PULSE0CYCLE_SNAP1 (RO)
1740  *
1741  */
1742 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1743 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT (0U)
1744 #define QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_MASK) >> QEIV2_PULSE0CYCLE_SNAP1_PULSE0CYCLE_SNAP1_SHIFT)
1745 
1746 /* Bitfield definition for register: PULSE1_SNAP0 */
1747 /*
1748  * PULSE1_SNAP0 (RO)
1749  *
1750  */
1751 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK (0xFFFFFFFFUL)
1752 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT (0U)
1753 #define QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_MASK) >> QEIV2_PULSE1_SNAP0_PULSE1_SNAP0_SHIFT)
1754 
1755 /* Bitfield definition for register: PULSE1CYCLE_SNAP0 */
1756 /*
1757  * PULSE1CYCLE_SNAP0 (RO)
1758  *
1759  */
1760 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK (0xFFFFFFFFUL)
1761 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT (0U)
1762 #define QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_MASK) >> QEIV2_PULSE1CYCLE_SNAP0_PULSE1CYCLE_SNAP0_SHIFT)
1763 
1764 /* Bitfield definition for register: PULSE1_SNAP1 */
1765 /*
1766  * PULSE1_SNAP1 (RO)
1767  *
1768  */
1769 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK (0xFFFFFFFFUL)
1770 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT (0U)
1771 #define QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_MASK) >> QEIV2_PULSE1_SNAP1_PULSE1_SNAP1_SHIFT)
1772 
1773 /* Bitfield definition for register: PULSE1CYCLE_SNAP1 */
1774 /*
1775  * PULSE1CYCLE_SNAP1 (RO)
1776  *
1777  */
1778 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK (0xFFFFFFFFUL)
1779 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT (0U)
1780 #define QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_GET(x) (((uint32_t)(x) & QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_MASK) >> QEIV2_PULSE1CYCLE_SNAP1_PULSE1CYCLE_SNAP1_SHIFT)
1781 
1782 /* Bitfield definition for register: TIMESTAMP */
1783 /*
1784  * TIMESTAMP (RO)
1785  *
1786  * for SIN/COS mode, it saves the timestampe of the begining of first ADC sample time;
1787  * for ABZ mode, it saves the timestampe of edge of input signals
1788  */
1789 #define QEIV2_TIMESTAMP_TIMESTAMP_MASK (0xFFFFFFFFUL)
1790 #define QEIV2_TIMESTAMP_TIMESTAMP_SHIFT (0U)
1791 #define QEIV2_TIMESTAMP_TIMESTAMP_GET(x) (((uint32_t)(x) & QEIV2_TIMESTAMP_TIMESTAMP_MASK) >> QEIV2_TIMESTAMP_TIMESTAMP_SHIFT)
1792 
1793 /* Bitfield definition for register: ADC_THRESHOLD */
1794 /*
1795  * LOW_LIMIT (RW)
1796  *
1797  * for SINCOS mode, if (max+min/2) of the two adc result, is small than limit,
1798  * then this value is treated as unvalid, no position output.
1799  * this is uesd to avoid wrong adc resule(such as 0 or same sin cos value)
1800  */
1801 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK (0xFFFF0000UL)
1802 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT (16U)
1803 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK)
1804 #define QEIV2_ADC_THRESHOLD_LOW_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_LOW_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_LOW_LIMIT_SHIFT)
1805 
1806 /*
1807  * HIGH_LIMIT (RW)
1808  *
1809  * high limit for SINCOS mode adc result
1810  */
1811 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK (0xFFFFU)
1812 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT (0U)
1813 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SET(x) (((uint32_t)(x) << QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK)
1814 #define QEIV2_ADC_THRESHOLD_HIGH_LIMIT_GET(x) (((uint32_t)(x) & QEIV2_ADC_THRESHOLD_HIGH_LIMIT_MASK) >> QEIV2_ADC_THRESHOLD_HIGH_LIMIT_SHIFT)
1815 
1816 /* Bitfield definition for register: ADCX_CFG0 */
1817 /*
1818  * X_ADCSEL (RW)
1819  *
1820  */
1821 #define QEIV2_ADCX_CFG0_X_ADCSEL_MASK (0x100U)
1822 #define QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT (8U)
1823 #define QEIV2_ADCX_CFG0_X_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK)
1824 #define QEIV2_ADCX_CFG0_X_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADCSEL_MASK) >> QEIV2_ADCX_CFG0_X_ADCSEL_SHIFT)
1825 
1826 /*
1827  * X_ADC_ENABLE (RW)
1828  *
1829  */
1830 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK (0x80U)
1831 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT (7U)
1832 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK)
1833 #define QEIV2_ADCX_CFG0_X_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_ADC_ENABLE_MASK) >> QEIV2_ADCX_CFG0_X_ADC_ENABLE_SHIFT)
1834 
1835 /*
1836  * X_CHAN (RW)
1837  *
1838  */
1839 #define QEIV2_ADCX_CFG0_X_CHAN_MASK (0x1FU)
1840 #define QEIV2_ADCX_CFG0_X_CHAN_SHIFT (0U)
1841 #define QEIV2_ADCX_CFG0_X_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG0_X_CHAN_SHIFT) & QEIV2_ADCX_CFG0_X_CHAN_MASK)
1842 #define QEIV2_ADCX_CFG0_X_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG0_X_CHAN_MASK) >> QEIV2_ADCX_CFG0_X_CHAN_SHIFT)
1843 
1844 /* Bitfield definition for register: ADCX_CFG1 */
1845 /*
1846  * X_PARAM1 (RW)
1847  *
1848  */
1849 #define QEIV2_ADCX_CFG1_X_PARAM1_MASK (0xFFFF0000UL)
1850 #define QEIV2_ADCX_CFG1_X_PARAM1_SHIFT (16U)
1851 #define QEIV2_ADCX_CFG1_X_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM1_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM1_MASK)
1852 #define QEIV2_ADCX_CFG1_X_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM1_MASK) >> QEIV2_ADCX_CFG1_X_PARAM1_SHIFT)
1853 
1854 /*
1855  * X_PARAM0 (RW)
1856  *
1857  */
1858 #define QEIV2_ADCX_CFG1_X_PARAM0_MASK (0xFFFFU)
1859 #define QEIV2_ADCX_CFG1_X_PARAM0_SHIFT (0U)
1860 #define QEIV2_ADCX_CFG1_X_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG1_X_PARAM0_SHIFT) & QEIV2_ADCX_CFG1_X_PARAM0_MASK)
1861 #define QEIV2_ADCX_CFG1_X_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG1_X_PARAM0_MASK) >> QEIV2_ADCX_CFG1_X_PARAM0_SHIFT)
1862 
1863 /* Bitfield definition for register: ADCX_CFG2 */
1864 /*
1865  * X_OFFSET (RW)
1866  *
1867  */
1868 #define QEIV2_ADCX_CFG2_X_OFFSET_MASK (0xFFFFFFFFUL)
1869 #define QEIV2_ADCX_CFG2_X_OFFSET_SHIFT (0U)
1870 #define QEIV2_ADCX_CFG2_X_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCX_CFG2_X_OFFSET_SHIFT) & QEIV2_ADCX_CFG2_X_OFFSET_MASK)
1871 #define QEIV2_ADCX_CFG2_X_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCX_CFG2_X_OFFSET_MASK) >> QEIV2_ADCX_CFG2_X_OFFSET_SHIFT)
1872 
1873 /* Bitfield definition for register: ADCX_VAL_SW */
1874 /*
1875  * ADCX_VAL_SW (RW)
1876  *
1877  * adc X channel value when using adc inject feature.
1878  * 32bit signed value
1879  * NOTE: x_offset is not used when adc_inject_en is set, x_param0 and x_param1 are still used,
1880  * user can leave them as default if do not want to use them
1881  */
1882 #define QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_MASK (0xFFFFFFFFUL)
1883 #define QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_SHIFT (0U)
1884 #define QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_SET(x) (((uint32_t)(x) << QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_SHIFT) & QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_MASK)
1885 #define QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_GET(x) (((uint32_t)(x) & QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_MASK) >> QEIV2_ADCX_VAL_SW_ADCX_VAL_SW_SHIFT)
1886 
1887 /* Bitfield definition for register: ADCY_CFG0 */
1888 /*
1889  * Y_ADCSEL (RW)
1890  *
1891  */
1892 #define QEIV2_ADCY_CFG0_Y_ADCSEL_MASK (0x100U)
1893 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT (8U)
1894 #define QEIV2_ADCY_CFG0_Y_ADCSEL_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK)
1895 #define QEIV2_ADCY_CFG0_Y_ADCSEL_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADCSEL_MASK) >> QEIV2_ADCY_CFG0_Y_ADCSEL_SHIFT)
1896 
1897 /*
1898  * Y_ADC_ENABLE (RW)
1899  *
1900  */
1901 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK (0x80U)
1902 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT (7U)
1903 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK)
1904 #define QEIV2_ADCY_CFG0_Y_ADC_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_ADC_ENABLE_MASK) >> QEIV2_ADCY_CFG0_Y_ADC_ENABLE_SHIFT)
1905 
1906 /*
1907  * Y_CHAN (RW)
1908  *
1909  */
1910 #define QEIV2_ADCY_CFG0_Y_CHAN_MASK (0x1FU)
1911 #define QEIV2_ADCY_CFG0_Y_CHAN_SHIFT (0U)
1912 #define QEIV2_ADCY_CFG0_Y_CHAN_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG0_Y_CHAN_SHIFT) & QEIV2_ADCY_CFG0_Y_CHAN_MASK)
1913 #define QEIV2_ADCY_CFG0_Y_CHAN_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG0_Y_CHAN_MASK) >> QEIV2_ADCY_CFG0_Y_CHAN_SHIFT)
1914 
1915 /* Bitfield definition for register: ADCY_CFG1 */
1916 /*
1917  * Y_PARAM1 (RW)
1918  *
1919  */
1920 #define QEIV2_ADCY_CFG1_Y_PARAM1_MASK (0xFFFF0000UL)
1921 #define QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT (16U)
1922 #define QEIV2_ADCY_CFG1_Y_PARAM1_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK)
1923 #define QEIV2_ADCY_CFG1_Y_PARAM1_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM1_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM1_SHIFT)
1924 
1925 /*
1926  * Y_PARAM0 (RW)
1927  *
1928  */
1929 #define QEIV2_ADCY_CFG1_Y_PARAM0_MASK (0xFFFFU)
1930 #define QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT (0U)
1931 #define QEIV2_ADCY_CFG1_Y_PARAM0_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK)
1932 #define QEIV2_ADCY_CFG1_Y_PARAM0_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG1_Y_PARAM0_MASK) >> QEIV2_ADCY_CFG1_Y_PARAM0_SHIFT)
1933 
1934 /* Bitfield definition for register: ADCY_CFG2 */
1935 /*
1936  * Y_OFFSET (RW)
1937  *
1938  */
1939 #define QEIV2_ADCY_CFG2_Y_OFFSET_MASK (0xFFFFFFFFUL)
1940 #define QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT (0U)
1941 #define QEIV2_ADCY_CFG2_Y_OFFSET_SET(x) (((uint32_t)(x) << QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK)
1942 #define QEIV2_ADCY_CFG2_Y_OFFSET_GET(x) (((uint32_t)(x) & QEIV2_ADCY_CFG2_Y_OFFSET_MASK) >> QEIV2_ADCY_CFG2_Y_OFFSET_SHIFT)
1943 
1944 /* Bitfield definition for register: ADCY_VAL_SW */
1945 /*
1946  * ADCY_VAL_SW (RW)
1947  *
1948  */
1949 #define QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_MASK (0xFFFFFFFFUL)
1950 #define QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_SHIFT (0U)
1951 #define QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_SET(x) (((uint32_t)(x) << QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_SHIFT) & QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_MASK)
1952 #define QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_GET(x) (((uint32_t)(x) & QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_MASK) >> QEIV2_ADCY_VAL_SW_ADCY_VAL_SW_SHIFT)
1953 
1954 /* Bitfield definition for register: CAL_CFG */
1955 /*
1956  * XY_DELAY (RW)
1957  *
1958  * valid x/y delay, larger than this delay will be treated as invalid data.
1959  * Default 1.25us@200MHz; max 80ms;
1960  */
1961 #define QEIV2_CAL_CFG_XY_DELAY_MASK (0xFFFFFFUL)
1962 #define QEIV2_CAL_CFG_XY_DELAY_SHIFT (0U)
1963 #define QEIV2_CAL_CFG_XY_DELAY_SET(x) (((uint32_t)(x) << QEIV2_CAL_CFG_XY_DELAY_SHIFT) & QEIV2_CAL_CFG_XY_DELAY_MASK)
1964 #define QEIV2_CAL_CFG_XY_DELAY_GET(x) (((uint32_t)(x) & QEIV2_CAL_CFG_XY_DELAY_MASK) >> QEIV2_CAL_CFG_XY_DELAY_SHIFT)
1965 
1966 /* Bitfield definition for register: ADC_INJECT_CTRL */
1967 /*
1968  * ADC_INJECT_EN (RW)
1969  *
1970  * set to use adcx_val and adcy_val from software
1971  */
1972 #define QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_MASK (0x80000000UL)
1973 #define QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_SHIFT (31U)
1974 #define QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_SET(x) (((uint32_t)(x) << QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_SHIFT) & QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_MASK)
1975 #define QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_GET(x) (((uint32_t)(x) & QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_MASK) >> QEIV2_ADC_INJECT_CTRL_ADC_INJECT_EN_SHIFT)
1976 
1977 /*
1978  * ADCY_INJ_VALID (WO)
1979  *
1980  * set for adc X channel valid
1981  */
1982 #define QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_MASK (0x2U)
1983 #define QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_SHIFT (1U)
1984 #define QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_SET(x) (((uint32_t)(x) << QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_SHIFT) & QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_MASK)
1985 #define QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_GET(x) (((uint32_t)(x) & QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_MASK) >> QEIV2_ADC_INJECT_CTRL_ADCY_INJ_VALID_SHIFT)
1986 
1987 /*
1988  * ADCX_INJ_VALID (WO)
1989  *
1990  * set for adc Y channel valid
1991  */
1992 #define QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_MASK (0x1U)
1993 #define QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_SHIFT (0U)
1994 #define QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_SET(x) (((uint32_t)(x) << QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_SHIFT) & QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_MASK)
1995 #define QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_GET(x) (((uint32_t)(x) & QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_MASK) >> QEIV2_ADC_INJECT_CTRL_ADCX_INJ_VALID_SHIFT)
1996 
1997 /* Bitfield definition for register: PHASE_PARAM */
1998 /*
1999  * PHASE_PARAM (RW)
2000  *
2001  */
2002 #define QEIV2_PHASE_PARAM_PHASE_PARAM_MASK (0xFFFFFFFFUL)
2003 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT (0U)
2004 #define QEIV2_PHASE_PARAM_PHASE_PARAM_SET(x) (((uint32_t)(x) << QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK)
2005 #define QEIV2_PHASE_PARAM_PHASE_PARAM_GET(x) (((uint32_t)(x) & QEIV2_PHASE_PARAM_PHASE_PARAM_MASK) >> QEIV2_PHASE_PARAM_PHASE_PARAM_SHIFT)
2006 
2007 /* Bitfield definition for register: POS_ADJ */
2008 /*
2009  * POS_ADJ (RW)
2010  *
2011  */
2012 #define QEIV2_POS_ADJ_POS_ADJ_MASK (0xFFFFFFFFUL)
2013 #define QEIV2_POS_ADJ_POS_ADJ_SHIFT (0U)
2014 #define QEIV2_POS_ADJ_POS_ADJ_SET(x) (((uint32_t)(x) << QEIV2_POS_ADJ_POS_ADJ_SHIFT) & QEIV2_POS_ADJ_POS_ADJ_MASK)
2015 #define QEIV2_POS_ADJ_POS_ADJ_GET(x) (((uint32_t)(x) & QEIV2_POS_ADJ_POS_ADJ_MASK) >> QEIV2_POS_ADJ_POS_ADJ_SHIFT)
2016 
2017 /* Bitfield definition for register: POS_THRESHOLD */
2018 /*
2019  * POS_THRESHOLD (RW)
2020  *
2021  */
2022 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK (0xFFFFFFFFUL)
2023 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT (0U)
2024 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_SET(x) (((uint32_t)(x) << QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK)
2025 #define QEIV2_POS_THRESHOLD_POS_THRESHOLD_GET(x) (((uint32_t)(x) & QEIV2_POS_THRESHOLD_POS_THRESHOLD_MASK) >> QEIV2_POS_THRESHOLD_POS_THRESHOLD_SHIFT)
2026 
2027 /* Bitfield definition for register array: UVW_POS */
2028 /*
2029  * UVW_POS0 (RW)
2030  *
2031  */
2032 #define QEIV2_UVW_POS_UVW_POS0_MASK (0xFFFFFFFFUL)
2033 #define QEIV2_UVW_POS_UVW_POS0_SHIFT (0U)
2034 #define QEIV2_UVW_POS_UVW_POS0_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_UVW_POS0_SHIFT) & QEIV2_UVW_POS_UVW_POS0_MASK)
2035 #define QEIV2_UVW_POS_UVW_POS0_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_UVW_POS0_MASK) >> QEIV2_UVW_POS_UVW_POS0_SHIFT)
2036 
2037 /* Bitfield definition for register array: UVW_POS_CFG */
2038 /*
2039  * POS_EN (RW)
2040  *
2041  */
2042 #define QEIV2_UVW_POS_CFG_POS_EN_MASK (0x40U)
2043 #define QEIV2_UVW_POS_CFG_POS_EN_SHIFT (6U)
2044 #define QEIV2_UVW_POS_CFG_POS_EN_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_POS_EN_SHIFT) & QEIV2_UVW_POS_CFG_POS_EN_MASK)
2045 #define QEIV2_UVW_POS_CFG_POS_EN_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_POS_EN_MASK) >> QEIV2_UVW_POS_CFG_POS_EN_SHIFT)
2046 
2047 /*
2048  * U_POS_SEL (RW)
2049  *
2050  */
2051 #define QEIV2_UVW_POS_CFG_U_POS_SEL_MASK (0x30U)
2052 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT (4U)
2053 #define QEIV2_UVW_POS_CFG_U_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK)
2054 #define QEIV2_UVW_POS_CFG_U_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_U_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_U_POS_SEL_SHIFT)
2055 
2056 /*
2057  * V_POS_SEL (RW)
2058  *
2059  */
2060 #define QEIV2_UVW_POS_CFG_V_POS_SEL_MASK (0xCU)
2061 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT (2U)
2062 #define QEIV2_UVW_POS_CFG_V_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK)
2063 #define QEIV2_UVW_POS_CFG_V_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_V_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_V_POS_SEL_SHIFT)
2064 
2065 /*
2066  * W_POS_SEL (RW)
2067  *
2068  */
2069 #define QEIV2_UVW_POS_CFG_W_POS_SEL_MASK (0x3U)
2070 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT (0U)
2071 #define QEIV2_UVW_POS_CFG_W_POS_SEL_SET(x) (((uint32_t)(x) << QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK)
2072 #define QEIV2_UVW_POS_CFG_W_POS_SEL_GET(x) (((uint32_t)(x) & QEIV2_UVW_POS_CFG_W_POS_SEL_MASK) >> QEIV2_UVW_POS_CFG_W_POS_SEL_SHIFT)
2073 
2074 /* Bitfield definition for register: PHASE_CNT */
2075 /*
2076  * PHASE_CNT (RW)
2077  *
2078  */
2079 #define QEIV2_PHASE_CNT_PHASE_CNT_MASK (0xFFFFFFFFUL)
2080 #define QEIV2_PHASE_CNT_PHASE_CNT_SHIFT (0U)
2081 #define QEIV2_PHASE_CNT_PHASE_CNT_SET(x) (((uint32_t)(x) << QEIV2_PHASE_CNT_PHASE_CNT_SHIFT) & QEIV2_PHASE_CNT_PHASE_CNT_MASK)
2082 #define QEIV2_PHASE_CNT_PHASE_CNT_GET(x) (((uint32_t)(x) & QEIV2_PHASE_CNT_PHASE_CNT_MASK) >> QEIV2_PHASE_CNT_PHASE_CNT_SHIFT)
2083 
2084 /* Bitfield definition for register: PHASE_UPDATE */
2085 /*
2086  * INC (WO)
2087  *
2088  * set to add value to phase_cnt
2089  */
2090 #define QEIV2_PHASE_UPDATE_INC_MASK (0x80000000UL)
2091 #define QEIV2_PHASE_UPDATE_INC_SHIFT (31U)
2092 #define QEIV2_PHASE_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_INC_SHIFT) & QEIV2_PHASE_UPDATE_INC_MASK)
2093 #define QEIV2_PHASE_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_INC_MASK) >> QEIV2_PHASE_UPDATE_INC_SHIFT)
2094 
2095 /*
2096  * DEC (WO)
2097  *
2098  * set to minus value from phase_cnt(set inc and dec same time willl act inc)
2099  */
2100 #define QEIV2_PHASE_UPDATE_DEC_MASK (0x40000000UL)
2101 #define QEIV2_PHASE_UPDATE_DEC_SHIFT (30U)
2102 #define QEIV2_PHASE_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_DEC_SHIFT) & QEIV2_PHASE_UPDATE_DEC_MASK)
2103 #define QEIV2_PHASE_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_DEC_MASK) >> QEIV2_PHASE_UPDATE_DEC_SHIFT)
2104 
2105 /*
2106  * VALUE (WO)
2107  *
2108  * value to be added or minus from phase_cnt. only valid when inc or dec is set in one 32bit write operation
2109  */
2110 #define QEIV2_PHASE_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
2111 #define QEIV2_PHASE_UPDATE_VALUE_SHIFT (0U)
2112 #define QEIV2_PHASE_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_PHASE_UPDATE_VALUE_SHIFT) & QEIV2_PHASE_UPDATE_VALUE_MASK)
2113 #define QEIV2_PHASE_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_PHASE_UPDATE_VALUE_MASK) >> QEIV2_PHASE_UPDATE_VALUE_SHIFT)
2114 
2115 /* Bitfield definition for register: POSITION */
2116 /*
2117  * POSITION (RW)
2118  *
2119  */
2120 #define QEIV2_POSITION_POSITION_MASK (0xFFFFFFFFUL)
2121 #define QEIV2_POSITION_POSITION_SHIFT (0U)
2122 #define QEIV2_POSITION_POSITION_SET(x) (((uint32_t)(x) << QEIV2_POSITION_POSITION_SHIFT) & QEIV2_POSITION_POSITION_MASK)
2123 #define QEIV2_POSITION_POSITION_GET(x) (((uint32_t)(x) & QEIV2_POSITION_POSITION_MASK) >> QEIV2_POSITION_POSITION_SHIFT)
2124 
2125 /* Bitfield definition for register: POSITION_UPDATE */
2126 /*
2127  * INC (WO)
2128  *
2129  * set to add value to position
2130  */
2131 #define QEIV2_POSITION_UPDATE_INC_MASK (0x80000000UL)
2132 #define QEIV2_POSITION_UPDATE_INC_SHIFT (31U)
2133 #define QEIV2_POSITION_UPDATE_INC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_INC_SHIFT) & QEIV2_POSITION_UPDATE_INC_MASK)
2134 #define QEIV2_POSITION_UPDATE_INC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_INC_MASK) >> QEIV2_POSITION_UPDATE_INC_SHIFT)
2135 
2136 /*
2137  * DEC (WO)
2138  *
2139  * set to minus value from position(set inc and dec same time willl act inc)
2140  */
2141 #define QEIV2_POSITION_UPDATE_DEC_MASK (0x40000000UL)
2142 #define QEIV2_POSITION_UPDATE_DEC_SHIFT (30U)
2143 #define QEIV2_POSITION_UPDATE_DEC_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_DEC_SHIFT) & QEIV2_POSITION_UPDATE_DEC_MASK)
2144 #define QEIV2_POSITION_UPDATE_DEC_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_DEC_MASK) >> QEIV2_POSITION_UPDATE_DEC_SHIFT)
2145 
2146 /*
2147  * VALUE (WO)
2148  *
2149  * value to be added or minus from position. only valid when inc or dec is set in one 32bit write operation
2150  */
2151 #define QEIV2_POSITION_UPDATE_VALUE_MASK (0x3FFFFFFFUL)
2152 #define QEIV2_POSITION_UPDATE_VALUE_SHIFT (0U)
2153 #define QEIV2_POSITION_UPDATE_VALUE_SET(x) (((uint32_t)(x) << QEIV2_POSITION_UPDATE_VALUE_SHIFT) & QEIV2_POSITION_UPDATE_VALUE_MASK)
2154 #define QEIV2_POSITION_UPDATE_VALUE_GET(x) (((uint32_t)(x) & QEIV2_POSITION_UPDATE_VALUE_MASK) >> QEIV2_POSITION_UPDATE_VALUE_SHIFT)
2155 
2156 /* Bitfield definition for register: ANGLE */
2157 /*
2158  * ANGLE (RO)
2159  *
2160  */
2161 #define QEIV2_ANGLE_ANGLE_MASK (0xFFFFFFFFUL)
2162 #define QEIV2_ANGLE_ANGLE_SHIFT (0U)
2163 #define QEIV2_ANGLE_ANGLE_GET(x) (((uint32_t)(x) & QEIV2_ANGLE_ANGLE_MASK) >> QEIV2_ANGLE_ANGLE_SHIFT)
2164 
2165 /* Bitfield definition for register: POS_TIMEOUT */
2166 /*
2167  * ENABLE (RW)
2168  *
2169  * enable position timeout feature, if timeout, send valid again
2170  */
2171 #define QEIV2_POS_TIMEOUT_ENABLE_MASK (0x80000000UL)
2172 #define QEIV2_POS_TIMEOUT_ENABLE_SHIFT (31U)
2173 #define QEIV2_POS_TIMEOUT_ENABLE_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_ENABLE_SHIFT) & QEIV2_POS_TIMEOUT_ENABLE_MASK)
2174 #define QEIV2_POS_TIMEOUT_ENABLE_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_ENABLE_MASK) >> QEIV2_POS_TIMEOUT_ENABLE_SHIFT)
2175 
2176 /*
2177  * TIMEOUT (RW)
2178  *
2179  * postion timeout value
2180  */
2181 #define QEIV2_POS_TIMEOUT_TIMEOUT_MASK (0x7FFFFFFFUL)
2182 #define QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT (0U)
2183 #define QEIV2_POS_TIMEOUT_TIMEOUT_SET(x) (((uint32_t)(x) << QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK)
2184 #define QEIV2_POS_TIMEOUT_TIMEOUT_GET(x) (((uint32_t)(x) & QEIV2_POS_TIMEOUT_TIMEOUT_MASK) >> QEIV2_POS_TIMEOUT_TIMEOUT_SHIFT)
2185 
2186 /* Bitfield definition for register: CALC_STATE */
2187 /*
2188  * STATE (RO)
2189  *
2190  * 0：calculate finish
2191  * other: in calculating
2192  */
2193 #define QEIV2_CALC_STATE_STATE_MASK (0xF000000UL)
2194 #define QEIV2_CALC_STATE_STATE_SHIFT (24U)
2195 #define QEIV2_CALC_STATE_STATE_GET(x) (((uint32_t)(x) & QEIV2_CALC_STATE_STATE_MASK) >> QEIV2_CALC_STATE_STATE_SHIFT)
2196 
2197 /* Bitfield definition for register: TOGI_CFG0 */
2198 /*
2199  * SIN_TOGI (RW)
2200  *
2201  * set to use TOGI architecture for single SIN input
2202  */
2203 #define QEIV2_TOGI_CFG0_SIN_TOGI_MASK (0x80000000UL)
2204 #define QEIV2_TOGI_CFG0_SIN_TOGI_SHIFT (31U)
2205 #define QEIV2_TOGI_CFG0_SIN_TOGI_SET(x) (((uint32_t)(x) << QEIV2_TOGI_CFG0_SIN_TOGI_SHIFT) & QEIV2_TOGI_CFG0_SIN_TOGI_MASK)
2206 #define QEIV2_TOGI_CFG0_SIN_TOGI_GET(x) (((uint32_t)(x) & QEIV2_TOGI_CFG0_SIN_TOGI_MASK) >> QEIV2_TOGI_CFG0_SIN_TOGI_SHIFT)
2207 
2208 /* Bitfield definition for register: TOGI_CFG1 */
2209 /*
2210  * W_PARAM (RW)
2211  *
2212  * w_param is angle speed, which is 2*PI*signal_hz/adc_sample_rate*2^28.
2213  * for example, 50Hz signal with 1MHz ADC sample rate, angle speed is 2*3.14159*50/1000000*0x10000000,
2214  * which is 84331(0x1496B, default value)
2215  * if 50Hz with 2MHz sample rate, should config to 0xA4B6
2216  */
2217 #define QEIV2_TOGI_CFG1_W_PARAM_MASK (0xFFFFFFFUL)
2218 #define QEIV2_TOGI_CFG1_W_PARAM_SHIFT (0U)
2219 #define QEIV2_TOGI_CFG1_W_PARAM_SET(x) (((uint32_t)(x) << QEIV2_TOGI_CFG1_W_PARAM_SHIFT) & QEIV2_TOGI_CFG1_W_PARAM_MASK)
2220 #define QEIV2_TOGI_CFG1_W_PARAM_GET(x) (((uint32_t)(x) & QEIV2_TOGI_CFG1_W_PARAM_MASK) >> QEIV2_TOGI_CFG1_W_PARAM_SHIFT)
2221 
2222 /* Bitfield definition for register: SINP_ACC */
2223 /*
2224  * SINP_ACC (RO)
2225  *
2226  * positive SIN value acc in one period, updated when calculated SIN from pos to neg.
2227  * each SIN value is 16bit unsinged value(0x8000 for SIN30(0.5) )
2228  */
2229 #define QEIV2_SINP_ACC_SINP_ACC_MASK (0xFFFFFFFFUL)
2230 #define QEIV2_SINP_ACC_SINP_ACC_SHIFT (0U)
2231 #define QEIV2_SINP_ACC_SINP_ACC_GET(x) (((uint32_t)(x) & QEIV2_SINP_ACC_SINP_ACC_MASK) >> QEIV2_SINP_ACC_SINP_ACC_SHIFT)
2232 
2233 /* Bitfield definition for register: SINN_ACC */
2234 /*
2235  * SINN_ACC (RO)
2236  *
2237  * negative SIN value acc in one period, updated when calculated SIN from neg to pos
2238  * each SIN value is 16bit unsinged value(0x8000 for SIN330(-0.5) )
2239  */
2240 #define QEIV2_SINN_ACC_SINN_ACC_MASK (0xFFFFFFFFUL)
2241 #define QEIV2_SINN_ACC_SINN_ACC_SHIFT (0U)
2242 #define QEIV2_SINN_ACC_SINN_ACC_GET(x) (((uint32_t)(x) & QEIV2_SINN_ACC_SINN_ACC_MASK) >> QEIV2_SINN_ACC_SINN_ACC_SHIFT)
2243 
2244 /* Bitfield definition for register: COSP_ACC */
2245 /*
2246  * COSP_ACC (RO)
2247  *
2248  * positive COS value acc in one period, updated when calculated COS from pos to neg
2249  */
2250 #define QEIV2_COSP_ACC_COSP_ACC_MASK (0xFFFFFFFFUL)
2251 #define QEIV2_COSP_ACC_COSP_ACC_SHIFT (0U)
2252 #define QEIV2_COSP_ACC_COSP_ACC_GET(x) (((uint32_t)(x) & QEIV2_COSP_ACC_COSP_ACC_MASK) >> QEIV2_COSP_ACC_COSP_ACC_SHIFT)
2253 
2254 /* Bitfield definition for register: COSN_ACC */
2255 /*
2256  * COSN_ACC (RO)
2257  *
2258  * negative COS value acc in one period, updated when calculated COS from neg to pos
2259  */
2260 #define QEIV2_COSN_ACC_COSN_ACC_MASK (0xFFFFFFFFUL)
2261 #define QEIV2_COSN_ACC_COSN_ACC_SHIFT (0U)
2262 #define QEIV2_COSN_ACC_COSN_ACC_GET(x) (((uint32_t)(x) & QEIV2_COSN_ACC_COSN_ACC_MASK) >> QEIV2_COSN_ACC_COSN_ACC_SHIFT)
2263 
2264 
2265 
2266 /* COUNT register group index macro definition */
2267 #define QEIV2_COUNT_CURRENT (0UL)
2268 #define QEIV2_COUNT_READ (1UL)
2269 #define QEIV2_COUNT_SNAP0 (2UL)
2270 #define QEIV2_COUNT_SNAP1 (3UL)
2271 
2272 /* FILT_CFG register group index macro definition */
2273 #define QEIV2_FILT_CFG_FILT_CFG_A (0UL)
2274 #define QEIV2_FILT_CFG_FILT_CFG_B (1UL)
2275 #define QEIV2_FILT_CFG_FILT_CFG_Z (2UL)
2276 #define QEIV2_FILT_CFG_FILT_CFG_H (3UL)
2277 #define QEIV2_FILT_CFG_FILT_CFG_H2 (4UL)
2278 #define QEIV2_FILT_CFG_FILT_CFG_F (5UL)
2279 
2280 /* UVW_POS register group index macro definition */
2281 #define QEIV2_UVW_POS_UVW_POS0 (0UL)
2282 #define QEIV2_UVW_POS_UVW_POS1 (1UL)
2283 #define QEIV2_UVW_POS_UVW_POS2 (2UL)
2284 #define QEIV2_UVW_POS_UVW_POS3 (3UL)
2285 #define QEIV2_UVW_POS_UVW_POS4 (4UL)
2286 #define QEIV2_UVW_POS_UVW_POS5 (5UL)
2287 
2288 /* UVW_POS_CFG register group index macro definition */
2289 #define QEIV2_UVW_POS_CFG_UVW_POS0_CFG (0UL)
2290 #define QEIV2_UVW_POS_CFG_UVW_POS1_CFG (1UL)
2291 #define QEIV2_UVW_POS_CFG_UVW_POS2_CFG (2UL)
2292 #define QEIV2_UVW_POS_CFG_UVW_POS3_CFG (3UL)
2293 #define QEIV2_UVW_POS_CFG_UVW_POS4_CFG (4UL)
2294 #define QEIV2_UVW_POS_CFG_UVW_POS5_CFG (5UL)
2295 
2296 
2297 #endif /* HPM_QEIV2_H */
QEIV2_Type
Definition: hpm_qeiv2_regs.h:12