HPM SDK
HPMicro Software Development Kit
Data Fields
QEIV2_Type Struct Reference

#include <hpm_qeiv2_regs.h>

Data Fields

__RW uint32_t CR
 
__RW uint32_t PHCFG
 
__RW uint32_t WDGCFG
 
__RW uint32_t PHIDX
 
__RW uint32_t TRGOEN
 
__RW uint32_t READEN
 
__RW uint32_t ZCMP
 
__RW uint32_t PHCMP
 
__RW uint32_t SPDCMP
 
__RW uint32_t DMAEN
 
__RW uint32_t SR
 
__RW uint32_t IRQEN
 
struct {
   __RW uint32_t   Z
 
   __R uint32_t   PH
 
   __RW uint32_t   SPD
 
   __R uint32_t   TMR
 
} COUNT [4]
 
__R uint8_t RESERVED0 [16]
 
__RW uint32_t ZCMP2
 
__RW uint32_t PHCMP2
 
__RW uint32_t SPDCMP2
 
__RW uint32_t MATCH_CFG
 
__RW uint32_t FILT_CFG [6]
 
__R uint8_t RESERVED1 [88]
 
__RW uint32_t QEI_CFG
 
__R uint8_t RESERVED2 [12]
 
__RW uint32_t PULSE0_NUM
 
__RW uint32_t PULSE1_NUM
 
__R uint32_t CYCLE0_CNT
 
__R uint32_t CYCLE0PULSE_CNT
 
__R uint32_t CYCLE1_CNT
 
__R uint32_t CYCLE1PULSE_CNT
 
__R uint32_t CYCLE0_SNAP0
 
__R uint32_t CYCLE0_SNAP1
 
__R uint32_t CYCLE1_SNAP0
 
__R uint32_t CYCLE1_SNAP1
 
__R uint8_t RESERVED3 [8]
 
__RW uint32_t CYCLE0_NUM
 
__RW uint32_t CYCLE1_NUM
 
__R uint32_t PULSE0_CNT
 
__R uint32_t PULSE0CYCLE_CNT
 
__R uint32_t PULSE1_CNT
 
__R uint32_t PULSE1CYCLE_CNT
 
__R uint32_t PULSE0_SNAP0
 
__R uint32_t PULSE0CYCLE_SNAP0
 
__R uint32_t PULSE0_SNAP1
 
__R uint32_t PULSE0CYCLE_SNAP1
 
__R uint32_t PULSE1_SNAP0
 
__R uint32_t PULSE1CYCLE_SNAP0
 
__R uint32_t PULSE1_SNAP1
 
__R uint32_t PULSE1CYCLE_SNAP1
 
__R uint8_t RESERVED4 [136]
 
__RW uint32_t ADCX_CFG0
 
__RW uint32_t ADCX_CFG1
 
__RW uint32_t ADCX_CFG2
 
__R uint8_t RESERVED5 [4]
 
__RW uint32_t ADCY_CFG0
 
__RW uint32_t ADCY_CFG1
 
__RW uint32_t ADCY_CFG2
 
__R uint8_t RESERVED6 [4]
 
__RW uint32_t CAL_CFG
 
__R uint8_t RESERVED7 [12]
 
__RW uint32_t PHASE_PARAM
 
__R uint8_t RESERVED8 [4]
 
__RW uint32_t POS_THRESHOLD
 
__R uint8_t RESERVED9 [4]
 
__RW uint32_t UVW_POS [6]
 
__RW uint32_t UVW_POS_CFG [6]
 
__R uint8_t RESERVED10 [16]
 
__RW uint32_t PHASE_CNT
 
__W uint32_t PHASE_UPDATE
 
__RW uint32_t POSITION
 
__W uint32_t POSITION_UPDATE
 
__R uint32_t ANGLE
 
__RW uint32_t POS_TIMEOUT
 
struct {
   __RW uint32_t   Z
 
   __R uint32_t   PH
 
   __RW uint32_t   SPD
 
   __R uint32_t   TMR
 
} COUNT [4]
 
__R uint32_t TIMESTAMP
 
__RW uint32_t ADC_THRESHOLD
 
__RW uint32_t ADCX_VAL_SW
 
__RW uint32_t ADCY_VAL_SW
 
__RW uint32_t ADC_INJECT_CTRL
 
__RW uint32_t POS_ADJ
 
__R uint32_t CALC_STATE
 
__R uint8_t RESERVED11 [28]
 
__RW uint32_t TOGI_CFG0
 
__RW uint32_t TOGI_CFG1
 
__R uint8_t RESERVED12 [8]
 
__R uint32_t SINP_ACC
 
__R uint32_t SINN_ACC
 
__R uint32_t COSP_ACC
 
__R uint32_t COSN_ACC
 
struct {
   __RW uint32_t   Z
 
   __R uint32_t   PH
 
   __RW uint32_t   SPD
 
   __R uint32_t   TMR
 
} COUNT [4]
 
struct {
   __RW uint32_t   Z
 
   __R uint32_t   PH
 
   __RW uint32_t   SPD
 
   __R uint32_t   TMR
 
} COUNT [4]
 
__R uint8_t RESERVED13 [40]
 
__R uint8_t RESERVED14 [8]
 

Field Documentation

◆ ADC_INJECT_CTRL

__RW uint32_t QEIV2_Type::ADC_INJECT_CTRL

◆ ADC_THRESHOLD

__RW uint32_t QEIV2_Type::ADC_THRESHOLD

◆ ADCX_CFG0

__RW uint32_t QEIV2_Type::ADCX_CFG0

◆ ADCX_CFG1

__RW uint32_t QEIV2_Type::ADCX_CFG1

◆ ADCX_CFG2

__RW uint32_t QEIV2_Type::ADCX_CFG2

◆ ADCX_VAL_SW

__RW uint32_t QEIV2_Type::ADCX_VAL_SW

◆ ADCY_CFG0

__RW uint32_t QEIV2_Type::ADCY_CFG0

◆ ADCY_CFG1

__RW uint32_t QEIV2_Type::ADCY_CFG1

◆ ADCY_CFG2

__RW uint32_t QEIV2_Type::ADCY_CFG2

◆ ADCY_VAL_SW

__RW uint32_t QEIV2_Type::ADCY_VAL_SW

◆ ANGLE

__R uint32_t QEIV2_Type::ANGLE

◆ CAL_CFG

__RW uint32_t QEIV2_Type::CAL_CFG

◆ CALC_STATE

__R uint32_t QEIV2_Type::CALC_STATE

◆ COSN_ACC

__R uint32_t QEIV2_Type::COSN_ACC

◆ COSP_ACC

__R uint32_t QEIV2_Type::COSP_ACC

◆  [1/4]

struct { ... } QEIV2_Type::COUNT[4]

◆  [2/4]

struct { ... } QEIV2_Type::COUNT[4]

◆  [3/4]

struct { ... } QEIV2_Type::COUNT[4]

◆  [4/4]

struct { ... } QEIV2_Type::COUNT[4]

◆ CR

__RW uint32_t QEIV2_Type::CR

◆ CYCLE0_CNT

__R uint32_t QEIV2_Type::CYCLE0_CNT

◆ CYCLE0_NUM

__RW uint32_t QEIV2_Type::CYCLE0_NUM

◆ CYCLE0_SNAP0

__R uint32_t QEIV2_Type::CYCLE0_SNAP0

◆ CYCLE0_SNAP1

__R uint32_t QEIV2_Type::CYCLE0_SNAP1

◆ CYCLE0PULSE_CNT

__R uint32_t QEIV2_Type::CYCLE0PULSE_CNT

◆ CYCLE1_CNT

__R uint32_t QEIV2_Type::CYCLE1_CNT

◆ CYCLE1_NUM

__RW uint32_t QEIV2_Type::CYCLE1_NUM

◆ CYCLE1_SNAP0

__R uint32_t QEIV2_Type::CYCLE1_SNAP0

◆ CYCLE1_SNAP1

__R uint32_t QEIV2_Type::CYCLE1_SNAP1

◆ CYCLE1PULSE_CNT

__R uint32_t QEIV2_Type::CYCLE1PULSE_CNT

◆ DMAEN

__RW uint32_t QEIV2_Type::DMAEN

◆ FILT_CFG

__RW uint32_t QEIV2_Type::FILT_CFG

◆ IRQEN

__RW uint32_t QEIV2_Type::IRQEN

◆ MATCH_CFG

__RW uint32_t QEIV2_Type::MATCH_CFG

◆ PH

__R uint32_t QEIV2_Type::PH

◆ PHASE_CNT

__RW uint32_t QEIV2_Type::PHASE_CNT

◆ PHASE_PARAM

__RW uint32_t QEIV2_Type::PHASE_PARAM

◆ PHASE_UPDATE

__W uint32_t QEIV2_Type::PHASE_UPDATE

◆ PHCFG

__RW uint32_t QEIV2_Type::PHCFG

◆ PHCMP

__RW uint32_t QEIV2_Type::PHCMP

◆ PHCMP2

__RW uint32_t QEIV2_Type::PHCMP2

◆ PHIDX

__RW uint32_t QEIV2_Type::PHIDX

◆ POS_ADJ

__RW uint32_t QEIV2_Type::POS_ADJ

◆ POS_THRESHOLD

__RW uint32_t QEIV2_Type::POS_THRESHOLD

◆ POS_TIMEOUT

__RW uint32_t QEIV2_Type::POS_TIMEOUT

◆ POSITION

__RW uint32_t QEIV2_Type::POSITION

◆ POSITION_UPDATE

__W uint32_t QEIV2_Type::POSITION_UPDATE

◆ PULSE0_CNT

__R uint32_t QEIV2_Type::PULSE0_CNT

◆ PULSE0_NUM

__RW uint32_t QEIV2_Type::PULSE0_NUM

◆ PULSE0_SNAP0

__R uint32_t QEIV2_Type::PULSE0_SNAP0

◆ PULSE0_SNAP1

__R uint32_t QEIV2_Type::PULSE0_SNAP1

◆ PULSE0CYCLE_CNT

__R uint32_t QEIV2_Type::PULSE0CYCLE_CNT

◆ PULSE0CYCLE_SNAP0

__R uint32_t QEIV2_Type::PULSE0CYCLE_SNAP0

◆ PULSE0CYCLE_SNAP1

__R uint32_t QEIV2_Type::PULSE0CYCLE_SNAP1

◆ PULSE1_CNT

__R uint32_t QEIV2_Type::PULSE1_CNT

◆ PULSE1_NUM

__RW uint32_t QEIV2_Type::PULSE1_NUM

◆ PULSE1_SNAP0

__R uint32_t QEIV2_Type::PULSE1_SNAP0

◆ PULSE1_SNAP1

__R uint32_t QEIV2_Type::PULSE1_SNAP1

◆ PULSE1CYCLE_CNT

__R uint32_t QEIV2_Type::PULSE1CYCLE_CNT

◆ PULSE1CYCLE_SNAP0

__R uint32_t QEIV2_Type::PULSE1CYCLE_SNAP0

◆ PULSE1CYCLE_SNAP1

__R uint32_t QEIV2_Type::PULSE1CYCLE_SNAP1

◆ QEI_CFG

__RW uint32_t QEIV2_Type::QEI_CFG

◆ READEN

__RW uint32_t QEIV2_Type::READEN

◆ RESERVED0

__R uint8_t QEIV2_Type::RESERVED0

◆ RESERVED1

__R uint8_t QEIV2_Type::RESERVED1

◆ RESERVED10

__R uint8_t QEIV2_Type::RESERVED10

◆ RESERVED11

__R uint8_t QEIV2_Type::RESERVED11

◆ RESERVED12

__R uint8_t QEIV2_Type::RESERVED12

◆ RESERVED13

__R uint8_t QEIV2_Type::RESERVED13[40]

◆ RESERVED14

__R uint8_t QEIV2_Type::RESERVED14[8]

◆ RESERVED2

__R uint8_t QEIV2_Type::RESERVED2

◆ RESERVED3

__R uint8_t QEIV2_Type::RESERVED3

◆ RESERVED4

__R uint8_t QEIV2_Type::RESERVED4

◆ RESERVED5

__R uint8_t QEIV2_Type::RESERVED5

◆ RESERVED6

__R uint8_t QEIV2_Type::RESERVED6

◆ RESERVED7

__R uint8_t QEIV2_Type::RESERVED7

◆ RESERVED8

__R uint8_t QEIV2_Type::RESERVED8

◆ RESERVED9

__R uint8_t QEIV2_Type::RESERVED9

◆ SINN_ACC

__R uint32_t QEIV2_Type::SINN_ACC

◆ SINP_ACC

__R uint32_t QEIV2_Type::SINP_ACC

◆ SPD

__RW uint32_t QEIV2_Type::SPD

◆ SPDCMP

__RW uint32_t QEIV2_Type::SPDCMP

◆ SPDCMP2

__RW uint32_t QEIV2_Type::SPDCMP2

◆ SR

__RW uint32_t QEIV2_Type::SR

◆ TIMESTAMP

__R uint32_t QEIV2_Type::TIMESTAMP

◆ TMR

__R uint32_t QEIV2_Type::TMR

◆ TOGI_CFG0

__RW uint32_t QEIV2_Type::TOGI_CFG0

◆ TOGI_CFG1

__RW uint32_t QEIV2_Type::TOGI_CFG1

◆ TRGOEN

__RW uint32_t QEIV2_Type::TRGOEN

◆ UVW_POS

__RW uint32_t QEIV2_Type::UVW_POS

◆ UVW_POS_CFG

__RW uint32_t QEIV2_Type::UVW_POS_CFG

◆ WDGCFG

__RW uint32_t QEIV2_Type::WDGCFG

◆ Z

__RW uint32_t QEIV2_Type::Z

◆ ZCMP

__RW uint32_t QEIV2_Type::ZCMP

◆ ZCMP2

__RW uint32_t QEIV2_Type::ZCMP2
The documentation for this struct was generated from the following file: