HPM SDK
HPMicro Software Development Kit
hpm_qeov2_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_QEOV2_H
10 #define HPM_QEOV2_H
11 
12 typedef struct {
13  struct {
14  __RW uint32_t MODE; /* 0x0: analog waves mode */
15  __RW uint32_t RESOLUTION; /* 0x4: resolution of wave0/1/2 */
16  __RW uint32_t PHASE_SHIFT[3]; /* 0x8 - 0x10: wave0 phase shifter */
17  __RW uint32_t VD_INJECT; /* 0x14: wave vd inject value */
18  __R uint8_t RESERVED0[8]; /* 0x18 - 0x1F: Reserved */
19  __RW uint32_t VQ_INJECT; /* 0x20: wave vq inject value */
20  __R uint8_t RESERVED1[8]; /* 0x24 - 0x2B: Reserved */
21  __W uint32_t VD_VQ_LOAD; /* 0x2C: load wave0/1/2 vd vq value */
22  __RW uint32_t AMPLITUDE[3]; /* 0x30 - 0x38: wave0 amplitude */
23  __RW uint32_t MID_POINT[3]; /* 0x3C - 0x44: wave0 output middle point offset */
24  struct {
25  __RW uint32_t MIN_LEVEL0; /* 0x48: wave0 low area limit value */
26  __RW uint32_t MAX_LEVEL0; /* 0x4C: wave0 high area limit value */
27  } LIMIT0[3];
28  struct {
29  __RW uint32_t MIN_LEVEL1; /* 0x60: wave0 low area limit value level1 */
30  __RW uint32_t MAX_LEVEL1; /* 0x64: wave0 high area limit value level1 */
31  } LIMIT1[3];
32  __RW uint32_t DEADZONE_SHIFT[3]; /* 0x78 - 0x80: deadzone_shifter_wave0 */
33  __RW uint32_t PWM_CYCLE; /* 0x84: pwm_cycle */
34  __RW uint32_t FILTER; /* 0x88: wave input position filter */
35  } WAVE;
36  __R uint8_t RESERVED0[116]; /* 0x8C - 0xFF: Reserved */
37  struct {
38  __RW uint32_t MODE; /* 0x100: wave_a/b/z output mode */
39  __RW uint32_t RESOLUTION; /* 0x104: resolution of wave_a/b/z */
40  __RW uint32_t PHASE_SHIFT[3]; /* 0x108 - 0x110: wave_a phase shifter */
41  __RW uint32_t LINE_WIDTH; /* 0x114: Two-phase orthogonality wave 1/4 period */
42  __RW uint32_t WDOG_WIDTH; /* 0x118: wdog width of qeo */
43  __W uint32_t POSTION_SYNC; /* 0x11C: sync abz owned postion */
44  __RW uint32_t OVERALL_OFFSET; /* 0x120: abz overall position offset */
45  __RW uint32_t Z_START; /* 0x124: zero phase start line num */
46  __RW uint32_t Z_END; /* 0x128: zero phase end line num */
47  __RW uint32_t Z_OFFSET; /* 0x12C: zero phase start and end 1/4 line num */
48  __RW uint32_t Z_PULSE_WIDTH; /* 0x130: zero pulse witdth */
49  __RW uint32_t FILTER; /* 0x134: abz input position filter */
50  } ABZ;
51  __R uint8_t RESERVED1[8]; /* 0x138 - 0x13F: Reserved */
52  struct {
53  __RW uint32_t MODE; /* 0x140: pwm mode */
54  __RW uint32_t RESOLUTION; /* 0x144: resolution of pwm */
55  __RW uint32_t PHASE_SHIFT[4]; /* 0x148 - 0x154: pwm_a phase shifter */
56  __RW uint32_t PHASE_TABLE[24]; /* 0x158 - 0x1B4: pwm_phase_table 0 */
57  __RW uint32_t FILTER; /* 0x1B8: pwm input position filter */
58  } PWM;
59  __R uint8_t RESERVED2[60]; /* 0x1BC - 0x1F7: Reserved */
60  __RW uint32_t POSTION_SOFTWARE; /* 0x1F8: softwave inject postion */
61  __RW uint32_t POSTION_SEL; /* 0x1FC: select softwave inject postion */
62  __R uint32_t STATUS; /* 0x200: qeo status */
63  __R uint32_t DEBUG0; /* 0x204: qeo debug 0 */
64  __R uint32_t DEBUG1; /* 0x208: qeo debug 1 */
65  __R uint32_t DEBUG2; /* 0x20C: qeo debug 2 */
66  __R uint32_t DEBUG3; /* 0x210: qeo debug 3 */
67  __R uint32_t DEBUG4; /* 0x214: qeo debug 4 */
68  __R uint32_t DEBUG5; /* 0x218: qeo debug 5 */
69 } QEOV2_Type;
70 
71 
72 /* Bitfield definition for register of struct WAVE: MODE */
73 /*
74  * WAVE2_ABOVE_MAX_LIMIT (RW)
75  *
76  * wave2 above max limit mode.
77  * 0: output all bits are 1.
78  * 1: output 0x0.
79  * 2: output as level_max_limit2.level0_max_limit
80  */
81 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK (0xC0000000UL)
82 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT (30U)
83 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK)
84 #define QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_ABOVE_MAX_LIMIT_SHIFT)
85 
86 /*
87  * WAVE2_HIGH_AREA1_LIMIT (RW)
88  *
89  * wave2 high area1 limit mode.
90  * 0: output all bits are 1.
91  * 1: output as level_max_limit2.level0_max_limit
92  */
93 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK (0x20000000UL)
94 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT (29U)
95 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK)
96 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA1_LIMIT_SHIFT)
97 
98 /*
99  * WAVE2_HIGH_AREA0_LIMIT (RW)
100  *
101  * wave2 high area0 limit mode.
102  * 0: output all bits are 1.
103  * 1: output as level_max_limit2.level0_max_limit
104  */
105 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK (0x10000000UL)
106 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT (28U)
107 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK)
108 #define QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_HIGH_AREA0_LIMIT_SHIFT)
109 
110 /*
111  * WAVE2_LOW_AREA1_LIMIT (RW)
112  *
113  * wave2 low area1 limit mode.
114  * 0: output 0.
115  * 1: output as level_min_limit2.level1_min_limit
116  */
117 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK (0x8000000UL)
118 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT (27U)
119 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK)
120 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA1_LIMIT_SHIFT)
121 
122 /*
123  * WAVE2_LOW_AREA0_LIMIT (RW)
124  *
125  * wave2 low area0 limit mode.
126  * 0: output 0.
127  * 1: output as level_min_limit2.level1_min_limit
128  */
129 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK (0x4000000UL)
130 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT (26U)
131 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK)
132 #define QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_LOW_AREA0_LIMIT_SHIFT)
133 
134 /*
135  * WAVE2_BELOW_MIN_LIMIT (RW)
136  *
137  * wave2 below min limit mode.
138  * 0: output 0.
139  * 1: output all bits are 1.
140  * 2: output as level_min_limit2.level1_min_limit
141  */
142 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK (0x3000000UL)
143 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT (24U)
144 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK)
145 #define QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE2_BELOW_MIN_LIMIT_SHIFT)
146 
147 /*
148  * WAVE1_ABOVE_MAX_LIMIT (RW)
149  *
150  * wave1 above max limit mode.
151  * 0: output all bits are 1.
152  * 1: output 0x0.
153  * 2: output as level_max_limit1.level0_max_limit
154  */
155 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK (0xC00000UL)
156 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT (22U)
157 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK)
158 #define QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_ABOVE_MAX_LIMIT_SHIFT)
159 
160 /*
161  * WAVE1_HIGH_AREA1_LIMIT (RW)
162  *
163  * wave1 high area1 limit mode.
164  * 0: output all bits are 1.
165  * 1: output as level_max_limit1.level0_max_limit
166  */
167 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK (0x200000UL)
168 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT (21U)
169 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK)
170 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA1_LIMIT_SHIFT)
171 
172 /*
173  * WAVE1_HIGH_AREA0_LIMIT (RW)
174  *
175  * wave1 high area0 limit mode.
176  * 0: output all bits are 1.
177  * 1: output as level_max_limit1.level0_max_limit
178  */
179 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK (0x100000UL)
180 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT (20U)
181 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK)
182 #define QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_HIGH_AREA0_LIMIT_SHIFT)
183 
184 /*
185  * WAVE1_LOW_AREA1_LIMIT (RW)
186  *
187  * wave1 low area1 limit mode.
188  * 0: output 0.
189  * 1: output as level_min_limit1.level1_min_limit
190  */
191 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK (0x80000UL)
192 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT (19U)
193 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK)
194 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA1_LIMIT_SHIFT)
195 
196 /*
197  * WAVE1_LOW_AREA0_LIMIT (RW)
198  *
199  * wave1 low area0 limit mode.
200  * 0: output 0.
201  * 1: output as level_min_limit1.level1_min_limit
202  */
203 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK (0x40000UL)
204 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT (18U)
205 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK)
206 #define QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_LOW_AREA0_LIMIT_SHIFT)
207 
208 /*
209  * WAVE1_BELOW_MIN_LIMIT (RW)
210  *
211  * wave1 below min limit mode.
212  * 0: output 0.
213  * 1: output all bits are 1.
214  * 2: output as level_min_limit1.level1_min_limit
215  */
216 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK (0x30000UL)
217 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT (16U)
218 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK)
219 #define QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE1_BELOW_MIN_LIMIT_SHIFT)
220 
221 /*
222  * WAVE0_ABOVE_MAX_LIMIT (RW)
223  *
224  * wave0 above max limit mode.
225  * 0: output all bits are 1.
226  * 1: output 0x0.
227  * 2: output as level_max_limit0.level0_max_limit
228  */
229 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK (0xC000U)
230 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT (14U)
231 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK)
232 #define QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_ABOVE_MAX_LIMIT_SHIFT)
233 
234 /*
235  * WAVE0_HIGH_AREA1_LIMIT (RW)
236  *
237  * wave0 high area1 limit mode.
238  * 0: output all bits are 1.
239  * 1: output as level_max_limit0.level0_max_limit
240  */
241 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK (0x2000U)
242 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT (13U)
243 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK)
244 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA1_LIMIT_SHIFT)
245 
246 /*
247  * WAVE0_HIGH_AREA0_LIMIT (RW)
248  *
249  * wave0 high area0 limit mode.
250  * 0: output all bits are 1.
251  * 1: output as level_max_limit0.level0_max_limit
252  */
253 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK (0x1000U)
254 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT (12U)
255 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK)
256 #define QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_HIGH_AREA0_LIMIT_SHIFT)
257 
258 /*
259  * WAVE0_LOW_AREA1_LIMIT (RW)
260  *
261  * wave0 low area1 limit mode.
262  * 0: output 0.
263  * 1: output as level_min_limit0.level1_min_limit
264  */
265 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK (0x800U)
266 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT (11U)
267 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK)
268 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA1_LIMIT_SHIFT)
269 
270 /*
271  * WAVE0_LOW_AREA0_LIMIT (RW)
272  *
273  * wave0 low area0 limit mode.
274  * 0: output 0.
275  * 1: output as level_min_limit0.level1_min_limit
276  */
277 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK (0x400U)
278 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT (10U)
279 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK)
280 #define QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_LOW_AREA0_LIMIT_SHIFT)
281 
282 /*
283  * WAVE0_BELOW_MIN_LIMIT (RW)
284  *
285  * wave0 below min limit mode.
286  * 0: output 0.
287  * 1: output all bits are 1.
288  * 2: output as level_min_limit0.level1_min_limit
289  */
290 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK (0x300U)
291 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT (8U)
292 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK)
293 #define QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_MASK) >> QEOV2_WAVE_MODE_WAVE0_BELOW_MIN_LIMIT_SHIFT)
294 
295 /*
296  * SADDLE_TYPE (RW)
297  *
298  * saddle type seclect;
299  * 0:standard saddle.
300  * 1: triple-cos saddle.
301  */
302 #define QEOV2_WAVE_MODE_SADDLE_TYPE_MASK (0x80U)
303 #define QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT (7U)
304 #define QEOV2_WAVE_MODE_SADDLE_TYPE_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK)
305 #define QEOV2_WAVE_MODE_SADDLE_TYPE_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_SADDLE_TYPE_MASK) >> QEOV2_WAVE_MODE_SADDLE_TYPE_SHIFT)
306 
307 /*
308  * ENABLE_DQ_VALID (RW)
309  *
310  * enable vd or vq valid to trigger analog wave calcuation
311  * 0: disable.
312  * 1: enable.
313  */
314 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK (0x40U)
315 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT (6U)
316 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK)
317 #define QEOV2_WAVE_MODE_ENABLE_DQ_VALID_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_DQ_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_DQ_VALID_SHIFT)
318 
319 /*
320  * ENABLE_POS_VALID (RW)
321  *
322  * enable position valid to trigger analog wave calcuation
323  * 0: disable.
324  * 1: enable.
325  */
326 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK (0x20U)
327 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT (5U)
328 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK)
329 #define QEOV2_WAVE_MODE_ENABLE_POS_VALID_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_ENABLE_POS_VALID_MASK) >> QEOV2_WAVE_MODE_ENABLE_POS_VALID_SHIFT)
330 
331 /*
332  * EN_WAVE_VD_VQ_INJECT (RW)
333  *
334  * wave VdVq inject enable.
335  * 0: disable VdVq inject.
336  * 1: enable VdVq inject.
337  */
338 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK (0x10U)
339 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT (4U)
340 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK)
341 #define QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_MASK) >> QEOV2_WAVE_MODE_EN_WAVE_VD_VQ_INJECT_SHIFT)
342 
343 /*
344  * VD_VQ_SEL (RW)
345  *
346  * vd_vq sel ctrl:
347  * 0: from CLC.
348  * 1: from software.
349  */
350 #define QEOV2_WAVE_MODE_VD_VQ_SEL_MASK (0x4U)
351 #define QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT (2U)
352 #define QEOV2_WAVE_MODE_VD_VQ_SEL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK)
353 #define QEOV2_WAVE_MODE_VD_VQ_SEL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_VD_VQ_SEL_MASK) >> QEOV2_WAVE_MODE_VD_VQ_SEL_SHIFT)
354 
355 /*
356  * WAVES_OUTPUT_TYPE (RW)
357  *
358  * wave0/1/2 output mode.
359  * 0: cosine wave.
360  * 1: saddle wave.
361  * 2. abs cosine wave.
362  * 3. saw wave
363  */
364 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK (0x3U)
365 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT (0U)
366 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK)
367 #define QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_MASK) >> QEOV2_WAVE_MODE_WAVES_OUTPUT_TYPE_SHIFT)
368 
369 /* Bitfield definition for register of struct WAVE: RESOLUTION */
370 /*
371  * LINES (RW)
372  *
373  * wave0/1/2 resolution
374  */
375 #define QEOV2_WAVE_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
376 #define QEOV2_WAVE_RESOLUTION_LINES_SHIFT (0U)
377 #define QEOV2_WAVE_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_WAVE_RESOLUTION_LINES_SHIFT) & QEOV2_WAVE_RESOLUTION_LINES_MASK)
378 #define QEOV2_WAVE_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_WAVE_RESOLUTION_LINES_MASK) >> QEOV2_WAVE_RESOLUTION_LINES_SHIFT)
379 
380 /* Bitfield definition for register of struct WAVE: WAVE0 */
381 /*
382  * VAL (RW)
383  *
384  * wave0 phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period
385  */
386 #define QEOV2_WAVE_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
387 #define QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT (0U)
388 #define QEOV2_WAVE_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK)
389 #define QEOV2_WAVE_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_PHASE_SHIFT_VAL_MASK) >> QEOV2_WAVE_PHASE_SHIFT_VAL_SHIFT)
390 
391 /* Bitfield definition for register of struct WAVE: VD_INJECT */
392 /*
393  * VD_VAL (RW)
394  *
395  * Vd inject value
396  */
397 #define QEOV2_WAVE_VD_INJECT_VD_VAL_MASK (0xFFFFFFFFUL)
398 #define QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT (0U)
399 #define QEOV2_WAVE_VD_INJECT_VD_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK)
400 #define QEOV2_WAVE_VD_INJECT_VD_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VD_INJECT_VD_VAL_MASK) >> QEOV2_WAVE_VD_INJECT_VD_VAL_SHIFT)
401 
402 /* Bitfield definition for register of struct WAVE: VQ_INJECT */
403 /*
404  * VQ_VAL (RW)
405  *
406  * Vq inject value
407  */
408 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK (0xFFFFFFFFUL)
409 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT (0U)
410 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK)
411 #define QEOV2_WAVE_VQ_INJECT_VQ_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VQ_INJECT_VQ_VAL_MASK) >> QEOV2_WAVE_VQ_INJECT_VQ_VAL_SHIFT)
412 
413 /* Bitfield definition for register of struct WAVE: VD_VQ_LOAD */
414 /*
415  * LOAD (WO)
416  *
417  * load wave0/1/2 vd vq value. always read 0
418  * 0: vd vq keep previous value.
419  * 1: load wave0/1/2 vd vq value at sametime.
420  */
421 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK (0x1U)
422 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT (0U)
423 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_SET(x) (((uint32_t)(x) << QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK)
424 #define QEOV2_WAVE_VD_VQ_LOAD_LOAD_GET(x) (((uint32_t)(x) & QEOV2_WAVE_VD_VQ_LOAD_LOAD_MASK) >> QEOV2_WAVE_VD_VQ_LOAD_LOAD_SHIFT)
425 
426 /* Bitfield definition for register of struct WAVE: WAVE0 */
427 /*
428  * EN_SCAL (RW)
429  *
430  * enable wave amplitude scaling. 0: disable; 1: enable
431  */
432 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK (0x10000UL)
433 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT (16U)
434 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK)
435 #define QEOV2_WAVE_AMPLITUDE_EN_SCAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_EN_SCAL_MASK) >> QEOV2_WAVE_AMPLITUDE_EN_SCAL_SHIFT)
436 
437 /*
438  * AMP_VAL (RW)
439  *
440  * amplitude scaling value. bit15-12 are integer part value. bit11-0 are fraction value.
441  */
442 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK (0xFFFFU)
443 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT (0U)
444 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK)
445 #define QEOV2_WAVE_AMPLITUDE_AMP_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_AMPLITUDE_AMP_VAL_MASK) >> QEOV2_WAVE_AMPLITUDE_AMP_VAL_SHIFT)
446 
447 /* Bitfield definition for register of struct WAVE: WAVE0 */
448 /*
449  * VAL (RW)
450  *
451  * wave0 output middle point, use this value as 32 bit signed value. bit 31 is signed bit. bit30-27 is integer part value. bit26-0 is fraction value.
452  */
453 #define QEOV2_WAVE_MID_POINT_VAL_MASK (0xFFFFFFFFUL)
454 #define QEOV2_WAVE_MID_POINT_VAL_SHIFT (0U)
455 #define QEOV2_WAVE_MID_POINT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_MID_POINT_VAL_SHIFT) & QEOV2_WAVE_MID_POINT_VAL_MASK)
456 #define QEOV2_WAVE_MID_POINT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_MID_POINT_VAL_MASK) >> QEOV2_WAVE_MID_POINT_VAL_SHIFT)
457 
458 /* Bitfield definition for register of struct WAVE: MIN_LEVEL0 */
459 /*
460  * LIMIT_LEVEL0 (RW)
461  *
462  * low area limit level0
463  */
464 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL)
465 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT (0U)
466 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK)
467 #define QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MIN_LEVEL0_LIMIT_LEVEL0_SHIFT)
468 
469 /* Bitfield definition for register of struct WAVE: MAX_LEVEL0 */
470 /*
471  * LIMIT_LEVEL0 (RW)
472  *
473  * high area limit level0
474  */
475 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK (0xFFFFFFFFUL)
476 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT (0U)
477 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK)
478 #define QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_MASK) >> QEOV2_WAVE_LIMIT0_MAX_LEVEL0_LIMIT_LEVEL0_SHIFT)
479 
480 /* Bitfield definition for register of struct WAVE: MIN_LEVEL1 */
481 /*
482  * LIMIT_LEVEL1 (RW)
483  *
484  * low area limit level1
485  */
486 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL)
487 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT (0U)
488 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK)
489 #define QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MIN_LEVEL1_LIMIT_LEVEL1_SHIFT)
490 
491 /* Bitfield definition for register of struct WAVE: MAX_LEVEL1 */
492 /*
493  * LIMIT_LEVEL1 (RW)
494  *
495  * high area limit level1
496  */
497 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK (0xFFFFFFFFUL)
498 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT (0U)
499 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SET(x) (((uint32_t)(x) << QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK)
500 #define QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_GET(x) (((uint32_t)(x) & QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_MASK) >> QEOV2_WAVE_LIMIT1_MAX_LEVEL1_LIMIT_LEVEL1_SHIFT)
501 
502 /* Bitfield definition for register of struct WAVE: WAVE0 */
503 /*
504  * VAL (RW)
505  *
506  * wave0 deadzone shifter value
507  */
508 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
509 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT (0U)
510 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK)
511 #define QEOV2_WAVE_DEADZONE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_DEADZONE_SHIFT_VAL_MASK) >> QEOV2_WAVE_DEADZONE_SHIFT_VAL_SHIFT)
512 
513 /* Bitfield definition for register of struct WAVE: PWM_CYCLE */
514 /*
515  * VAL (RW)
516  *
517  * pwm_cycle
518  */
519 #define QEOV2_WAVE_PWM_CYCLE_VAL_MASK (0xFFFFFFFFUL)
520 #define QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT (0U)
521 #define QEOV2_WAVE_PWM_CYCLE_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK)
522 #define QEOV2_WAVE_PWM_CYCLE_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_PWM_CYCLE_VAL_MASK) >> QEOV2_WAVE_PWM_CYCLE_VAL_SHIFT)
523 
524 /* Bitfield definition for register of struct WAVE: FILTER */
525 /*
526  * VAL (RW)
527  *
528  * wave_filter
529  */
530 #define QEOV2_WAVE_FILTER_VAL_MASK (0xFFFFFFFFUL)
531 #define QEOV2_WAVE_FILTER_VAL_SHIFT (0U)
532 #define QEOV2_WAVE_FILTER_VAL_SET(x) (((uint32_t)(x) << QEOV2_WAVE_FILTER_VAL_SHIFT) & QEOV2_WAVE_FILTER_VAL_MASK)
533 #define QEOV2_WAVE_FILTER_VAL_GET(x) (((uint32_t)(x) & QEOV2_WAVE_FILTER_VAL_MASK) >> QEOV2_WAVE_FILTER_VAL_SHIFT)
534 
535 /* Bitfield definition for register of struct ABZ: MODE */
536 /*
537  * ABZ_OUTPUT_ENABLE (RW)
538  *
539  * abz output enable：
540  * 0：abz output disable, all keep 0
541  * 1：abz output enable.
542  */
543 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK (0x80000000UL)
544 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT (31U)
545 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK)
546 #define QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_MASK) >> QEOV2_ABZ_MODE_ABZ_OUTPUT_ENABLE_SHIFT)
547 
548 /*
549  * REVERSE_EDGE_TYPE (RW)
550  *
551  * pulse reverse wave，reverse edge point:
552  * 0: between pulse's posedge and negedge, min period dedicated by the num line_width
553  * 1: edge change point flow pulse's negedge.
554  */
555 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK (0x10000000UL)
556 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT (28U)
557 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK)
558 #define QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_MASK) >> QEOV2_ABZ_MODE_REVERSE_EDGE_TYPE_SHIFT)
559 
560 /*
561  * POSITION_SYNC_MODE (RW)
562  *
563  * position sync mode:
564  * 0: only sync integer line part into qeo own position.
565  * 1: sync integer and fraction part into qeo own position.
566  */
567 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK (0x8000000UL)
568 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT (27U)
569 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK)
570 #define QEOV2_ABZ_MODE_POSITION_SYNC_MODE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_POSITION_SYNC_MODE_MASK) >> QEOV2_ABZ_MODE_POSITION_SYNC_MODE_SHIFT)
571 
572 /*
573  * EN_WDOG (RW)
574  *
575  * enable abz wdog:
576  * 0: disable abz wdog.
577  * 1: enable abz wdog.
578  */
579 #define QEOV2_ABZ_MODE_EN_WDOG_MASK (0x1000000UL)
580 #define QEOV2_ABZ_MODE_EN_WDOG_SHIFT (24U)
581 #define QEOV2_ABZ_MODE_EN_WDOG_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_EN_WDOG_SHIFT) & QEOV2_ABZ_MODE_EN_WDOG_MASK)
582 #define QEOV2_ABZ_MODE_EN_WDOG_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_EN_WDOG_MASK) >> QEOV2_ABZ_MODE_EN_WDOG_SHIFT)
583 
584 /*
585  * Z_POLARITY (RW)
586  *
587  * wave_z polarity.
588  * 0: normal output.
589  * 1: invert normal output
590  */
591 #define QEOV2_ABZ_MODE_Z_POLARITY_MASK (0x100000UL)
592 #define QEOV2_ABZ_MODE_Z_POLARITY_SHIFT (20U)
593 #define QEOV2_ABZ_MODE_Z_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_POLARITY_SHIFT) & QEOV2_ABZ_MODE_Z_POLARITY_MASK)
594 #define QEOV2_ABZ_MODE_Z_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_POLARITY_MASK) >> QEOV2_ABZ_MODE_Z_POLARITY_SHIFT)
595 
596 /*
597  * B_POLARITY (RW)
598  *
599  * wave_b polarity.
600  * 0: normal output.
601  * 1: invert normal output
602  */
603 #define QEOV2_ABZ_MODE_B_POLARITY_MASK (0x10000UL)
604 #define QEOV2_ABZ_MODE_B_POLARITY_SHIFT (16U)
605 #define QEOV2_ABZ_MODE_B_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_B_POLARITY_SHIFT) & QEOV2_ABZ_MODE_B_POLARITY_MASK)
606 #define QEOV2_ABZ_MODE_B_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_B_POLARITY_MASK) >> QEOV2_ABZ_MODE_B_POLARITY_SHIFT)
607 
608 /*
609  * A_POLARITY (RW)
610  *
611  * wave_a polarity.
612  * 0: normal output.
613  * 1: invert normal output
614  */
615 #define QEOV2_ABZ_MODE_A_POLARITY_MASK (0x1000U)
616 #define QEOV2_ABZ_MODE_A_POLARITY_SHIFT (12U)
617 #define QEOV2_ABZ_MODE_A_POLARITY_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_A_POLARITY_SHIFT) & QEOV2_ABZ_MODE_A_POLARITY_MASK)
618 #define QEOV2_ABZ_MODE_A_POLARITY_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_A_POLARITY_MASK) >> QEOV2_ABZ_MODE_A_POLARITY_SHIFT)
619 
620 /*
621  * Z_TYPE (RW)
622  *
623  * wave_z type:
624  * 0: zero pulse type, start and end line number decided by z_start、z_end and z_offset.
625  * 1: zero pulse type, z output start to high when position= z_start, and mantain numbers of 1/4 line cfg in z_pulse_width register
626  * 2: reserved
627  * 3: wave_z output as tree-phase wave same as wave_a/wave_b
628  */
629 #define QEOV2_ABZ_MODE_Z_TYPE_MASK (0x300U)
630 #define QEOV2_ABZ_MODE_Z_TYPE_SHIFT (8U)
631 #define QEOV2_ABZ_MODE_Z_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_Z_TYPE_SHIFT) & QEOV2_ABZ_MODE_Z_TYPE_MASK)
632 #define QEOV2_ABZ_MODE_Z_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_Z_TYPE_MASK) >> QEOV2_ABZ_MODE_Z_TYPE_SHIFT)
633 
634 /*
635  * B_TYPE (RW)
636  *
637  * wave_b type:
638  * 0: Two-phase orthogonality wave_b.
639  * 1: reverse wave of pulse/reverse type.
640  * 2: down wave of up/down type.
641  * 3: Three-phase orthogonality wave_b.
642  */
643 #define QEOV2_ABZ_MODE_B_TYPE_MASK (0x30U)
644 #define QEOV2_ABZ_MODE_B_TYPE_SHIFT (4U)
645 #define QEOV2_ABZ_MODE_B_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_B_TYPE_SHIFT) & QEOV2_ABZ_MODE_B_TYPE_MASK)
646 #define QEOV2_ABZ_MODE_B_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_B_TYPE_MASK) >> QEOV2_ABZ_MODE_B_TYPE_SHIFT)
647 
648 /*
649  * A_TYPE (RW)
650  *
651  * wave_a type:
652  * 0: Two-phase orthogonality wave_a.
653  * 1: pulse wave of pulse/reverse type.
654  * 2: up wave of up/down type.
655  * 3: Three-phase orthogonality wave_a.
656  */
657 #define QEOV2_ABZ_MODE_A_TYPE_MASK (0x3U)
658 #define QEOV2_ABZ_MODE_A_TYPE_SHIFT (0U)
659 #define QEOV2_ABZ_MODE_A_TYPE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_MODE_A_TYPE_SHIFT) & QEOV2_ABZ_MODE_A_TYPE_MASK)
660 #define QEOV2_ABZ_MODE_A_TYPE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_MODE_A_TYPE_MASK) >> QEOV2_ABZ_MODE_A_TYPE_SHIFT)
661 
662 /* Bitfield definition for register of struct ABZ: RESOLUTION */
663 /*
664  * LINES (RW)
665  *
666  * wave_a/b/z resolution
667  */
668 #define QEOV2_ABZ_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
669 #define QEOV2_ABZ_RESOLUTION_LINES_SHIFT (0U)
670 #define QEOV2_ABZ_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_ABZ_RESOLUTION_LINES_SHIFT) & QEOV2_ABZ_RESOLUTION_LINES_MASK)
671 #define QEOV2_ABZ_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_ABZ_RESOLUTION_LINES_MASK) >> QEOV2_ABZ_RESOLUTION_LINES_SHIFT)
672 
673 /* Bitfield definition for register of struct ABZ: A */
674 /*
675  * VAL (RW)
676  *
677  * wave_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period.
678  */
679 #define QEOV2_ABZ_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
680 #define QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT (0U)
681 #define QEOV2_ABZ_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK)
682 #define QEOV2_ABZ_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_PHASE_SHIFT_VAL_MASK) >> QEOV2_ABZ_PHASE_SHIFT_VAL_SHIFT)
683 
684 /* Bitfield definition for register of struct ABZ: LINE_WIDTH */
685 /*
686  * LINE (RW)
687  *
688  * the num of system clk by 1/4 period when using as Two-phase orthogonality.
689  */
690 #define QEOV2_ABZ_LINE_WIDTH_LINE_MASK (0xFFFFFFFFUL)
691 #define QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT (0U)
692 #define QEOV2_ABZ_LINE_WIDTH_LINE_SET(x) (((uint32_t)(x) << QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK)
693 #define QEOV2_ABZ_LINE_WIDTH_LINE_GET(x) (((uint32_t)(x) & QEOV2_ABZ_LINE_WIDTH_LINE_MASK) >> QEOV2_ABZ_LINE_WIDTH_LINE_SHIFT)
694 
695 /* Bitfield definition for register of struct ABZ: WDOG_WIDTH */
696 /*
697  * WIDTH (RW)
698  *
699  * wave will step 1/4 line to reminder user QEO still in controlled if QEO has no any toggle after the num of wdog_width sys clk.
700  */
701 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK (0xFFFFFFFFUL)
702 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT (0U)
703 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_SET(x) (((uint32_t)(x) << QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK)
704 #define QEOV2_ABZ_WDOG_WIDTH_WIDTH_GET(x) (((uint32_t)(x) & QEOV2_ABZ_WDOG_WIDTH_WIDTH_MASK) >> QEOV2_ABZ_WDOG_WIDTH_WIDTH_SHIFT)
705 
706 /* Bitfield definition for register of struct ABZ: POSTION_SYNC */
707 /*
708  * POSTION (WO)
709  *
710  * load next valid postion into abz owned postion. always read 0
711  * 0: sync abz owned postion with next valid postion.
712  * 1: not sync.
713  */
714 #define QEOV2_ABZ_POSTION_SYNC_POSTION_MASK (0x1U)
715 #define QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT (0U)
716 #define QEOV2_ABZ_POSTION_SYNC_POSTION_SET(x) (((uint32_t)(x) << QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK)
717 #define QEOV2_ABZ_POSTION_SYNC_POSTION_GET(x) (((uint32_t)(x) & QEOV2_ABZ_POSTION_SYNC_POSTION_MASK) >> QEOV2_ABZ_POSTION_SYNC_POSTION_SHIFT)
718 
719 /* Bitfield definition for register of struct ABZ: OVERALL_OFFSET */
720 /*
721  * VAL (RW)
722  *
723  * abz position overall offset, it affects abz position before resolution convert
724  */
725 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK (0xFFFFFFFFUL)
726 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT (0U)
727 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK)
728 #define QEOV2_ABZ_OVERALL_OFFSET_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_OVERALL_OFFSET_VAL_MASK) >> QEOV2_ABZ_OVERALL_OFFSET_VAL_SHIFT)
729 
730 /* Bitfield definition for register of struct ABZ: Z_START */
731 /*
732  * Z_START (RW)
733  *
734  * number of Z start line
735  */
736 #define QEOV2_ABZ_Z_START_Z_START_MASK (0xFFFFFFFFUL)
737 #define QEOV2_ABZ_Z_START_Z_START_SHIFT (0U)
738 #define QEOV2_ABZ_Z_START_Z_START_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_START_Z_START_SHIFT) & QEOV2_ABZ_Z_START_Z_START_MASK)
739 #define QEOV2_ABZ_Z_START_Z_START_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_START_Z_START_MASK) >> QEOV2_ABZ_Z_START_Z_START_SHIFT)
740 
741 /* Bitfield definition for register of struct ABZ: Z_END */
742 /*
743  * Z_END (RW)
744  *
745  * number of Z end line
746  */
747 #define QEOV2_ABZ_Z_END_Z_END_MASK (0xFFFFFFFFUL)
748 #define QEOV2_ABZ_Z_END_Z_END_SHIFT (0U)
749 #define QEOV2_ABZ_Z_END_Z_END_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_END_Z_END_SHIFT) & QEOV2_ABZ_Z_END_Z_END_MASK)
750 #define QEOV2_ABZ_Z_END_Z_END_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_END_Z_END_MASK) >> QEOV2_ABZ_Z_END_Z_END_SHIFT)
751 
752 /* Bitfield definition for register of struct ABZ: Z_OFFSET */
753 /*
754  * Z_END_OFFSET (RW)
755  *
756  * number of Z end 1/4 line
757  */
758 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK (0x300U)
759 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT (8U)
760 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK)
761 #define QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_END_OFFSET_SHIFT)
762 
763 /*
764  * Z_START_OFFSET (RW)
765  *
766  * number of Z start 1/4 line
767  */
768 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK (0x30U)
769 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT (4U)
770 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK)
771 #define QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_MASK) >> QEOV2_ABZ_Z_OFFSET_Z_START_OFFSET_SHIFT)
772 
773 /* Bitfield definition for register of struct ABZ: Z_PULSE_WIDTH */
774 /*
775  * VAL (RW)
776  *
777  * number of z_pulse_width
778  */
779 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK (0xFFFFFFFFUL)
780 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT (0U)
781 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK)
782 #define QEOV2_ABZ_Z_PULSE_WIDTH_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_Z_PULSE_WIDTH_VAL_MASK) >> QEOV2_ABZ_Z_PULSE_WIDTH_VAL_SHIFT)
783 
784 /* Bitfield definition for register of struct ABZ: FILTER */
785 /*
786  * VAL (RW)
787  *
788  * abz_filter
789  */
790 #define QEOV2_ABZ_FILTER_VAL_MASK (0xFFFFFFFFUL)
791 #define QEOV2_ABZ_FILTER_VAL_SHIFT (0U)
792 #define QEOV2_ABZ_FILTER_VAL_SET(x) (((uint32_t)(x) << QEOV2_ABZ_FILTER_VAL_SHIFT) & QEOV2_ABZ_FILTER_VAL_MASK)
793 #define QEOV2_ABZ_FILTER_VAL_GET(x) (((uint32_t)(x) & QEOV2_ABZ_FILTER_VAL_MASK) >> QEOV2_ABZ_FILTER_VAL_SHIFT)
794 
795 /* Bitfield definition for register of struct PWM: MODE */
796 /*
797  * PWM7_SAFETY (RW)
798  *
799  * PWM safety mode phase table
800  */
801 #define QEOV2_PWM_MODE_PWM7_SAFETY_MASK (0xC0000000UL)
802 #define QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT (30U)
803 #define QEOV2_PWM_MODE_PWM7_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK)
804 #define QEOV2_PWM_MODE_PWM7_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM7_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM7_SAFETY_SHIFT)
805 
806 /*
807  * PWM6_SAFETY (RW)
808  *
809  * PWM safety mode phase table
810  */
811 #define QEOV2_PWM_MODE_PWM6_SAFETY_MASK (0x30000000UL)
812 #define QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT (28U)
813 #define QEOV2_PWM_MODE_PWM6_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK)
814 #define QEOV2_PWM_MODE_PWM6_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM6_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM6_SAFETY_SHIFT)
815 
816 /*
817  * PWM5_SAFETY (RW)
818  *
819  * PWM safety mode phase table
820  */
821 #define QEOV2_PWM_MODE_PWM5_SAFETY_MASK (0xC000000UL)
822 #define QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT (26U)
823 #define QEOV2_PWM_MODE_PWM5_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK)
824 #define QEOV2_PWM_MODE_PWM5_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM5_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM5_SAFETY_SHIFT)
825 
826 /*
827  * PWM4_SAFETY (RW)
828  *
829  * PWM safety mode phase table
830  */
831 #define QEOV2_PWM_MODE_PWM4_SAFETY_MASK (0x3000000UL)
832 #define QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT (24U)
833 #define QEOV2_PWM_MODE_PWM4_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK)
834 #define QEOV2_PWM_MODE_PWM4_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM4_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM4_SAFETY_SHIFT)
835 
836 /*
837  * PWM3_SAFETY (RW)
838  *
839  * PWM safety mode phase table
840  */
841 #define QEOV2_PWM_MODE_PWM3_SAFETY_MASK (0xC00000UL)
842 #define QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT (22U)
843 #define QEOV2_PWM_MODE_PWM3_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK)
844 #define QEOV2_PWM_MODE_PWM3_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM3_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM3_SAFETY_SHIFT)
845 
846 /*
847  * PWM2_SAFETY (RW)
848  *
849  * PWM safety mode phase table
850  */
851 #define QEOV2_PWM_MODE_PWM2_SAFETY_MASK (0x300000UL)
852 #define QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT (20U)
853 #define QEOV2_PWM_MODE_PWM2_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK)
854 #define QEOV2_PWM_MODE_PWM2_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM2_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM2_SAFETY_SHIFT)
855 
856 /*
857  * PWM1_SAFETY (RW)
858  *
859  * PWM safety mode phase table
860  */
861 #define QEOV2_PWM_MODE_PWM1_SAFETY_MASK (0xC0000UL)
862 #define QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT (18U)
863 #define QEOV2_PWM_MODE_PWM1_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK)
864 #define QEOV2_PWM_MODE_PWM1_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM1_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM1_SAFETY_SHIFT)
865 
866 /*
867  * PWM0_SAFETY (RW)
868  *
869  * PWM safety mode phase table
870  */
871 #define QEOV2_PWM_MODE_PWM0_SAFETY_MASK (0x30000UL)
872 #define QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT (16U)
873 #define QEOV2_PWM_MODE_PWM0_SAFETY_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK)
874 #define QEOV2_PWM_MODE_PWM0_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM0_SAFETY_MASK) >> QEOV2_PWM_MODE_PWM0_SAFETY_SHIFT)
875 
876 /*
877  * ENABLE_PWM (RW)
878  *
879  * enable PWM force output
880  * 0: disable
881  * 1: enable
882  */
883 #define QEOV2_PWM_MODE_ENABLE_PWM_MASK (0x8000U)
884 #define QEOV2_PWM_MODE_ENABLE_PWM_SHIFT (15U)
885 #define QEOV2_PWM_MODE_ENABLE_PWM_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_ENABLE_PWM_SHIFT) & QEOV2_PWM_MODE_ENABLE_PWM_MASK)
886 #define QEOV2_PWM_MODE_ENABLE_PWM_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_ENABLE_PWM_MASK) >> QEOV2_PWM_MODE_ENABLE_PWM_SHIFT)
887 
888 /*
889  * PWM_ENTER_SAFETY_MODE (RW)
890  *
891  * PWM enter safety mode
892  * 0: not enter
893  * 1: enter
894  */
895 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK (0x200U)
896 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT (9U)
897 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK)
898 #define QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_MASK) >> QEOV2_PWM_MODE_PWM_ENTER_SAFETY_MODE_SHIFT)
899 
900 /*
901  * PWM_SAFETY_BYPASS (RW)
902  *
903  * PWM safety mode bypass
904  * 0: not bypass
905  * 1: bypass
906  */
907 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK (0x100U)
908 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT (8U)
909 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK)
910 #define QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_MASK) >> QEOV2_PWM_MODE_PWM_SAFETY_BYPASS_SHIFT)
911 
912 /*
913  * REVISE_UP_DN (RW)
914  *
915  * exchange PWM pairs’ output
916  * 0: not exchange.
917  * 1: exchange.
918  */
919 #define QEOV2_PWM_MODE_REVISE_UP_DN_MASK (0x10U)
920 #define QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT (4U)
921 #define QEOV2_PWM_MODE_REVISE_UP_DN_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK)
922 #define QEOV2_PWM_MODE_REVISE_UP_DN_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_REVISE_UP_DN_MASK) >> QEOV2_PWM_MODE_REVISE_UP_DN_SHIFT)
923 
924 /*
925  * PHASE_NUM (RW)
926  *
927  * pwm force phase number.
928  */
929 #define QEOV2_PWM_MODE_PHASE_NUM_MASK (0xFU)
930 #define QEOV2_PWM_MODE_PHASE_NUM_SHIFT (0U)
931 #define QEOV2_PWM_MODE_PHASE_NUM_SET(x) (((uint32_t)(x) << QEOV2_PWM_MODE_PHASE_NUM_SHIFT) & QEOV2_PWM_MODE_PHASE_NUM_MASK)
932 #define QEOV2_PWM_MODE_PHASE_NUM_GET(x) (((uint32_t)(x) & QEOV2_PWM_MODE_PHASE_NUM_MASK) >> QEOV2_PWM_MODE_PHASE_NUM_SHIFT)
933 
934 /* Bitfield definition for register of struct PWM: RESOLUTION */
935 /*
936  * LINES (RW)
937  *
938  * pwm resolution
939  */
940 #define QEOV2_PWM_RESOLUTION_LINES_MASK (0xFFFFFFFFUL)
941 #define QEOV2_PWM_RESOLUTION_LINES_SHIFT (0U)
942 #define QEOV2_PWM_RESOLUTION_LINES_SET(x) (((uint32_t)(x) << QEOV2_PWM_RESOLUTION_LINES_SHIFT) & QEOV2_PWM_RESOLUTION_LINES_MASK)
943 #define QEOV2_PWM_RESOLUTION_LINES_GET(x) (((uint32_t)(x) & QEOV2_PWM_RESOLUTION_LINES_MASK) >> QEOV2_PWM_RESOLUTION_LINES_SHIFT)
944 
945 /* Bitfield definition for register of struct PWM: A */
946 /*
947  * VAL (RW)
948  *
949  * pwm_a phase shifter value, default is 0x0. write other value will shift phase early as (cfg_value/2^32) period
950  */
951 #define QEOV2_PWM_PHASE_SHIFT_VAL_MASK (0xFFFFFFFFUL)
952 #define QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT (0U)
953 #define QEOV2_PWM_PHASE_SHIFT_VAL_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK)
954 #define QEOV2_PWM_PHASE_SHIFT_VAL_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_SHIFT_VAL_MASK) >> QEOV2_PWM_PHASE_SHIFT_VAL_SHIFT)
955 
956 /* Bitfield definition for register of struct PWM: POSEDGE0 */
957 /*
958  * PWM7 (RW)
959  *
960  * pwm phase table value
961  */
962 #define QEOV2_PWM_PHASE_TABLE_PWM7_MASK (0xC000U)
963 #define QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT (14U)
964 #define QEOV2_PWM_PHASE_TABLE_PWM7_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK)
965 #define QEOV2_PWM_PHASE_TABLE_PWM7_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM7_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM7_SHIFT)
966 
967 /*
968  * PWM6 (RW)
969  *
970  * pwm phase table value
971  */
972 #define QEOV2_PWM_PHASE_TABLE_PWM6_MASK (0x3000U)
973 #define QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT (12U)
974 #define QEOV2_PWM_PHASE_TABLE_PWM6_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK)
975 #define QEOV2_PWM_PHASE_TABLE_PWM6_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM6_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM6_SHIFT)
976 
977 /*
978  * PWM5 (RW)
979  *
980  * pwm phase table value
981  */
982 #define QEOV2_PWM_PHASE_TABLE_PWM5_MASK (0xC00U)
983 #define QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT (10U)
984 #define QEOV2_PWM_PHASE_TABLE_PWM5_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK)
985 #define QEOV2_PWM_PHASE_TABLE_PWM5_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM5_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM5_SHIFT)
986 
987 /*
988  * PWM4 (RW)
989  *
990  * pwm phase table value
991  */
992 #define QEOV2_PWM_PHASE_TABLE_PWM4_MASK (0x300U)
993 #define QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT (8U)
994 #define QEOV2_PWM_PHASE_TABLE_PWM4_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK)
995 #define QEOV2_PWM_PHASE_TABLE_PWM4_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM4_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM4_SHIFT)
996 
997 /*
998  * PWM3 (RW)
999  *
1000  * pwm phase table value
1001  */
1002 #define QEOV2_PWM_PHASE_TABLE_PWM3_MASK (0xC0U)
1003 #define QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT (6U)
1004 #define QEOV2_PWM_PHASE_TABLE_PWM3_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK)
1005 #define QEOV2_PWM_PHASE_TABLE_PWM3_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM3_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM3_SHIFT)
1006 
1007 /*
1008  * PWM2 (RW)
1009  *
1010  * pwm phase table value
1011  */
1012 #define QEOV2_PWM_PHASE_TABLE_PWM2_MASK (0x30U)
1013 #define QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT (4U)
1014 #define QEOV2_PWM_PHASE_TABLE_PWM2_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK)
1015 #define QEOV2_PWM_PHASE_TABLE_PWM2_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM2_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM2_SHIFT)
1016 
1017 /*
1018  * PWM1 (RW)
1019  *
1020  * pwm phase table value
1021  */
1022 #define QEOV2_PWM_PHASE_TABLE_PWM1_MASK (0xCU)
1023 #define QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT (2U)
1024 #define QEOV2_PWM_PHASE_TABLE_PWM1_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK)
1025 #define QEOV2_PWM_PHASE_TABLE_PWM1_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM1_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM1_SHIFT)
1026 
1027 /*
1028  * PWM0 (RW)
1029  *
1030  * pwm phase table value
1031  */
1032 #define QEOV2_PWM_PHASE_TABLE_PWM0_MASK (0x3U)
1033 #define QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT (0U)
1034 #define QEOV2_PWM_PHASE_TABLE_PWM0_SET(x) (((uint32_t)(x) << QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK)
1035 #define QEOV2_PWM_PHASE_TABLE_PWM0_GET(x) (((uint32_t)(x) & QEOV2_PWM_PHASE_TABLE_PWM0_MASK) >> QEOV2_PWM_PHASE_TABLE_PWM0_SHIFT)
1036 
1037 /* Bitfield definition for register of struct PWM: FILTER */
1038 /*
1039  * VAL (RW)
1040  *
1041  * pwm_filter
1042  */
1043 #define QEOV2_PWM_FILTER_VAL_MASK (0xFFFFFFFFUL)
1044 #define QEOV2_PWM_FILTER_VAL_SHIFT (0U)
1045 #define QEOV2_PWM_FILTER_VAL_SET(x) (((uint32_t)(x) << QEOV2_PWM_FILTER_VAL_SHIFT) & QEOV2_PWM_FILTER_VAL_MASK)
1046 #define QEOV2_PWM_FILTER_VAL_GET(x) (((uint32_t)(x) & QEOV2_PWM_FILTER_VAL_MASK) >> QEOV2_PWM_FILTER_VAL_SHIFT)
1047 
1048 /* Bitfield definition for register: POSTION_SOFTWARE */
1049 /*
1050  * POSTION_SOFTWAVE (RW)
1051  *
1052  * softwave inject postion
1053  */
1054 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK (0xFFFFFFFFUL)
1055 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT (0U)
1056 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SET(x) (((uint32_t)(x) << QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK)
1057 #define QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_GET(x) (((uint32_t)(x) & QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_MASK) >> QEOV2_POSTION_SOFTWARE_POSTION_SOFTWAVE_SHIFT)
1058 
1059 /* Bitfield definition for register: POSTION_SEL */
1060 /*
1061  * POSTION_SEL (RW)
1062  *
1063  * enable softwave inject postion.
1064  * 0: disable.
1065  * 1: enable.
1066  */
1067 #define QEOV2_POSTION_SEL_POSTION_SEL_MASK (0x1U)
1068 #define QEOV2_POSTION_SEL_POSTION_SEL_SHIFT (0U)
1069 #define QEOV2_POSTION_SEL_POSTION_SEL_SET(x) (((uint32_t)(x) << QEOV2_POSTION_SEL_POSTION_SEL_SHIFT) & QEOV2_POSTION_SEL_POSTION_SEL_MASK)
1070 #define QEOV2_POSTION_SEL_POSTION_SEL_GET(x) (((uint32_t)(x) & QEOV2_POSTION_SEL_POSTION_SEL_MASK) >> QEOV2_POSTION_SEL_POSTION_SEL_SHIFT)
1071 
1072 /* Bitfield definition for register: STATUS */
1073 /*
1074  * PWM_FOURCE (RO)
1075  *
1076  * qeo_pwm_force observe
1077  */
1078 #define QEOV2_STATUS_PWM_FOURCE_MASK (0xFFFF0000UL)
1079 #define QEOV2_STATUS_PWM_FOURCE_SHIFT (16U)
1080 #define QEOV2_STATUS_PWM_FOURCE_GET(x) (((uint32_t)(x) & QEOV2_STATUS_PWM_FOURCE_MASK) >> QEOV2_STATUS_PWM_FOURCE_SHIFT)
1081 
1082 /*
1083  * PWM_SAFETY (RO)
1084  *
1085  * pwm_fault status
1086  */
1087 #define QEOV2_STATUS_PWM_SAFETY_MASK (0x1U)
1088 #define QEOV2_STATUS_PWM_SAFETY_SHIFT (0U)
1089 #define QEOV2_STATUS_PWM_SAFETY_GET(x) (((uint32_t)(x) & QEOV2_STATUS_PWM_SAFETY_MASK) >> QEOV2_STATUS_PWM_SAFETY_SHIFT)
1090 
1091 /* Bitfield definition for register: DEBUG0 */
1092 /*
1093  * VALUE_DAC0 (RO)
1094  *
1095  * wave0
1096  */
1097 #define QEOV2_DEBUG0_VALUE_DAC0_MASK (0xFFFFFFFFUL)
1098 #define QEOV2_DEBUG0_VALUE_DAC0_SHIFT (0U)
1099 #define QEOV2_DEBUG0_VALUE_DAC0_GET(x) (((uint32_t)(x) & QEOV2_DEBUG0_VALUE_DAC0_MASK) >> QEOV2_DEBUG0_VALUE_DAC0_SHIFT)
1100 
1101 /* Bitfield definition for register: DEBUG1 */
1102 /*
1103  * QEO_FINISH (RO)
1104  *
1105  * qeo finish observe
1106  */
1107 #define QEOV2_DEBUG1_QEO_FINISH_MASK (0x10000000UL)
1108 #define QEOV2_DEBUG1_QEO_FINISH_SHIFT (28U)
1109 #define QEOV2_DEBUG1_QEO_FINISH_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_QEO_FINISH_MASK) >> QEOV2_DEBUG1_QEO_FINISH_SHIFT)
1110 
1111 /*
1112  * PAD_Z (RO)
1113  *
1114  * pad_z observe
1115  */
1116 #define QEOV2_DEBUG1_PAD_Z_MASK (0x1000000UL)
1117 #define QEOV2_DEBUG1_PAD_Z_SHIFT (24U)
1118 #define QEOV2_DEBUG1_PAD_Z_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_Z_MASK) >> QEOV2_DEBUG1_PAD_Z_SHIFT)
1119 
1120 /*
1121  * PAD_B (RO)
1122  *
1123  * pad_b observe
1124  */
1125 #define QEOV2_DEBUG1_PAD_B_MASK (0x100000UL)
1126 #define QEOV2_DEBUG1_PAD_B_SHIFT (20U)
1127 #define QEOV2_DEBUG1_PAD_B_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_B_MASK) >> QEOV2_DEBUG1_PAD_B_SHIFT)
1128 
1129 /*
1130  * PAD_A (RO)
1131  *
1132  * pad_a observe
1133  */
1134 #define QEOV2_DEBUG1_PAD_A_MASK (0x10000UL)
1135 #define QEOV2_DEBUG1_PAD_A_SHIFT (16U)
1136 #define QEOV2_DEBUG1_PAD_A_GET(x) (((uint32_t)(x) & QEOV2_DEBUG1_PAD_A_MASK) >> QEOV2_DEBUG1_PAD_A_SHIFT)
1137 
1138 /* Bitfield definition for register: DEBUG2 */
1139 /*
1140  * ABZ_OWN_POSTION (RO)
1141  *
1142  * abz_own_postion observe
1143  */
1144 #define QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL)
1145 #define QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT (0U)
1146 #define QEOV2_DEBUG2_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEOV2_DEBUG2_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG2_ABZ_OWN_POSTION_SHIFT)
1147 
1148 /* Bitfield definition for register: DEBUG3 */
1149 /*
1150  * ABZ_OWN_POSTION (RO)
1151  *
1152  * abz_own_postion observe
1153  */
1154 #define QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK (0xFFFFFFFFUL)
1155 #define QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT (0U)
1156 #define QEOV2_DEBUG3_ABZ_OWN_POSTION_GET(x) (((uint32_t)(x) & QEOV2_DEBUG3_ABZ_OWN_POSTION_MASK) >> QEOV2_DEBUG3_ABZ_OWN_POSTION_SHIFT)
1157 
1158 /* Bitfield definition for register: DEBUG4 */
1159 /*
1160  * VALUE_DAC1 (RO)
1161  *
1162  * wave1
1163  */
1164 #define QEOV2_DEBUG4_VALUE_DAC1_MASK (0xFFFFFFFFUL)
1165 #define QEOV2_DEBUG4_VALUE_DAC1_SHIFT (0U)
1166 #define QEOV2_DEBUG4_VALUE_DAC1_GET(x) (((uint32_t)(x) & QEOV2_DEBUG4_VALUE_DAC1_MASK) >> QEOV2_DEBUG4_VALUE_DAC1_SHIFT)
1167 
1168 /* Bitfield definition for register: DEBUG5 */
1169 /*
1170  * VALUE_DAC2 (RO)
1171  *
1172  * wave2
1173  */
1174 #define QEOV2_DEBUG5_VALUE_DAC2_MASK (0xFFFFFFFFUL)
1175 #define QEOV2_DEBUG5_VALUE_DAC2_SHIFT (0U)
1176 #define QEOV2_DEBUG5_VALUE_DAC2_GET(x) (((uint32_t)(x) & QEOV2_DEBUG5_VALUE_DAC2_MASK) >> QEOV2_DEBUG5_VALUE_DAC2_SHIFT)
1177 
1178 
1179 
1180 /* PHASE_SHIFT register group index macro definition */
1181 #define QEOV2_WAVE_PHASE_SHIFT_WAVE0 (0UL)
1182 #define QEOV2_WAVE_PHASE_SHIFT_WAVE1 (1UL)
1183 #define QEOV2_WAVE_PHASE_SHIFT_WAVE2 (2UL)
1184 
1185 /* AMPLITUDE register group index macro definition */
1186 #define QEOV2_WAVE_AMPLITUDE_WAVE0 (0UL)
1187 #define QEOV2_WAVE_AMPLITUDE_WAVE1 (1UL)
1188 #define QEOV2_WAVE_AMPLITUDE_WAVE2 (2UL)
1189 
1190 /* MID_POINT register group index macro definition */
1191 #define QEOV2_WAVE_MID_POINT_WAVE0 (0UL)
1192 #define QEOV2_WAVE_MID_POINT_WAVE1 (1UL)
1193 #define QEOV2_WAVE_MID_POINT_WAVE2 (2UL)
1194 
1195 /* LIMIT0 register group index macro definition */
1196 #define QEOV2_LIMIT0_WAVE0 (0UL)
1197 #define QEOV2_LIMIT0_WAVE1 (1UL)
1198 #define QEOV2_LIMIT0_WAVE2 (2UL)
1199 
1200 /* LIMIT1 register group index macro definition */
1201 #define QEOV2_LIMIT1_WAVE0 (0UL)
1202 #define QEOV2_LIMIT1_WAVE1 (1UL)
1203 #define QEOV2_LIMIT1_WAVE2 (2UL)
1204 
1205 /* DEADZONE_SHIFT register group index macro definition */
1206 #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE0 (0UL)
1207 #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE1 (1UL)
1208 #define QEOV2_WAVE_DEADZONE_SHIFT_WAVE2 (2UL)
1209 
1210 /* PHASE_SHIFT register group index macro definition */
1211 #define QEOV2_ABZ_PHASE_SHIFT_A (0UL)
1212 #define QEOV2_ABZ_PHASE_SHIFT_B (1UL)
1213 #define QEOV2_ABZ_PHASE_SHIFT_Z (2UL)
1214 
1215 /* PHASE_SHIFT register group index macro definition */
1216 #define QEOV2_PWM_PHASE_SHIFT_A (0UL)
1217 #define QEOV2_PWM_PHASE_SHIFT_B (1UL)
1218 #define QEOV2_PWM_PHASE_SHIFT_C (2UL)
1219 #define QEOV2_PWM_PHASE_SHIFT_D (3UL)
1220 
1221 /* PHASE_TABLE register group index macro definition */
1222 #define QEOV2_PWM_PHASE_TABLE_POSEDGE0 (0UL)
1223 #define QEOV2_PWM_PHASE_TABLE_POSEDGE1 (1UL)
1224 #define QEOV2_PWM_PHASE_TABLE_POSEDGE2 (2UL)
1225 #define QEOV2_PWM_PHASE_TABLE_POSEDGE3 (3UL)
1226 #define QEOV2_PWM_PHASE_TABLE_POSEDGE4 (4UL)
1227 #define QEOV2_PWM_PHASE_TABLE_POSEDGE5 (5UL)
1228 #define QEOV2_PWM_PHASE_TABLE_POSEDGE6 (6UL)
1229 #define QEOV2_PWM_PHASE_TABLE_POSEDGE7 (7UL)
1230 #define QEOV2_PWM_PHASE_TABLE_POSEDGE8 (8UL)
1231 #define QEOV2_PWM_PHASE_TABLE_POSEDGE9 (9UL)
1232 #define QEOV2_PWM_PHASE_TABLE_POSEDGE10 (10UL)
1233 #define QEOV2_PWM_PHASE_TABLE_POSEDGE11 (11UL)
1234 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE0 (12UL)
1235 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE1 (13UL)
1236 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE2 (14UL)
1237 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE3 (15UL)
1238 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE4 (16UL)
1239 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE5 (17UL)
1240 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE6 (18UL)
1241 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE7 (19UL)
1242 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE8 (20UL)
1243 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE9 (21UL)
1244 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE10 (22UL)
1245 #define QEOV2_PWM_PHASE_TABLE_NEGEDGE11 (23UL)
1246 
1247 
1248 #endif /* HPM_QEOV2_H */
QEOV2_Type
Definition: hpm_qeov2_regs.h:12