HPM SDK
HPMicro Software Development Kit
hpm_enet_soc_drv.h
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1 /*
2  * Copyright (c) 2023 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 #ifndef HPM_ENET_SOC_DRV_H
8 #define HPM_ENET_SOC_DRV_H
9 
10 #include "hpm_soc.h"
11 
12 #if defined __cplusplus
13 extern "C" {
14 #endif
15 
16 static inline hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type)
17 {
19 
20  if (ptr == HPM_ENET0) {
22  ptr->CTRL2 |= ENET_CTRL2_ENET0_PHY_INF_SEL_SET(inf_type);
23  } else {
25  }
26 
27  return stat;
28 }
29 
31 {
33 
34  if (ptr == HPM_ENET0) {
36  } else {
38  }
39 
40  return stat;
41 }
42 
44 {
46 
47  if (ptr == HPM_ENET0) {
49  } else {
51  }
52 
53  return stat;
54 }
55 
56 static inline hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay)
57 {
59 
60  if (ptr == HPM_ENET0) {
63  } else {
65  }
66 
67  return stat;
68 }
69 
70 static inline hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal)
71 {
73 
74  /* use an internal PLL clock as reference clock for rmii mode */
75  if (ptr == HPM_ENET0) {
76  if (internal == true) {
77  /* use a pll clock */
79  } else {
80  /* use an external clock as reference clock for rmii mode */
81  ptr->CTRL2 |= ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK; /* use an external clock */
82  }
83  } else {
85  }
86 
87  return stat;
88 }
89 
91 {
93 
94  if (ptr == HPM_ENET0) {
95  /* use an internal PLL clock for rgmii mode */
97  } else {
99  }
100 
101  return stat;
102 }
103 
104 #if defined __cplusplus
105 } /* __cplusplus */
106 #endif
107 
108 #endif /* HPM_ENET_SOC_DRV_H */
#define HPM_ENET0
Definition: hpm_soc_ip.h:374
#define ENET_CTRL2_ENET0_REFCLK_OE_MASK
Definition: hpm_enet_regs.h:5489
#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_SET(x)
Definition: hpm_enet_regs.h:5460
#define ENET_CTRL2_ENET0_PHY_INF_SEL_SET(x)
Definition: hpm_enet_regs.h:5503
#define ENET_CTRL2_ENET0_PHY_INF_SEL_MASK
Definition: hpm_enet_regs.h:5501
#define ENET_CTRL2_ENET0_LPI_IRQ_EN_MASK
Definition: hpm_enet_regs.h:5478
#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_SET(x)
Definition: hpm_enet_regs.h:5469
#define ENET_CTRL0_ENET0_TXCLK_DLY_SEL_MASK
Definition: hpm_enet_regs.h:5467
#define ENET_CTRL2_ENET0_RMII_TXCLK_SEL_MASK
Definition: hpm_enet_regs.h:5524
#define ENET_CTRL0_ENET0_RXCLK_DLY_SEL_MASK
Definition: hpm_enet_regs.h:5458
static hpm_stat_t enet_rmii_enable_clock(ENET_Type *ptr, bool internal)
Definition: hpm_enet_soc_drv.h:70
static hpm_stat_t enet_disable_lpi_interrupt(ENET_Type *ptr)
Definition: hpm_enet_soc_drv.h:43
static hpm_stat_t enet_intf_selection(ENET_Type *ptr, uint8_t inf_type)
Definition: hpm_enet_soc_drv.h:16
static hpm_stat_t enet_rgmii_set_clock_delay(ENET_Type *ptr, uint8_t tx_delay, uint8_t rx_delay)
Definition: hpm_enet_soc_drv.h:56
static hpm_stat_t enet_rgmii_enable_clock(ENET_Type *ptr)
Definition: hpm_enet_soc_drv.h:90
static hpm_stat_t enet_enable_lpi_interrupt(ENET_Type *ptr)
Definition: hpm_enet_soc_drv.h:30
uint32_t hpm_stat_t
Definition: hpm_common.h:135
@ status_invalid_argument
Definition: hpm_common.h:191
@ status_success
Definition: hpm_common.h:189
Definition: hpm_enet_regs.h:12
__RW uint32_t CTRL2
Definition: hpm_enet_regs.h:134
__RW uint32_t CTRL0
Definition: hpm_enet_regs.h:132