PLLCTL driver APIs. More...
Macros | |
| #define | PLLCTL_PLL_VCO_FREQ_MIN (375000000U) |
| #define | PLLCTL_PLL_VCO_FREQ_MAX (2200000000U) |
| #define | PLLCTL_PLL_LOCK_SS_RESET PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK |
| #define | PLLCTL_PLL_LOCK_REFDIV PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK |
| #define | PLLCTL_PLL_LOCK_POSTDIV1 PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK |
| #define | PLLCTL_PLL_LOCK_SS_SPREAD PLLCTL_PLL_LOCK_LOCK_SS_SPREAD_MASK |
| #define | PLLCTL_PLL_LOCK_SS_DIVVAL PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK |
| #define | PLLCTL_PLL_LOCK_ALL |
Enumerations | |
| enum | { status_pllctl_not_enabled = ((uint32_t)( status_group_pllctl )*1000U + (uint32_t)( 1 )) , status_pllctl_out_of_range = ((uint32_t)( status_group_pllctl )*1000U + (uint32_t)( 2 )) } |
| enum | pllctl_ss_type { pllctl_ss_centerspread = 0 , pllctl_ss_downspread = 1 } |
Functions | |
| static hpm_stat_t | pllctl_pll_ss_disable (PLLCTL_Type *ptr, uint8_t pll) |
| Disables spread spectrum mode for a specified PLL. More... | |
| static hpm_stat_t | pllctl_pll_powerdown (PLLCTL_Type *ptr, uint8_t pll) |
| Powers down a specified PLL. More... | |
| static hpm_stat_t | pllctl_pll_poweron (PLLCTL_Type *ptr, uint8_t pll) |
| Powers on a specified PLL. More... | |
| static hpm_stat_t | pllctl_set_postdiv1 (PLLCTL_Type *ptr, uint8_t pll, uint8_t div) |
| Sets the post-divider (postdiv1) for a specified PLL. More... | |
| static hpm_stat_t | pllctl_set_fbdiv_int (PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) |
| Sets the feedback divider for PLL integer mode. More... | |
| static hpm_stat_t | pllctl_set_fbdiv_frac (PLLCTL_Type *ptr, uint8_t pll, uint16_t fbdiv) |
| Sets the feedback divider for PLL fraction mode. More... | |
| static hpm_stat_t | pllctl_set_frac (PLLCTL_Type *ptr, uint8_t pll, uint32_t frac) |
| Sets the fractional part for PLL fraction mode. More... | |
| static hpm_stat_t | pllctl_get_div (PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) |
| Gets the current divider value for a specified PLL divider. More... | |
| static bool | pllctl_div_is_stable (PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index) |
| Checks if a specified PLL divider has stabilized. More... | |
| static hpm_stat_t | pllctl_set_div (PLLCTL_Type *ptr, uint8_t pll, uint8_t div_index, uint16_t div) |
| Sets the divider value for a specified PLL divider. More... | |
| static bool | pllctl_pll_is_enabled (PLLCTL_Type *ptr, uint8_t pll) |
| Checks if a specified PLL is enabled. More... | |
| static bool | pllctl_xtal_is_stable (PLLCTL_Type *ptr) |
| Checks if the crystal oscillator has stabilized. More... | |
| static bool | pllctl_xtal_is_enabled (PLLCTL_Type *ptr) |
| Checks if the crystal oscillator is enabled. More... | |
| static void | pllctl_xtal_set_rampup_time (PLLCTL_Type *ptr, uint32_t cycles) |
| Sets the ramp-up time for the crystal oscillator. More... | |
| static bool | pllctl_pll_is_locked (PLLCTL_Type *ptr, uint8_t pll) |
| Checks if a specified PLL is locked. More... | |
| hpm_stat_t | pllctl_set_pll_work_mode (PLLCTL_Type *ptr, uint8_t pll, bool int_mode) |
| Sets the operating mode of a specified PLL. More... | |
| hpm_stat_t | pllctl_set_refdiv (PLLCTL_Type *ptr, uint8_t pll, uint8_t div) |
| Sets the reference divider for a specified PLL. More... | |
| hpm_stat_t | pllctl_init_int_pll_with_freq (PLLCTL_Type *ptr, uint8_t pll, uint32_t freq_in_hz) |
| Initializes a PLL in integer mode for a specific frequency. More... | |
| hpm_stat_t | pllctl_init_frac_pll_with_freq (PLLCTL_Type *ptr, uint8_t pll, uint32_t freq_in_hz) |
| Initializes a PLL in fractional mode for a specific frequency. More... | |
| uint32_t | pllctl_get_pll_freq_in_hz (PLLCTL_Type *ptr, uint8_t pll) |
| Gets the current frequency of a specified PLL. More... | |
| hpm_stat_t | pllctl_pll_ss_enable (PLLCTL_Type *ptr, uint8_t pll, uint8_t spread, uint8_t div, bool down_spread) |
| Enables spread spectrum mode for a specified PLL. More... | |
| hpm_stat_t | pllctl_pll_setup_spread_spectrum (PLLCTL_Type *ptr, uint8_t pll, uint8_t ss_range, uint32_t modulation_freq, pllctl_ss_type ss_type) |
| Configures spread spectrum settings for a specified PLL. More... | |
PLLCTL driver APIs.
| #define PLLCTL_PLL_LOCK_ALL |
| #define PLLCTL_PLL_LOCK_POSTDIV1 PLLCTL_PLL_LOCK_LOCK_POSTDIV1_MASK |
| #define PLLCTL_PLL_LOCK_REFDIV PLLCTL_PLL_LOCK_LOCK_REFDIV_MASK |
| #define PLLCTL_PLL_LOCK_SS_DIVVAL PLLCTL_PLL_LOCK_LOCK_SS_DIVVAL_MASK |
| #define PLLCTL_PLL_LOCK_SS_RESET PLLCTL_PLL_LOCK_LOCK_SS_RSTPTR_MASK |
| #define PLLCTL_PLL_LOCK_SS_SPREAD PLLCTL_PLL_LOCK_LOCK_SS_SPREAD_MASK |
| #define PLLCTL_PLL_VCO_FREQ_MAX (2200000000U) |
| #define PLLCTL_PLL_VCO_FREQ_MIN (375000000U) |
| enum pllctl_ss_type |
|
inlinestatic |
Checks if a specified PLL divider has stabilized.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to check |
| [in] | div_index | Divider index (0: DIV0, 1: DIV1) |
|
inlinestatic |
Gets the current divider value for a specified PLL divider.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to query |
| [in] | div_index | Divider index (0: DIV0, 1: DIV1) |
| uint32_t pllctl_get_pll_freq_in_hz | ( | PLLCTL_Type * | ptr, |
| uint8_t | pll | ||
| ) |
Gets the current frequency of a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to query |
| hpm_stat_t pllctl_init_frac_pll_with_freq | ( | PLLCTL_Type * | ptr, |
| uint8_t | pll, | ||
| uint32_t | freq_in_hz | ||
| ) |
Initializes a PLL in fractional mode for a specific frequency.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | freq_in_hz | Desired output frequency in Hertz |
| hpm_stat_t pllctl_init_int_pll_with_freq | ( | PLLCTL_Type * | ptr, |
| uint8_t | pll, | ||
| uint32_t | freq_in_hz | ||
| ) |
Initializes a PLL in integer mode for a specific frequency.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | freq_in_hz | Desired output frequency in Hertz |
|
inlinestatic |
Checks if a specified PLL is enabled.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to check |
|
inlinestatic |
Checks if a specified PLL is locked.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to check |
|
inlinestatic |
Powers down a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
|
inlinestatic |
Powers on a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| hpm_stat_t pllctl_pll_setup_spread_spectrum | ( | PLLCTL_Type * | ptr, |
| uint8_t | pll, | ||
| uint8_t | ss_range, | ||
| uint32_t | modulation_freq, | ||
| pllctl_ss_type | ss_type | ||
| ) |
Configures spread spectrum settings for a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | ss_range | Spread spectrum range (0.x%) |
| [in] | modulation_freq | Desired modulation frequency in Hertz |
| [in] | ss_type | Type of spread spectrum modulation |
|
inlinestatic |
Disables spread spectrum mode for a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| hpm_stat_t pllctl_pll_ss_enable | ( | PLLCTL_Type * | ptr, |
| uint8_t | pll, | ||
| uint8_t | spread, | ||
| uint8_t | div, | ||
| bool | down_spread | ||
| ) |
Enables spread spectrum mode for a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | spread | Spread spectrum depth (0.x%) |
| [in] | div | Spread spectrum divider (1-63) |
| [in] | down_spread | true for down-spread, false for center-spread |
|
inlinestatic |
Sets the divider value for a specified PLL divider.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | div_index | Divider index (0: DIV0, 1: DIV1) |
| [in] | div | Divider value (1-based) |
|
inlinestatic |
Sets the feedback divider for PLL fraction mode.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | fbdiv | Feedback divider value (0x1~0x1000) |
|
inlinestatic |
Sets the feedback divider for PLL integer mode.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | fbdiv | Feedback divider value (0x1~0x1000) |
|
inlinestatic |
Sets the fractional part for PLL fraction mode.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | frac | 24-bit fractional value (0-2^24-1) |
| hpm_stat_t pllctl_set_pll_work_mode | ( | PLLCTL_Type * | ptr, |
| uint8_t | pll, | ||
| bool | int_mode | ||
| ) |
Sets the operating mode of a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | int_mode | true for integer mode, false for fractional mode |
|
inlinestatic |
Sets the post-divider (postdiv1) for a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | div | Post-divider value (1-7) |
| hpm_stat_t pllctl_set_refdiv | ( | PLLCTL_Type * | ptr, |
| uint8_t | pll, | ||
| uint8_t | div | ||
| ) |
Sets the reference divider for a specified PLL.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | pll | Index of the PLL to configure |
| [in] | div | Reference divider value (1-63) |
|
inlinestatic |
Checks if the crystal oscillator is enabled.
| [in] | ptr | Base address of the PLLCTL peripheral |
|
inlinestatic |
Checks if the crystal oscillator has stabilized.
| [in] | ptr | Base address of the PLLCTL peripheral |
|
inlinestatic |
Sets the ramp-up time for the crystal oscillator.
| [in] | ptr | Base address of the PLLCTL peripheral |
| [in] | cycles | Number of IRC24M clock cycles for ramp-up |