HPM SDK
HPMicro Software Development Kit
hpm_owr_regs.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_OWR_H
10 #define HPM_OWR_H
11 
12 typedef struct {
13  __RW uint32_t CTRL; /* 0x0: Control Register */
14  __RW uint32_t DIV_CFG; /* 0x4: */
15  __RW uint32_t RESET; /* 0x8: */
16  __RW uint32_t CMD; /* 0xC: */
17  __RW uint32_t DATA; /* 0x10: */
18  __R uint8_t RESERVED0[64]; /* 0x14 - 0x53: Reserved */
19  __RW uint32_t RX_CNT; /* 0x54: */
20  __RW uint32_t GLB_CFG; /* 0x58: */
21  __R uint8_t RESERVED1[4]; /* 0x5C - 0x5F: Reserved */
22  __RW uint32_t DMA_EN; /* 0x60: */
23  __R uint8_t RESERVED2[12]; /* 0x64 - 0x6F: Reserved */
24  __W uint32_t IRQ_STS; /* 0x70: */
25  __RW uint32_t IRQ_EN; /* 0x74: */
26 } OWR_Type;
27 
28 
29 /* Bitfield definition for register: CTRL */
30 /*
31  * RPPBIT (RW)
32  *
33  * Reset/Presence-detect Pulse. This bit is self-clearing and is cleared after the presence or absence of an
34  * external device is determined.
35  * writing 1 generate reset pulse and sample the bus for the presence pulse from the external device.
36  * When reading:
37  * 0 Reset pulse complete.
38  * 1 Sequence not complete.
39  */
40 #define OWR_CTRL_RPPBIT_MASK (0x80U)
41 #define OWR_CTRL_RPPBIT_SHIFT (7U)
42 #define OWR_CTRL_RPPBIT_SET(x) (((uint32_t)(x) << OWR_CTRL_RPPBIT_SHIFT) & OWR_CTRL_RPPBIT_MASK)
43 #define OWR_CTRL_RPPBIT_GET(x) (((uint32_t)(x) & OWR_CTRL_RPPBIT_MASK) >> OWR_CTRL_RPPBIT_SHIFT)
44 
45 /*
46  * PSTBIT (RO)
47  *
48  * Presence status bit,this bit is valid after the RPP bit is self-cleared.
49  * 0 Device is not present.
50  * 1 Device is present
51  */
52 #define OWR_CTRL_PSTBIT_MASK (0x40U)
53 #define OWR_CTRL_PSTBIT_SHIFT (6U)
54 #define OWR_CTRL_PSTBIT_GET(x) (((uint32_t)(x) & OWR_CTRL_PSTBIT_MASK) >> OWR_CTRL_PSTBIT_SHIFT)
55 
56 /* Bitfield definition for register: DIV_CFG */
57 /*
58  * DIV_CFG (RW)
59  *
60  * for 1us clock divider;
61  * 2; div3, 3: div4; … 255: div256
62  * 0 and 1 are un supported configuation
63  */
64 #define OWR_DIV_CFG_DIV_CFG_MASK (0xFFU)
65 #define OWR_DIV_CFG_DIV_CFG_SHIFT (0U)
66 #define OWR_DIV_CFG_DIV_CFG_SET(x) (((uint32_t)(x) << OWR_DIV_CFG_DIV_CFG_SHIFT) & OWR_DIV_CFG_DIV_CFG_MASK)
67 #define OWR_DIV_CFG_DIV_CFG_GET(x) (((uint32_t)(x) & OWR_DIV_CFG_DIV_CFG_MASK) >> OWR_DIV_CFG_DIV_CFG_SHIFT)
68 
69 /* Bitfield definition for register: RESET */
70 /*
71  * SW_RESET (RW)
72  *
73  * set to reset register 0x00, 0x04,0x10,0x14, 0x18 and related logic.
74  * Clr to exit software reset
75  */
76 #define OWR_RESET_SW_RESET_MASK (0x1U)
77 #define OWR_RESET_SW_RESET_SHIFT (0U)
78 #define OWR_RESET_SW_RESET_SET(x) (((uint32_t)(x) << OWR_RESET_SW_RESET_SHIFT) & OWR_RESET_SW_RESET_MASK)
79 #define OWR_RESET_SW_RESET_GET(x) (((uint32_t)(x) & OWR_RESET_SW_RESET_MASK) >> OWR_RESET_SW_RESET_SHIFT)
80 
81 /* Bitfield definition for register: CMD */
82 /*
83  * CMD (RW)
84  *
85  * Search ROM Accelerator(srabit). This bit is cleared when the reset-presence-pulse bit rppbit is set.
86  * 0 Deactivate the search ROM accelerator.
87  * 1 Switch to search ROM accelerator mode.
88  */
89 #define OWR_CMD_CMD_MASK (0x2U)
90 #define OWR_CMD_CMD_SHIFT (1U)
91 #define OWR_CMD_CMD_SET(x) (((uint32_t)(x) << OWR_CMD_CMD_SHIFT) & OWR_CMD_CMD_MASK)
92 #define OWR_CMD_CMD_GET(x) (((uint32_t)(x) & OWR_CMD_CMD_MASK) >> OWR_CMD_CMD_SHIFT)
93 
94 /* Bitfield definition for register: DATA */
95 /*
96  * TXRX_DATA (RW)
97  *
98  * When writing:
99  * The data byte is written to the transmit buffer.
100  * When reading:
101  * A data byte is read from the receive buffer. The data is valid only when irq_sts.rbf is set.
102  */
103 #define OWR_DATA_TXRX_DATA_MASK (0xFFU)
104 #define OWR_DATA_TXRX_DATA_SHIFT (0U)
105 #define OWR_DATA_TXRX_DATA_SET(x) (((uint32_t)(x) << OWR_DATA_TXRX_DATA_SHIFT) & OWR_DATA_TXRX_DATA_MASK)
106 #define OWR_DATA_TXRX_DATA_GET(x) (((uint32_t)(x) & OWR_DATA_TXRX_DATA_MASK) >> OWR_DATA_TXRX_DATA_SHIFT)
107 
108 /* Bitfield definition for register: RX_CNT */
109 /*
110  * RX_CNT (RW)
111  *
112  * define RX byte number.
113  * After one byte is received and read, if value is not one, hardware will trigger new read process
114  * (write 0xFF to txrx_data, after txrx_data is read, or negedge rbf). It's used together with dma for multiple receive bytes
115  * NOTE, In SRA mode, must set rx_cnt to 1. txdma will send data to start receive process.
116  */
117 #define OWR_RX_CNT_RX_CNT_MASK (0xFFU)
118 #define OWR_RX_CNT_RX_CNT_SHIFT (0U)
119 #define OWR_RX_CNT_RX_CNT_SET(x) (((uint32_t)(x) << OWR_RX_CNT_RX_CNT_SHIFT) & OWR_RX_CNT_RX_CNT_MASK)
120 #define OWR_RX_CNT_RX_CNT_GET(x) (((uint32_t)(x) & OWR_RX_CNT_RX_CNT_MASK) >> OWR_RX_CNT_RX_CNT_SHIFT)
121 
122 /* Bitfield definition for register: GLB_CFG */
123 /*
124  * FORCE_CLK_ON (RW)
125  *
126  * force enable 1us clock
127  */
128 #define OWR_GLB_CFG_FORCE_CLK_ON_MASK (0x2U)
129 #define OWR_GLB_CFG_FORCE_CLK_ON_SHIFT (1U)
130 #define OWR_GLB_CFG_FORCE_CLK_ON_SET(x) (((uint32_t)(x) << OWR_GLB_CFG_FORCE_CLK_ON_SHIFT) & OWR_GLB_CFG_FORCE_CLK_ON_MASK)
131 #define OWR_GLB_CFG_FORCE_CLK_ON_GET(x) (((uint32_t)(x) & OWR_GLB_CFG_FORCE_CLK_ON_MASK) >> OWR_GLB_CFG_FORCE_CLK_ON_SHIFT)
132 
133 /* Bitfield definition for register: DMA_EN */
134 /*
135  * TX_DMA_EN (RW)
136  *
137  */
138 #define OWR_DMA_EN_TX_DMA_EN_MASK (0x2U)
139 #define OWR_DMA_EN_TX_DMA_EN_SHIFT (1U)
140 #define OWR_DMA_EN_TX_DMA_EN_SET(x) (((uint32_t)(x) << OWR_DMA_EN_TX_DMA_EN_SHIFT) & OWR_DMA_EN_TX_DMA_EN_MASK)
141 #define OWR_DMA_EN_TX_DMA_EN_GET(x) (((uint32_t)(x) & OWR_DMA_EN_TX_DMA_EN_MASK) >> OWR_DMA_EN_TX_DMA_EN_SHIFT)
142 
143 /*
144  * RX_DMA_EN (RW)
145  *
146  */
147 #define OWR_DMA_EN_RX_DMA_EN_MASK (0x1U)
148 #define OWR_DMA_EN_RX_DMA_EN_SHIFT (0U)
149 #define OWR_DMA_EN_RX_DMA_EN_SET(x) (((uint32_t)(x) << OWR_DMA_EN_RX_DMA_EN_SHIFT) & OWR_DMA_EN_RX_DMA_EN_MASK)
150 #define OWR_DMA_EN_RX_DMA_EN_GET(x) (((uint32_t)(x) & OWR_DMA_EN_RX_DMA_EN_MASK) >> OWR_DMA_EN_RX_DMA_EN_SHIFT)
151 
152 /* Bitfield definition for register: IRQ_STS */
153 /*
154  * RSRF (W1C)
155  *
156  * Receive Shift Register Full.
157  */
158 #define OWR_IRQ_STS_RSRF_MASK (0x20U)
159 #define OWR_IRQ_STS_RSRF_SHIFT (5U)
160 #define OWR_IRQ_STS_RSRF_SET(x) (((uint32_t)(x) << OWR_IRQ_STS_RSRF_SHIFT) & OWR_IRQ_STS_RSRF_MASK)
161 #define OWR_IRQ_STS_RSRF_GET(x) (((uint32_t)(x) & OWR_IRQ_STS_RSRF_MASK) >> OWR_IRQ_STS_RSRF_SHIFT)
162 
163 /*
164  * RBF (W1C)
165  *
166  * Receive Buffer Full. This flag prevents new data from being shifted into the receive buffer from the receive shift register.
167  * 0 No new data
168  * 1 A byte is waiting to be read from the TX/RX register
169  */
170 #define OWR_IRQ_STS_RBF_MASK (0x10U)
171 #define OWR_IRQ_STS_RBF_SHIFT (4U)
172 #define OWR_IRQ_STS_RBF_SET(x) (((uint32_t)(x) << OWR_IRQ_STS_RBF_SHIFT) & OWR_IRQ_STS_RBF_MASK)
173 #define OWR_IRQ_STS_RBF_GET(x) (((uint32_t)(x) & OWR_IRQ_STS_RBF_MASK) >> OWR_IRQ_STS_RBF_SHIFT)
174 
175 /*
176  * TEMT (W1C)
177  *
178  * Transmit Shift Register Empty.
179  */
180 #define OWR_IRQ_STS_TEMT_MASK (0x8U)
181 #define OWR_IRQ_STS_TEMT_SHIFT (3U)
182 #define OWR_IRQ_STS_TEMT_SET(x) (((uint32_t)(x) << OWR_IRQ_STS_TEMT_SHIFT) & OWR_IRQ_STS_TEMT_MASK)
183 #define OWR_IRQ_STS_TEMT_GET(x) (((uint32_t)(x) & OWR_IRQ_STS_TEMT_MASK) >> OWR_IRQ_STS_TEMT_SHIFT)
184 
185 /*
186  * TBE (W1C)
187  *
188  * Transmit Buffer Empty.
189  */
190 #define OWR_IRQ_STS_TBE_MASK (0x4U)
191 #define OWR_IRQ_STS_TBE_SHIFT (2U)
192 #define OWR_IRQ_STS_TBE_SET(x) (((uint32_t)(x) << OWR_IRQ_STS_TBE_SHIFT) & OWR_IRQ_STS_TBE_MASK)
193 #define OWR_IRQ_STS_TBE_GET(x) (((uint32_t)(x) & OWR_IRQ_STS_TBE_MASK) >> OWR_IRQ_STS_TBE_SHIFT)
194 
195 /*
196  * PST_DET (W1C)
197  *
198  * Presence Detect. After an 1-Wire reset has been issued, this flag is set after the appropriate amount of time(tpst) for a presence detect pulse to have occurred.
199  */
200 #define OWR_IRQ_STS_PST_DET_MASK (0x1U)
201 #define OWR_IRQ_STS_PST_DET_SHIFT (0U)
202 #define OWR_IRQ_STS_PST_DET_SET(x) (((uint32_t)(x) << OWR_IRQ_STS_PST_DET_SHIFT) & OWR_IRQ_STS_PST_DET_MASK)
203 #define OWR_IRQ_STS_PST_DET_GET(x) (((uint32_t)(x) & OWR_IRQ_STS_PST_DET_MASK) >> OWR_IRQ_STS_PST_DET_SHIFT)
204 
205 /* Bitfield definition for register: IRQ_EN */
206 /*
207  * ERSF (RW)
208  *
209  */
210 #define OWR_IRQ_EN_ERSF_MASK (0x20U)
211 #define OWR_IRQ_EN_ERSF_SHIFT (5U)
212 #define OWR_IRQ_EN_ERSF_SET(x) (((uint32_t)(x) << OWR_IRQ_EN_ERSF_SHIFT) & OWR_IRQ_EN_ERSF_MASK)
213 #define OWR_IRQ_EN_ERSF_GET(x) (((uint32_t)(x) & OWR_IRQ_EN_ERSF_MASK) >> OWR_IRQ_EN_ERSF_SHIFT)
214 
215 /*
216  * ERBF (RW)
217  *
218  */
219 #define OWR_IRQ_EN_ERBF_MASK (0x10U)
220 #define OWR_IRQ_EN_ERBF_SHIFT (4U)
221 #define OWR_IRQ_EN_ERBF_SET(x) (((uint32_t)(x) << OWR_IRQ_EN_ERBF_SHIFT) & OWR_IRQ_EN_ERBF_MASK)
222 #define OWR_IRQ_EN_ERBF_GET(x) (((uint32_t)(x) & OWR_IRQ_EN_ERBF_MASK) >> OWR_IRQ_EN_ERBF_SHIFT)
223 
224 /*
225  * ETMT (RW)
226  *
227  */
228 #define OWR_IRQ_EN_ETMT_MASK (0x8U)
229 #define OWR_IRQ_EN_ETMT_SHIFT (3U)
230 #define OWR_IRQ_EN_ETMT_SET(x) (((uint32_t)(x) << OWR_IRQ_EN_ETMT_SHIFT) & OWR_IRQ_EN_ETMT_MASK)
231 #define OWR_IRQ_EN_ETMT_GET(x) (((uint32_t)(x) & OWR_IRQ_EN_ETMT_MASK) >> OWR_IRQ_EN_ETMT_SHIFT)
232 
233 /*
234  * ETBE (RW)
235  *
236  */
237 #define OWR_IRQ_EN_ETBE_MASK (0x4U)
238 #define OWR_IRQ_EN_ETBE_SHIFT (2U)
239 #define OWR_IRQ_EN_ETBE_SET(x) (((uint32_t)(x) << OWR_IRQ_EN_ETBE_SHIFT) & OWR_IRQ_EN_ETBE_MASK)
240 #define OWR_IRQ_EN_ETBE_GET(x) (((uint32_t)(x) & OWR_IRQ_EN_ETBE_MASK) >> OWR_IRQ_EN_ETBE_SHIFT)
241 
242 /*
243  * EPD (RW)
244  *
245  */
246 #define OWR_IRQ_EN_EPD_MASK (0x1U)
247 #define OWR_IRQ_EN_EPD_SHIFT (0U)
248 #define OWR_IRQ_EN_EPD_SET(x) (((uint32_t)(x) << OWR_IRQ_EN_EPD_SHIFT) & OWR_IRQ_EN_EPD_MASK)
249 #define OWR_IRQ_EN_EPD_GET(x) (((uint32_t)(x) & OWR_IRQ_EN_EPD_MASK) >> OWR_IRQ_EN_EPD_SHIFT)
250 
251 
252 
253 
254 #endif /* HPM_OWR_H */
OWR_Type
Definition: hpm_owr_regs.h:12