hpm_romapi_xpi_nor_def.h

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/*
 * Copyright (c) 2021 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */
#ifndef HPM_ROMAPI_XPI_NOR_DEF_H
#define HPM_ROMAPI_XPI_NOR_DEF_H
 
#include "hpm_common.h"
#include "hpm_romapi_xpi_def.h"
 
#define XPI_NOR_CFG_TAG 0x524f4E58U 
enum {
    xpi_nor_property_total_size,                            
    xpi_nor_property_page_size,                             
    xpi_nor_property_sector_size,                           
    xpi_nor_property_block_size,                            
    xpi_nor_property_max = xpi_nor_property_block_size,
};
 
 
enum {
    xpi_nor_clk_safe_clk_freq = 1,
};
 
enum {
    xpi_nor_option_misc_spi_only = 1,           
    xpi_nor_option_misc_internal_loopback = 2,  
    xpi_nor_option_misc_ext_dqs = 3,            
};
 
enum {
    xpi_nor_connection_sel_chna_cs0,               
    xpi_nor_connection_sel_chnb_cs0,               
    xpi_nor_connection_sel_chna_cs0_chnb_cs0,     
    xpi_nor_connection_sel_chna_cs0_cs1,           
    xpi_nor_connection_sel_chnb_cs0_cs1            
};
 
typedef enum {
    xpi_nor_quad_en_auto_or_ignore = 0U,                        
    xpi_nor_quad_en_set_bit6_in_status_reg1 = 1U,               
    xpi_nor_quad_en_set_bit1_in_status_reg2 = 2U,               
    xpi_nor_quad_en_set_bit7_in_status_reg2 = 3U,               
    xpi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd = 4U,   
} xpi_nor_quad_enable_seq_t;
 
typedef enum {
    xpi_working_mode_extend_spi,    
    xpi_working_mode_xpi,           
    xpi_working_mode_hyperbus,      
} xpi_working_mode_t;
 
 
typedef enum {
    xpi_nor_cfg_cmd_type_no_cfg = 0U,   
    xpi_nor_cfg_cmd_type_generic = 1U,  
    xpi_nor_cfg_cmd_type_spi2xpi = 2U,  
    xpi_nor_cfg_cmd_type_xpi2spi = 3U,  
} xpi_nor_cfg_cmd_type_t;
 
typedef enum {
    xpi_nor_probe_sfdp_sdr = 0U,    
    xpi_nor_probe_sfdp_ddr = 1U,    
    xpi_nor_quad_read_0xeb = 2U,    
    xpi_nor_dual_read_0xbb = 3U,    
    xpi_nor_hyperbus_1v8 = 4U,      
    xpi_nor_hyperbus_3v0 = 5U,      
    xpi_nor_octabus_ddr = 6U,       
    xpi_nor_octabus_sdr = 7U,       
    xpi_nor_xccela_ddr = 8U,        
    xpi_nor_xccela_sdr = 9U,        
    xpi_nor_ecoxip_ddr = 10U,       
    xpi_nor_ecoxip_sdr = 11U,       
} xpi_nor_probe_t;
 
typedef enum {
    xpi_std_nor_seq_idx_read = 0U,                     
    xpi_std_nor_seq_idx_page_program = 1U,             
    xpi_std_nor_seq_idx_read_status = 2U,              
    xpi_std_nor_seq_idx_read_status_xpi = 3U,          
    xpi_std_nor_seq_idx_write_enable = 4U,             
    xpi_std_nor_seq_idx_write_enable_xpi = 5U,         
    xpi_std_nor_seq_idx_erase_sector = 6U,             
    xpi_std_nor_seq_idx_erase_block = 7U,              
    xpi_std_nor_seq_idx_erase_chip = 8U,               
    xpi_std_nor_seq_idx_max = 9,                       
} xpi_std_nor_instr_idx_t;
 
#define XPI_NOR_CFG_OPTION_TAG (0xfcf90U)
 
typedef struct {
    union {
        struct {
            uint32_t words: 4;       
            uint32_t reserved: 8;    
            uint32_t tag: 20;        
        };
        uint32_t U;
    } header;
    union {
        struct {
            uint32_t freq_opt: 4;                
            uint32_t misc: 4;                    
            uint32_t dummy_cycles: 8;            
            uint32_t quad_enable_seq: 4;         
            uint32_t cmd_pads_after_init: 4;     
            uint32_t cmd_pads_after_por: 4;      
            uint32_t probe_type: 4;              
        };
        uint32_t U;
    } option0;
    union {
        struct {
            uint32_t drive_strength: 8;      
            uint32_t connection_sel: 4;      
            uint32_t pin_group_sel: 4;       
            uint32_t io_voltage: 4;          
            uint32_t reserved: 12;           
        };
        uint32_t U;
    } option1;
    union {
        struct {
            uint32_t flash_size_option:8;               
            uint32_t flash_sector_size_option:4;        
            uint32_t flash_sector_erase_cmd_option:4;   
            uint32_t reserved:20;
        };
        uint32_t U;
    } option2;
} xpi_nor_config_option_t;
 
enum {
    serial_nor_sector_size_4kb,     
    serial_nor_sector_size_32kb,    
    serial_nor_sector_size_64kb,    
    serial_nor_sector_size_256kb,   
};
 
enum  {
    serial_nor_erase_type_4kb,      
    serial_nor_erase_type_32kb,     
    serial_nor_erase_type_64kb,     
    serial_nor_erase_type_256kb,    
};
 
enum {
    flash_size_4mb,     
    flash_size_8mb,     
    flash_size_16mb,    
};
 
typedef struct {
    uint8_t cfg_cmd_type;       
    uint8_t param_size;         
} device_mode_cfg_t;
 
typedef struct {
    uint32_t instr_seq[4];  
    uint32_t param;         
} device_mode_param_t;
 
typedef struct {
    uint32_t size_in_kbytes;                
    uint16_t page_size;                     
    uint16_t sector_size_kbytes;            
    uint16_t block_size_kbytes;             
    uint8_t busy_offset;                    
    uint8_t busy_polarity;                  
    uint8_t data_pads;                      
    uint8_t en_ddr_mode;                    
    uint8_t clk_freq_for_device_cfg;        
    uint8_t working_mode_por;               
    uint8_t working_mode;                   
    uint8_t en_diff_clk;                    
    uint8_t data_valid_time;                
    uint8_t en_half_clk_for_non_read_cmd;   
    uint8_t clk_freq_for_non_read_cmd;      
    uint8_t dll_dly_target;                 
    uint8_t io_voltage;                     
    uint8_t reserved0;                      
    uint8_t cs_hold_time;                   
    uint8_t cs_setup_time;                  
    uint8_t cs_interval;                    
    uint8_t en_dev_mode_cfg;                
    uint32_t flash_state_ctx;               
    device_mode_cfg_t mode_cfg_list[2];     
    uint32_t mode_cfg_param[2];             
    uint32_t reserved1;                     
    struct {
        uint32_t entry[4];
    } cfg_instr_seq[2];                      
} xpi_device_info_t;
 
typedef struct {
    uint32_t tag;                         
    uint32_t reserved0;                   
    uint8_t rxclk_src;                    
    uint8_t clk_freq;                     
    uint8_t drive_strength;               
    uint8_t column_addr_size;             
    uint8_t rxclk_src_for_init;           
    uint8_t config_in_progress;           
    uint8_t reserved[2];                  
    struct {
        uint8_t enable;                   
        uint8_t group;                    
        uint8_t reserved[2];
    } chn_info[4];                        
    xpi_device_info_t device_info;       
    xpi_instr_seq_t instr_set[xpi_std_nor_seq_idx_max];
} xpi_nor_config_t;
 
typedef union {
    struct {
        uint32_t wait_time: 7;              
        uint32_t wait_time_unit: 1;         
        uint32_t reset_gpio: 8;             
        uint32_t restore_sequence: 4;       
        uint32_t exit_no_cmd_sequence: 4;   
        uint32_t current_mode: 4;           
        uint32_t por_mode: 4;               
    };
    uint32_t U;
} flash_run_context_t;
 
enum {
    status_xpi_nor_sfdp_not_found = MAKE_STATUS(status_group_xpi_nor, 0),                       
    status_xpi_nor_ddr_read_dummy_cycle_probe_failed = MAKE_STATUS(status_group_xpi_nor, 1),    
    status_xpi_nor_flash_not_found = MAKE_STATUS(status_group_xpi_nor, 2),                      
};
 
typedef struct {
    uint32_t version;
    hpm_stat_t (*get_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option);
    hpm_stat_t (*init)(XPI_Type *base, xpi_nor_config_t *nor_config);
    hpm_stat_t
    (*enable_write)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr);
    hpm_stat_t (*get_status)(XPI_Type *base,
                             xpi_xfer_channel_t channel,
                             const xpi_nor_config_t *nor_config,
                             uint32_t addr,
                             uint16_t *out_status);
    hpm_stat_t
    (*wait_busy)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr);
    hpm_stat_t (*erase)(XPI_Type *base,
                        xpi_xfer_channel_t channel,
                        const xpi_nor_config_t *nor_config,
                        uint32_t start,
                        uint32_t length);
    hpm_stat_t (*erase_chip)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config);
    hpm_stat_t
    (*erase_sector)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr);
    hpm_stat_t
    (*erase_block)(XPI_Type *base, xpi_xfer_channel_t channel, const xpi_nor_config_t *nor_config, uint32_t addr);
    hpm_stat_t (*program)(XPI_Type *base,
                          xpi_xfer_channel_t channel,
                          const xpi_nor_config_t *nor_config,
                          const uint32_t *src,
                          uint32_t dst_addr,
                          uint32_t length);
    hpm_stat_t (*read)(XPI_Type *base,
                       xpi_xfer_channel_t channel,
                       const xpi_nor_config_t *nor_config,
                       uint32_t *dst,
                       uint32_t start,
                       uint32_t length);
    hpm_stat_t (*page_program_nonblocking)(XPI_Type *base,
                                           xpi_xfer_channel_t channel,
                                           const xpi_nor_config_t *nor_config,
                                           const uint32_t *src,
                                           uint32_t dst_addr,
                                           uint32_t length);
    hpm_stat_t (*erase_sector_nonblocking)(XPI_Type *base,
                                           xpi_xfer_channel_t channel,
                                           const xpi_nor_config_t *nor_config,
                                           uint32_t addr);
    hpm_stat_t (*erase_block_nonblocking)(XPI_Type *base,
                                          xpi_xfer_channel_t channel,
                                          const xpi_nor_config_t *nor_config,
                                          uint32_t addr);
    hpm_stat_t (*erase_chip_nonblocking)(XPI_Type *base,
                                         xpi_xfer_channel_t channel,
                                         const xpi_nor_config_t *nor_config);
 
    uint32_t reserved0[3];
 
    hpm_stat_t (*auto_config)(XPI_Type *base, xpi_nor_config_t *nor_cfg, xpi_nor_config_option_t *cfg_option);
 
    hpm_stat_t (*get_property)(XPI_Type *base, xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value);
 
    uint32_t reserved1;
 
    hpm_stat_t (*post_erase_sector_nonblocking)(XPI_Type *base, xpi_xfer_channel_t chn, xpi_nor_config_t *nor_cfg, uint32_t addr);
 
    hpm_stat_t (*post_erase_block_nonblocking)(XPI_Type *base, xpi_xfer_channel_t chn, xpi_nor_config_t *nor_cfg, uint32_t addr);
 
    hpm_stat_t (*post_erase_chip_nonblocking)(XPI_Type *base, xpi_xfer_channel_t chn, xpi_nor_config_t *nor_cfg);
 
    hpm_stat_t (*post_page_program_nonblocking)(XPI_Type *base, xpi_xfer_channel_t chn, xpi_nor_config_t *nor_config,
                                           const uint32_t *src, uint32_t dst_addr, uint32_t length);
    void (*sip_flash_power_on)(XPI_Type *base);
 
    void (*sip_flash_power_off)(XPI_Type *base);
 
    void (*enable_hybrid_xpi)(XPI_Type *base);
 
    void (*disable_hybrid_xpi)(XPI_Type *base);
 
} xpi_nor_driver_interface_t;
 
#endif /* HPM_ROMAPI_XPI_NOR_DEF_H */