#include <hpm_ddrctl_regs.h>

Data Fields
__RW uint32_t	MSTR

__R uint32_t	STAT

__R uint8_t	RESERVED0 [8]

__RW uint32_t	MRCTRL0

__RW uint32_t	MRCTRL1

__R uint32_t	MRSTAT

__R uint8_t	RESERVED1 [20]

__RW uint32_t	PWRCTL

__RW uint32_t	PWRTMG

__RW uint32_t	HWLPCTL

__R uint8_t	RESERVED2 [20]

__RW uint32_t	RFSHCTL0

__RW uint32_t	RFSHCTL1

__R uint8_t	RESERVED3 [8]

__RW uint32_t	RFSHCTL3

__RW uint32_t	RFSHTMG

__R uint8_t	RESERVED4 [60]

__R uint32_t	ECCUADDR0

__R uint8_t	RESERVED5 [24]

__RW uint32_t	CRCPARCTL0

__R uint8_t	RESERVED6 [8]

__R uint32_t	CRCPARSTAT

__RW uint32_t	INIT0

__RW uint32_t	INIT1

__R uint8_t	RESERVED7 [4]

__RW uint32_t	INIT3

__RW uint32_t	INIT4

__RW uint32_t	INIT5

__R uint8_t	RESERVED8 [8]

__RW uint32_t	DIMMCTL

__RW uint32_t	RANKCTL

__R uint8_t	RESERVED9 [8]

__RW uint32_t	DRAMTMG0

__RW uint32_t	DRAMTMG1

__RW uint32_t	DRAMTMG2

__RW uint32_t	DRAMTMG3

__RW uint32_t	DRAMTMG4

__RW uint32_t	DRAMTMG5

__R uint8_t	RESERVED10 [8]

__RW uint32_t	DRAMTMG8

__R uint8_t	RESERVED11 [92]

__RW uint32_t	ZQCTL0

__RW uint32_t	ZQCTL1

__R uint8_t	RESERVED12 [4]

__R uint32_t	ZQSTAT

__RW uint32_t	DFITMG0

__RW uint32_t	DFITMG1

__RW uint32_t	DFILPCFG0

__R uint8_t	RESERVED13 [4]

__RW uint32_t	DFIUPD0

__RW uint32_t	DFIUPD1

__RW uint32_t	DFIUPD2

__RW uint32_t	DFIUPD3

__RW uint32_t	DFIMISC

__RW uint32_t	DFITMG2

__R uint8_t	RESERVED14 [72]

__RW uint32_t	ADDRMAP0

__RW uint32_t	ADDRMAP1

__RW uint32_t	ADDRMAP2

__RW uint32_t	ADDRMAP3

__RW uint32_t	ADDRMAP4

__RW uint32_t	ADDRMAP5

__RW uint32_t	ADDRMAP6

__R uint8_t	RESERVED15 [36]

__RW uint32_t	ODTCFG

__RW uint32_t	ODTMAP

__R uint8_t	RESERVED16 [8]

__RW uint32_t	SCHED

__RW uint32_t	SCHED1

__R uint8_t	RESERVED17 [4]

__RW uint32_t	PERFHPR1

__R uint8_t	RESERVED18 [4]

__RW uint32_t	PERFLPR1

__R uint8_t	RESERVED19 [4]

__RW uint32_t	PERFWR1

__R uint8_t	RESERVED20 [4]

__RW uint32_t	PERFVPR1

__RW uint32_t	PERFVPW1

__R uint8_t	RESERVED21 [132]

__RW uint32_t	DBG0

__RW uint32_t	DBG1

__R uint32_t	DBGCAM

__RW uint32_t	DBGCMD

__R uint32_t	DBGSTAT

__R uint8_t	RESERVED22 [232]

__R uint32_t	PSTAT

__RW uint32_t	PCCFG

struct {
__RW uint32_t R

__RW uint32_t W

__RW uint32_t C

struct {
__RW uint32_t MASKCH

__RW uint32_t VALUECH

} ID [16]

__RW uint32_t CTRL

__RW uint32_t QOS0

__RW uint32_t QOS1

__RW uint32_t WQOS0

__RW uint32_t WQOS1

__R uint8_t RESERVED0 [16]

}	PCFG [16]

struct {
__RW uint32_t BASE

__RW uint32_t SIZE

}	SAR [4]

__RW uint32_t	SBRCTL

__R uint32_t	SBRSTAT

__RW uint32_t	SBRWDATA0

__R uint8_t	RESERVED23 [4]

Field Documentation

◆ ADDRMAP0

__RW uint32_t DDRCTL_Type::ADDRMAP0

◆ ADDRMAP1

__RW uint32_t DDRCTL_Type::ADDRMAP1

◆ ADDRMAP2

__RW uint32_t DDRCTL_Type::ADDRMAP2

◆ ADDRMAP3

__RW uint32_t DDRCTL_Type::ADDRMAP3

◆ ADDRMAP4

__RW uint32_t DDRCTL_Type::ADDRMAP4

◆ ADDRMAP5

__RW uint32_t DDRCTL_Type::ADDRMAP5

◆ ADDRMAP6

__RW uint32_t DDRCTL_Type::ADDRMAP6

◆ BASE

__RW uint32_t DDRCTL_Type::BASE

◆ C

__RW uint32_t DDRCTL_Type::C

◆ CRCPARCTL0

__RW uint32_t DDRCTL_Type::CRCPARCTL0

◆ CRCPARSTAT

__R uint32_t DDRCTL_Type::CRCPARSTAT

◆ CTRL

__RW uint32_t DDRCTL_Type::CTRL

◆ DBG0

__RW uint32_t DDRCTL_Type::DBG0

◆ DBG1

__RW uint32_t DDRCTL_Type::DBG1

◆ DBGCAM

__R uint32_t DDRCTL_Type::DBGCAM

◆ DBGCMD

__RW uint32_t DDRCTL_Type::DBGCMD

◆ DBGSTAT

__R uint32_t DDRCTL_Type::DBGSTAT

◆ DFILPCFG0

__RW uint32_t DDRCTL_Type::DFILPCFG0

◆ DFIMISC

__RW uint32_t DDRCTL_Type::DFIMISC

◆ DFITMG0

__RW uint32_t DDRCTL_Type::DFITMG0

◆ DFITMG1

__RW uint32_t DDRCTL_Type::DFITMG1

◆ DFITMG2

__RW uint32_t DDRCTL_Type::DFITMG2

◆ DFIUPD0

__RW uint32_t DDRCTL_Type::DFIUPD0

◆ DFIUPD1

__RW uint32_t DDRCTL_Type::DFIUPD1

◆ DFIUPD2

__RW uint32_t DDRCTL_Type::DFIUPD2

◆ DFIUPD3

__RW uint32_t DDRCTL_Type::DFIUPD3

◆ DIMMCTL

__RW uint32_t DDRCTL_Type::DIMMCTL

◆ DRAMTMG0

__RW uint32_t DDRCTL_Type::DRAMTMG0

◆ DRAMTMG1

__RW uint32_t DDRCTL_Type::DRAMTMG1

◆ DRAMTMG2

__RW uint32_t DDRCTL_Type::DRAMTMG2

◆ DRAMTMG3

__RW uint32_t DDRCTL_Type::DRAMTMG3

◆ DRAMTMG4

__RW uint32_t DDRCTL_Type::DRAMTMG4

◆ DRAMTMG5

__RW uint32_t DDRCTL_Type::DRAMTMG5

◆ DRAMTMG8

__RW uint32_t DDRCTL_Type::DRAMTMG8

◆ ECCUADDR0

__R uint32_t DDRCTL_Type::ECCUADDR0

◆ HWLPCTL

__RW uint32_t DDRCTL_Type::HWLPCTL

◆

struct { ... } DDRCTL_Type::ID[16]

◆ INIT0

__RW uint32_t DDRCTL_Type::INIT0

◆ INIT1

__RW uint32_t DDRCTL_Type::INIT1

◆ INIT3

__RW uint32_t DDRCTL_Type::INIT3

◆ INIT4

__RW uint32_t DDRCTL_Type::INIT4

◆ INIT5

__RW uint32_t DDRCTL_Type::INIT5

◆ MASKCH

__RW uint32_t DDRCTL_Type::MASKCH

◆ MRCTRL0

__RW uint32_t DDRCTL_Type::MRCTRL0

◆ MRCTRL1

__RW uint32_t DDRCTL_Type::MRCTRL1

◆ MRSTAT

__R uint32_t DDRCTL_Type::MRSTAT

◆ MSTR

__RW uint32_t DDRCTL_Type::MSTR

◆ ODTCFG

__RW uint32_t DDRCTL_Type::ODTCFG

◆ ODTMAP

__RW uint32_t DDRCTL_Type::ODTMAP

◆ PCCFG

__RW uint32_t DDRCTL_Type::PCCFG

◆

struct { ... } DDRCTL_Type::PCFG[16]

◆ PERFHPR1

__RW uint32_t DDRCTL_Type::PERFHPR1

◆ PERFLPR1

__RW uint32_t DDRCTL_Type::PERFLPR1

◆ PERFVPR1

__RW uint32_t DDRCTL_Type::PERFVPR1

◆ PERFVPW1

__RW uint32_t DDRCTL_Type::PERFVPW1

◆ PERFWR1

__RW uint32_t DDRCTL_Type::PERFWR1

◆ PSTAT

__R uint32_t DDRCTL_Type::PSTAT

◆ PWRCTL

__RW uint32_t DDRCTL_Type::PWRCTL

◆ PWRTMG

__RW uint32_t DDRCTL_Type::PWRTMG

◆ QOS0

__RW uint32_t DDRCTL_Type::QOS0

◆ QOS1

__RW uint32_t DDRCTL_Type::QOS1

◆ R

__RW uint32_t DDRCTL_Type::R

◆ RANKCTL

__RW uint32_t DDRCTL_Type::RANKCTL

◆ RESERVED0

__R uint8_t DDRCTL_Type::RESERVED0[16]

◆ RESERVED1

__R uint8_t DDRCTL_Type::RESERVED1[20]

◆ RESERVED10

__R uint8_t DDRCTL_Type::RESERVED10[8]

◆ RESERVED11

__R uint8_t DDRCTL_Type::RESERVED11[92]

◆ RESERVED12

__R uint8_t DDRCTL_Type::RESERVED12[4]

◆ RESERVED13

__R uint8_t DDRCTL_Type::RESERVED13[4]

◆ RESERVED14

__R uint8_t DDRCTL_Type::RESERVED14[72]

◆ RESERVED15

__R uint8_t DDRCTL_Type::RESERVED15[36]

◆ RESERVED16

__R uint8_t DDRCTL_Type::RESERVED16[8]

◆ RESERVED17

__R uint8_t DDRCTL_Type::RESERVED17[4]

◆ RESERVED18

__R uint8_t DDRCTL_Type::RESERVED18[4]

◆ RESERVED19

__R uint8_t DDRCTL_Type::RESERVED19[4]

◆ RESERVED2

__R uint8_t DDRCTL_Type::RESERVED2[20]

◆ RESERVED20

__R uint8_t DDRCTL_Type::RESERVED20[4]

◆ RESERVED21

__R uint8_t DDRCTL_Type::RESERVED21[132]

◆ RESERVED22

__R uint8_t DDRCTL_Type::RESERVED22[232]

◆ RESERVED23

__R uint8_t DDRCTL_Type::RESERVED23[4]

◆ RESERVED3

__R uint8_t DDRCTL_Type::RESERVED3[8]

◆ RESERVED4

__R uint8_t DDRCTL_Type::RESERVED4[60]

◆ RESERVED5

__R uint8_t DDRCTL_Type::RESERVED5[24]

◆ RESERVED6

__R uint8_t DDRCTL_Type::RESERVED6[8]

◆ RESERVED7

__R uint8_t DDRCTL_Type::RESERVED7[4]

◆ RESERVED8

__R uint8_t DDRCTL_Type::RESERVED8[8]

◆ RESERVED9

__R uint8_t DDRCTL_Type::RESERVED9[8]

◆ RFSHCTL0

__RW uint32_t DDRCTL_Type::RFSHCTL0

◆ RFSHCTL1

__RW uint32_t DDRCTL_Type::RFSHCTL1

◆ RFSHCTL3

__RW uint32_t DDRCTL_Type::RFSHCTL3

◆ RFSHTMG

__RW uint32_t DDRCTL_Type::RFSHTMG

◆

struct { ... } DDRCTL_Type::SAR[4]

◆ SBRCTL

__RW uint32_t DDRCTL_Type::SBRCTL

◆ SBRSTAT

__R uint32_t DDRCTL_Type::SBRSTAT

◆ SBRWDATA0

__RW uint32_t DDRCTL_Type::SBRWDATA0

◆ SCHED

__RW uint32_t DDRCTL_Type::SCHED

◆ SCHED1

__RW uint32_t DDRCTL_Type::SCHED1

◆ SIZE

__RW uint32_t DDRCTL_Type::SIZE

◆ STAT

__R uint32_t DDRCTL_Type::STAT

◆ VALUECH

__RW uint32_t DDRCTL_Type::VALUECH

◆ W

__RW uint32_t DDRCTL_Type::W

◆ WQOS0

__RW uint32_t DDRCTL_Type::WQOS0

◆ WQOS1

__RW uint32_t DDRCTL_Type::WQOS1

◆ ZQCTL0

__RW uint32_t DDRCTL_Type::ZQCTL0

◆ ZQCTL1

__RW uint32_t DDRCTL_Type::ZQCTL1

◆ ZQSTAT

__R uint32_t DDRCTL_Type::ZQSTAT

The documentation for this struct was generated from the following file:

/home/docs/checkouts/readthedocs.org/user_builds/hpm-sdk/checkouts/latest/soc/HPM6800/ip/hpm_ddrctl_regs.h

Data Fields