#include <hpm_ffa_regs.h>
Data Fields | |
| __RW uint32_t | CTRL |
| __RW uint32_t | STATUS |
| __RW uint32_t | INT_EN |
| __R uint8_t | RESERVED0 [20] |
| __RW uint32_t | OP_CTRL |
| __RW uint32_t | OP_CMD |
| union { | |
| __RW uint32_t OP_REG0 | |
| __RW uint32_t OP_FIR_MISC | |
| __RW uint32_t OP_FFT_MISC | |
| }; | |
| union { | |
| __RW uint32_t OP_REG1 | |
| __RW uint32_t OP_FIR_MISC1 | |
| }; | |
| union { | |
| __RW uint32_t OP_REG2 | |
| __RW uint32_t OP_FFT_INRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG3 | |
| __RW uint32_t OP_FIR_INBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG4 | |
| __RW uint32_t OP_FIR_COEFBUF | |
| __RW uint32_t OP_FFT_OUTRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG5 | |
| __RW uint32_t OP_FIR_OUTBUF | |
| }; | |
| __RW uint32_t | OP_REG6 |
| __RW uint32_t | OP_REG7 |
| union { | |
| __RW uint32_t OP_REG0 | |
| __RW uint32_t OP_FIR_MISC | |
| __RW uint32_t OP_FFT_MISC | |
| }; | |
| union { | |
| __RW uint32_t OP_REG1 | |
| __RW uint32_t OP_FIR_MISC1 | |
| }; | |
| union { | |
| __RW uint32_t OP_REG2 | |
| __RW uint32_t OP_FFT_INRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG3 | |
| __RW uint32_t OP_FIR_INBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG4 | |
| __RW uint32_t OP_FIR_COEFBUF | |
| __RW uint32_t OP_FFT_OUTRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG5 | |
| __RW uint32_t OP_FIR_OUTBUF | |
| }; | |
| __RW uint32_t | FP_CTRL |
| __RW uint32_t | FP_ST |
| __R uint8_t | RESERVED1 [8] |
| union { | |
| __RW uint32_t OP_REG0 | |
| __RW uint32_t OP_FIR_MISC | |
| __RW uint32_t OP_FFT_MISC | |
| }; | |
| union { | |
| __RW uint32_t OP_REG1 | |
| __RW uint32_t OP_FIR_MISC1 | |
| }; | |
| union { | |
| __RW uint32_t OP_REG2 | |
| __RW uint32_t OP_FFT_INRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG3 | |
| __RW uint32_t OP_FIR_INBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG4 | |
| __RW uint32_t OP_FIR_COEFBUF | |
| __RW uint32_t OP_FFT_OUTRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG5 | |
| __RW uint32_t OP_FIR_OUTBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG0 | |
| __RW uint32_t OP_FIR_MISC | |
| __RW uint32_t OP_FFT_MISC | |
| }; | |
| union { | |
| __RW uint32_t OP_REG1 | |
| __RW uint32_t OP_FIR_MISC1 | |
| }; | |
| union { | |
| __RW uint32_t OP_REG2 | |
| __RW uint32_t OP_FFT_INRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG3 | |
| __RW uint32_t OP_FIR_INBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG4 | |
| __RW uint32_t OP_FIR_COEFBUF | |
| __RW uint32_t OP_FFT_OUTRBUF | |
| }; | |
| union { | |
| __RW uint32_t OP_REG5 | |
| __RW uint32_t OP_FIR_OUTBUF | |
| }; | |
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| __RW uint32_t FFA_Type::CTRL |
| __RW uint32_t FFA_Type::FP_CTRL |
| __RW uint32_t FFA_Type::FP_ST |
| __RW uint32_t FFA_Type::INT_EN |
| __RW uint32_t FFA_Type::OP_CMD |
| __RW uint32_t FFA_Type::OP_CTRL |
| __RW uint32_t FFA_Type::OP_FFT_INRBUF |
| __RW uint32_t FFA_Type::OP_FFT_MISC |
| __RW uint32_t FFA_Type::OP_FFT_OUTRBUF |
| __RW uint32_t FFA_Type::OP_FIR_COEFBUF |
| __RW uint32_t FFA_Type::OP_FIR_INBUF |
| __RW uint32_t FFA_Type::OP_FIR_MISC |
| __RW uint32_t FFA_Type::OP_FIR_MISC1 |
| __RW uint32_t FFA_Type::OP_FIR_OUTBUF |
| __RW uint32_t FFA_Type::OP_REG0 |
| __RW uint32_t FFA_Type::OP_REG1 |
| __RW uint32_t FFA_Type::OP_REG2 |
| __RW uint32_t FFA_Type::OP_REG3 |
| __RW uint32_t FFA_Type::OP_REG4 |
| __RW uint32_t FFA_Type::OP_REG5 |
| __RW uint32_t FFA_Type::OP_REG6 |
| __RW uint32_t FFA_Type::OP_REG7 |
| __R uint8_t FFA_Type::RESERVED0 |
| __R uint8_t FFA_Type::RESERVED1 |
| __RW uint32_t FFA_Type::STATUS |