#include <hpm_mipi_dsi_phy_regs.h>

Data Fields
__RW uint32_t	CLANE_PARA0

__RW uint32_t	CLANE_PARA1

__RW uint32_t	CLANE_PARA2

__RW uint32_t	CLANE_PARA3

__RW uint32_t	DLANE0_PARA0

__RW uint32_t	DLANE0_PARA1

__RW uint32_t	DLANE0_PARA2

__RW uint32_t	DLANE0_PARA3

__RW uint32_t	DLANE0_PARA4

__RW uint32_t	DLANE1_PARA0

__RW uint32_t	DLANE1_PARA1

__RW uint32_t	DLANE1_PARA2

__RW uint32_t	DLANE1_PARA3

__RW uint32_t	DLANE2_PARA0

__RW uint32_t	DLANE2_PARA1

__RW uint32_t	DLANE2_PARA2

__RW uint32_t	DLANE2_PARA3

__RW uint32_t	DLANE3_PARA0

__RW uint32_t	DLANE3_PARA1

__RW uint32_t	DLANE3_PARA2

__RW uint32_t	DLANE3_PARA3

__RW uint32_t	COMMON_PARA0

__RW uint32_t	CTRL_PARA0

__RW uint32_t	PLL_CTRL_PARA0

__R uint8_t	RESERVED0 [4]

__RW uint32_t	RCAL_CTRL

__RW uint32_t	TRIM_PARA

__RW uint32_t	TEST_PARA0

__RW uint32_t	TEST_PARA1

__RW uint32_t	MISC_PARA

__RW uint32_t	CLANE_PARA4

__RW uint32_t	INTERFACE_PARA

__RW uint32_t	PCS_RESERVED_PIN_PARA

__R uint8_t	RESERVED1 [8]

__RW uint32_t	CLANE_DATA_PARA

__RW uint32_t	PMA_LANE_SEL_PARA

Field Documentation

◆ CLANE_DATA_PARA

__RW uint32_t MIPI_DSI_PHY_Type::CLANE_DATA_PARA

◆ CLANE_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::CLANE_PARA0

◆ CLANE_PARA1

__RW uint32_t MIPI_DSI_PHY_Type::CLANE_PARA1

◆ CLANE_PARA2

__RW uint32_t MIPI_DSI_PHY_Type::CLANE_PARA2

◆ CLANE_PARA3

__RW uint32_t MIPI_DSI_PHY_Type::CLANE_PARA3

◆ CLANE_PARA4

__RW uint32_t MIPI_DSI_PHY_Type::CLANE_PARA4

◆ COMMON_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::COMMON_PARA0

◆ CTRL_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::CTRL_PARA0

◆ DLANE0_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::DLANE0_PARA0

◆ DLANE0_PARA1

__RW uint32_t MIPI_DSI_PHY_Type::DLANE0_PARA1

◆ DLANE0_PARA2

__RW uint32_t MIPI_DSI_PHY_Type::DLANE0_PARA2

◆ DLANE0_PARA3

__RW uint32_t MIPI_DSI_PHY_Type::DLANE0_PARA3

◆ DLANE0_PARA4

__RW uint32_t MIPI_DSI_PHY_Type::DLANE0_PARA4

◆ DLANE1_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::DLANE1_PARA0

◆ DLANE1_PARA1

__RW uint32_t MIPI_DSI_PHY_Type::DLANE1_PARA1

◆ DLANE1_PARA2

__RW uint32_t MIPI_DSI_PHY_Type::DLANE1_PARA2

◆ DLANE1_PARA3

__RW uint32_t MIPI_DSI_PHY_Type::DLANE1_PARA3

◆ DLANE2_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::DLANE2_PARA0

◆ DLANE2_PARA1

__RW uint32_t MIPI_DSI_PHY_Type::DLANE2_PARA1

◆ DLANE2_PARA2

__RW uint32_t MIPI_DSI_PHY_Type::DLANE2_PARA2

◆ DLANE2_PARA3

__RW uint32_t MIPI_DSI_PHY_Type::DLANE2_PARA3

◆ DLANE3_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::DLANE3_PARA0

◆ DLANE3_PARA1

__RW uint32_t MIPI_DSI_PHY_Type::DLANE3_PARA1

◆ DLANE3_PARA2

__RW uint32_t MIPI_DSI_PHY_Type::DLANE3_PARA2

◆ DLANE3_PARA3

__RW uint32_t MIPI_DSI_PHY_Type::DLANE3_PARA3

◆ INTERFACE_PARA

__RW uint32_t MIPI_DSI_PHY_Type::INTERFACE_PARA

◆ MISC_PARA

__RW uint32_t MIPI_DSI_PHY_Type::MISC_PARA

◆ PCS_RESERVED_PIN_PARA

__RW uint32_t MIPI_DSI_PHY_Type::PCS_RESERVED_PIN_PARA

◆ PLL_CTRL_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::PLL_CTRL_PARA0

◆ PMA_LANE_SEL_PARA

__RW uint32_t MIPI_DSI_PHY_Type::PMA_LANE_SEL_PARA

◆ RCAL_CTRL

__RW uint32_t MIPI_DSI_PHY_Type::RCAL_CTRL

◆ RESERVED0

__R uint8_t MIPI_DSI_PHY_Type::RESERVED0[4]

◆ RESERVED1

__R uint8_t MIPI_DSI_PHY_Type::RESERVED1[8]

◆ TEST_PARA0

__RW uint32_t MIPI_DSI_PHY_Type::TEST_PARA0

◆ TEST_PARA1

__RW uint32_t MIPI_DSI_PHY_Type::TEST_PARA1

◆ TRIM_PARA

__RW uint32_t MIPI_DSI_PHY_Type::TRIM_PARA

The documentation for this struct was generated from the following file:

/home/docs/checkouts/readthedocs.org/user_builds/hpm-sdk/checkouts/latest/soc/HPM6800/ip/hpm_mipi_dsi_phy_regs.h

Data Fields