HPM SDK
HPMicro Software Development Kit
Data Fields
SDXC_Type Struct Reference

#include <hpm_sdxc_regs.h>

Data Fields

__RW uint32_t SDMASA
 
__RW uint32_t BLK_ATTR
 
__RW uint32_t CMD_ARG
 
__RW uint32_t CMD_XFER
 
__R uint32_t RESP [4]
 
__RW uint32_t BUF_DATA
 
__R uint32_t PSTATE
 
__RW uint32_t PROT_CTRL
 
__RW uint32_t SYS_CTRL
 
__RW uint32_t INT_STAT
 
__RW uint32_t INT_STAT_EN
 
__RW uint32_t INT_SIGNAL_EN
 
__RW uint32_t AC_HOST_CTRL
 
__R uint32_t CAPABILITIES1
 
__R uint32_t CAPABILITIES2
 
__R uint32_t CURR_CAPABILITIES1
 
__R uint32_t CURR_CAPABILITIES2
 
__W uint32_t FORCE_EVENT
 
__R uint32_t ADMA_ERR_STAT
 
__RW uint32_t ADMA_SYS_ADDR
 
__R uint8_t RESERVED0 [4]
 
__R uint16_t PRESET [11]
 
__R uint8_t RESERVED1 [2]
 
__RW uint32_t ADMA_ID_ADDR
 
__R uint8_t RESERVED2 [106]
 
__R uint16_t P_EMBEDDED_CNTRL
 
__R uint16_t P_VENDOR_SPECIFIC_AREA
 
__R uint16_t P_VENDOR2_SPECIFIC_AREA
 
__R uint8_t RESERVED3 [16]
 
__R uint16_t SLOT_INTR_STATUS
 
__R uint8_t RESERVED4 [130]
 
__R uint32_t CQVER
 
__R uint32_t CQCAP
 
__RW uint32_t CQCFG
 
__RW uint32_t CQCTL
 
__RW uint32_t CQIS
 
__RW uint32_t CQISE
 
__RW uint32_t CQISGE
 
__RW uint32_t CQIC
 
__RW uint32_t CQTDLBA
 
__R uint8_t RESERVED5 [4]
 
__RW uint32_t CQTDBR
 
__RW uint32_t CQTCN
 
__RW uint32_t CQDQS
 
__RW uint32_t CQDPT
 
__RW uint32_t CQTCLR
 
__R uint8_t RESERVED6 [4]
 
__RW uint32_t CQSSC1
 
__RW uint32_t CQSSC2
 
__R uint32_t CQCRDCT
 
__R uint8_t RESERVED7 [4]
 
__RW uint32_t CQRMEM
 
__R uint32_t CQTERRI
 
__R uint32_t CQCRI
 
__R uint32_t CQCRA
 
__R uint8_t RESERVED8 [800]
 
__R uint32_t MSHC_VER_ID
 
__R uint32_t MSHC_VER_TYPE
 
__R uint8_t RESERVED9 [36]
 
__RW uint32_t EMMC_BOOT_CTRL
 
__R uint8_t RESERVED10 [16]
 
__RW uint32_t AUTO_TUNING_CTRL
 
__RW uint32_t AUTO_TUNING_STAT
 
__R uint8_t RESERVED11 [10936]
 
__RW uint32_t MISC_CTRL0
 
__RW uint32_t MISC_CTRL1
 

Field Documentation

◆ AC_HOST_CTRL

__RW uint32_t SDXC_Type::AC_HOST_CTRL

◆ ADMA_ERR_STAT

__R uint32_t SDXC_Type::ADMA_ERR_STAT

◆ ADMA_ID_ADDR

__RW uint32_t SDXC_Type::ADMA_ID_ADDR

◆ ADMA_SYS_ADDR

__RW uint32_t SDXC_Type::ADMA_SYS_ADDR

◆ AUTO_TUNING_CTRL

__RW uint32_t SDXC_Type::AUTO_TUNING_CTRL

◆ AUTO_TUNING_STAT

__RW uint32_t SDXC_Type::AUTO_TUNING_STAT

◆ BLK_ATTR

__RW uint32_t SDXC_Type::BLK_ATTR

◆ BUF_DATA

__RW uint32_t SDXC_Type::BUF_DATA

◆ CAPABILITIES1

__R uint32_t SDXC_Type::CAPABILITIES1

◆ CAPABILITIES2

__R uint32_t SDXC_Type::CAPABILITIES2

◆ CMD_ARG

__RW uint32_t SDXC_Type::CMD_ARG

◆ CMD_XFER

__RW uint32_t SDXC_Type::CMD_XFER

◆ CQCAP

__R uint32_t SDXC_Type::CQCAP

◆ CQCFG

__RW uint32_t SDXC_Type::CQCFG

◆ CQCRA

__R uint32_t SDXC_Type::CQCRA

◆ CQCRDCT

__R uint32_t SDXC_Type::CQCRDCT

◆ CQCRI

__R uint32_t SDXC_Type::CQCRI

◆ CQCTL

__RW uint32_t SDXC_Type::CQCTL

◆ CQDPT

__RW uint32_t SDXC_Type::CQDPT

◆ CQDQS

__RW uint32_t SDXC_Type::CQDQS

◆ CQIC

__RW uint32_t SDXC_Type::CQIC

◆ CQIS

__RW uint32_t SDXC_Type::CQIS

◆ CQISE

__RW uint32_t SDXC_Type::CQISE

◆ CQISGE

__RW uint32_t SDXC_Type::CQISGE

◆ CQRMEM

__RW uint32_t SDXC_Type::CQRMEM

◆ CQSSC1

__RW uint32_t SDXC_Type::CQSSC1

◆ CQSSC2

__RW uint32_t SDXC_Type::CQSSC2

◆ CQTCLR

__RW uint32_t SDXC_Type::CQTCLR

◆ CQTCN

__RW uint32_t SDXC_Type::CQTCN

◆ CQTDBR

__RW uint32_t SDXC_Type::CQTDBR

◆ CQTDLBA

__RW uint32_t SDXC_Type::CQTDLBA

◆ CQTERRI

__R uint32_t SDXC_Type::CQTERRI

◆ CQVER

__R uint32_t SDXC_Type::CQVER

◆ CURR_CAPABILITIES1

__R uint32_t SDXC_Type::CURR_CAPABILITIES1

◆ CURR_CAPABILITIES2

__R uint32_t SDXC_Type::CURR_CAPABILITIES2

◆ EMMC_BOOT_CTRL

__RW uint32_t SDXC_Type::EMMC_BOOT_CTRL

◆ FORCE_EVENT

__W uint32_t SDXC_Type::FORCE_EVENT

◆ INT_SIGNAL_EN

__RW uint32_t SDXC_Type::INT_SIGNAL_EN

◆ INT_STAT

__RW uint32_t SDXC_Type::INT_STAT

◆ INT_STAT_EN

__RW uint32_t SDXC_Type::INT_STAT_EN

◆ MISC_CTRL0

__RW uint32_t SDXC_Type::MISC_CTRL0

◆ MISC_CTRL1

__RW uint32_t SDXC_Type::MISC_CTRL1

◆ MSHC_VER_ID

__R uint32_t SDXC_Type::MSHC_VER_ID

◆ MSHC_VER_TYPE

__R uint32_t SDXC_Type::MSHC_VER_TYPE

◆ P_EMBEDDED_CNTRL

__R uint16_t SDXC_Type::P_EMBEDDED_CNTRL

◆ P_VENDOR2_SPECIFIC_AREA

__R uint16_t SDXC_Type::P_VENDOR2_SPECIFIC_AREA

◆ P_VENDOR_SPECIFIC_AREA

__R uint16_t SDXC_Type::P_VENDOR_SPECIFIC_AREA

◆ PRESET

__R uint16_t SDXC_Type::PRESET

◆ PROT_CTRL

__RW uint32_t SDXC_Type::PROT_CTRL

◆ PSTATE

__R uint32_t SDXC_Type::PSTATE

◆ RESERVED0

__R uint8_t SDXC_Type::RESERVED0

◆ RESERVED1

__R uint8_t SDXC_Type::RESERVED1

◆ RESERVED10

__R uint8_t SDXC_Type::RESERVED10

◆ RESERVED11

__R uint8_t SDXC_Type::RESERVED11

◆ RESERVED2

__R uint8_t SDXC_Type::RESERVED2

◆ RESERVED3

__R uint8_t SDXC_Type::RESERVED3

◆ RESERVED4

__R uint8_t SDXC_Type::RESERVED4

◆ RESERVED5

__R uint8_t SDXC_Type::RESERVED5

◆ RESERVED6

__R uint8_t SDXC_Type::RESERVED6

◆ RESERVED7

__R uint8_t SDXC_Type::RESERVED7

◆ RESERVED8

__R uint8_t SDXC_Type::RESERVED8

◆ RESERVED9

__R uint8_t SDXC_Type::RESERVED9

◆ RESP

__R uint32_t SDXC_Type::RESP

◆ SDMASA

__RW uint32_t SDXC_Type::SDMASA

◆ SLOT_INTR_STATUS

__R uint16_t SDXC_Type::SLOT_INTR_STATUS

◆ SYS_CTRL

__RW uint32_t SDXC_Type::SYS_CTRL
The documentation for this struct was generated from the following file: