HPM SDK
HPMicro Software Development Kit
VSC_Type Struct Reference

#include <hpm_vsc_regs.h>

Data Fields

__RW uint32_t ABC_MODE
 
__RW uint32_t ADC_CHAN_ASSIGN
 
__RW uint32_t VALUE_A_DATA_OPT
 
__R uint8_t RESERVED0 [4]
 
__RW uint32_t VALUE_B_DATA_OPT
 
__R uint8_t RESERVED1 [4]
 
__RW uint32_t VALUE_C_DATA_OPT
 
__R uint8_t RESERVED2 [4]
 
__RW uint32_t VALUE_A_OFFSET
 
__RW uint32_t VALUE_B_OFFSET
 
__RW uint32_t VALUE_C_OFFSET
 
__RW uint32_t IRQ_STATUS
 
__RW uint32_t VALUE_A_SW
 
__RW uint32_t VALUE_B_SW
 
__RW uint32_t VALUE_C_SW
 
__W uint32_t VALUE_SW_READY
 
__W uint32_t TRIGGER_SW
 
__RW uint32_t TIMELOCK
 
__RW uint32_t POSITION_SW
 
__RW uint32_t ADC_WAIT_CYCLE
 
__RW uint32_t POS_WAIT_CYCLE
 
__RW uint32_t IRQ_ENABLE
 
__RW uint32_t ADC_PHASE_TOLERATE
 
__RW uint32_t POS_POLE
 
__R uint8_t RESERVED3 [160]
 
__R uint32_t ID_POSEDGE
 
__R uint32_t IQ_POSEDGE
 
__R uint32_t ID_NEGEDGE
 
__R uint32_t IQ_NEGEDGE
 
__R uint32_t ALPHA_POSEDGE
 
__R uint32_t BETA_POSEDGE
 
__R uint32_t ALPHA_NEGEDGE
 
__R uint32_t BETA_NEGEDGE
 
__R uint32_t TIMESTAMP_LOCKED
 
__R uint32_t DEBUG_STATUS0
 

Field Documentation

◆ ABC_MODE

__RW uint32_t VSC_Type::ABC_MODE

◆ ADC_CHAN_ASSIGN

__RW uint32_t VSC_Type::ADC_CHAN_ASSIGN

◆ ADC_PHASE_TOLERATE

__RW uint32_t VSC_Type::ADC_PHASE_TOLERATE

◆ ADC_WAIT_CYCLE

__RW uint32_t VSC_Type::ADC_WAIT_CYCLE

◆ ALPHA_NEGEDGE

__R uint32_t VSC_Type::ALPHA_NEGEDGE

◆ ALPHA_POSEDGE

__R uint32_t VSC_Type::ALPHA_POSEDGE

◆ BETA_NEGEDGE

__R uint32_t VSC_Type::BETA_NEGEDGE

◆ BETA_POSEDGE

__R uint32_t VSC_Type::BETA_POSEDGE

◆ DEBUG_STATUS0

__R uint32_t VSC_Type::DEBUG_STATUS0

◆ ID_NEGEDGE

__R uint32_t VSC_Type::ID_NEGEDGE

◆ ID_POSEDGE

__R uint32_t VSC_Type::ID_POSEDGE

◆ IQ_NEGEDGE

__R uint32_t VSC_Type::IQ_NEGEDGE

◆ IQ_POSEDGE

__R uint32_t VSC_Type::IQ_POSEDGE

◆ IRQ_ENABLE

__RW uint32_t VSC_Type::IRQ_ENABLE

◆ IRQ_STATUS

__RW uint32_t VSC_Type::IRQ_STATUS

◆ POS_POLE

__RW uint32_t VSC_Type::POS_POLE

◆ POS_WAIT_CYCLE

__RW uint32_t VSC_Type::POS_WAIT_CYCLE

◆ POSITION_SW

__RW uint32_t VSC_Type::POSITION_SW

◆ RESERVED0

__R uint8_t VSC_Type::RESERVED0

◆ RESERVED1

__R uint8_t VSC_Type::RESERVED1

◆ RESERVED2

__R uint8_t VSC_Type::RESERVED2

◆ RESERVED3

__R uint8_t VSC_Type::RESERVED3

◆ TIMELOCK

__RW uint32_t VSC_Type::TIMELOCK

◆ TIMESTAMP_LOCKED

__R uint32_t VSC_Type::TIMESTAMP_LOCKED

◆ TRIGGER_SW

__W uint32_t VSC_Type::TRIGGER_SW

◆ VALUE_A_DATA_OPT

__RW uint32_t VSC_Type::VALUE_A_DATA_OPT

◆ VALUE_A_OFFSET

__RW uint32_t VSC_Type::VALUE_A_OFFSET

◆ VALUE_A_SW

__RW uint32_t VSC_Type::VALUE_A_SW

◆ VALUE_B_DATA_OPT

__RW uint32_t VSC_Type::VALUE_B_DATA_OPT

◆ VALUE_B_OFFSET

__RW uint32_t VSC_Type::VALUE_B_OFFSET

◆ VALUE_B_SW

__RW uint32_t VSC_Type::VALUE_B_SW

◆ VALUE_C_DATA_OPT

__RW uint32_t VSC_Type::VALUE_C_DATA_OPT

◆ VALUE_C_OFFSET

__RW uint32_t VSC_Type::VALUE_C_OFFSET

◆ VALUE_C_SW

__RW uint32_t VSC_Type::VALUE_C_SW

◆ VALUE_SW_READY

__W uint32_t VSC_Type::VALUE_SW_READY

The documentation for this struct was generated from the following file: