56. SDM

56.1. Overview

The SDM sample project demonstrates the function of data sampling and amplitude detection of the data stream output by the Sigma-Delta modulator of SDM peripherals.

56.2. Board Setting

Please refer to Pin Description for specific board. Different hardware setting are used depending on whether an AD sampling chip is on the development board.

If there is no onboard AD sampling chip on the development board, please using an external sampling chip and connect the output CLK and DAT pins of the sampling chip to the CLK and DAT pins of the SDM on the board.
If there is onboard AD sampling chip, simply connect the analog signal to the input interface of the sampling chip.

56.3. Note

This example provides a conversion formula for input voltage and output value suitable for Sigma-Delta modulators such as AD7400 and NSI1306 (Full-scale ±320 mV). If you are using a different type of Sigma-Delta modulator, please check the conversion formula.

56.4. Running the example

When running the project, the serial port will output the following information, allowing you to enter different numbers to execute different test functions:

sdm example
*********************************************************************
*                                                                   *
*                         SDM Example Menu                          *
* Please enter one of following SDM function test(e.g. 1 or 2 ...): *
* 1 - SDM sample data in polling mode                               *
* 2 - SDM amplitude threshold check                                 *
* 3 - SDM sample data in interrupt mode                             *
* 4 - SDM sample data with sync signal                              *
*                                                                   *
*********************************************************************

56.4.1. 1. SDM sample data in polling mode

SDM Polling Data Valid Flag and Reading Sample Data from FIFO.

Selected option: 1

sdm sample data in polling mode.
57mV
17mV
31mV
14mV
01mV
28mV
17mV
05mV
19mV
21mV
02mV
19mV
43mV
17mV
29mV
24mV

56.4.2. 2. SDM amplitude threshold check

SDM detects voltage over-limit events. The high voltage threshold for amplitude detection is set to SDM_AMPLITUDE_HIGH_THRESHOLD. When the input analog voltage increases from below this threshold to above it, an error interrupt is triggered.

Selected option: 2

Set amplitude high threshold 240mV
sdm channel comparator detected amplitude over the high threshold
voltage: 253.75mV

56.4.3. 3. SDM sample data in interrupt mode

SDM samples data from FIFO with the data ready flag. When the data in the FIFO reaches a preset threshold, SDM triggers a data ready interrupt. During the interrupt handler, data is read, and stop the sampling when the number of data read reaches TEST_DATA_COUNT.

Selected option: 3

sdm sample data in interrupt mode.
39mV
08mV
96mV
87mV
85mV
86mV
86mV
84mV
81mV
88mV
01mV
23mV
08mV
97mV
92mV
97mV

56.4.4. 4. SDM sample data with sync signal

In this case, GPTMR is used to output the synchronization signal, it connects to SDM sync input signal through TRGMMUX configuration. When the output signal of GPTMR rises, the synchronization event of SDM is triggered. SDM samples data with synchronization signals. When a synchronization event occurs, SDM begins sampling data into the FIFO. Once the data in the FIFO reaches a preset threshold, SDM triggers a data ready interrupt to read the data, and the hardware clears the synchronization event flag, halting further sampling until the next synchronization event takes place.

Selected option: 4

sdm sample data with sync signal. 1 time
88mV
84mV
90mV
87mV
91mV
92mV
85mV
85mV
sdm sample data with sync signal. 2 time
90mV
96mV
97mV
93mV
94mV
86mV
89mV
90mV
sdm sample data with sync signal. 3 time
94mV
03mV
97mV
91mV
89mV
87mV
93mV
97mV
sdm sample data with sync signal. 4 time
93mV
13mV
14mV
16mV
17mV
13mV
14mV
12mV