hpm_sec_regs.h File Reference

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Data Structures
struct	SEC_Type

Macros
#define	SEC_SECURE_STATE_ALLOW_NSC_MASK   (0x20000UL)
#define	SEC_SECURE_STATE_ALLOW_NSC_SHIFT   (17U)
#define	SEC_SECURE_STATE_ALLOW_NSC_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_NSC_MASK) >> SEC_SECURE_STATE_ALLOW_NSC_SHIFT)
#define	SEC_SECURE_STATE_ALLOW_SEC_MASK   (0x10000UL)
#define	SEC_SECURE_STATE_ALLOW_SEC_SHIFT   (16U)
#define	SEC_SECURE_STATE_ALLOW_SEC_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_SEC_MASK) >> SEC_SECURE_STATE_ALLOW_SEC_SHIFT)
#define	SEC_SECURE_STATE_PMIC_FAIL_MASK   (0x80U)
#define	SEC_SECURE_STATE_PMIC_FAIL_SHIFT   (7U)
#define	SEC_SECURE_STATE_PMIC_FAIL_SET(x)   (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_FAIL_SHIFT) & SEC_SECURE_STATE_PMIC_FAIL_MASK)
#define	SEC_SECURE_STATE_PMIC_FAIL_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_FAIL_MASK) >> SEC_SECURE_STATE_PMIC_FAIL_SHIFT)
#define	SEC_SECURE_STATE_PMIC_NSC_MASK   (0x40U)
#define	SEC_SECURE_STATE_PMIC_NSC_SHIFT   (6U)
#define	SEC_SECURE_STATE_PMIC_NSC_SET(x)   (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_NSC_SHIFT) & SEC_SECURE_STATE_PMIC_NSC_MASK)
#define	SEC_SECURE_STATE_PMIC_NSC_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_NSC_MASK) >> SEC_SECURE_STATE_PMIC_NSC_SHIFT)
#define	SEC_SECURE_STATE_PMIC_SEC_MASK   (0x20U)
#define	SEC_SECURE_STATE_PMIC_SEC_SHIFT   (5U)
#define	SEC_SECURE_STATE_PMIC_SEC_SET(x)   (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_SEC_SHIFT) & SEC_SECURE_STATE_PMIC_SEC_MASK)
#define	SEC_SECURE_STATE_PMIC_SEC_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_SEC_MASK) >> SEC_SECURE_STATE_PMIC_SEC_SHIFT)
#define	SEC_SECURE_STATE_PMIC_INS_MASK   (0x10U)
#define	SEC_SECURE_STATE_PMIC_INS_SHIFT   (4U)
#define	SEC_SECURE_STATE_PMIC_INS_SET(x)   (((uint32_t)(x) << SEC_SECURE_STATE_PMIC_INS_SHIFT) & SEC_SECURE_STATE_PMIC_INS_MASK)
#define	SEC_SECURE_STATE_PMIC_INS_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_PMIC_INS_MASK) >> SEC_SECURE_STATE_PMIC_INS_SHIFT)
#define	SEC_SECURE_STATE_CONFIG_LOCK_MASK   (0x8U)
#define	SEC_SECURE_STATE_CONFIG_LOCK_SHIFT   (3U)
#define	SEC_SECURE_STATE_CONFIG_LOCK_SET(x)   (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & SEC_SECURE_STATE_CONFIG_LOCK_MASK)
#define	SEC_SECURE_STATE_CONFIG_LOCK_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) >> SEC_SECURE_STATE_CONFIG_LOCK_SHIFT)
#define	SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK   (0x1U)
#define	SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT   (0U)
#define	SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET(x)   (((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK)
#define	SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET(x)   (((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT)
#define	SEC_VIOLATION_CONFIG_LOCK_NSC_MASK   (0x80000000UL)
#define	SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT   (31U)
#define	SEC_VIOLATION_CONFIG_LOCK_NSC_SET(x)   (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK)
#define	SEC_VIOLATION_CONFIG_LOCK_NSC_GET(x)   (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT)
#define	SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK   (0x7FFF0000UL)
#define	SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT   (16U)
#define	SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET(x)   (((uint32_t)(x) << SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK)
#define	SEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET(x)   (((uint32_t)(x) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT)
#define	SEC_VIOLATION_CONFIG_LOCK_SEC_MASK   (0x8000U)
#define	SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT   (15U)
#define	SEC_VIOLATION_CONFIG_LOCK_SEC_SET(x)   (((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK)
#define	SEC_VIOLATION_CONFIG_LOCK_SEC_GET(x)   (((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT)
#define	SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK   (0x7FFFU)
#define	SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT   (0U)
#define	SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET(x)   (((uint32_t)(x) << SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK)
#define	SEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET(x)   (((uint32_t)(x) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT)
#define	SEC_ESCALATE_CONFIG_LOCK_NSC_MASK   (0x80000000UL)
#define	SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT   (31U)
#define	SEC_ESCALATE_CONFIG_LOCK_NSC_SET(x)   (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK)
#define	SEC_ESCALATE_CONFIG_LOCK_NSC_GET(x)   (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT)
#define	SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK   (0x7FFF0000UL)
#define	SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT   (16U)
#define	SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET(x)   (((uint32_t)(x) << SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK)
#define	SEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET(x)   (((uint32_t)(x) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT)
#define	SEC_ESCALATE_CONFIG_LOCK_SEC_MASK   (0x8000U)
#define	SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT   (15U)
#define	SEC_ESCALATE_CONFIG_LOCK_SEC_SET(x)   (((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK)
#define	SEC_ESCALATE_CONFIG_LOCK_SEC_GET(x)   (((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT)
#define	SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK   (0x7FFFU)
#define	SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT   (0U)
#define	SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET(x)   (((uint32_t)(x) << SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK)
#define	SEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET(x)   (((uint32_t)(x) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT)
#define	SEC_EVENT_EVENT_MASK   (0xFFFF0000UL)
#define	SEC_EVENT_EVENT_SHIFT   (16U)
#define	SEC_EVENT_EVENT_GET(x)   (((uint32_t)(x) & SEC_EVENT_EVENT_MASK) >> SEC_EVENT_EVENT_SHIFT)
#define	SEC_EVENT_PMIC_ESC_NSC_MASK   (0x8U)
#define	SEC_EVENT_PMIC_ESC_NSC_SHIFT   (3U)
#define	SEC_EVENT_PMIC_ESC_NSC_GET(x)   (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_NSC_MASK) >> SEC_EVENT_PMIC_ESC_NSC_SHIFT)
#define	SEC_EVENT_PMIC_ESC_SEC_MASK   (0x4U)
#define	SEC_EVENT_PMIC_ESC_SEC_SHIFT   (2U)
#define	SEC_EVENT_PMIC_ESC_SEC_GET(x)   (((uint32_t)(x) & SEC_EVENT_PMIC_ESC_SEC_MASK) >> SEC_EVENT_PMIC_ESC_SEC_SHIFT)
#define	SEC_LIFECYCLE_LIFECYCLE_MASK   (0xFFU)
#define	SEC_LIFECYCLE_LIFECYCLE_SHIFT   (0U)
#define	SEC_LIFECYCLE_LIFECYCLE_GET(x)   (((uint32_t)(x) & SEC_LIFECYCLE_LIFECYCLE_MASK) >> SEC_LIFECYCLE_LIFECYCLE_SHIFT)

Macro Definition Documentation

SEC_ESCALATE_CONFIG_LOCK_NSC_GET

#define SEC_ESCALATE_CONFIG_LOCK_NSC_GET

(

x

)

(((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT)

SEC_ESCALATE_CONFIG_LOCK_NSC_MASK

#define SEC_ESCALATE_CONFIG_LOCK_NSC_MASK   (0x80000000UL)

SEC_ESCALATE_CONFIG_LOCK_NSC_SET

#define SEC_ESCALATE_CONFIG_LOCK_NSC_SET

(

x

)

(((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_NSC_MASK)

SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT

#define SEC_ESCALATE_CONFIG_LOCK_NSC_SHIFT   (31U)

SEC_ESCALATE_CONFIG_LOCK_SEC_GET

#define SEC_ESCALATE_CONFIG_LOCK_SEC_GET

(

x

)

(((uint32_t)(x) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK) >> SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT)

SEC_ESCALATE_CONFIG_LOCK_SEC_MASK

#define SEC_ESCALATE_CONFIG_LOCK_SEC_MASK   (0x8000U)

SEC_ESCALATE_CONFIG_LOCK_SEC_SET

#define SEC_ESCALATE_CONFIG_LOCK_SEC_SET

(

x

)

(((uint32_t)(x) << SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT) & SEC_ESCALATE_CONFIG_LOCK_SEC_MASK)

SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT

#define SEC_ESCALATE_CONFIG_LOCK_SEC_SHIFT   (15U)

SEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET

#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_GET

(

x

)

(((uint32_t)(x) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT)

SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK

#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK   (0x7FFF0000UL)

SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET

#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SET

(

x

)

(((uint32_t)(x) << SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_NSC_VIO_CFG_MASK)

SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT

#define SEC_ESCALATE_CONFIG_NSC_VIO_CFG_SHIFT   (16U)

SEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET

#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_GET

(

x

)

(((uint32_t)(x) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK) >> SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT)

SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK

#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK   (0x7FFFU)

SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET

#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SET

(

x

)

(((uint32_t)(x) << SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_ESCALATE_CONFIG_SEC_VIO_CFG_MASK)

SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT

#define SEC_ESCALATE_CONFIG_SEC_VIO_CFG_SHIFT   (0U)

SEC_EVENT_EVENT_GET

#define SEC_EVENT_EVENT_GET

(

x

)

(((uint32_t)(x) & SEC_EVENT_EVENT_MASK) >> SEC_EVENT_EVENT_SHIFT)

SEC_EVENT_EVENT_MASK

#define SEC_EVENT_EVENT_MASK   (0xFFFF0000UL)

SEC_EVENT_EVENT_SHIFT

#define SEC_EVENT_EVENT_SHIFT   (16U)

SEC_EVENT_PMIC_ESC_NSC_GET

#define SEC_EVENT_PMIC_ESC_NSC_GET

(

x

)

(((uint32_t)(x) & SEC_EVENT_PMIC_ESC_NSC_MASK) >> SEC_EVENT_PMIC_ESC_NSC_SHIFT)

SEC_EVENT_PMIC_ESC_NSC_MASK

#define SEC_EVENT_PMIC_ESC_NSC_MASK   (0x8U)

SEC_EVENT_PMIC_ESC_NSC_SHIFT

#define SEC_EVENT_PMIC_ESC_NSC_SHIFT   (3U)

SEC_EVENT_PMIC_ESC_SEC_GET

#define SEC_EVENT_PMIC_ESC_SEC_GET

(

x

)

(((uint32_t)(x) & SEC_EVENT_PMIC_ESC_SEC_MASK) >> SEC_EVENT_PMIC_ESC_SEC_SHIFT)

SEC_EVENT_PMIC_ESC_SEC_MASK

#define SEC_EVENT_PMIC_ESC_SEC_MASK   (0x4U)

SEC_EVENT_PMIC_ESC_SEC_SHIFT

#define SEC_EVENT_PMIC_ESC_SEC_SHIFT   (2U)

SEC_LIFECYCLE_LIFECYCLE_GET

#define SEC_LIFECYCLE_LIFECYCLE_GET

(

x

)

(((uint32_t)(x) & SEC_LIFECYCLE_LIFECYCLE_MASK) >> SEC_LIFECYCLE_LIFECYCLE_SHIFT)

SEC_LIFECYCLE_LIFECYCLE_MASK

#define SEC_LIFECYCLE_LIFECYCLE_MASK   (0xFFU)

SEC_LIFECYCLE_LIFECYCLE_SHIFT

#define SEC_LIFECYCLE_LIFECYCLE_SHIFT   (0U)

SEC_SECURE_STATE_ALLOW_NSC_GET

#define SEC_SECURE_STATE_ALLOW_NSC_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_NSC_MASK) >> SEC_SECURE_STATE_ALLOW_NSC_SHIFT)

SEC_SECURE_STATE_ALLOW_NSC_MASK

#define SEC_SECURE_STATE_ALLOW_NSC_MASK   (0x20000UL)

SEC_SECURE_STATE_ALLOW_NSC_SHIFT

#define SEC_SECURE_STATE_ALLOW_NSC_SHIFT   (17U)

SEC_SECURE_STATE_ALLOW_SEC_GET

#define SEC_SECURE_STATE_ALLOW_SEC_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_ALLOW_SEC_MASK) >> SEC_SECURE_STATE_ALLOW_SEC_SHIFT)

SEC_SECURE_STATE_ALLOW_SEC_MASK

#define SEC_SECURE_STATE_ALLOW_SEC_MASK   (0x10000UL)

SEC_SECURE_STATE_ALLOW_SEC_SHIFT

#define SEC_SECURE_STATE_ALLOW_SEC_SHIFT   (16U)

SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET

#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK) >> SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT)

SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK

#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK   (0x1U)

SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET

#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SET

(

x

)

(((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT) & SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_MASK)

SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT

#define SEC_SECURE_STATE_CONFIG_ALLOW_RESTART_SHIFT   (0U)

SEC_SECURE_STATE_CONFIG_LOCK_GET

#define SEC_SECURE_STATE_CONFIG_LOCK_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_CONFIG_LOCK_MASK) >> SEC_SECURE_STATE_CONFIG_LOCK_SHIFT)

SEC_SECURE_STATE_CONFIG_LOCK_MASK

#define SEC_SECURE_STATE_CONFIG_LOCK_MASK   (0x8U)

SEC_SECURE_STATE_CONFIG_LOCK_SET

#define SEC_SECURE_STATE_CONFIG_LOCK_SET

(

x

)

(((uint32_t)(x) << SEC_SECURE_STATE_CONFIG_LOCK_SHIFT) & SEC_SECURE_STATE_CONFIG_LOCK_MASK)

SEC_SECURE_STATE_CONFIG_LOCK_SHIFT

#define SEC_SECURE_STATE_CONFIG_LOCK_SHIFT   (3U)

SEC_SECURE_STATE_PMIC_FAIL_GET

#define SEC_SECURE_STATE_PMIC_FAIL_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_PMIC_FAIL_MASK) >> SEC_SECURE_STATE_PMIC_FAIL_SHIFT)

SEC_SECURE_STATE_PMIC_FAIL_MASK

#define SEC_SECURE_STATE_PMIC_FAIL_MASK   (0x80U)

SEC_SECURE_STATE_PMIC_FAIL_SET

#define SEC_SECURE_STATE_PMIC_FAIL_SET

(

x

)

(((uint32_t)(x) << SEC_SECURE_STATE_PMIC_FAIL_SHIFT) & SEC_SECURE_STATE_PMIC_FAIL_MASK)

SEC_SECURE_STATE_PMIC_FAIL_SHIFT

#define SEC_SECURE_STATE_PMIC_FAIL_SHIFT   (7U)

SEC_SECURE_STATE_PMIC_INS_GET

#define SEC_SECURE_STATE_PMIC_INS_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_PMIC_INS_MASK) >> SEC_SECURE_STATE_PMIC_INS_SHIFT)

SEC_SECURE_STATE_PMIC_INS_MASK

#define SEC_SECURE_STATE_PMIC_INS_MASK   (0x10U)

SEC_SECURE_STATE_PMIC_INS_SET

#define SEC_SECURE_STATE_PMIC_INS_SET

(

x

)

(((uint32_t)(x) << SEC_SECURE_STATE_PMIC_INS_SHIFT) & SEC_SECURE_STATE_PMIC_INS_MASK)

SEC_SECURE_STATE_PMIC_INS_SHIFT

#define SEC_SECURE_STATE_PMIC_INS_SHIFT   (4U)

SEC_SECURE_STATE_PMIC_NSC_GET

#define SEC_SECURE_STATE_PMIC_NSC_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_PMIC_NSC_MASK) >> SEC_SECURE_STATE_PMIC_NSC_SHIFT)

SEC_SECURE_STATE_PMIC_NSC_MASK

#define SEC_SECURE_STATE_PMIC_NSC_MASK   (0x40U)

SEC_SECURE_STATE_PMIC_NSC_SET

#define SEC_SECURE_STATE_PMIC_NSC_SET

(

x

)

(((uint32_t)(x) << SEC_SECURE_STATE_PMIC_NSC_SHIFT) & SEC_SECURE_STATE_PMIC_NSC_MASK)

SEC_SECURE_STATE_PMIC_NSC_SHIFT

#define SEC_SECURE_STATE_PMIC_NSC_SHIFT   (6U)

SEC_SECURE_STATE_PMIC_SEC_GET

#define SEC_SECURE_STATE_PMIC_SEC_GET

(

x

)

(((uint32_t)(x) & SEC_SECURE_STATE_PMIC_SEC_MASK) >> SEC_SECURE_STATE_PMIC_SEC_SHIFT)

SEC_SECURE_STATE_PMIC_SEC_MASK

#define SEC_SECURE_STATE_PMIC_SEC_MASK   (0x20U)

SEC_SECURE_STATE_PMIC_SEC_SET

#define SEC_SECURE_STATE_PMIC_SEC_SET

(

x

)

(((uint32_t)(x) << SEC_SECURE_STATE_PMIC_SEC_SHIFT) & SEC_SECURE_STATE_PMIC_SEC_MASK)

SEC_SECURE_STATE_PMIC_SEC_SHIFT

#define SEC_SECURE_STATE_PMIC_SEC_SHIFT   (5U)

SEC_VIOLATION_CONFIG_LOCK_NSC_GET

#define SEC_VIOLATION_CONFIG_LOCK_NSC_GET

(

x

)

(((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT)

SEC_VIOLATION_CONFIG_LOCK_NSC_MASK

#define SEC_VIOLATION_CONFIG_LOCK_NSC_MASK   (0x80000000UL)

SEC_VIOLATION_CONFIG_LOCK_NSC_SET

#define SEC_VIOLATION_CONFIG_LOCK_NSC_SET

(

x

)

(((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_NSC_MASK)

SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT

#define SEC_VIOLATION_CONFIG_LOCK_NSC_SHIFT   (31U)

SEC_VIOLATION_CONFIG_LOCK_SEC_GET

#define SEC_VIOLATION_CONFIG_LOCK_SEC_GET

(

x

)

(((uint32_t)(x) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK) >> SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT)

SEC_VIOLATION_CONFIG_LOCK_SEC_MASK

#define SEC_VIOLATION_CONFIG_LOCK_SEC_MASK   (0x8000U)

SEC_VIOLATION_CONFIG_LOCK_SEC_SET

#define SEC_VIOLATION_CONFIG_LOCK_SEC_SET

(

x

)

(((uint32_t)(x) << SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT) & SEC_VIOLATION_CONFIG_LOCK_SEC_MASK)

SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT

#define SEC_VIOLATION_CONFIG_LOCK_SEC_SHIFT   (15U)

SEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET

#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_GET

(

x

)

(((uint32_t)(x) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT)

SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK

#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK   (0x7FFF0000UL)

SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET

#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SET

(

x

)

(((uint32_t)(x) << SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_NSC_VIO_CFG_MASK)

SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT

#define SEC_VIOLATION_CONFIG_NSC_VIO_CFG_SHIFT   (16U)

SEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET

#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_GET

(

x

)

(((uint32_t)(x) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK) >> SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT)

SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK

#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK   (0x7FFFU)

SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET

#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SET

(

x

)

(((uint32_t)(x) << SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT) & SEC_VIOLATION_CONFIG_SEC_VIO_CFG_MASK)

SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT

#define SEC_VIOLATION_CONFIG_SEC_VIO_CFG_SHIFT   (0U)