HPM SDK
HPMicro Software Development Kit
hpm_sei_regs.h
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1 /*
2  * Copyright (c) 2021-2025 HPMicro
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 
9 #ifndef HPM_SEI_H
10 #define HPM_SEI_H
11 
12 typedef struct {
13  struct {
14  struct {
15  __RW uint32_t CTRL; /* 0x0: Engine control register */
16  __RW uint32_t PTR_CFG; /* 0x4: Pointer configuration register */
17  __RW uint32_t WDG_CFG; /* 0x8: Watch dog configuration register */
18  __R uint8_t RESERVED0[4]; /* 0xC - 0xF: Reserved */
19  __R uint32_t EXE_STA; /* 0x10: Execution status */
20  __R uint32_t EXE_PTR; /* 0x14: Execution pointer */
21  __R uint32_t EXE_INST; /* 0x18: Execution instruction */
22  __R uint32_t WDG_STA; /* 0x1C: Watch dog status */
23  } ENGINE;
24  struct {
25  __RW uint32_t CTRL; /* 0x20: Transceiver control register */
26  __RW uint32_t TYPE_CFG; /* 0x24: Transceiver configuration register */
27  __RW uint32_t BAUD_CFG; /* 0x28: Transceiver baud rate register */
28  __RW uint32_t DATA_CFG; /* 0x2C: Transceiver data timing configuration */
29  __RW uint32_t CLK_CFG; /* 0x30: Transceiver clock timing configuration */
30  __R uint8_t RESERVED0[4]; /* 0x34 - 0x37: Reserved */
31  __R uint32_t PIN; /* 0x38: Transceiver pin status */
32  __R uint32_t STATE; /* 0x3C: FSM of asynchronous */
33  } XCVR;
34  struct {
35  __RW uint32_t IN_CFG; /* 0x40: Trigger input configuration */
36  __W uint32_t SW; /* 0x44: Software trigger */
37  __RW uint32_t PRD_CFG; /* 0x48: Period trigger configuration */
38  __RW uint32_t PRD; /* 0x4C: Trigger period */
39  __RW uint32_t OUT_CFG; /* 0x50: Trigger output configuration */
40  __R uint8_t RESERVED0[12]; /* 0x54 - 0x5F: Reserved */
41  __R uint32_t PRD_STS; /* 0x60: Period trigger status */
42  __R uint32_t PRD_CNT; /* 0x64: Period trigger counter */
43  __R uint8_t RESERVED1[24]; /* 0x68 - 0x7F: Reserved */
44  } TRG;
45  struct {
46  __RW uint32_t CMD[4]; /* 0x80 - 0x8C: Trigger command */
47  __R uint8_t RESERVED0[16]; /* 0x90 - 0x9F: Reserved */
48  __R uint32_t TIME[4]; /* 0xA0 - 0xAC: Trigger Time */
49  __R uint8_t RESERVED1[16]; /* 0xB0 - 0xBF: Reserved */
50  } TRG_TABLE;
51  struct {
52  __RW uint32_t MODE; /* 0xC0: command register mode */
53  __RW uint32_t IDX; /* 0xC4: command register configuration */
54  __R uint8_t RESERVED0[24]; /* 0xC8 - 0xDF: Reserved */
55  __RW uint32_t CMD; /* 0xE0: command */
56  __RW uint32_t SET; /* 0xE4: command bit set register */
57  __RW uint32_t CLR; /* 0xE8: command bit clear register */
58  __RW uint32_t INV; /* 0xEC: command bit invert register */
59  __R uint32_t IN; /* 0xF0: Commad input */
60  __R uint32_t OUT; /* 0xF4: Command output */
61  __RW uint32_t STS; /* 0xF8: Command status */
62  __R uint8_t RESERVED1[4]; /* 0xFC - 0xFF: Reserved */
63  } CMD;
64  struct {
65  __RW uint32_t MIN; /* 0x100: command start value */
66  __RW uint32_t MAX; /* 0x104: command end value */
67  __RW uint32_t MSK; /* 0x108: command compare bit enable */
68  __R uint8_t RESERVED0[4]; /* 0x10C - 0x10F: Reserved */
69  __RW uint32_t PTA; /* 0x110: command pointer 0 - 3 */
70  __RW uint32_t PTB; /* 0x114: command pointer 4 - 7 */
71  __R uint8_t RESERVED1[8]; /* 0x118 - 0x11F: Reserved */
72  } CMD_TABLE[8];
73  struct {
74  __RW uint32_t TRAN[4]; /* 0x200 - 0x20C: Latch state transition configuration */
75  __RW uint32_t CFG; /* 0x210: Latch configuration */
76  __R uint8_t RESERVED0[4]; /* 0x214 - 0x217: Reserved */
77  __R uint32_t TIME; /* 0x218: Latch time */
78  __R uint32_t STS; /* 0x21C: Latch status */
79  } LATCH[4];
80  struct {
81  __RW uint32_t SMP_EN; /* 0x280: Sample selection register */
82  __RW uint32_t SMP_CFG; /* 0x284: Sample configuration */
83  __RW uint32_t SMP_DAT; /* 0x288: Sample data */
84  __R uint8_t RESERVED0[4]; /* 0x28C - 0x28F: Reserved */
85  __RW uint32_t SMP_POS; /* 0x290: Sample override position */
86  __RW uint32_t SMP_REV; /* 0x294: Sample override revolution */
87  __RW uint32_t SMP_SPD; /* 0x298: Sample override speed */
88  __RW uint32_t SMP_ACC; /* 0x29C: Sample override accelerate */
89  __RW uint32_t UPD_EN; /* 0x2A0: Update configuration */
90  __RW uint32_t UPD_CFG; /* 0x2A4: Update configuration */
91  __RW uint32_t UPD_DAT; /* 0x2A8: Update data */
92  __RW uint32_t UPD_TIME; /* 0x2AC: Update overide time */
93  __RW uint32_t UPD_POS; /* 0x2B0: Update override position */
94  __RW uint32_t UPD_REV; /* 0x2B4: Update override revolution */
95  __RW uint32_t UPD_SPD; /* 0x2B8: Update override speed */
96  __RW uint32_t UPD_ACC; /* 0x2BC: Update override accelerate */
97  __R uint32_t SMP_VAL; /* 0x2C0: Sample valid */
98  __R uint32_t SMP_STS; /* 0x2C4: Sample status */
99  __R uint8_t RESERVED1[4]; /* 0x2C8 - 0x2CB: Reserved */
100  __R uint32_t TIME_IN; /* 0x2CC: input time */
101  __R uint32_t POS_IN; /* 0x2D0: Input position */
102  __R uint32_t REV_IN; /* 0x2D4: Input revolution */
103  __R uint32_t SPD_IN; /* 0x2D8: Input speed */
104  __R uint32_t ACC_IN; /* 0x2DC: Input accelerate */
105  __R uint8_t RESERVED2[4]; /* 0x2E0 - 0x2E3: Reserved */
106  __R uint32_t UPD_STS; /* 0x2E4: Update status */
107  __R uint8_t RESERVED3[24]; /* 0x2E8 - 0x2FF: Reserved */
108  } POS;
109  struct {
110  __RW uint32_t INT_EN; /* 0x300: Interrupt Enable */
111  __W uint32_t INT_FLAG; /* 0x304: Interrupt flag */
112  __R uint32_t INT_STS; /* 0x308: Interrupt status */
113  __R uint8_t RESERVED0[4]; /* 0x30C - 0x30F: Reserved */
114  __RW uint32_t POINTER0; /* 0x310: Match pointer 0 */
115  __RW uint32_t POINTER1; /* 0x314: Match pointer 1 */
116  __RW uint32_t INSTR0; /* 0x318: Match instruction 0 */
117  __RW uint32_t INSTR1; /* 0x31C: Match instruction 1 */
118  } IRQ;
119  __RW uint32_t DMA_EN; /* 0x320: DMA Enable */
120  __R uint8_t RESERVED0[220]; /* 0x324 - 0x3FF: Reserved */
121  } CTRL[2];
122  __R uint8_t RESERVED0[11264]; /* 0x800 - 0x33FF: Reserved */
123  __RW uint32_t INSTR[64]; /* 0x3400 - 0x34FC: Instructions */
124  __R uint8_t RESERVED1[768]; /* 0x3500 - 0x37FF: Reserved */
125  struct {
126  __RW uint32_t MODE; /* 0x3800: */
127  __RW uint32_t IDX; /* 0x3804: Data register bit index */
128  __RW uint32_t GOLD; /* 0x3808: Gold data for data check */
129  __RW uint32_t CRCINIT; /* 0x380C: CRC calculation initial vector */
130  __RW uint32_t CRCPOLY; /* 0x3810: CRC calculation polynomial */
131  __R uint8_t RESERVED0[12]; /* 0x3814 - 0x381F: Reserved */
132  __RW uint32_t DATA; /* 0x3820: Data value */
133  __RW uint32_t SET; /* 0x3824: Data bit set */
134  __RW uint32_t CLR; /* 0x3828: Data bit clear */
135  __RW uint32_t INV; /* 0x382C: Data bit invert */
136  __R uint32_t IN; /* 0x3830: Data input */
137  __R uint32_t OUT; /* 0x3834: Data output */
138  __RW uint32_t STS; /* 0x3838: Data status */
139  __R uint8_t RESERVED1[4]; /* 0x383C - 0x383F: Reserved */
140  } DAT[10];
141 } SEI_Type;
142 
143 
144 /* Bitfield definition for register of struct array CTRL: CTRL */
145 /*
146  * WATCH (RW)
147  *
148  * Enable watch dog
149  * 0: Watch dog disabled
150  * 1: Watch dog enabled
151  */
152 #define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL)
153 #define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U)
154 #define SEI_CTRL_ENGINE_CTRL_WATCH_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK)
155 #define SEI_CTRL_ENGINE_CTRL_WATCH_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT)
156 
157 /*
158  * ARMING (RW)
159  *
160  * Wait for trigger before excuting
161  * 0: Execute on enable
162  * 1: Wait trigger before exection after enabled
163  */
164 #define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL)
165 #define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U)
166 #define SEI_CTRL_ENGINE_CTRL_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK)
167 #define SEI_CTRL_ENGINE_CTRL_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT)
168 
169 /*
170  * EXCEPT (RW)
171  *
172  * Explain timout as exception
173  * 0: when timeout, pointer move to next instruction
174  * 1: when timeout, pointer jump to timeout vector
175  */
176 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U)
177 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U)
178 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK)
179 #define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT)
180 
181 /*
182  * REWIND (RW)
183  *
184  * Rewind execution pointer
185  * 0: run
186  * 1: clean status and rewind
187  */
188 #define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U)
189 #define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U)
190 #define SEI_CTRL_ENGINE_CTRL_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK)
191 #define SEI_CTRL_ENGINE_CTRL_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT)
192 
193 /*
194  * ENABLE (RW)
195  *
196  * Enable
197  * 0: disable
198  * 1: enable
199  */
200 #define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U)
201 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U)
202 #define SEI_CTRL_ENGINE_CTRL_ENABLE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK)
203 #define SEI_CTRL_ENGINE_CTRL_ENABLE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT)
204 
205 /* Bitfield definition for register of struct array CTRL: PTR_CFG */
206 /*
207  * DAT_CDM (RW)
208  *
209  * Select DATA register to receive CDM bit in BiSSC slave mode
210  * 0: ignore
211  * 1: command
212  * 2: data register 2
213  * 3: data register 3
214  * ...
215  * 29:data register 29
216  * 30: value 0 when send, ignore in receive
217  * 31: value1 when send, ignore in receive
218  */
219 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL)
220 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U)
221 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK)
222 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT)
223 
224 /*
225  * DAT_BASE (RW)
226  *
227  * Bias for data register access, if calculated index bigger than 32, index will wrap around
228  * 0: real data index
229  * 1: access index is 1 greater than instruction address
230  * 2: access index is 2 greater than instruction address
231  * ...
232  * 31: access index is 31 greater than instruction address
233  */
234 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL)
235 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U)
236 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK)
237 #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT)
238 
239 /*
240  * POINTER_WDOG (RW)
241  *
242  * Pointer to the instruction that the program starts executing after the instruction timeout. The timeout is WDOG_TIME
243  */
244 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U)
245 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U)
246 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK)
247 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT)
248 
249 /*
250  * POINTER_INIT (RW)
251  *
252  * Initial execute pointer
253  */
254 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU)
255 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U)
256 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK)
257 #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT)
258 
259 /* Bitfield definition for register of struct array CTRL: WDG_CFG */
260 /*
261  * WDOG_TIME (RW)
262  *
263  * Time out count for each instruction, counter in bit time.
264  */
265 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU)
266 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U)
267 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK)
268 #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT)
269 
270 /* Bitfield definition for register of struct array CTRL: EXE_STA */
271 /*
272  * TRIGERED (RO)
273  *
274  * Execution has been triggered
275  * 0: Execution not triggered
276  * 1: Execution triggered
277  */
278 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL)
279 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U)
280 #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT)
281 
282 /*
283  * ARMED (RO)
284  *
285  * Waiting for trigger for execution
286  * 0: Not in waiting status
287  * 1: In waiting status
288  */
289 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL)
290 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U)
291 #define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT)
292 
293 /*
294  * EXPIRE (RO)
295  *
296  * Watchdog timer expired
297  * 0: Not expired
298  * 1: Expired
299  */
300 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U)
301 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U)
302 #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT)
303 
304 /*
305  * STALL (RO)
306  *
307  * Program finished
308  * 0: Program is executing
309  * 1: Program finished
310  */
311 #define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U)
312 #define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U)
313 #define SEI_CTRL_ENGINE_EXE_STA_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT)
314 
315 /* Bitfield definition for register of struct array CTRL: EXE_PTR */
316 /*
317  * HALT_CNT (RO)
318  *
319  * Halt count in halt instrution
320  */
321 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL)
322 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U)
323 #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT)
324 
325 /*
326  * BIT_CNT (RO)
327  *
328  * Bit count in send and receive instruction execution
329  */
330 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL)
331 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U)
332 #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT)
333 
334 /*
335  * POINTER (RO)
336  *
337  * Current program pointer
338  */
339 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU)
340 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U)
341 #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT)
342 
343 /* Bitfield definition for register of struct array CTRL: EXE_INST */
344 /*
345  * INST (RO)
346  *
347  * Current instruction
348  */
349 #define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL)
350 #define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U)
351 #define SEI_CTRL_ENGINE_EXE_INST_INST_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT)
352 
353 /* Bitfield definition for register of struct array CTRL: WDG_STA */
354 /*
355  * WDOG_CNT (RO)
356  *
357  * Current watch dog counter value
358  */
359 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU)
360 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U)
361 #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT)
362 
363 /* Bitfield definition for register of struct array CTRL: CTRL */
364 /*
365  * TRISMP (RW)
366  *
367  * Tipple sampe
368  * 0: sample 1 time for data transition
369  * 1: sample 3 times in receive and result in 2oo3
370  */
371 #define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U)
372 #define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U)
373 #define SEI_CTRL_XCVR_CTRL_TRISMP_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK)
374 #define SEI_CTRL_XCVR_CTRL_TRISMP_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT)
375 
376 /*
377  * PAR_CLR (WC)
378  *
379  * Clear parity error, this is a self clear bit
380  * 0: no effect
381  * 1: clear parity error
382  */
383 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U)
384 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U)
385 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK)
386 #define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT)
387 
388 /*
389  * RESTART (WC)
390  *
391  * Restart transceiver, this is a self clear bit
392  * 0: no effect
393  * 1: reset transceiver
394  */
395 #define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U)
396 #define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U)
397 #define SEI_CTRL_XCVR_CTRL_RESTART_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK)
398 #define SEI_CTRL_XCVR_CTRL_RESTART_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT)
399 
400 /*
401  * MODE (RW)
402  *
403  * Transceiver mode
404  * 0: synchronous maaster
405  * 1: synchronous slave
406  * 2: asynchronous mode
407  * 3: asynchronous mode
408  */
409 #define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U)
410 #define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U)
411 #define SEI_CTRL_XCVR_CTRL_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK)
412 #define SEI_CTRL_XCVR_CTRL_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT)
413 
414 /* Bitfield definition for register of struct array CTRL: TYPE_CFG */
415 /*
416  * WAIT_LEN (RW)
417  *
418  * Number of extra stop bit for asynchronous mode
419  * 0: 1 bit
420  * 1: 2 bit
421  * ...
422  * 255: 256 bit
423  */
424 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL)
425 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U)
426 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK)
427 #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT)
428 
429 /*
430  * DATA_LEN (RW)
431  *
432  * Number of data bit for asynchronous mode
433  * 0: 1 bit
434  * 1: 2 bit
435  * ...
436  * 31: 32 bit
437  */
438 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL)
439 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U)
440 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK)
441 #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT)
442 
443 /*
444  * PAR_POL (RW)
445  *
446  * Polarity of parity for asynchronous mode
447  * 0: even
448  * 1: odd
449  */
450 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U)
451 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U)
452 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK)
453 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT)
454 
455 /*
456  * PAR_EN (RW)
457  *
458  * enable parity check for asynchronous mode
459  * 0: disable
460  * 1: enable
461  */
462 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U)
463 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U)
464 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK)
465 #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT)
466 
467 /*
468  * DA_IDLEZ (RW)
469  *
470  * Idle state driver of data line
471  * 0: output
472  * 1: high-Z
473  */
474 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U)
475 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U)
476 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK)
477 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT)
478 
479 /*
480  * CK_IDLEZ (RW)
481  *
482  * Idle state driver of clock line
483  * 0: output
484  * 1: high-Z
485  */
486 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U)
487 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U)
488 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK)
489 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT)
490 
491 /*
492  * DA_IDLEV (RW)
493  *
494  * Idle state value of data line
495  * 0: data'0'
496  * 1: data'1'
497  */
498 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U)
499 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U)
500 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK)
501 #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT)
502 
503 /*
504  * CK_IDLEV (RW)
505  *
506  * Idle state value of clock line
507  * 0: data'0'
508  * 1: data'1'
509  */
510 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U)
511 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U)
512 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK)
513 #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT)
514 
515 /* Bitfield definition for register of struct array CTRL: BAUD_CFG */
516 /*
517  * SYNC_POINT (RW)
518  *
519  * Baud synchronous time, minmum bit time
520  */
521 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL)
522 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U)
523 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK)
524 #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT)
525 
526 /*
527  * BAUD_DIV (RW)
528  *
529  * Baud rate, bit time in system clock cycle
530  */
531 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU)
532 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U)
533 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK)
534 #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT)
535 
536 /* Bitfield definition for register of struct array CTRL: DATA_CFG */
537 /*
538  * TXD_POINT (RW)
539  *
540  * data transmit point in system clcok cycle
541  */
542 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL)
543 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U)
544 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK)
545 #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT)
546 
547 /*
548  * RXD_POINT (RW)
549  *
550  * data receive point in system clcok cycle
551  */
552 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU)
553 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U)
554 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK)
555 #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT)
556 
557 /* Bitfield definition for register of struct array CTRL: CLK_CFG */
558 /*
559  * CK1_POINT (RW)
560  *
561  * clock point 1 in system clcok cycle
562  */
563 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL)
564 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U)
565 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK)
566 #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT)
567 
568 /*
569  * CK0_POINT (RW)
570  *
571  * clock point 0 in system clcok cycle
572  */
573 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU)
574 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U)
575 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET(x) (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK)
576 #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT)
577 
578 /* Bitfield definition for register of struct array CTRL: PIN */
579 /*
580  * OE_CK (RO)
581  *
582  * CK drive state
583  * 0: input
584  * 1: output
585  */
586 #define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL)
587 #define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U)
588 #define SEI_CTRL_XCVR_PIN_OE_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT)
589 
590 /*
591  * DI_CK (RO)
592  *
593  * CK state
594  * 0: data 0
595  * 1: data 1
596  */
597 #define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL)
598 #define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U)
599 #define SEI_CTRL_XCVR_PIN_DI_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT)
600 
601 /*
602  * DO_CK (RO)
603  *
604  * CK output
605  * 0: data 0
606  * 1: data 1
607  */
608 #define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL)
609 #define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U)
610 #define SEI_CTRL_XCVR_PIN_DO_CK_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT)
611 
612 /*
613  * OE_RX (RO)
614  *
615  * RX drive state
616  * 0: input
617  * 1: output
618  */
619 #define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL)
620 #define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U)
621 #define SEI_CTRL_XCVR_PIN_OE_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT)
622 
623 /*
624  * DI_RX (RO)
625  *
626  * RX state
627  * 0: data 0
628  * 1: data 1
629  */
630 #define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL)
631 #define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U)
632 #define SEI_CTRL_XCVR_PIN_DI_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT)
633 
634 /*
635  * DO_RX (RO)
636  *
637  * RX output
638  * 0: data 0
639  * 1: data 1
640  */
641 #define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL)
642 #define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U)
643 #define SEI_CTRL_XCVR_PIN_DO_RX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT)
644 
645 /*
646  * OE_DE (RO)
647  *
648  * DE drive state
649  * 0: input
650  * 1: output
651  */
652 #define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U)
653 #define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U)
654 #define SEI_CTRL_XCVR_PIN_OE_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT)
655 
656 /*
657  * DI_DE (RO)
658  *
659  * DE state
660  * 0: data 0
661  * 1: data 1
662  */
663 #define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U)
664 #define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U)
665 #define SEI_CTRL_XCVR_PIN_DI_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT)
666 
667 /*
668  * DO_DE (RO)
669  *
670  * DE output
671  * 0: data 0
672  * 1: data 1
673  */
674 #define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U)
675 #define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U)
676 #define SEI_CTRL_XCVR_PIN_DO_DE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT)
677 
678 /*
679  * OE_TX (RO)
680  *
681  * TX drive state
682  * 0: input
683  * 1: output
684  */
685 #define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U)
686 #define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U)
687 #define SEI_CTRL_XCVR_PIN_OE_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT)
688 
689 /*
690  * DI_TX (RO)
691  *
692  * TX state
693  * 0: data 0
694  * 1: data 1
695  */
696 #define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U)
697 #define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U)
698 #define SEI_CTRL_XCVR_PIN_DI_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT)
699 
700 /*
701  * DO_TX (RO)
702  *
703  * TX output
704  * 0: data 0
705  * 1: data 1
706  */
707 #define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U)
708 #define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U)
709 #define SEI_CTRL_XCVR_PIN_DO_TX_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT)
710 
711 /* Bitfield definition for register of struct array CTRL: STATE */
712 /*
713  * RECV_STATE (RO)
714  *
715  * FSM of asynchronous receive
716  */
717 #define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL)
718 #define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U)
719 #define SEI_CTRL_XCVR_STATE_RECV_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT)
720 
721 /*
722  * SEND_STATE (RO)
723  *
724  * FSM of asynchronous transmit
725  */
726 #define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL)
727 #define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U)
728 #define SEI_CTRL_XCVR_STATE_SEND_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT)
729 
730 /* Bitfield definition for register of struct array CTRL: IN_CFG */
731 /*
732  * PRD_EN (RW)
733  *
734  * Enable period trigger (tigger 2)
735  * 0: periodical trigger disabled
736  * 1: periodical trigger enabled
737  */
738 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL)
739 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U)
740 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK)
741 #define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT)
742 
743 /*
744  * SYNC_SEL (RW)
745  *
746  * Synchronize sigal selection (tigger 2)
747  * 0: trigger in 0
748  * 1: trigger in 1
749  * ...
750  * 7: trigger in 7
751  */
752 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL)
753 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U)
754 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK)
755 #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT)
756 
757 /*
758  * IN1_EN (RW)
759  *
760  * Enable trigger 1
761  * 0: disable trigger 1
762  * 1: enable trigger 1
763  */
764 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U)
765 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U)
766 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK)
767 #define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT)
768 
769 /*
770  * IN1_SEL (RW)
771  *
772  * Trigger 1 sigal selection
773  * 0: trigger in 0
774  * 1: trigger in 1
775  * ...
776  * 7: trigger in 7
777  */
778 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U)
779 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U)
780 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK)
781 #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT)
782 
783 /*
784  * IN0_EN (RW)
785  *
786  * Enable trigger 0
787  * 0: disable trigger 1
788  * 1: enable trigger 1
789  */
790 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U)
791 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U)
792 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK)
793 #define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT)
794 
795 /*
796  * IN0_SEL (RW)
797  *
798  * Trigger 0 sigal selection
799  * 0: trigger in 0
800  * 1: trigger in 1
801  * ...
802  * 7: trigger in 7
803  */
804 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U)
805 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U)
806 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK)
807 #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT)
808 
809 /* Bitfield definition for register of struct array CTRL: SW */
810 /*
811  * SOFT (WC)
812  *
813  * Software trigger (tigger 3). this bit is self-clear
814  * 0: trigger source disabled
815  * 1: trigger source enabled
816  */
817 #define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U)
818 #define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U)
819 #define SEI_CTRL_TRG_SW_SOFT_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK)
820 #define SEI_CTRL_TRG_SW_SOFT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT)
821 
822 /* Bitfield definition for register of struct array CTRL: PRD_CFG */
823 /*
824  * ARMING (RW)
825  *
826  * Wait for trigger synchronous before trigger
827  * 0: Trigger directly
828  * 1: Wait trigger source before period trigger
829  */
830 #define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL)
831 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U)
832 #define SEI_CTRL_TRG_PRD_CFG_ARMING_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK)
833 #define SEI_CTRL_TRG_PRD_CFG_ARMING_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT)
834 
835 /*
836  * SYNC (RW)
837  *
838  * Synchronous
839  * 0: Not synchronous
840  * 1: Synchronous every trigger source
841  */
842 #define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U)
843 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U)
844 #define SEI_CTRL_TRG_PRD_CFG_SYNC_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK)
845 #define SEI_CTRL_TRG_PRD_CFG_SYNC_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT)
846 
847 /* Bitfield definition for register of struct array CTRL: PRD */
848 /*
849  * PERIOD (RW)
850  *
851  * Trigger period
852  */
853 #define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL)
854 #define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U)
855 #define SEI_CTRL_TRG_PRD_PERIOD_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK)
856 #define SEI_CTRL_TRG_PRD_PERIOD_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT)
857 
858 /* Bitfield definition for register of struct array CTRL: OUT_CFG */
859 /*
860  * OUT3_EN (RW)
861  *
862  * Enable trigger 3
863  * 0: disable trigger 3
864  * 1: enable trigger 3
865  */
866 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL)
867 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U)
868 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK)
869 #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT)
870 
871 /*
872  * OUT3_SEL (RW)
873  *
874  * Trigger 3 sigal selection
875  * 0: trigger out 0
876  * 1: trigger out 1
877  * ...
878  * 7: trigger out 7
879  */
880 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL)
881 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U)
882 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK)
883 #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT)
884 
885 /*
886  * OUT2_EN (RW)
887  *
888  * Enable trigger 2
889  * 0: disable trigger 2
890  * 1: enable trigger 2
891  */
892 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL)
893 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U)
894 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK)
895 #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT)
896 
897 /*
898  * OUT2_SEL (RW)
899  *
900  * Trigger 2 sigal selection
901  * 0: trigger out 0
902  * 1: trigger out 1
903  * ...
904  * 7: trigger out 7
905  */
906 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL)
907 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U)
908 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK)
909 #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT)
910 
911 /*
912  * OUT1_EN (RW)
913  *
914  * Enable trigger 1
915  * 0: disable trigger 1
916  * 1: enable trigger 1
917  */
918 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U)
919 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U)
920 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK)
921 #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT)
922 
923 /*
924  * OUT1_SEL (RW)
925  *
926  * Trigger 1 sigal selection
927  * 0: trigger out 0
928  * 1: trigger out 1
929  * ...
930  * 7: trigger out 7
931  */
932 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U)
933 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U)
934 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK)
935 #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT)
936 
937 /*
938  * OUT0_EN (RW)
939  *
940  * Enable trigger 0
941  * 0: disable trigger 1
942  * 1: enable trigger 1
943  */
944 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U)
945 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U)
946 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK)
947 #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT)
948 
949 /*
950  * OUT0_SEL (RW)
951  *
952  * Trigger 0 sigal selection
953  * 0: trigger out 0
954  * 1: trigger out 1
955  * ...
956  * 7: trigger out 7
957  */
958 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U)
959 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U)
960 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK)
961 #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT)
962 
963 /* Bitfield definition for register of struct array CTRL: PRD_STS */
964 /*
965  * TRIGERED (RO)
966  *
967  * Period has been triggered
968  * 0: Not triggered
969  * 1: Triggered
970  */
971 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL)
972 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U)
973 #define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT)
974 
975 /*
976  * ARMED (RO)
977  *
978  * Waiting for trigger
979  * 0: Not in waiting status
980  * 1: In waiting status
981  */
982 #define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL)
983 #define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U)
984 #define SEI_CTRL_TRG_PRD_STS_ARMED_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT)
985 
986 /* Bitfield definition for register of struct array CTRL: PRD_CNT */
987 /*
988  * PERIOD_CNT (RO)
989  *
990  * Trigger period counter
991  */
992 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL)
993 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U)
994 #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT)
995 
996 /* Bitfield definition for register of struct array CTRL: 0 */
997 /*
998  * CMD_TRIGGER0 (RW)
999  *
1000  * Trigger command
1001  */
1002 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL)
1003 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U)
1004 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK)
1005 #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT)
1006 
1007 /* Bitfield definition for register of struct array CTRL: 0 */
1008 /*
1009  * TRIGGER0_TIME (RO)
1010  *
1011  * Trigger time
1012  */
1013 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL)
1014 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U)
1015 #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT)
1016 
1017 /* Bitfield definition for register of struct array CTRL: MODE */
1018 /*
1019  * WLEN (RW)
1020  *
1021  * word length
1022  * 0: 1 bit
1023  * 1: 2 bit
1024  * ...
1025  * 31: 32 bit
1026  */
1027 #define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL)
1028 #define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U)
1029 #define SEI_CTRL_CMD_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK)
1030 #define SEI_CTRL_CMD_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT)
1031 
1032 /*
1033  * WORDER (RW)
1034  *
1035  * word order
1036  * 0: sample as bit order
1037  * 1: different from bit order
1038  */
1039 #define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U)
1040 #define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U)
1041 #define SEI_CTRL_CMD_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK)
1042 #define SEI_CTRL_CMD_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT)
1043 
1044 /*
1045  * BORDER (RW)
1046  *
1047  * bit order
1048  * 0: LSB first
1049  * 1: MSB first
1050  */
1051 #define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U)
1052 #define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U)
1053 #define SEI_CTRL_CMD_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK)
1054 #define SEI_CTRL_CMD_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT)
1055 
1056 /*
1057  * SIGNED (RW)
1058  *
1059  * Signed
1060  * 0: unsigned value
1061  * 1: signed value
1062  */
1063 #define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U)
1064 #define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U)
1065 #define SEI_CTRL_CMD_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK)
1066 #define SEI_CTRL_CMD_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT)
1067 
1068 /*
1069  * REWIND (WC)
1070  *
1071  * Write 1 to rewind read/write pointer, this is a self clear bit
1072  */
1073 #define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U)
1074 #define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U)
1075 #define SEI_CTRL_CMD_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK)
1076 #define SEI_CTRL_CMD_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT)
1077 
1078 /*
1079  * MODE (RW)
1080  *
1081  * Data mode(CMD register only support data mode)
1082  * 0: data mode
1083  * 1: check mode
1084  * 2: CRC mode
1085  */
1086 #define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U)
1087 #define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U)
1088 #define SEI_CTRL_CMD_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK)
1089 #define SEI_CTRL_CMD_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT)
1090 
1091 /* Bitfield definition for register of struct array CTRL: IDX */
1092 /*
1093  * LAST_BIT (RW)
1094  *
1095  * Last bit index for tranceive
1096  */
1097 #define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL)
1098 #define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U)
1099 #define SEI_CTRL_CMD_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK)
1100 #define SEI_CTRL_CMD_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT)
1101 
1102 /*
1103  * FIRST_BIT (RW)
1104  *
1105  * First bit index for tranceive
1106  */
1107 #define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL)
1108 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U)
1109 #define SEI_CTRL_CMD_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK)
1110 #define SEI_CTRL_CMD_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT)
1111 
1112 /*
1113  * MAX_BIT (RW)
1114  *
1115  * Highest bit index
1116  */
1117 #define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U)
1118 #define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U)
1119 #define SEI_CTRL_CMD_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK)
1120 #define SEI_CTRL_CMD_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT)
1121 
1122 /*
1123  * MIN_BIT (RW)
1124  *
1125  * Lowest bit index
1126  */
1127 #define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU)
1128 #define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U)
1129 #define SEI_CTRL_CMD_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK)
1130 #define SEI_CTRL_CMD_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT)
1131 
1132 /* Bitfield definition for register of struct array CTRL: CMD */
1133 /*
1134  * DATA (RW)
1135  *
1136  * DATA
1137  */
1138 #define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL)
1139 #define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U)
1140 #define SEI_CTRL_CMD_CMD_DATA_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK)
1141 #define SEI_CTRL_CMD_CMD_DATA_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT)
1142 
1143 /* Bitfield definition for register of struct array CTRL: SET */
1144 /*
1145  * DATA_SET (RW)
1146  *
1147  * DATA bit set
1148  */
1149 #define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL)
1150 #define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U)
1151 #define SEI_CTRL_CMD_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK)
1152 #define SEI_CTRL_CMD_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT)
1153 
1154 /* Bitfield definition for register of struct array CTRL: CLR */
1155 /*
1156  * DATA_CLR (RW)
1157  *
1158  * DATA bit clear
1159  */
1160 #define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
1161 #define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U)
1162 #define SEI_CTRL_CMD_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK)
1163 #define SEI_CTRL_CMD_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT)
1164 
1165 /* Bitfield definition for register of struct array CTRL: INV */
1166 /*
1167  * DATA_TGL (RW)
1168  *
1169  * DATA bit toggle
1170  */
1171 #define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL)
1172 #define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U)
1173 #define SEI_CTRL_CMD_INV_DATA_TGL_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK)
1174 #define SEI_CTRL_CMD_INV_DATA_TGL_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT)
1175 
1176 /* Bitfield definition for register of struct array CTRL: IN */
1177 /*
1178  * DATA_IN (RO)
1179  *
1180  * Commad input
1181  */
1182 #define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL)
1183 #define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U)
1184 #define SEI_CTRL_CMD_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT)
1185 
1186 /* Bitfield definition for register of struct array CTRL: OUT */
1187 /*
1188  * DATA_OUT (RO)
1189  *
1190  * Command output
1191  */
1192 #define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
1193 #define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U)
1194 #define SEI_CTRL_CMD_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT)
1195 
1196 /* Bitfield definition for register of struct array CTRL: STS */
1197 /*
1198  * WORD_IDX (RO)
1199  *
1200  * Word index
1201  */
1202 #define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL)
1203 #define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U)
1204 #define SEI_CTRL_CMD_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT)
1205 
1206 /*
1207  * WORD_CNT (RO)
1208  *
1209  * Word counter
1210  */
1211 #define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U)
1212 #define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U)
1213 #define SEI_CTRL_CMD_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT)
1214 
1215 /*
1216  * BIT_IDX (RO)
1217  *
1218  * Bit index
1219  */
1220 #define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU)
1221 #define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U)
1222 #define SEI_CTRL_CMD_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT)
1223 
1224 /* Bitfield definition for register of struct array CTRL: MIN */
1225 /*
1226  * CMD_MIN (RW)
1227  *
1228  * minimum command value
1229  */
1230 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL)
1231 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U)
1232 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK)
1233 #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT)
1234 
1235 /* Bitfield definition for register of struct array CTRL: MAX */
1236 /*
1237  * CMD_MAX (RW)
1238  *
1239  * maximum command value
1240  */
1241 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL)
1242 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U)
1243 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK)
1244 #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT)
1245 
1246 /* Bitfield definition for register of struct array CTRL: MSK */
1247 /*
1248  * CMD_MASK (RW)
1249  *
1250  * compare mask
1251  */
1252 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL)
1253 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U)
1254 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK)
1255 #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT)
1256 
1257 /* Bitfield definition for register of struct array CTRL: PTA */
1258 /*
1259  * PTR3 (RW)
1260  *
1261  * pointer3
1262  */
1263 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL)
1264 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U)
1265 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK)
1266 #define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT)
1267 
1268 /*
1269  * PTR2 (RW)
1270  *
1271  * pointer2
1272  */
1273 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL)
1274 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U)
1275 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK)
1276 #define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT)
1277 
1278 /*
1279  * PTR1 (RW)
1280  *
1281  * pointer1
1282  */
1283 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U)
1284 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U)
1285 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK)
1286 #define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT)
1287 
1288 /*
1289  * PTR0 (RW)
1290  *
1291  * pointer0
1292  */
1293 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU)
1294 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U)
1295 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK)
1296 #define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT)
1297 
1298 /* Bitfield definition for register of struct array CTRL: PTB */
1299 /*
1300  * PTR7 (RW)
1301  *
1302  * pointer7
1303  */
1304 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL)
1305 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U)
1306 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK)
1307 #define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT)
1308 
1309 /*
1310  * PTR6 (RW)
1311  *
1312  * pointer6
1313  */
1314 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL)
1315 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U)
1316 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK)
1317 #define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT)
1318 
1319 /*
1320  * PTR5 (RW)
1321  *
1322  * pointer5
1323  */
1324 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U)
1325 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U)
1326 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK)
1327 #define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT)
1328 
1329 /*
1330  * PTR4 (RW)
1331  *
1332  * pointer4
1333  */
1334 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU)
1335 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U)
1336 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET(x) (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK)
1337 #define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET(x) (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT)
1338 
1339 /* Bitfield definition for register of struct array CTRL: 0_1 */
1340 /*
1341  * POINTER (RW)
1342  *
1343  * pointer
1344  */
1345 #define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL)
1346 #define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U)
1347 #define SEI_CTRL_LATCH_TRAN_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK)
1348 #define SEI_CTRL_LATCH_TRAN_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT)
1349 
1350 /*
1351  * CFG_TM (RW)
1352  *
1353  * timeout
1354  * 0: high
1355  * 1: low
1356  * 2: rise
1357  * 3: fall
1358  */
1359 #define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL)
1360 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U)
1361 #define SEI_CTRL_LATCH_TRAN_CFG_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK)
1362 #define SEI_CTRL_LATCH_TRAN_CFG_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT)
1363 
1364 /*
1365  * CFG_TXD (RW)
1366  *
1367  * data send
1368  * 0: high
1369  * 1: low
1370  * 2: rise
1371  * 3: fall
1372  */
1373 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U)
1374 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U)
1375 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK)
1376 #define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT)
1377 
1378 /*
1379  * CFG_CLK (RW)
1380  *
1381  * clock(only support master mode)
1382  * 0: high
1383  * 1: low
1384  * 2: rise
1385  * 3: fall
1386  */
1387 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U)
1388 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U)
1389 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK)
1390 #define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT)
1391 
1392 /*
1393  * CFG_PTR (RW)
1394  *
1395  * pointer
1396  * 0: match
1397  * 1: not match
1398  * 2:entry
1399  * 3:leave
1400  */
1401 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U)
1402 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U)
1403 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK)
1404 #define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT)
1405 
1406 /*
1407  * OV_TM (RW)
1408  *
1409  * override timeout check
1410  */
1411 #define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U)
1412 #define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U)
1413 #define SEI_CTRL_LATCH_TRAN_OV_TM_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK)
1414 #define SEI_CTRL_LATCH_TRAN_OV_TM_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT)
1415 
1416 /*
1417  * OV_TXD (RW)
1418  *
1419  * override TX data check
1420  */
1421 #define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U)
1422 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U)
1423 #define SEI_CTRL_LATCH_TRAN_OV_TXD_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK)
1424 #define SEI_CTRL_LATCH_TRAN_OV_TXD_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT)
1425 
1426 /*
1427  * OV_CLK (RW)
1428  *
1429  * override clock check
1430  */
1431 #define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U)
1432 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U)
1433 #define SEI_CTRL_LATCH_TRAN_OV_CLK_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK)
1434 #define SEI_CTRL_LATCH_TRAN_OV_CLK_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT)
1435 
1436 /*
1437  * OV_PTR (RW)
1438  *
1439  * override pointer check
1440  */
1441 #define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U)
1442 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U)
1443 #define SEI_CTRL_LATCH_TRAN_OV_PTR_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK)
1444 #define SEI_CTRL_LATCH_TRAN_OV_PTR_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT)
1445 
1446 /* Bitfield definition for register of struct array CTRL: CFG */
1447 /*
1448  * EN (RW)
1449  *
1450  * Enable latch
1451  * 0: disable
1452  * 1: enable
1453  */
1454 #define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL)
1455 #define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U)
1456 #define SEI_CTRL_LATCH_CFG_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK)
1457 #define SEI_CTRL_LATCH_CFG_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT)
1458 
1459 /*
1460  * SELECT (RW)
1461  *
1462  * Output select
1463  * 0: state0-state1
1464  * 1: state1-state2
1465  * 2: state2-state3
1466  * 3: state3-state0
1467  */
1468 #define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL)
1469 #define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U)
1470 #define SEI_CTRL_LATCH_CFG_SELECT_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK)
1471 #define SEI_CTRL_LATCH_CFG_SELECT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT)
1472 
1473 /*
1474  * DELAY (RW)
1475  *
1476  * Delay in system clock cycle, for state transition
1477  */
1478 #define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU)
1479 #define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U)
1480 #define SEI_CTRL_LATCH_CFG_DELAY_SET(x) (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK)
1481 #define SEI_CTRL_LATCH_CFG_DELAY_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT)
1482 
1483 /* Bitfield definition for register of struct array CTRL: TIME */
1484 /*
1485  * LAT_TIME (RO)
1486  *
1487  * Latch time
1488  */
1489 #define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL)
1490 #define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U)
1491 #define SEI_CTRL_LATCH_TIME_LAT_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT)
1492 
1493 /* Bitfield definition for register of struct array CTRL: STS */
1494 /*
1495  * STATE (RO)
1496  *
1497  * State
1498  */
1499 #define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL)
1500 #define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U)
1501 #define SEI_CTRL_LATCH_STS_STATE_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT)
1502 
1503 /*
1504  * LAT_CNT (RO)
1505  *
1506  * Latch counter
1507  */
1508 #define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU)
1509 #define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U)
1510 #define SEI_CTRL_LATCH_STS_LAT_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT)
1511 
1512 /* Bitfield definition for register of struct array CTRL: SMP_EN */
1513 /*
1514  * ACC_EN (RW)
1515  *
1516  * Position include acceleration
1517  * 0: use acceleration from sample override acceleration register
1518  * 1: use acceleration from motor group
1519  */
1520 #define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL)
1521 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U)
1522 #define SEI_CTRL_POS_SMP_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK)
1523 #define SEI_CTRL_POS_SMP_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT)
1524 
1525 /*
1526  * ACC_SEL (RW)
1527  *
1528  * Data register for acceleration transfer
1529  */
1530 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL)
1531 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U)
1532 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK)
1533 #define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT)
1534 
1535 /*
1536  * SPD_EN (RW)
1537  *
1538  * Position include speed
1539  * 0: use speed from sample override speed register
1540  * 1: use speed from motor group
1541  */
1542 #define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL)
1543 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U)
1544 #define SEI_CTRL_POS_SMP_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK)
1545 #define SEI_CTRL_POS_SMP_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT)
1546 
1547 /*
1548  * SPD_SEL (RW)
1549  *
1550  * Data register for speed transfer
1551  */
1552 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL)
1553 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U)
1554 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK)
1555 #define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT)
1556 
1557 /*
1558  * REV_EN (RW)
1559  *
1560  * Position include revolution
1561  * 0: use revolution from sample override revolution register
1562  * 1: use revolution from motor group
1563  */
1564 #define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U)
1565 #define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U)
1566 #define SEI_CTRL_POS_SMP_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK)
1567 #define SEI_CTRL_POS_SMP_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT)
1568 
1569 /*
1570  * REV_SEL (RW)
1571  *
1572  * Data register for revolution transfer
1573  */
1574 #define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U)
1575 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U)
1576 #define SEI_CTRL_POS_SMP_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK)
1577 #define SEI_CTRL_POS_SMP_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT)
1578 
1579 /*
1580  * POS_EN (RW)
1581  *
1582  * Position include position
1583  * 0: use position from sample override position register
1584  * 1: use position from motor group
1585  */
1586 #define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U)
1587 #define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U)
1588 #define SEI_CTRL_POS_SMP_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK)
1589 #define SEI_CTRL_POS_SMP_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT)
1590 
1591 /*
1592  * POS_SEL (RW)
1593  *
1594  * Data register for position transfer
1595  */
1596 #define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU)
1597 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U)
1598 #define SEI_CTRL_POS_SMP_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK)
1599 #define SEI_CTRL_POS_SMP_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT)
1600 
1601 /* Bitfield definition for register of struct array CTRL: SMP_CFG */
1602 /*
1603  * ONCE (RW)
1604  *
1605  * Sample one time
1606  * 0: Sample during windows time
1607  * 1: Close sample window after first sample
1608  */
1609 #define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL)
1610 #define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U)
1611 #define SEI_CTRL_POS_SMP_CFG_ONCE_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK)
1612 #define SEI_CTRL_POS_SMP_CFG_ONCE_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT)
1613 
1614 /*
1615  * LAT_SEL (RW)
1616  *
1617  * Latch selection
1618  * 0: latch 0
1619  * 1: latch 1
1620  * 2: latch 2
1621  * 3: latch 3
1622  */
1623 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL)
1624 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U)
1625 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK)
1626 #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT)
1627 
1628 /*
1629  * WINDOW (RW)
1630  *
1631  * Sample window, in clock cycle
1632  */
1633 #define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU)
1634 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U)
1635 #define SEI_CTRL_POS_SMP_CFG_WINDOW_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK)
1636 #define SEI_CTRL_POS_SMP_CFG_WINDOW_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT)
1637 
1638 /* Bitfield definition for register of struct array CTRL: SMP_DAT */
1639 /*
1640  * DAT_SEL (RW)
1641  *
1642  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when SAMPLE happens.
1643  * Note: CRC register will be cleared automatically by SAMPLE if select the DATA register used for CRC.
1644  */
1645 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1646 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U)
1647 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK)
1648 #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT)
1649 
1650 /* Bitfield definition for register of struct array CTRL: SMP_POS */
1651 /*
1652  * POS (RW)
1653  *
1654  * Sample override position
1655  */
1656 #define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL)
1657 #define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U)
1658 #define SEI_CTRL_POS_SMP_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK)
1659 #define SEI_CTRL_POS_SMP_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT)
1660 
1661 /* Bitfield definition for register of struct array CTRL: SMP_REV */
1662 /*
1663  * REV (RW)
1664  *
1665  * Sample override revolution
1666  */
1667 #define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL)
1668 #define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U)
1669 #define SEI_CTRL_POS_SMP_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK)
1670 #define SEI_CTRL_POS_SMP_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT)
1671 
1672 /* Bitfield definition for register of struct array CTRL: SMP_SPD */
1673 /*
1674  * SPD (RW)
1675  *
1676  * Sample override speed
1677  */
1678 #define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL)
1679 #define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U)
1680 #define SEI_CTRL_POS_SMP_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK)
1681 #define SEI_CTRL_POS_SMP_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT)
1682 
1683 /* Bitfield definition for register of struct array CTRL: SMP_ACC */
1684 /*
1685  * ACC (RW)
1686  *
1687  * Sample override accelerate
1688  */
1689 #define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL)
1690 #define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U)
1691 #define SEI_CTRL_POS_SMP_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK)
1692 #define SEI_CTRL_POS_SMP_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT)
1693 
1694 /* Bitfield definition for register of struct array CTRL: UPD_EN */
1695 /*
1696  * ACC_EN (RW)
1697  *
1698  * Position include acceleration
1699  * 0: use acceleration from update override acceleration register
1700  * 1: use acceleration from data register
1701  */
1702 #define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL)
1703 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U)
1704 #define SEI_CTRL_POS_UPD_EN_ACC_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK)
1705 #define SEI_CTRL_POS_UPD_EN_ACC_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT)
1706 
1707 /*
1708  * ACC_SEL (RW)
1709  *
1710  * Data register for acceleration transfer
1711  */
1712 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL)
1713 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U)
1714 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK)
1715 #define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT)
1716 
1717 /*
1718  * SPD_EN (RW)
1719  *
1720  * Position include speed
1721  * 0: use speed from update override speed register
1722  * 1: use speed from data register
1723  */
1724 #define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL)
1725 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U)
1726 #define SEI_CTRL_POS_UPD_EN_SPD_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK)
1727 #define SEI_CTRL_POS_UPD_EN_SPD_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT)
1728 
1729 /*
1730  * SPD_SEL (RW)
1731  *
1732  * Data register for speed transfer
1733  */
1734 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL)
1735 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U)
1736 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK)
1737 #define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT)
1738 
1739 /*
1740  * REV_EN (RW)
1741  *
1742  * Position include revolution
1743  * 0: use revolution from update override revolution register
1744  * 1: use revolution from data register
1745  */
1746 #define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U)
1747 #define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U)
1748 #define SEI_CTRL_POS_UPD_EN_REV_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK)
1749 #define SEI_CTRL_POS_UPD_EN_REV_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT)
1750 
1751 /*
1752  * REV_SEL (RW)
1753  *
1754  * Data register for revolution transfer
1755  */
1756 #define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U)
1757 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U)
1758 #define SEI_CTRL_POS_UPD_EN_REV_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK)
1759 #define SEI_CTRL_POS_UPD_EN_REV_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT)
1760 
1761 /*
1762  * POS_EN (RW)
1763  *
1764  * Position include position
1765  * 0: use position from update override position register
1766  * 1: use position from data register
1767  */
1768 #define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U)
1769 #define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U)
1770 #define SEI_CTRL_POS_UPD_EN_POS_EN_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK)
1771 #define SEI_CTRL_POS_UPD_EN_POS_EN_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT)
1772 
1773 /*
1774  * POS_SEL (RW)
1775  *
1776  * Data register for position transfer
1777  */
1778 #define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU)
1779 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U)
1780 #define SEI_CTRL_POS_UPD_EN_POS_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK)
1781 #define SEI_CTRL_POS_UPD_EN_POS_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT)
1782 
1783 /* Bitfield definition for register of struct array CTRL: UPD_CFG */
1784 /*
1785  * TIME_OVRD (RW)
1786  *
1787  * Use override time
1788  * 0: use time sample from motor group
1789  * 1: use override time
1790  */
1791 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL)
1792 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U)
1793 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK)
1794 #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT)
1795 
1796 /*
1797  * ONERR (RW)
1798  *
1799  * Sample one time
1800  * 0: Sample during windows time
1801  * 1: Close sample window after first sample
1802  */
1803 #define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL)
1804 #define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U)
1805 #define SEI_CTRL_POS_UPD_CFG_ONERR_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK)
1806 #define SEI_CTRL_POS_UPD_CFG_ONERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT)
1807 
1808 /*
1809  * LAT_SEL (RW)
1810  *
1811  * Latch selection
1812  * 0: latch 0
1813  * 1: latch 1
1814  * 2: latch 2
1815  * 3: latch 3
1816  */
1817 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL)
1818 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U)
1819 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK)
1820 #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT)
1821 
1822 /* Bitfield definition for register of struct array CTRL: UPD_DAT */
1823 /*
1824  * DAT_SEL (RW)
1825  *
1826  * Data register sampled, each bit represent a data register, select the DATA registers need to be updated when UPDATE happen.
1827  * Note: CRC register will be cleared automatically by UPDATE if select the DATA register used for CRC.
1828  */
1829 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL)
1830 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U)
1831 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK)
1832 #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT)
1833 
1834 /* Bitfield definition for register of struct array CTRL: UPD_TIME */
1835 /*
1836  * TIME (RW)
1837  *
1838  * Update override time
1839  */
1840 #define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL)
1841 #define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U)
1842 #define SEI_CTRL_POS_UPD_TIME_TIME_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK)
1843 #define SEI_CTRL_POS_UPD_TIME_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT)
1844 
1845 /* Bitfield definition for register of struct array CTRL: UPD_POS */
1846 /*
1847  * POS (RW)
1848  *
1849  * Update override position
1850  */
1851 #define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL)
1852 #define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U)
1853 #define SEI_CTRL_POS_UPD_POS_POS_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK)
1854 #define SEI_CTRL_POS_UPD_POS_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT)
1855 
1856 /* Bitfield definition for register of struct array CTRL: UPD_REV */
1857 /*
1858  * REV (RW)
1859  *
1860  * Update override revolution
1861  */
1862 #define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL)
1863 #define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U)
1864 #define SEI_CTRL_POS_UPD_REV_REV_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK)
1865 #define SEI_CTRL_POS_UPD_REV_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT)
1866 
1867 /* Bitfield definition for register of struct array CTRL: UPD_SPD */
1868 /*
1869  * SPD (RW)
1870  *
1871  * Update override speed
1872  */
1873 #define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL)
1874 #define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U)
1875 #define SEI_CTRL_POS_UPD_SPD_SPD_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK)
1876 #define SEI_CTRL_POS_UPD_SPD_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT)
1877 
1878 /* Bitfield definition for register of struct array CTRL: UPD_ACC */
1879 /*
1880  * ACC (RW)
1881  *
1882  * Update override accelerate
1883  */
1884 #define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL)
1885 #define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U)
1886 #define SEI_CTRL_POS_UPD_ACC_ACC_SET(x) (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK)
1887 #define SEI_CTRL_POS_UPD_ACC_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT)
1888 
1889 /* Bitfield definition for register of struct array CTRL: SMP_VAL */
1890 /*
1891  * ACC (RO)
1892  *
1893  * Position include acceleration
1894  */
1895 #define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL)
1896 #define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U)
1897 #define SEI_CTRL_POS_SMP_VAL_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT)
1898 
1899 /*
1900  * SPD (RO)
1901  *
1902  * Position include speed
1903  */
1904 #define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL)
1905 #define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U)
1906 #define SEI_CTRL_POS_SMP_VAL_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT)
1907 
1908 /*
1909  * REV (RO)
1910  *
1911  * Position include revolution
1912  */
1913 #define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U)
1914 #define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U)
1915 #define SEI_CTRL_POS_SMP_VAL_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT)
1916 
1917 /*
1918  * POS (RO)
1919  *
1920  * Position include position
1921  */
1922 #define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U)
1923 #define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U)
1924 #define SEI_CTRL_POS_SMP_VAL_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT)
1925 
1926 /* Bitfield definition for register of struct array CTRL: SMP_STS */
1927 /*
1928  * OCCUR (RO)
1929  *
1930  * Sample occured
1931  * 0: Sample not happened
1932  * 1: Sample occured
1933  */
1934 #define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL)
1935 #define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U)
1936 #define SEI_CTRL_POS_SMP_STS_OCCUR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT)
1937 
1938 /*
1939  * WIN_CNT (RO)
1940  *
1941  * Sample window counter
1942  */
1943 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU)
1944 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U)
1945 #define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT)
1946 
1947 /* Bitfield definition for register of struct array CTRL: TIME_IN */
1948 /*
1949  * TIME (RO)
1950  *
1951  * input time
1952  */
1953 #define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL)
1954 #define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U)
1955 #define SEI_CTRL_POS_TIME_IN_TIME_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT)
1956 
1957 /* Bitfield definition for register of struct array CTRL: POS_IN */
1958 /*
1959  * POS (RO)
1960  *
1961  * Input position
1962  */
1963 #define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL)
1964 #define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U)
1965 #define SEI_CTRL_POS_POS_IN_POS_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT)
1966 
1967 /* Bitfield definition for register of struct array CTRL: REV_IN */
1968 /*
1969  * REV (RO)
1970  *
1971  * Input revolution
1972  */
1973 #define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL)
1974 #define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U)
1975 #define SEI_CTRL_POS_REV_IN_REV_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT)
1976 
1977 /* Bitfield definition for register of struct array CTRL: SPD_IN */
1978 /*
1979  * SPD (RO)
1980  *
1981  * Input speed
1982  */
1983 #define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL)
1984 #define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U)
1985 #define SEI_CTRL_POS_SPD_IN_SPD_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT)
1986 
1987 /* Bitfield definition for register of struct array CTRL: ACC_IN */
1988 /*
1989  * ACC (RO)
1990  *
1991  * Input accelerate
1992  */
1993 #define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL)
1994 #define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U)
1995 #define SEI_CTRL_POS_ACC_IN_ACC_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT)
1996 
1997 /* Bitfield definition for register of struct array CTRL: UPD_STS */
1998 /*
1999  * UPD_ERR (RO)
2000  *
2001  * Update error
2002  * 0: data receive normally
2003  * 1: data receive error
2004  */
2005 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL)
2006 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U)
2007 #define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT)
2008 
2009 /* Bitfield definition for register of struct array CTRL: INT_EN */
2010 /*
2011  * TRG_ERR3 (RW)
2012  *
2013  * Trigger3 failed
2014  */
2015 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL)
2016 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U)
2017 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK)
2018 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT)
2019 
2020 /*
2021  * TRG_ERR2 (RW)
2022  *
2023  * Trigger2 failed
2024  */
2025 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL)
2026 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U)
2027 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK)
2028 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT)
2029 
2030 /*
2031  * TRG_ERR1 (RW)
2032  *
2033  * Trigger1 failed
2034  */
2035 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL)
2036 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U)
2037 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK)
2038 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT)
2039 
2040 /*
2041  * TRG_ERR0 (RW)
2042  *
2043  * Trigger0 failed
2044  */
2045 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL)
2046 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U)
2047 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK)
2048 #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT)
2049 
2050 /*
2051  * TRIGER3 (RW)
2052  *
2053  * Trigger3
2054  */
2055 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL)
2056 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U)
2057 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK)
2058 #define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT)
2059 
2060 /*
2061  * TRIGER2 (RW)
2062  *
2063  * Trigger2
2064  */
2065 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL)
2066 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U)
2067 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK)
2068 #define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT)
2069 
2070 /*
2071  * TRIGER1 (RW)
2072  *
2073  * Trigger1
2074  */
2075 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL)
2076 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U)
2077 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK)
2078 #define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT)
2079 
2080 /*
2081  * TRIGER0 (RW)
2082  *
2083  * Trigger0
2084  */
2085 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL)
2086 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U)
2087 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK)
2088 #define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT)
2089 
2090 /*
2091  * SMP_ERR (RW)
2092  *
2093  * Sample error
2094  */
2095 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL)
2096 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U)
2097 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK)
2098 #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT)
2099 
2100 /*
2101  * LATCH3 (RW)
2102  *
2103  * Latch3
2104  */
2105 #define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL)
2106 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U)
2107 #define SEI_CTRL_IRQ_INT_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK)
2108 #define SEI_CTRL_IRQ_INT_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT)
2109 
2110 /*
2111  * LATCH2 (RW)
2112  *
2113  * Latch2
2114  */
2115 #define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL)
2116 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U)
2117 #define SEI_CTRL_IRQ_INT_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK)
2118 #define SEI_CTRL_IRQ_INT_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT)
2119 
2120 /*
2121  * LATCH1 (RW)
2122  *
2123  * Latch1
2124  */
2125 #define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL)
2126 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U)
2127 #define SEI_CTRL_IRQ_INT_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK)
2128 #define SEI_CTRL_IRQ_INT_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT)
2129 
2130 /*
2131  * LATCH0 (RW)
2132  *
2133  * Latch0
2134  */
2135 #define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL)
2136 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U)
2137 #define SEI_CTRL_IRQ_INT_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK)
2138 #define SEI_CTRL_IRQ_INT_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT)
2139 
2140 /*
2141  * TIMEOUT (RW)
2142  *
2143  * Timeout
2144  */
2145 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U)
2146 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U)
2147 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK)
2148 #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT)
2149 
2150 /*
2151  * TRX_ERR (RW)
2152  *
2153  * Transfer error
2154  */
2155 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U)
2156 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U)
2157 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK)
2158 #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT)
2159 
2160 /*
2161  * INSTR1_END (RW)
2162  *
2163  * Instruction 1 end
2164  */
2165 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U)
2166 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U)
2167 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK)
2168 #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT)
2169 
2170 /*
2171  * INSTR0_END (RW)
2172  *
2173  * Instruction 0 end
2174  */
2175 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U)
2176 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U)
2177 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK)
2178 #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT)
2179 
2180 /*
2181  * PTR1_END (RW)
2182  *
2183  * Pointer 1 end
2184  */
2185 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U)
2186 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U)
2187 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK)
2188 #define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT)
2189 
2190 /*
2191  * PTR0_END (RW)
2192  *
2193  * Pointer 0 end
2194  */
2195 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U)
2196 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U)
2197 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK)
2198 #define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT)
2199 
2200 /*
2201  * INSTR1_ST (RW)
2202  *
2203  * Instruction 1 start
2204  */
2205 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U)
2206 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U)
2207 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK)
2208 #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT)
2209 
2210 /*
2211  * INSTR0_ST (RW)
2212  *
2213  * Instruction 0 start
2214  */
2215 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U)
2216 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U)
2217 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK)
2218 #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT)
2219 
2220 /*
2221  * PTR1_ST (RW)
2222  *
2223  * Pointer 1 start
2224  */
2225 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U)
2226 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U)
2227 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK)
2228 #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT)
2229 
2230 /*
2231  * PTR0_ST (RW)
2232  *
2233  * Pointer 0 start
2234  */
2235 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U)
2236 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U)
2237 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK)
2238 #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT)
2239 
2240 /*
2241  * WDOG (RW)
2242  *
2243  * Watch dog
2244  */
2245 #define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U)
2246 #define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U)
2247 #define SEI_CTRL_IRQ_INT_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK)
2248 #define SEI_CTRL_IRQ_INT_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT)
2249 
2250 /*
2251  * EXCEPT (RW)
2252  *
2253  * Exception
2254  */
2255 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U)
2256 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U)
2257 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK)
2258 #define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT)
2259 
2260 /*
2261  * STALL (RW)
2262  *
2263  * Stall
2264  */
2265 #define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U)
2266 #define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U)
2267 #define SEI_CTRL_IRQ_INT_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK)
2268 #define SEI_CTRL_IRQ_INT_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT)
2269 
2270 /* Bitfield definition for register of struct array CTRL: INT_FLAG */
2271 /*
2272  * TRG_ERR3 (W1C)
2273  *
2274  * Trigger3 failed
2275  */
2276 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL)
2277 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U)
2278 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK)
2279 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT)
2280 
2281 /*
2282  * TRG_ERR2 (W1C)
2283  *
2284  * Trigger2 failed
2285  */
2286 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL)
2287 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U)
2288 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK)
2289 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT)
2290 
2291 /*
2292  * TRG_ERR1 (W1C)
2293  *
2294  * Trigger1 failed
2295  */
2296 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL)
2297 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U)
2298 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK)
2299 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT)
2300 
2301 /*
2302  * TRG_ERR0 (W1C)
2303  *
2304  * Trigger0 failed
2305  */
2306 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL)
2307 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U)
2308 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK)
2309 #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT)
2310 
2311 /*
2312  * TRIGER3 (W1C)
2313  *
2314  * Trigger3
2315  */
2316 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL)
2317 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U)
2318 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK)
2319 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT)
2320 
2321 /*
2322  * TRIGER2 (W1C)
2323  *
2324  * Trigger2
2325  */
2326 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL)
2327 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U)
2328 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK)
2329 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT)
2330 
2331 /*
2332  * TRIGER1 (W1C)
2333  *
2334  * Trigger1
2335  */
2336 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL)
2337 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U)
2338 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK)
2339 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT)
2340 
2341 /*
2342  * TRIGER0 (W1C)
2343  *
2344  * Trigger0
2345  */
2346 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL)
2347 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U)
2348 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK)
2349 #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT)
2350 
2351 /*
2352  * SMP_ERR (W1C)
2353  *
2354  * Sample error
2355  */
2356 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL)
2357 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U)
2358 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK)
2359 #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT)
2360 
2361 /*
2362  * LATCH3 (W1C)
2363  *
2364  * Latch3
2365  */
2366 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL)
2367 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U)
2368 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK)
2369 #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT)
2370 
2371 /*
2372  * LATCH2 (W1C)
2373  *
2374  * Latch2
2375  */
2376 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL)
2377 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U)
2378 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK)
2379 #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT)
2380 
2381 /*
2382  * LATCH1 (W1C)
2383  *
2384  * Latch1
2385  */
2386 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL)
2387 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U)
2388 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK)
2389 #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT)
2390 
2391 /*
2392  * LATCH0 (W1C)
2393  *
2394  * Latch0
2395  */
2396 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL)
2397 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U)
2398 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK)
2399 #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT)
2400 
2401 /*
2402  * TIMEOUT (W1C)
2403  *
2404  * Timeout
2405  */
2406 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U)
2407 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U)
2408 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK)
2409 #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT)
2410 
2411 /*
2412  * TRX_ERR (W1C)
2413  *
2414  * Transfer error
2415  */
2416 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U)
2417 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U)
2418 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK)
2419 #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT)
2420 
2421 /*
2422  * INSTR1_END (W1C)
2423  *
2424  * Instruction 1 end
2425  */
2426 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U)
2427 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U)
2428 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK)
2429 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT)
2430 
2431 /*
2432  * INSTR0_END (W1C)
2433  *
2434  * Instruction 0 end
2435  */
2436 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U)
2437 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U)
2438 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK)
2439 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT)
2440 
2441 /*
2442  * PTR1_END (W1C)
2443  *
2444  * Pointer 1 end
2445  */
2446 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U)
2447 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U)
2448 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK)
2449 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT)
2450 
2451 /*
2452  * PTR0_END (W1C)
2453  *
2454  * Pointer 0 end
2455  */
2456 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U)
2457 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U)
2458 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK)
2459 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT)
2460 
2461 /*
2462  * INSTR1_ST (W1C)
2463  *
2464  * Instruction 1 start
2465  */
2466 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U)
2467 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U)
2468 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK)
2469 #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT)
2470 
2471 /*
2472  * INSTR0_ST (W1C)
2473  *
2474  * Instruction 0 start
2475  */
2476 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U)
2477 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U)
2478 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK)
2479 #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT)
2480 
2481 /*
2482  * PTR1_ST (W1C)
2483  *
2484  * Pointer 1 start
2485  */
2486 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U)
2487 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U)
2488 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK)
2489 #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT)
2490 
2491 /*
2492  * PTR0_ST (W1C)
2493  *
2494  * Pointer 0 start
2495  */
2496 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U)
2497 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U)
2498 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK)
2499 #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT)
2500 
2501 /*
2502  * WDOG (W1C)
2503  *
2504  * Watch dog
2505  */
2506 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U)
2507 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U)
2508 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK)
2509 #define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT)
2510 
2511 /*
2512  * EXCEPT (W1C)
2513  *
2514  * Exception
2515  */
2516 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U)
2517 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U)
2518 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK)
2519 #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT)
2520 
2521 /*
2522  * STALL (W1C)
2523  *
2524  * Stall
2525  */
2526 #define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U)
2527 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U)
2528 #define SEI_CTRL_IRQ_INT_FLAG_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK)
2529 #define SEI_CTRL_IRQ_INT_FLAG_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT)
2530 
2531 /* Bitfield definition for register of struct array CTRL: INT_STS */
2532 /*
2533  * TRG_ERR3 (RO)
2534  *
2535  * Trigger3 failed
2536  */
2537 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL)
2538 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U)
2539 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT)
2540 
2541 /*
2542  * TRG_ERR2 (RO)
2543  *
2544  * Trigger2 failed
2545  */
2546 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL)
2547 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U)
2548 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT)
2549 
2550 /*
2551  * TRG_ERR1 (RO)
2552  *
2553  * Trigger1 failed
2554  */
2555 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL)
2556 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U)
2557 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT)
2558 
2559 /*
2560  * TRG_ERR0 (RO)
2561  *
2562  * Trigger0 failed
2563  */
2564 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL)
2565 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U)
2566 #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT)
2567 
2568 /*
2569  * TRIGER3 (RO)
2570  *
2571  * Trigger3
2572  */
2573 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL)
2574 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U)
2575 #define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT)
2576 
2577 /*
2578  * TRIGER2 (RO)
2579  *
2580  * Trigger2
2581  */
2582 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL)
2583 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U)
2584 #define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT)
2585 
2586 /*
2587  * TRIGER1 (RO)
2588  *
2589  * Trigger1
2590  */
2591 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL)
2592 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U)
2593 #define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT)
2594 
2595 /*
2596  * TRIGER0 (RO)
2597  *
2598  * Trigger0
2599  */
2600 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL)
2601 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U)
2602 #define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT)
2603 
2604 /*
2605  * SMP_ERR (RO)
2606  *
2607  * Sample error
2608  */
2609 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL)
2610 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U)
2611 #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT)
2612 
2613 /*
2614  * LATCH3 (RO)
2615  *
2616  * Latch3
2617  */
2618 #define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL)
2619 #define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U)
2620 #define SEI_CTRL_IRQ_INT_STS_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT)
2621 
2622 /*
2623  * LATCH2 (RO)
2624  *
2625  * Latch2
2626  */
2627 #define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL)
2628 #define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U)
2629 #define SEI_CTRL_IRQ_INT_STS_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT)
2630 
2631 /*
2632  * LATCH1 (RO)
2633  *
2634  * Latch1
2635  */
2636 #define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL)
2637 #define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U)
2638 #define SEI_CTRL_IRQ_INT_STS_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT)
2639 
2640 /*
2641  * LATCH0 (RO)
2642  *
2643  * Latch0
2644  */
2645 #define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL)
2646 #define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U)
2647 #define SEI_CTRL_IRQ_INT_STS_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT)
2648 
2649 /*
2650  * TIMEOUT (RO)
2651  *
2652  * Timeout
2653  */
2654 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U)
2655 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U)
2656 #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT)
2657 
2658 /*
2659  * TRX_ERR (RO)
2660  *
2661  * Transfer error
2662  */
2663 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U)
2664 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U)
2665 #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT)
2666 
2667 /*
2668  * INSTR1_END (RO)
2669  *
2670  * Instruction 1 end
2671  */
2672 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U)
2673 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U)
2674 #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT)
2675 
2676 /*
2677  * INSTR0_END (RO)
2678  *
2679  * Instruction 0 end
2680  */
2681 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U)
2682 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U)
2683 #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT)
2684 
2685 /*
2686  * PTR1_END (RO)
2687  *
2688  * Pointer 1 end
2689  */
2690 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U)
2691 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U)
2692 #define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT)
2693 
2694 /*
2695  * PTR0_END (RO)
2696  *
2697  * Pointer 0 end
2698  */
2699 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U)
2700 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U)
2701 #define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT)
2702 
2703 /*
2704  * INSTR1_ST (RO)
2705  *
2706  * Instruction 1 start
2707  */
2708 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U)
2709 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U)
2710 #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT)
2711 
2712 /*
2713  * INSTR0_ST (RO)
2714  *
2715  * Instruction 0 start
2716  */
2717 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U)
2718 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U)
2719 #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT)
2720 
2721 /*
2722  * PTR1_ST (RO)
2723  *
2724  * Pointer 1 start
2725  */
2726 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U)
2727 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U)
2728 #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT)
2729 
2730 /*
2731  * PTR0_ST (RO)
2732  *
2733  * Pointer 0 start
2734  */
2735 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U)
2736 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U)
2737 #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT)
2738 
2739 /*
2740  * WDOG (RO)
2741  *
2742  * Watch dog
2743  */
2744 #define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U)
2745 #define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U)
2746 #define SEI_CTRL_IRQ_INT_STS_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT)
2747 
2748 /*
2749  * EXCEPT (RO)
2750  *
2751  * Exception
2752  */
2753 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U)
2754 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U)
2755 #define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT)
2756 
2757 /*
2758  * STALL (RO)
2759  *
2760  * Stall
2761  */
2762 #define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U)
2763 #define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U)
2764 #define SEI_CTRL_IRQ_INT_STS_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT)
2765 
2766 /* Bitfield definition for register of struct array CTRL: POINTER0 */
2767 /*
2768  * POINTER (RW)
2769  *
2770  * Match pointer 0
2771  */
2772 #define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU)
2773 #define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U)
2774 #define SEI_CTRL_IRQ_POINTER0_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK)
2775 #define SEI_CTRL_IRQ_POINTER0_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT)
2776 
2777 /* Bitfield definition for register of struct array CTRL: POINTER1 */
2778 /*
2779  * POINTER (RW)
2780  *
2781  * Match pointer 1
2782  */
2783 #define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU)
2784 #define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U)
2785 #define SEI_CTRL_IRQ_POINTER1_POINTER_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK)
2786 #define SEI_CTRL_IRQ_POINTER1_POINTER_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT)
2787 
2788 /* Bitfield definition for register of struct array CTRL: INSTR0 */
2789 /*
2790  * INSTR (RW)
2791  *
2792  * Match instruction 0
2793  */
2794 #define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL)
2795 #define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U)
2796 #define SEI_CTRL_IRQ_INSTR0_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK)
2797 #define SEI_CTRL_IRQ_INSTR0_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT)
2798 
2799 /* Bitfield definition for register of struct array CTRL: INSTR1 */
2800 /*
2801  * INSTR (RW)
2802  *
2803  * Match instruction 1
2804  */
2805 #define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL)
2806 #define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U)
2807 #define SEI_CTRL_IRQ_INSTR1_INSTR_SET(x) (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK)
2808 #define SEI_CTRL_IRQ_INSTR1_INSTR_GET(x) (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT)
2809 
2810 /* Bitfield definition for register of struct array CTRL: DMA_EN */
2811 /*
2812  * TRG_ERR3 (RW)
2813  *
2814  * Trigger3 failed
2815  */
2816 #define SEI_CTRL_DMA_EN_TRG_ERR3_MASK (0x80000000UL)
2817 #define SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT (31U)
2818 #define SEI_CTRL_DMA_EN_TRG_ERR3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK)
2819 #define SEI_CTRL_DMA_EN_TRG_ERR3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT)
2820 
2821 /*
2822  * TRG_ERR2 (RW)
2823  *
2824  * Trigger2 failed
2825  */
2826 #define SEI_CTRL_DMA_EN_TRG_ERR2_MASK (0x40000000UL)
2827 #define SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT (30U)
2828 #define SEI_CTRL_DMA_EN_TRG_ERR2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK)
2829 #define SEI_CTRL_DMA_EN_TRG_ERR2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT)
2830 
2831 /*
2832  * TRG_ERR1 (RW)
2833  *
2834  * Trigger1 failed
2835  */
2836 #define SEI_CTRL_DMA_EN_TRG_ERR1_MASK (0x20000000UL)
2837 #define SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT (29U)
2838 #define SEI_CTRL_DMA_EN_TRG_ERR1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK)
2839 #define SEI_CTRL_DMA_EN_TRG_ERR1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT)
2840 
2841 /*
2842  * TRG_ERR0 (RW)
2843  *
2844  * Trigger0 failed
2845  */
2846 #define SEI_CTRL_DMA_EN_TRG_ERR0_MASK (0x10000000UL)
2847 #define SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT (28U)
2848 #define SEI_CTRL_DMA_EN_TRG_ERR0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK)
2849 #define SEI_CTRL_DMA_EN_TRG_ERR0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT)
2850 
2851 /*
2852  * TRIGER3 (RW)
2853  *
2854  * Trigger3
2855  */
2856 #define SEI_CTRL_DMA_EN_TRIGER3_MASK (0x8000000UL)
2857 #define SEI_CTRL_DMA_EN_TRIGER3_SHIFT (27U)
2858 #define SEI_CTRL_DMA_EN_TRIGER3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER3_SHIFT) & SEI_CTRL_DMA_EN_TRIGER3_MASK)
2859 #define SEI_CTRL_DMA_EN_TRIGER3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER3_MASK) >> SEI_CTRL_DMA_EN_TRIGER3_SHIFT)
2860 
2861 /*
2862  * TRIGER2 (RW)
2863  *
2864  * Trigger2
2865  */
2866 #define SEI_CTRL_DMA_EN_TRIGER2_MASK (0x4000000UL)
2867 #define SEI_CTRL_DMA_EN_TRIGER2_SHIFT (26U)
2868 #define SEI_CTRL_DMA_EN_TRIGER2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER2_SHIFT) & SEI_CTRL_DMA_EN_TRIGER2_MASK)
2869 #define SEI_CTRL_DMA_EN_TRIGER2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER2_MASK) >> SEI_CTRL_DMA_EN_TRIGER2_SHIFT)
2870 
2871 /*
2872  * TRIGER1 (RW)
2873  *
2874  * Trigger1
2875  */
2876 #define SEI_CTRL_DMA_EN_TRIGER1_MASK (0x2000000UL)
2877 #define SEI_CTRL_DMA_EN_TRIGER1_SHIFT (25U)
2878 #define SEI_CTRL_DMA_EN_TRIGER1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER1_SHIFT) & SEI_CTRL_DMA_EN_TRIGER1_MASK)
2879 #define SEI_CTRL_DMA_EN_TRIGER1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER1_MASK) >> SEI_CTRL_DMA_EN_TRIGER1_SHIFT)
2880 
2881 /*
2882  * TRIGER0 (RW)
2883  *
2884  * Trigger0
2885  */
2886 #define SEI_CTRL_DMA_EN_TRIGER0_MASK (0x1000000UL)
2887 #define SEI_CTRL_DMA_EN_TRIGER0_SHIFT (24U)
2888 #define SEI_CTRL_DMA_EN_TRIGER0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER0_SHIFT) & SEI_CTRL_DMA_EN_TRIGER0_MASK)
2889 #define SEI_CTRL_DMA_EN_TRIGER0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER0_MASK) >> SEI_CTRL_DMA_EN_TRIGER0_SHIFT)
2890 
2891 /*
2892  * SMP_ERR (RW)
2893  *
2894  * Sample error
2895  */
2896 #define SEI_CTRL_DMA_EN_SMP_ERR_MASK (0x100000UL)
2897 #define SEI_CTRL_DMA_EN_SMP_ERR_SHIFT (20U)
2898 #define SEI_CTRL_DMA_EN_SMP_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_SMP_ERR_SHIFT) & SEI_CTRL_DMA_EN_SMP_ERR_MASK)
2899 #define SEI_CTRL_DMA_EN_SMP_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_SMP_ERR_MASK) >> SEI_CTRL_DMA_EN_SMP_ERR_SHIFT)
2900 
2901 /*
2902  * LATCH3 (RW)
2903  *
2904  * Latch3
2905  */
2906 #define SEI_CTRL_DMA_EN_LATCH3_MASK (0x80000UL)
2907 #define SEI_CTRL_DMA_EN_LATCH3_SHIFT (19U)
2908 #define SEI_CTRL_DMA_EN_LATCH3_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH3_SHIFT) & SEI_CTRL_DMA_EN_LATCH3_MASK)
2909 #define SEI_CTRL_DMA_EN_LATCH3_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH3_MASK) >> SEI_CTRL_DMA_EN_LATCH3_SHIFT)
2910 
2911 /*
2912  * LATCH2 (RW)
2913  *
2914  * Latch2
2915  */
2916 #define SEI_CTRL_DMA_EN_LATCH2_MASK (0x40000UL)
2917 #define SEI_CTRL_DMA_EN_LATCH2_SHIFT (18U)
2918 #define SEI_CTRL_DMA_EN_LATCH2_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH2_SHIFT) & SEI_CTRL_DMA_EN_LATCH2_MASK)
2919 #define SEI_CTRL_DMA_EN_LATCH2_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH2_MASK) >> SEI_CTRL_DMA_EN_LATCH2_SHIFT)
2920 
2921 /*
2922  * LATCH1 (RW)
2923  *
2924  * Latch1
2925  */
2926 #define SEI_CTRL_DMA_EN_LATCH1_MASK (0x20000UL)
2927 #define SEI_CTRL_DMA_EN_LATCH1_SHIFT (17U)
2928 #define SEI_CTRL_DMA_EN_LATCH1_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH1_SHIFT) & SEI_CTRL_DMA_EN_LATCH1_MASK)
2929 #define SEI_CTRL_DMA_EN_LATCH1_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH1_MASK) >> SEI_CTRL_DMA_EN_LATCH1_SHIFT)
2930 
2931 /*
2932  * LATCH0 (RW)
2933  *
2934  * Latch0
2935  */
2936 #define SEI_CTRL_DMA_EN_LATCH0_MASK (0x10000UL)
2937 #define SEI_CTRL_DMA_EN_LATCH0_SHIFT (16U)
2938 #define SEI_CTRL_DMA_EN_LATCH0_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH0_SHIFT) & SEI_CTRL_DMA_EN_LATCH0_MASK)
2939 #define SEI_CTRL_DMA_EN_LATCH0_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH0_MASK) >> SEI_CTRL_DMA_EN_LATCH0_SHIFT)
2940 
2941 /*
2942  * TIMEOUT (RW)
2943  *
2944  * Timeout
2945  */
2946 #define SEI_CTRL_DMA_EN_TIMEOUT_MASK (0x2000U)
2947 #define SEI_CTRL_DMA_EN_TIMEOUT_SHIFT (13U)
2948 #define SEI_CTRL_DMA_EN_TIMEOUT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TIMEOUT_SHIFT) & SEI_CTRL_DMA_EN_TIMEOUT_MASK)
2949 #define SEI_CTRL_DMA_EN_TIMEOUT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TIMEOUT_MASK) >> SEI_CTRL_DMA_EN_TIMEOUT_SHIFT)
2950 
2951 /*
2952  * TRX_ERR (RW)
2953  *
2954  * Transfer error
2955  */
2956 #define SEI_CTRL_DMA_EN_TRX_ERR_MASK (0x1000U)
2957 #define SEI_CTRL_DMA_EN_TRX_ERR_SHIFT (12U)
2958 #define SEI_CTRL_DMA_EN_TRX_ERR_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRX_ERR_SHIFT) & SEI_CTRL_DMA_EN_TRX_ERR_MASK)
2959 #define SEI_CTRL_DMA_EN_TRX_ERR_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRX_ERR_MASK) >> SEI_CTRL_DMA_EN_TRX_ERR_SHIFT)
2960 
2961 /*
2962  * INSTR1_END (RW)
2963  *
2964  * Instruction 1 end
2965  */
2966 #define SEI_CTRL_DMA_EN_INSTR1_END_MASK (0x800U)
2967 #define SEI_CTRL_DMA_EN_INSTR1_END_SHIFT (11U)
2968 #define SEI_CTRL_DMA_EN_INSTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_END_MASK)
2969 #define SEI_CTRL_DMA_EN_INSTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_END_MASK) >> SEI_CTRL_DMA_EN_INSTR1_END_SHIFT)
2970 
2971 /*
2972  * INSTR0_END (RW)
2973  *
2974  * Instruction 0 end
2975  */
2976 #define SEI_CTRL_DMA_EN_INSTR0_END_MASK (0x400U)
2977 #define SEI_CTRL_DMA_EN_INSTR0_END_SHIFT (10U)
2978 #define SEI_CTRL_DMA_EN_INSTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_END_MASK)
2979 #define SEI_CTRL_DMA_EN_INSTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_END_MASK) >> SEI_CTRL_DMA_EN_INSTR0_END_SHIFT)
2980 
2981 /*
2982  * PTR1_END (RW)
2983  *
2984  * Pointer 1 end
2985  */
2986 #define SEI_CTRL_DMA_EN_PTR1_END_MASK (0x200U)
2987 #define SEI_CTRL_DMA_EN_PTR1_END_SHIFT (9U)
2988 #define SEI_CTRL_DMA_EN_PTR1_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_END_SHIFT) & SEI_CTRL_DMA_EN_PTR1_END_MASK)
2989 #define SEI_CTRL_DMA_EN_PTR1_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_END_MASK) >> SEI_CTRL_DMA_EN_PTR1_END_SHIFT)
2990 
2991 /*
2992  * PTR0_END (RW)
2993  *
2994  * Pointer 0 end
2995  */
2996 #define SEI_CTRL_DMA_EN_PTR0_END_MASK (0x100U)
2997 #define SEI_CTRL_DMA_EN_PTR0_END_SHIFT (8U)
2998 #define SEI_CTRL_DMA_EN_PTR0_END_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_END_SHIFT) & SEI_CTRL_DMA_EN_PTR0_END_MASK)
2999 #define SEI_CTRL_DMA_EN_PTR0_END_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_END_MASK) >> SEI_CTRL_DMA_EN_PTR0_END_SHIFT)
3000 
3001 /*
3002  * INSTR1_ST (RW)
3003  *
3004  * Instruction 1 start
3005  */
3006 #define SEI_CTRL_DMA_EN_INSTR1_ST_MASK (0x80U)
3007 #define SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT (7U)
3008 #define SEI_CTRL_DMA_EN_INSTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK)
3009 #define SEI_CTRL_DMA_EN_INSTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT)
3010 
3011 /*
3012  * INSTR0_ST (RW)
3013  *
3014  * Instruction 0 start
3015  */
3016 #define SEI_CTRL_DMA_EN_INSTR0_ST_MASK (0x40U)
3017 #define SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT (6U)
3018 #define SEI_CTRL_DMA_EN_INSTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK)
3019 #define SEI_CTRL_DMA_EN_INSTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT)
3020 
3021 /*
3022  * PTR1_ST (RW)
3023  *
3024  * Pointer 1 start
3025  */
3026 #define SEI_CTRL_DMA_EN_PTR1_ST_MASK (0x20U)
3027 #define SEI_CTRL_DMA_EN_PTR1_ST_SHIFT (5U)
3028 #define SEI_CTRL_DMA_EN_PTR1_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR1_ST_MASK)
3029 #define SEI_CTRL_DMA_EN_PTR1_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_ST_MASK) >> SEI_CTRL_DMA_EN_PTR1_ST_SHIFT)
3030 
3031 /*
3032  * PTR0_ST (RW)
3033  *
3034  * Pointer 0 start
3035  */
3036 #define SEI_CTRL_DMA_EN_PTR0_ST_MASK (0x10U)
3037 #define SEI_CTRL_DMA_EN_PTR0_ST_SHIFT (4U)
3038 #define SEI_CTRL_DMA_EN_PTR0_ST_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR0_ST_MASK)
3039 #define SEI_CTRL_DMA_EN_PTR0_ST_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_ST_MASK) >> SEI_CTRL_DMA_EN_PTR0_ST_SHIFT)
3040 
3041 /*
3042  * WDOG (RW)
3043  *
3044  * Watch dog
3045  */
3046 #define SEI_CTRL_DMA_EN_WDOG_MASK (0x4U)
3047 #define SEI_CTRL_DMA_EN_WDOG_SHIFT (2U)
3048 #define SEI_CTRL_DMA_EN_WDOG_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_WDOG_SHIFT) & SEI_CTRL_DMA_EN_WDOG_MASK)
3049 #define SEI_CTRL_DMA_EN_WDOG_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_WDOG_MASK) >> SEI_CTRL_DMA_EN_WDOG_SHIFT)
3050 
3051 /*
3052  * EXCEPT (RW)
3053  *
3054  * Exception
3055  */
3056 #define SEI_CTRL_DMA_EN_EXCEPT_MASK (0x2U)
3057 #define SEI_CTRL_DMA_EN_EXCEPT_SHIFT (1U)
3058 #define SEI_CTRL_DMA_EN_EXCEPT_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_EXCEPT_SHIFT) & SEI_CTRL_DMA_EN_EXCEPT_MASK)
3059 #define SEI_CTRL_DMA_EN_EXCEPT_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_EXCEPT_MASK) >> SEI_CTRL_DMA_EN_EXCEPT_SHIFT)
3060 
3061 /*
3062  * STALL (RW)
3063  *
3064  * Stall
3065  */
3066 #define SEI_CTRL_DMA_EN_STALL_MASK (0x1U)
3067 #define SEI_CTRL_DMA_EN_STALL_SHIFT (0U)
3068 #define SEI_CTRL_DMA_EN_STALL_SET(x) (((uint32_t)(x) << SEI_CTRL_DMA_EN_STALL_SHIFT) & SEI_CTRL_DMA_EN_STALL_MASK)
3069 #define SEI_CTRL_DMA_EN_STALL_GET(x) (((uint32_t)(x) & SEI_CTRL_DMA_EN_STALL_MASK) >> SEI_CTRL_DMA_EN_STALL_SHIFT)
3070 
3071 /* Bitfield definition for register array: INSTR */
3072 /*
3073  * OP (RW)
3074  *
3075  * operation
3076  * 0: halt
3077  * 1: jump
3078  * 2: send with timeout check
3079  * 3: send without timout check
3080  * 4: wait with timeout check
3081  * 5: wait without timout check
3082  * 6: receive with timeout check
3083  * 7: receive without timout check
3084  */
3085 #define SEI_INSTR_OP_MASK (0x1C000000UL)
3086 #define SEI_INSTR_OP_SHIFT (26U)
3087 #define SEI_INSTR_OP_SET(x) (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK)
3088 #define SEI_INSTR_OP_GET(x) (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT)
3089 
3090 /*
3091  * CK (RW)
3092  *
3093  * clock
3094  * 0: low
3095  * 1: rise-fall
3096  * 2: fall-rise
3097  * 3: high
3098  */
3099 #define SEI_INSTR_CK_MASK (0x3000000UL)
3100 #define SEI_INSTR_CK_SHIFT (24U)
3101 #define SEI_INSTR_CK_SET(x) (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK)
3102 #define SEI_INSTR_CK_GET(x) (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT)
3103 
3104 /*
3105  * CRC (RW)
3106  *
3107  * CRC register
3108  * 0: don't calculate CRC
3109  * 1: do not set this value
3110  * 2: data register 2
3111  * 3: data register 3
3112  * ...
3113  * 29: data register 29
3114  * 30: value 0 when send, wait 0 in receive
3115  * 31: value1 when send, wait 1 in receive
3116  */
3117 #define SEI_INSTR_CRC_MASK (0x1F0000UL)
3118 #define SEI_INSTR_CRC_SHIFT (16U)
3119 #define SEI_INSTR_CRC_SET(x) (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK)
3120 #define SEI_INSTR_CRC_GET(x) (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT)
3121 
3122 /*
3123  * DAT (RW)
3124  *
3125  * DATA register
3126  * 0: ignore data
3127  * 1: command
3128  * 2: data register 2
3129  * 3: data register 3
3130  * ...
3131  * 29: data register 29
3132  * 30: value 0 when send, wait 0 in receive
3133  * 31: value1 when send, wait 1 in receive
3134  */
3135 #define SEI_INSTR_DAT_MASK (0x1F00U)
3136 #define SEI_INSTR_DAT_SHIFT (8U)
3137 #define SEI_INSTR_DAT_SET(x) (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK)
3138 #define SEI_INSTR_DAT_GET(x) (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT)
3139 
3140 /*
3141  * OPR (RW)
3142  *
3143  * a. When OP is 0, this area is the halt time in baudrate, 0 represents infinite time.
3144  * b. When OP is 1, this area is the the pointer to the command table.
3145  * OPR[4]=1, OPR[3:0] value is CMD_TABLE instruct pointer;
3146  * OPR[4]=0, OPR[3:0]=0 is INIT_POINTER;
3147  * OPR[4]=0, OPR[3:0]=1 is WDG_POINTER.
3148  * c. When OP is 2-7, this area is the data length as fellow:
3149  * 0: 1 bit
3150  * 1: 2 bit
3151  * ...
3152  * 31: 32 bit
3153  */
3154 #define SEI_INSTR_OPR_MASK (0x1FU)
3155 #define SEI_INSTR_OPR_SHIFT (0U)
3156 #define SEI_INSTR_OPR_SET(x) (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK)
3157 #define SEI_INSTR_OPR_GET(x) (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT)
3158 
3159 /* Bitfield definition for register of struct array DAT: MODE */
3160 /*
3161  * CRC_LEN (RW)
3162  *
3163  * CRC length
3164  * 0: 1 bit
3165  * 1: 2 bit
3166  * ...
3167  * 31: 32 bit
3168  */
3169 #define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL)
3170 #define SEI_DAT_MODE_CRC_LEN_SHIFT (24U)
3171 #define SEI_DAT_MODE_CRC_LEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK)
3172 #define SEI_DAT_MODE_CRC_LEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT)
3173 
3174 /*
3175  * WLEN (RW)
3176  *
3177  * word length
3178  * 0: 1 bit
3179  * 1: 2 bit
3180  * ...
3181  * 31: 32 bit
3182  */
3183 #define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL)
3184 #define SEI_DAT_MODE_WLEN_SHIFT (16U)
3185 #define SEI_DAT_MODE_WLEN_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK)
3186 #define SEI_DAT_MODE_WLEN_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT)
3187 
3188 /*
3189  * CRC_SHIFT (RW)
3190  *
3191  * CRC shift mode, this mode is used to perform repeat code check
3192  * 0: CRC
3193  * 1: shift mode
3194  */
3195 #define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U)
3196 #define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U)
3197 #define SEI_DAT_MODE_CRC_SHIFT_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK)
3198 #define SEI_DAT_MODE_CRC_SHIFT_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT)
3199 
3200 /*
3201  * CRC_INV (RW)
3202  *
3203  * CRC invert
3204  * 0: use CRC
3205  * 1: use inverted CRC
3206  */
3207 #define SEI_DAT_MODE_CRC_INV_MASK (0x1000U)
3208 #define SEI_DAT_MODE_CRC_INV_SHIFT (12U)
3209 #define SEI_DAT_MODE_CRC_INV_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK)
3210 #define SEI_DAT_MODE_CRC_INV_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT)
3211 
3212 /*
3213  * WORDER (RW)
3214  *
3215  * word order
3216  * 0: sample as bit order
3217  * 1: different from bit order
3218  */
3219 #define SEI_DAT_MODE_WORDER_MASK (0x800U)
3220 #define SEI_DAT_MODE_WORDER_SHIFT (11U)
3221 #define SEI_DAT_MODE_WORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK)
3222 #define SEI_DAT_MODE_WORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT)
3223 
3224 /*
3225  * BORDER (RW)
3226  *
3227  * bit order
3228  * 0: LSB first
3229  * 1: MSB first
3230  */
3231 #define SEI_DAT_MODE_BORDER_MASK (0x400U)
3232 #define SEI_DAT_MODE_BORDER_SHIFT (10U)
3233 #define SEI_DAT_MODE_BORDER_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK)
3234 #define SEI_DAT_MODE_BORDER_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT)
3235 
3236 /*
3237  * SIGNED (RW)
3238  *
3239  * Signed
3240  * 0: unsigned value
3241  * 1: signed value
3242  */
3243 #define SEI_DAT_MODE_SIGNED_MASK (0x200U)
3244 #define SEI_DAT_MODE_SIGNED_SHIFT (9U)
3245 #define SEI_DAT_MODE_SIGNED_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK)
3246 #define SEI_DAT_MODE_SIGNED_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT)
3247 
3248 /*
3249  * REWIND (RW)
3250  *
3251  * Write 1 to rewind read/write pointer, this is a self clear bit
3252  */
3253 #define SEI_DAT_MODE_REWIND_MASK (0x100U)
3254 #define SEI_DAT_MODE_REWIND_SHIFT (8U)
3255 #define SEI_DAT_MODE_REWIND_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK)
3256 #define SEI_DAT_MODE_REWIND_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT)
3257 
3258 /*
3259  * MODE (RW)
3260  *
3261  * Data mode
3262  * 0: data mode
3263  * 1: check mode
3264  * 2: CRC mode
3265  */
3266 #define SEI_DAT_MODE_MODE_MASK (0x3U)
3267 #define SEI_DAT_MODE_MODE_SHIFT (0U)
3268 #define SEI_DAT_MODE_MODE_SET(x) (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK)
3269 #define SEI_DAT_MODE_MODE_GET(x) (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT)
3270 
3271 /* Bitfield definition for register of struct array DAT: IDX */
3272 /*
3273  * LAST_BIT (RW)
3274  *
3275  * Last bit index for tranceive
3276  */
3277 #define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL)
3278 #define SEI_DAT_IDX_LAST_BIT_SHIFT (24U)
3279 #define SEI_DAT_IDX_LAST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK)
3280 #define SEI_DAT_IDX_LAST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT)
3281 
3282 /*
3283  * FIRST_BIT (RW)
3284  *
3285  * First bit index for tranceive
3286  */
3287 #define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL)
3288 #define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U)
3289 #define SEI_DAT_IDX_FIRST_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK)
3290 #define SEI_DAT_IDX_FIRST_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT)
3291 
3292 /*
3293  * MAX_BIT (RW)
3294  *
3295  * Highest bit index
3296  */
3297 #define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U)
3298 #define SEI_DAT_IDX_MAX_BIT_SHIFT (8U)
3299 #define SEI_DAT_IDX_MAX_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK)
3300 #define SEI_DAT_IDX_MAX_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT)
3301 
3302 /*
3303  * MIN_BIT (RW)
3304  *
3305  * Lowest bit index
3306  */
3307 #define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU)
3308 #define SEI_DAT_IDX_MIN_BIT_SHIFT (0U)
3309 #define SEI_DAT_IDX_MIN_BIT_SET(x) (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK)
3310 #define SEI_DAT_IDX_MIN_BIT_GET(x) (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT)
3311 
3312 /* Bitfield definition for register of struct array DAT: GOLD */
3313 /*
3314  * GOLD_VALUE (RW)
3315  *
3316  * Gold value for check mode
3317  */
3318 #define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL)
3319 #define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U)
3320 #define SEI_DAT_GOLD_GOLD_VALUE_SET(x) (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK)
3321 #define SEI_DAT_GOLD_GOLD_VALUE_GET(x) (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT)
3322 
3323 /* Bitfield definition for register of struct array DAT: CRCINIT */
3324 /*
3325  * CRC_INIT (RW)
3326  *
3327  * CRC initial value
3328  */
3329 #define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL)
3330 #define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U)
3331 #define SEI_DAT_CRCINIT_CRC_INIT_SET(x) (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK)
3332 #define SEI_DAT_CRCINIT_CRC_INIT_GET(x) (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT)
3333 
3334 /* Bitfield definition for register of struct array DAT: CRCPOLY */
3335 /*
3336  * CRC_POLY (RW)
3337  *
3338  * CRC polymonial
3339  */
3340 #define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL)
3341 #define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U)
3342 #define SEI_DAT_CRCPOLY_CRC_POLY_SET(x) (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK)
3343 #define SEI_DAT_CRCPOLY_CRC_POLY_GET(x) (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT)
3344 
3345 /* Bitfield definition for register of struct array DAT: DATA */
3346 /*
3347  * DATA (RW)
3348  *
3349  * DATA
3350  */
3351 #define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL)
3352 #define SEI_DAT_DATA_DATA_SHIFT (0U)
3353 #define SEI_DAT_DATA_DATA_SET(x) (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK)
3354 #define SEI_DAT_DATA_DATA_GET(x) (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT)
3355 
3356 /* Bitfield definition for register of struct array DAT: SET */
3357 /*
3358  * DATA_SET (RW)
3359  *
3360  * DATA bit set
3361  */
3362 #define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL)
3363 #define SEI_DAT_SET_DATA_SET_SHIFT (0U)
3364 #define SEI_DAT_SET_DATA_SET_SET(x) (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK)
3365 #define SEI_DAT_SET_DATA_SET_GET(x) (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT)
3366 
3367 /* Bitfield definition for register of struct array DAT: CLR */
3368 /*
3369  * DATA_CLR (RW)
3370  *
3371  * DATA bit clear
3372  */
3373 #define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL)
3374 #define SEI_DAT_CLR_DATA_CLR_SHIFT (0U)
3375 #define SEI_DAT_CLR_DATA_CLR_SET(x) (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK)
3376 #define SEI_DAT_CLR_DATA_CLR_GET(x) (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT)
3377 
3378 /* Bitfield definition for register of struct array DAT: INV */
3379 /*
3380  * DATA_INV (RW)
3381  *
3382  * DATA bit toggle
3383  */
3384 #define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL)
3385 #define SEI_DAT_INV_DATA_INV_SHIFT (0U)
3386 #define SEI_DAT_INV_DATA_INV_SET(x) (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK)
3387 #define SEI_DAT_INV_DATA_INV_GET(x) (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT)
3388 
3389 /* Bitfield definition for register of struct array DAT: IN */
3390 /*
3391  * DATA_IN (RO)
3392  *
3393  * Data input
3394  */
3395 #define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL)
3396 #define SEI_DAT_IN_DATA_IN_SHIFT (0U)
3397 #define SEI_DAT_IN_DATA_IN_GET(x) (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT)
3398 
3399 /* Bitfield definition for register of struct array DAT: OUT */
3400 /*
3401  * DATA_OUT (RO)
3402  *
3403  * Data output
3404  */
3405 #define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL)
3406 #define SEI_DAT_OUT_DATA_OUT_SHIFT (0U)
3407 #define SEI_DAT_OUT_DATA_OUT_GET(x) (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT)
3408 
3409 /* Bitfield definition for register of struct array DAT: STS */
3410 /*
3411  * CRC_IDX (RO)
3412  *
3413  * CRC index
3414  */
3415 #define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL)
3416 #define SEI_DAT_STS_CRC_IDX_SHIFT (24U)
3417 #define SEI_DAT_STS_CRC_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT)
3418 
3419 /*
3420  * WORD_IDX (RO)
3421  *
3422  * Word index
3423  */
3424 #define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL)
3425 #define SEI_DAT_STS_WORD_IDX_SHIFT (16U)
3426 #define SEI_DAT_STS_WORD_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT)
3427 
3428 /*
3429  * WORD_CNT (RO)
3430  *
3431  * Word counter
3432  */
3433 #define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U)
3434 #define SEI_DAT_STS_WORD_CNT_SHIFT (8U)
3435 #define SEI_DAT_STS_WORD_CNT_GET(x) (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT)
3436 
3437 /*
3438  * BIT_IDX (RO)
3439  *
3440  * Bit index
3441  */
3442 #define SEI_DAT_STS_BIT_IDX_MASK (0x1FU)
3443 #define SEI_DAT_STS_BIT_IDX_SHIFT (0U)
3444 #define SEI_DAT_STS_BIT_IDX_GET(x) (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT)
3445 
3446 
3447 
3448 /* CMD register group index macro definition */
3449 #define SEI_CTRL_TRG_TABLE_CMD_0 (0UL)
3450 #define SEI_CTRL_TRG_TABLE_CMD_1 (1UL)
3451 #define SEI_CTRL_TRG_TABLE_CMD_2 (2UL)
3452 #define SEI_CTRL_TRG_TABLE_CMD_3 (3UL)
3453 
3454 /* TIME register group index macro definition */
3455 #define SEI_CTRL_TRG_TABLE_TIME_0 (0UL)
3456 #define SEI_CTRL_TRG_TABLE_TIME_1 (1UL)
3457 #define SEI_CTRL_TRG_TABLE_TIME_2 (2UL)
3458 #define SEI_CTRL_TRG_TABLE_TIME_3 (3UL)
3459 
3460 /* CMD_TABLE register group index macro definition */
3461 #define SEI_CMD_TABLE_0 (0UL)
3462 #define SEI_CMD_TABLE_1 (1UL)
3463 #define SEI_CMD_TABLE_2 (2UL)
3464 #define SEI_CMD_TABLE_3 (3UL)
3465 #define SEI_CMD_TABLE_4 (4UL)
3466 #define SEI_CMD_TABLE_5 (5UL)
3467 #define SEI_CMD_TABLE_6 (6UL)
3468 #define SEI_CMD_TABLE_7 (7UL)
3469 
3470 /* TRAN register group index macro definition */
3471 #define SEI_CTRL_LATCH_TRAN_0_1 (0UL)
3472 #define SEI_CTRL_LATCH_TRAN_1_2 (1UL)
3473 #define SEI_CTRL_LATCH_TRAN_2_3 (2UL)
3474 #define SEI_CTRL_LATCH_TRAN_3_0 (3UL)
3475 
3476 /* LATCH register group index macro definition */
3477 #define SEI_LATCH_0 (0UL)
3478 #define SEI_LATCH_1 (1UL)
3479 #define SEI_LATCH_2 (2UL)
3480 #define SEI_LATCH_3 (3UL)
3481 
3482 /* CTRL register group index macro definition */
3483 #define SEI_CTRL_0 (0UL)
3484 #define SEI_CTRL_1 (1UL)
3485 
3486 /* INSTR register group index macro definition */
3487 #define SEI_INSTR_0 (0UL)
3488 #define SEI_INSTR_1 (1UL)
3489 #define SEI_INSTR_2 (2UL)
3490 #define SEI_INSTR_3 (3UL)
3491 #define SEI_INSTR_4 (4UL)
3492 #define SEI_INSTR_5 (5UL)
3493 #define SEI_INSTR_6 (6UL)
3494 #define SEI_INSTR_7 (7UL)
3495 #define SEI_INSTR_8 (8UL)
3496 #define SEI_INSTR_9 (9UL)
3497 #define SEI_INSTR_10 (10UL)
3498 #define SEI_INSTR_11 (11UL)
3499 #define SEI_INSTR_12 (12UL)
3500 #define SEI_INSTR_13 (13UL)
3501 #define SEI_INSTR_14 (14UL)
3502 #define SEI_INSTR_15 (15UL)
3503 #define SEI_INSTR_16 (16UL)
3504 #define SEI_INSTR_17 (17UL)
3505 #define SEI_INSTR_18 (18UL)
3506 #define SEI_INSTR_19 (19UL)
3507 #define SEI_INSTR_20 (20UL)
3508 #define SEI_INSTR_21 (21UL)
3509 #define SEI_INSTR_22 (22UL)
3510 #define SEI_INSTR_23 (23UL)
3511 #define SEI_INSTR_24 (24UL)
3512 #define SEI_INSTR_25 (25UL)
3513 #define SEI_INSTR_26 (26UL)
3514 #define SEI_INSTR_27 (27UL)
3515 #define SEI_INSTR_28 (28UL)
3516 #define SEI_INSTR_29 (29UL)
3517 #define SEI_INSTR_30 (30UL)
3518 #define SEI_INSTR_31 (31UL)
3519 #define SEI_INSTR_32 (32UL)
3520 #define SEI_INSTR_33 (33UL)
3521 #define SEI_INSTR_34 (34UL)
3522 #define SEI_INSTR_35 (35UL)
3523 #define SEI_INSTR_36 (36UL)
3524 #define SEI_INSTR_37 (37UL)
3525 #define SEI_INSTR_38 (38UL)
3526 #define SEI_INSTR_39 (39UL)
3527 #define SEI_INSTR_40 (40UL)
3528 #define SEI_INSTR_41 (41UL)
3529 #define SEI_INSTR_42 (42UL)
3530 #define SEI_INSTR_43 (43UL)
3531 #define SEI_INSTR_44 (44UL)
3532 #define SEI_INSTR_45 (45UL)
3533 #define SEI_INSTR_46 (46UL)
3534 #define SEI_INSTR_47 (47UL)
3535 #define SEI_INSTR_48 (48UL)
3536 #define SEI_INSTR_49 (49UL)
3537 #define SEI_INSTR_50 (50UL)
3538 #define SEI_INSTR_51 (51UL)
3539 #define SEI_INSTR_52 (52UL)
3540 #define SEI_INSTR_53 (53UL)
3541 #define SEI_INSTR_54 (54UL)
3542 #define SEI_INSTR_55 (55UL)
3543 #define SEI_INSTR_56 (56UL)
3544 #define SEI_INSTR_57 (57UL)
3545 #define SEI_INSTR_58 (58UL)
3546 #define SEI_INSTR_59 (59UL)
3547 #define SEI_INSTR_60 (60UL)
3548 #define SEI_INSTR_61 (61UL)
3549 #define SEI_INSTR_62 (62UL)
3550 #define SEI_INSTR_63 (63UL)
3551 
3552 /* DAT register group index macro definition */
3553 #define SEI_DAT_0 (0UL)
3554 #define SEI_DAT_1 (1UL)
3555 #define SEI_DAT_2 (2UL)
3556 #define SEI_DAT_3 (3UL)
3557 #define SEI_DAT_4 (4UL)
3558 #define SEI_DAT_5 (5UL)
3559 #define SEI_DAT_6 (6UL)
3560 #define SEI_DAT_7 (7UL)
3561 #define SEI_DAT_8 (8UL)
3562 #define SEI_DAT_9 (9UL)
3563 
3564 
3565 #endif /* HPM_SEI_H */
MIN
#define MIN(a, b)
Definition: hpm_common.h:49
MAX
#define MAX(a, b)
Definition: hpm_common.h:46
SEI_Type
Definition: hpm_sei_regs.h:12