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Data Structures | |
| struct | SEI_Type |
| #define SEI_CMD_TABLE_0 (0UL) |
| #define SEI_CMD_TABLE_1 (1UL) |
| #define SEI_CMD_TABLE_2 (2UL) |
| #define SEI_CMD_TABLE_3 (3UL) |
| #define SEI_CMD_TABLE_4 (4UL) |
| #define SEI_CMD_TABLE_5 (5UL) |
| #define SEI_CMD_TABLE_6 (6UL) |
| #define SEI_CMD_TABLE_7 (7UL) |
| #define SEI_CTRL_0 (0UL) |
| #define SEI_CTRL_1 (1UL) |
| #define SEI_CTRL_CMD_CLR_DATA_CLR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) >> SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) |
| #define SEI_CTRL_CMD_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_CLR_DATA_CLR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT) & SEI_CTRL_CMD_CLR_DATA_CLR_MASK) |
| #define SEI_CTRL_CMD_CLR_DATA_CLR_SHIFT (0U) |
| #define SEI_CTRL_CMD_CMD_DATA_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_CMD_DATA_MASK) >> SEI_CTRL_CMD_CMD_DATA_SHIFT) |
| #define SEI_CTRL_CMD_CMD_DATA_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_CMD_DATA_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_CMD_DATA_SHIFT) & SEI_CTRL_CMD_CMD_DATA_MASK) |
| #define SEI_CTRL_CMD_CMD_DATA_SHIFT (0U) |
| #define SEI_CTRL_CMD_IDX_FIRST_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) >> SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) |
| #define SEI_CTRL_CMD_IDX_FIRST_BIT_MASK (0x1F0000UL) |
| #define SEI_CTRL_CMD_IDX_FIRST_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_FIRST_BIT_MASK) |
| #define SEI_CTRL_CMD_IDX_FIRST_BIT_SHIFT (16U) |
| #define SEI_CTRL_CMD_IDX_LAST_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) >> SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) |
| #define SEI_CTRL_CMD_IDX_LAST_BIT_MASK (0x1F000000UL) |
| #define SEI_CTRL_CMD_IDX_LAST_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT) & SEI_CTRL_CMD_IDX_LAST_BIT_MASK) |
| #define SEI_CTRL_CMD_IDX_LAST_BIT_SHIFT (24U) |
| #define SEI_CTRL_CMD_IDX_MAX_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) >> SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) |
| #define SEI_CTRL_CMD_IDX_MAX_BIT_MASK (0x1F00U) |
| #define SEI_CTRL_CMD_IDX_MAX_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MAX_BIT_MASK) |
| #define SEI_CTRL_CMD_IDX_MAX_BIT_SHIFT (8U) |
| #define SEI_CTRL_CMD_IDX_MIN_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) >> SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) |
| #define SEI_CTRL_CMD_IDX_MIN_BIT_MASK (0x1FU) |
| #define SEI_CTRL_CMD_IDX_MIN_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT) & SEI_CTRL_CMD_IDX_MIN_BIT_MASK) |
| #define SEI_CTRL_CMD_IDX_MIN_BIT_SHIFT (0U) |
| #define SEI_CTRL_CMD_IN_DATA_IN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_IN_DATA_IN_MASK) >> SEI_CTRL_CMD_IN_DATA_IN_SHIFT) |
| #define SEI_CTRL_CMD_IN_DATA_IN_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_IN_DATA_IN_SHIFT (0U) |
| #define SEI_CTRL_CMD_INV_DATA_TGL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) >> SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) |
| #define SEI_CTRL_CMD_INV_DATA_TGL_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_INV_DATA_TGL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_INV_DATA_TGL_SHIFT) & SEI_CTRL_CMD_INV_DATA_TGL_MASK) |
| #define SEI_CTRL_CMD_INV_DATA_TGL_SHIFT (0U) |
| #define SEI_CTRL_CMD_MODE_BORDER_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_MODE_BORDER_MASK) >> SEI_CTRL_CMD_MODE_BORDER_SHIFT) |
| #define SEI_CTRL_CMD_MODE_BORDER_MASK (0x400U) |
| #define SEI_CTRL_CMD_MODE_BORDER_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_MODE_BORDER_SHIFT) & SEI_CTRL_CMD_MODE_BORDER_MASK) |
| #define SEI_CTRL_CMD_MODE_BORDER_SHIFT (10U) |
| #define SEI_CTRL_CMD_MODE_MODE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_MODE_MODE_MASK) >> SEI_CTRL_CMD_MODE_MODE_SHIFT) |
| #define SEI_CTRL_CMD_MODE_MODE_MASK (0x3U) |
| #define SEI_CTRL_CMD_MODE_MODE_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_MODE_MODE_SHIFT) & SEI_CTRL_CMD_MODE_MODE_MASK) |
| #define SEI_CTRL_CMD_MODE_MODE_SHIFT (0U) |
| #define SEI_CTRL_CMD_MODE_REWIND_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_MODE_REWIND_MASK) >> SEI_CTRL_CMD_MODE_REWIND_SHIFT) |
| #define SEI_CTRL_CMD_MODE_REWIND_MASK (0x100U) |
| #define SEI_CTRL_CMD_MODE_REWIND_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_MODE_REWIND_SHIFT) & SEI_CTRL_CMD_MODE_REWIND_MASK) |
| #define SEI_CTRL_CMD_MODE_REWIND_SHIFT (8U) |
| #define SEI_CTRL_CMD_MODE_SIGNED_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_MODE_SIGNED_MASK) >> SEI_CTRL_CMD_MODE_SIGNED_SHIFT) |
| #define SEI_CTRL_CMD_MODE_SIGNED_MASK (0x200U) |
| #define SEI_CTRL_CMD_MODE_SIGNED_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_MODE_SIGNED_SHIFT) & SEI_CTRL_CMD_MODE_SIGNED_MASK) |
| #define SEI_CTRL_CMD_MODE_SIGNED_SHIFT (9U) |
| #define SEI_CTRL_CMD_MODE_WLEN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WLEN_MASK) >> SEI_CTRL_CMD_MODE_WLEN_SHIFT) |
| #define SEI_CTRL_CMD_MODE_WLEN_MASK (0x1F0000UL) |
| #define SEI_CTRL_CMD_MODE_WLEN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WLEN_SHIFT) & SEI_CTRL_CMD_MODE_WLEN_MASK) |
| #define SEI_CTRL_CMD_MODE_WLEN_SHIFT (16U) |
| #define SEI_CTRL_CMD_MODE_WORDER_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_MODE_WORDER_MASK) >> SEI_CTRL_CMD_MODE_WORDER_SHIFT) |
| #define SEI_CTRL_CMD_MODE_WORDER_MASK (0x800U) |
| #define SEI_CTRL_CMD_MODE_WORDER_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_MODE_WORDER_SHIFT) & SEI_CTRL_CMD_MODE_WORDER_MASK) |
| #define SEI_CTRL_CMD_MODE_WORDER_SHIFT (11U) |
| #define SEI_CTRL_CMD_OUT_DATA_OUT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_OUT_DATA_OUT_MASK) >> SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT) |
| #define SEI_CTRL_CMD_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_OUT_DATA_OUT_SHIFT (0U) |
| #define SEI_CTRL_CMD_SET_DATA_SET_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_SET_DATA_SET_MASK) >> SEI_CTRL_CMD_SET_DATA_SET_SHIFT) |
| #define SEI_CTRL_CMD_SET_DATA_SET_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_SET_DATA_SET_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_SET_DATA_SET_SHIFT) & SEI_CTRL_CMD_SET_DATA_SET_MASK) |
| #define SEI_CTRL_CMD_SET_DATA_SET_SHIFT (0U) |
| #define SEI_CTRL_CMD_STS_BIT_IDX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_STS_BIT_IDX_MASK) >> SEI_CTRL_CMD_STS_BIT_IDX_SHIFT) |
| #define SEI_CTRL_CMD_STS_BIT_IDX_MASK (0x1FU) |
| #define SEI_CTRL_CMD_STS_BIT_IDX_SHIFT (0U) |
| #define SEI_CTRL_CMD_STS_WORD_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_CNT_MASK) >> SEI_CTRL_CMD_STS_WORD_CNT_SHIFT) |
| #define SEI_CTRL_CMD_STS_WORD_CNT_MASK (0x1F00U) |
| #define SEI_CTRL_CMD_STS_WORD_CNT_SHIFT (8U) |
| #define SEI_CTRL_CMD_STS_WORD_IDX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_STS_WORD_IDX_MASK) >> SEI_CTRL_CMD_STS_WORD_IDX_SHIFT) |
| #define SEI_CTRL_CMD_STS_WORD_IDX_MASK (0x1F0000UL) |
| #define SEI_CTRL_CMD_STS_WORD_IDX_SHIFT (16U) |
| #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) >> SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT) & SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_MASK) |
| #define SEI_CTRL_CMD_TABLE_MAX_CMD_MAX_SHIFT (0U) |
| #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) >> SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT) & SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_MASK) |
| #define SEI_CTRL_CMD_TABLE_MIN_CMD_MIN_SHIFT (0U) |
| #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) >> SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT) & SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_MASK) |
| #define SEI_CTRL_CMD_TABLE_MSK_CMD_MASK_SHIFT (0U) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK (0xFFU) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR0_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR0_SHIFT (0U) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK (0xFF00U) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR1_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR1_SHIFT (8U) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK (0xFF0000UL) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR2_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR2_SHIFT (16U) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) >> SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK (0xFF000000UL) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT) & SEI_CTRL_CMD_TABLE_PTA_PTR3_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTA_PTR3_SHIFT (24U) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR4_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK (0xFFU) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR4_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR4_SHIFT (0U) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR5_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK (0xFF00U) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR5_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR5_SHIFT (8U) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR6_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK (0xFF0000UL) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR6_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR6_SHIFT (16U) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR7_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) >> SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK (0xFF000000UL) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT) & SEI_CTRL_CMD_TABLE_PTB_PTR7_MASK) |
| #define SEI_CTRL_CMD_TABLE_PTB_PTR7_SHIFT (24U) |
| #define SEI_CTRL_DMA_EN_EXCEPT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_EXCEPT_MASK) >> SEI_CTRL_DMA_EN_EXCEPT_SHIFT) |
| #define SEI_CTRL_DMA_EN_EXCEPT_MASK (0x2U) |
| #define SEI_CTRL_DMA_EN_EXCEPT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_EXCEPT_SHIFT) & SEI_CTRL_DMA_EN_EXCEPT_MASK) |
| #define SEI_CTRL_DMA_EN_EXCEPT_SHIFT (1U) |
| #define SEI_CTRL_DMA_EN_INSTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_END_MASK) >> SEI_CTRL_DMA_EN_INSTR0_END_SHIFT) |
| #define SEI_CTRL_DMA_EN_INSTR0_END_MASK (0x400U) |
| #define SEI_CTRL_DMA_EN_INSTR0_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_END_MASK) |
| #define SEI_CTRL_DMA_EN_INSTR0_END_SHIFT (10U) |
| #define SEI_CTRL_DMA_EN_INSTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT) |
| #define SEI_CTRL_DMA_EN_INSTR0_ST_MASK (0x40U) |
| #define SEI_CTRL_DMA_EN_INSTR0_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR0_ST_MASK) |
| #define SEI_CTRL_DMA_EN_INSTR0_ST_SHIFT (6U) |
| #define SEI_CTRL_DMA_EN_INSTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_END_MASK) >> SEI_CTRL_DMA_EN_INSTR1_END_SHIFT) |
| #define SEI_CTRL_DMA_EN_INSTR1_END_MASK (0x800U) |
| #define SEI_CTRL_DMA_EN_INSTR1_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_END_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_END_MASK) |
| #define SEI_CTRL_DMA_EN_INSTR1_END_SHIFT (11U) |
| #define SEI_CTRL_DMA_EN_INSTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK) >> SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT) |
| #define SEI_CTRL_DMA_EN_INSTR1_ST_MASK (0x80U) |
| #define SEI_CTRL_DMA_EN_INSTR1_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_INSTR1_ST_MASK) |
| #define SEI_CTRL_DMA_EN_INSTR1_ST_SHIFT (7U) |
| #define SEI_CTRL_DMA_EN_LATCH0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH0_MASK) >> SEI_CTRL_DMA_EN_LATCH0_SHIFT) |
| #define SEI_CTRL_DMA_EN_LATCH0_MASK (0x10000UL) |
| #define SEI_CTRL_DMA_EN_LATCH0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH0_SHIFT) & SEI_CTRL_DMA_EN_LATCH0_MASK) |
| #define SEI_CTRL_DMA_EN_LATCH0_SHIFT (16U) |
| #define SEI_CTRL_DMA_EN_LATCH1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH1_MASK) >> SEI_CTRL_DMA_EN_LATCH1_SHIFT) |
| #define SEI_CTRL_DMA_EN_LATCH1_MASK (0x20000UL) |
| #define SEI_CTRL_DMA_EN_LATCH1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH1_SHIFT) & SEI_CTRL_DMA_EN_LATCH1_MASK) |
| #define SEI_CTRL_DMA_EN_LATCH1_SHIFT (17U) |
| #define SEI_CTRL_DMA_EN_LATCH2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH2_MASK) >> SEI_CTRL_DMA_EN_LATCH2_SHIFT) |
| #define SEI_CTRL_DMA_EN_LATCH2_MASK (0x40000UL) |
| #define SEI_CTRL_DMA_EN_LATCH2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH2_SHIFT) & SEI_CTRL_DMA_EN_LATCH2_MASK) |
| #define SEI_CTRL_DMA_EN_LATCH2_SHIFT (18U) |
| #define SEI_CTRL_DMA_EN_LATCH3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_LATCH3_MASK) >> SEI_CTRL_DMA_EN_LATCH3_SHIFT) |
| #define SEI_CTRL_DMA_EN_LATCH3_MASK (0x80000UL) |
| #define SEI_CTRL_DMA_EN_LATCH3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_LATCH3_SHIFT) & SEI_CTRL_DMA_EN_LATCH3_MASK) |
| #define SEI_CTRL_DMA_EN_LATCH3_SHIFT (19U) |
| #define SEI_CTRL_DMA_EN_PTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_END_MASK) >> SEI_CTRL_DMA_EN_PTR0_END_SHIFT) |
| #define SEI_CTRL_DMA_EN_PTR0_END_MASK (0x100U) |
| #define SEI_CTRL_DMA_EN_PTR0_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_END_SHIFT) & SEI_CTRL_DMA_EN_PTR0_END_MASK) |
| #define SEI_CTRL_DMA_EN_PTR0_END_SHIFT (8U) |
| #define SEI_CTRL_DMA_EN_PTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR0_ST_MASK) >> SEI_CTRL_DMA_EN_PTR0_ST_SHIFT) |
| #define SEI_CTRL_DMA_EN_PTR0_ST_MASK (0x10U) |
| #define SEI_CTRL_DMA_EN_PTR0_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR0_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR0_ST_MASK) |
| #define SEI_CTRL_DMA_EN_PTR0_ST_SHIFT (4U) |
| #define SEI_CTRL_DMA_EN_PTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_END_MASK) >> SEI_CTRL_DMA_EN_PTR1_END_SHIFT) |
| #define SEI_CTRL_DMA_EN_PTR1_END_MASK (0x200U) |
| #define SEI_CTRL_DMA_EN_PTR1_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_END_SHIFT) & SEI_CTRL_DMA_EN_PTR1_END_MASK) |
| #define SEI_CTRL_DMA_EN_PTR1_END_SHIFT (9U) |
| #define SEI_CTRL_DMA_EN_PTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_PTR1_ST_MASK) >> SEI_CTRL_DMA_EN_PTR1_ST_SHIFT) |
| #define SEI_CTRL_DMA_EN_PTR1_ST_MASK (0x20U) |
| #define SEI_CTRL_DMA_EN_PTR1_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_PTR1_ST_SHIFT) & SEI_CTRL_DMA_EN_PTR1_ST_MASK) |
| #define SEI_CTRL_DMA_EN_PTR1_ST_SHIFT (5U) |
| #define SEI_CTRL_DMA_EN_SMP_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_SMP_ERR_MASK) >> SEI_CTRL_DMA_EN_SMP_ERR_SHIFT) |
| #define SEI_CTRL_DMA_EN_SMP_ERR_MASK (0x100000UL) |
| #define SEI_CTRL_DMA_EN_SMP_ERR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_SMP_ERR_SHIFT) & SEI_CTRL_DMA_EN_SMP_ERR_MASK) |
| #define SEI_CTRL_DMA_EN_SMP_ERR_SHIFT (20U) |
| #define SEI_CTRL_DMA_EN_STALL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_STALL_MASK) >> SEI_CTRL_DMA_EN_STALL_SHIFT) |
| #define SEI_CTRL_DMA_EN_STALL_MASK (0x1U) |
| #define SEI_CTRL_DMA_EN_STALL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_STALL_SHIFT) & SEI_CTRL_DMA_EN_STALL_MASK) |
| #define SEI_CTRL_DMA_EN_STALL_SHIFT (0U) |
| #define SEI_CTRL_DMA_EN_TIMEOUT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TIMEOUT_MASK) >> SEI_CTRL_DMA_EN_TIMEOUT_SHIFT) |
| #define SEI_CTRL_DMA_EN_TIMEOUT_MASK (0x2000U) |
| #define SEI_CTRL_DMA_EN_TIMEOUT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TIMEOUT_SHIFT) & SEI_CTRL_DMA_EN_TIMEOUT_MASK) |
| #define SEI_CTRL_DMA_EN_TIMEOUT_SHIFT (13U) |
| #define SEI_CTRL_DMA_EN_TRG_ERR0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRG_ERR0_MASK (0x10000000UL) |
| #define SEI_CTRL_DMA_EN_TRG_ERR0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR0_MASK) |
| #define SEI_CTRL_DMA_EN_TRG_ERR0_SHIFT (28U) |
| #define SEI_CTRL_DMA_EN_TRG_ERR1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRG_ERR1_MASK (0x20000000UL) |
| #define SEI_CTRL_DMA_EN_TRG_ERR1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR1_MASK) |
| #define SEI_CTRL_DMA_EN_TRG_ERR1_SHIFT (29U) |
| #define SEI_CTRL_DMA_EN_TRG_ERR2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRG_ERR2_MASK (0x40000000UL) |
| #define SEI_CTRL_DMA_EN_TRG_ERR2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR2_MASK) |
| #define SEI_CTRL_DMA_EN_TRG_ERR2_SHIFT (30U) |
| #define SEI_CTRL_DMA_EN_TRG_ERR3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK) >> SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRG_ERR3_MASK (0x80000000UL) |
| #define SEI_CTRL_DMA_EN_TRG_ERR3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT) & SEI_CTRL_DMA_EN_TRG_ERR3_MASK) |
| #define SEI_CTRL_DMA_EN_TRG_ERR3_SHIFT (31U) |
| #define SEI_CTRL_DMA_EN_TRIGER0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER0_MASK) >> SEI_CTRL_DMA_EN_TRIGER0_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRIGER0_MASK (0x1000000UL) |
| #define SEI_CTRL_DMA_EN_TRIGER0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER0_SHIFT) & SEI_CTRL_DMA_EN_TRIGER0_MASK) |
| #define SEI_CTRL_DMA_EN_TRIGER0_SHIFT (24U) |
| #define SEI_CTRL_DMA_EN_TRIGER1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER1_MASK) >> SEI_CTRL_DMA_EN_TRIGER1_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRIGER1_MASK (0x2000000UL) |
| #define SEI_CTRL_DMA_EN_TRIGER1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER1_SHIFT) & SEI_CTRL_DMA_EN_TRIGER1_MASK) |
| #define SEI_CTRL_DMA_EN_TRIGER1_SHIFT (25U) |
| #define SEI_CTRL_DMA_EN_TRIGER2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER2_MASK) >> SEI_CTRL_DMA_EN_TRIGER2_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRIGER2_MASK (0x4000000UL) |
| #define SEI_CTRL_DMA_EN_TRIGER2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER2_SHIFT) & SEI_CTRL_DMA_EN_TRIGER2_MASK) |
| #define SEI_CTRL_DMA_EN_TRIGER2_SHIFT (26U) |
| #define SEI_CTRL_DMA_EN_TRIGER3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRIGER3_MASK) >> SEI_CTRL_DMA_EN_TRIGER3_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRIGER3_MASK (0x8000000UL) |
| #define SEI_CTRL_DMA_EN_TRIGER3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRIGER3_SHIFT) & SEI_CTRL_DMA_EN_TRIGER3_MASK) |
| #define SEI_CTRL_DMA_EN_TRIGER3_SHIFT (27U) |
| #define SEI_CTRL_DMA_EN_TRX_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_TRX_ERR_MASK) >> SEI_CTRL_DMA_EN_TRX_ERR_SHIFT) |
| #define SEI_CTRL_DMA_EN_TRX_ERR_MASK (0x1000U) |
| #define SEI_CTRL_DMA_EN_TRX_ERR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_TRX_ERR_SHIFT) & SEI_CTRL_DMA_EN_TRX_ERR_MASK) |
| #define SEI_CTRL_DMA_EN_TRX_ERR_SHIFT (12U) |
| #define SEI_CTRL_DMA_EN_WDOG_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_DMA_EN_WDOG_MASK) >> SEI_CTRL_DMA_EN_WDOG_SHIFT) |
| #define SEI_CTRL_DMA_EN_WDOG_MASK (0x4U) |
| #define SEI_CTRL_DMA_EN_WDOG_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_DMA_EN_WDOG_SHIFT) & SEI_CTRL_DMA_EN_WDOG_MASK) |
| #define SEI_CTRL_DMA_EN_WDOG_SHIFT (2U) |
| #define SEI_CTRL_ENGINE_CTRL_ARMING_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) >> SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) |
| #define SEI_CTRL_ENGINE_CTRL_ARMING_MASK (0x10000UL) |
| #define SEI_CTRL_ENGINE_CTRL_ARMING_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT) & SEI_CTRL_ENGINE_CTRL_ARMING_MASK) |
| #define SEI_CTRL_ENGINE_CTRL_ARMING_SHIFT (16U) |
| #define SEI_CTRL_ENGINE_CTRL_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) >> SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) |
| #define SEI_CTRL_ENGINE_CTRL_ENABLE_MASK (0x1U) |
| #define SEI_CTRL_ENGINE_CTRL_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT) & SEI_CTRL_ENGINE_CTRL_ENABLE_MASK) |
| #define SEI_CTRL_ENGINE_CTRL_ENABLE_SHIFT (0U) |
| #define SEI_CTRL_ENGINE_CTRL_EXCEPT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) >> SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) |
| #define SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK (0x100U) |
| #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT) & SEI_CTRL_ENGINE_CTRL_EXCEPT_MASK) |
| #define SEI_CTRL_ENGINE_CTRL_EXCEPT_SHIFT (8U) |
| #define SEI_CTRL_ENGINE_CTRL_REWIND_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) >> SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) |
| #define SEI_CTRL_ENGINE_CTRL_REWIND_MASK (0x10U) |
| #define SEI_CTRL_ENGINE_CTRL_REWIND_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT) & SEI_CTRL_ENGINE_CTRL_REWIND_MASK) |
| #define SEI_CTRL_ENGINE_CTRL_REWIND_SHIFT (4U) |
| #define SEI_CTRL_ENGINE_CTRL_WATCH_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) >> SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) |
| #define SEI_CTRL_ENGINE_CTRL_WATCH_MASK (0x1000000UL) |
| #define SEI_CTRL_ENGINE_CTRL_WATCH_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT) & SEI_CTRL_ENGINE_CTRL_WATCH_MASK) |
| #define SEI_CTRL_ENGINE_CTRL_WATCH_SHIFT (24U) |
| #define SEI_CTRL_ENGINE_EXE_INST_INST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_INST_INST_MASK) >> SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_INST_INST_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_ENGINE_EXE_INST_INST_SHIFT (0U) |
| #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_MASK (0x1F0000UL) |
| #define SEI_CTRL_ENGINE_EXE_PTR_BIT_CNT_SHIFT (16U) |
| #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_MASK (0x1F000000UL) |
| #define SEI_CTRL_ENGINE_EXE_PTR_HALT_CNT_SHIFT (24U) |
| #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK) >> SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_MASK (0xFFU) |
| #define SEI_CTRL_ENGINE_EXE_PTR_POINTER_SHIFT (0U) |
| #define SEI_CTRL_ENGINE_EXE_STA_ARMED_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_STA_ARMED_MASK (0x10000UL) |
| #define SEI_CTRL_ENGINE_EXE_STA_ARMED_SHIFT (16U) |
| #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK) >> SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_MASK (0x100U) |
| #define SEI_CTRL_ENGINE_EXE_STA_EXPIRE_SHIFT (8U) |
| #define SEI_CTRL_ENGINE_EXE_STA_STALL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_STALL_MASK) >> SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_STA_STALL_MASK (0x1U) |
| #define SEI_CTRL_ENGINE_EXE_STA_STALL_SHIFT (0U) |
| #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK) >> SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT) |
| #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_MASK (0x100000UL) |
| #define SEI_CTRL_ENGINE_EXE_STA_TRIGERED_SHIFT (20U) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK (0x1F0000UL) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_MASK) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_BASE_SHIFT (16U) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK (0x1F000000UL) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_MASK) |
| #define SEI_CTRL_ENGINE_PTR_CFG_DAT_CDM_SHIFT (24U) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK (0xFFU) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_MASK) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_INIT_SHIFT (0U) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) >> SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK (0xFF00U) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT) & SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_MASK) |
| #define SEI_CTRL_ENGINE_PTR_CFG_POINTER_WDOG_SHIFT (8U) |
| #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) >> SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) |
| #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK (0xFFFFU) |
| #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT) & SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_MASK) |
| #define SEI_CTRL_ENGINE_WDG_CFG_WDOG_TIME_SHIFT (0U) |
| #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK) >> SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT) |
| #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_MASK (0xFFFFU) |
| #define SEI_CTRL_ENGINE_WDG_STA_WDOG_CNT_SHIFT (0U) |
| #define SEI_CTRL_IRQ_INSTR0_INSTR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) |
| #define SEI_CTRL_IRQ_INSTR0_INSTR_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_IRQ_INSTR0_INSTR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR0_INSTR_MASK) |
| #define SEI_CTRL_IRQ_INSTR0_INSTR_SHIFT (0U) |
| #define SEI_CTRL_IRQ_INSTR1_INSTR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) >> SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) |
| #define SEI_CTRL_IRQ_INSTR1_INSTR_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_IRQ_INSTR1_INSTR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT) & SEI_CTRL_IRQ_INSTR1_INSTR_MASK) |
| #define SEI_CTRL_IRQ_INSTR1_INSTR_SHIFT (0U) |
| #define SEI_CTRL_IRQ_INT_EN_EXCEPT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK (0x2U) |
| #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_EN_EXCEPT_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_EXCEPT_SHIFT (1U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK (0x400U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_END_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_END_SHIFT (10U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK (0x40U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR0_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR0_ST_SHIFT (6U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK (0x800U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_END_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_END_SHIFT (11U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK (0x80U) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_INSTR1_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_INSTR1_ST_SHIFT (7U) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH0_MASK (0x10000UL) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH0_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH0_SHIFT (16U) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH1_MASK (0x20000UL) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH1_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH1_SHIFT (17U) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH2_MASK (0x40000UL) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH2_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH2_SHIFT (18U) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH3_MASK (0x80000UL) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_EN_LATCH3_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_LATCH3_SHIFT (19U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK (0x100U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_END_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_END_SHIFT (8U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK (0x10U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR0_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_PTR0_ST_SHIFT (4U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK (0x200U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_END_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_END_SHIFT (9U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK (0x20U) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_EN_PTR1_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_PTR1_ST_SHIFT (5U) |
| #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK (0x100000UL) |
| #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_SMP_ERR_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_SMP_ERR_SHIFT (20U) |
| #define SEI_CTRL_IRQ_INT_EN_STALL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) >> SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_STALL_MASK (0x1U) |
| #define SEI_CTRL_IRQ_INT_EN_STALL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_STALL_SHIFT) & SEI_CTRL_IRQ_INT_EN_STALL_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_STALL_SHIFT (0U) |
| #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK (0x2000U) |
| #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_EN_TIMEOUT_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TIMEOUT_SHIFT (13U) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK (0x10000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR0_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR0_SHIFT (28U) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK (0x20000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR1_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR1_SHIFT (29U) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK (0x40000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR2_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR2_SHIFT (30U) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK (0x80000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRG_ERR3_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRG_ERR3_SHIFT (31U) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK (0x1000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER0_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER0_SHIFT (24U) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK (0x2000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER1_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER1_SHIFT (25U) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK (0x4000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER2_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER2_SHIFT (26U) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK (0x8000000UL) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRIGER3_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRIGER3_SHIFT (27U) |
| #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK (0x1000U) |
| #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_EN_TRX_ERR_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_TRX_ERR_SHIFT (12U) |
| #define SEI_CTRL_IRQ_INT_EN_WDOG_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) >> SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) |
| #define SEI_CTRL_IRQ_INT_EN_WDOG_MASK (0x4U) |
| #define SEI_CTRL_IRQ_INT_EN_WDOG_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_EN_WDOG_MASK) |
| #define SEI_CTRL_IRQ_INT_EN_WDOG_SHIFT (2U) |
| #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK (0x2U) |
| #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_EXCEPT_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_EXCEPT_SHIFT (1U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK (0x400U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_END_SHIFT (10U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK (0x40U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR0_ST_SHIFT (6U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK (0x800U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_END_SHIFT (11U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK (0x80U) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_INSTR1_ST_SHIFT (7U) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK (0x10000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH0_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH0_SHIFT (16U) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK (0x20000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH1_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH1_SHIFT (17U) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK (0x40000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH2_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH2_SHIFT (18U) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK (0x80000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_LATCH3_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_LATCH3_SHIFT (19U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK (0x100U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_END_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_END_SHIFT (8U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK (0x10U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR0_ST_SHIFT (4U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK (0x200U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_END_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_END_SHIFT (9U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK (0x20U) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_PTR1_ST_SHIFT (5U) |
| #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK (0x100000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_SMP_ERR_SHIFT (20U) |
| #define SEI_CTRL_IRQ_INT_FLAG_STALL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) >> SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_STALL_MASK (0x1U) |
| #define SEI_CTRL_IRQ_INT_FLAG_STALL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_STALL_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_STALL_SHIFT (0U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK (0x2000U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TIMEOUT_SHIFT (13U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK (0x10000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR0_SHIFT (28U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK (0x20000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR1_SHIFT (29U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK (0x40000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR2_SHIFT (30U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK (0x80000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRG_ERR3_SHIFT (31U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK (0x1000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER0_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER0_SHIFT (24U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK (0x2000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER1_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER1_SHIFT (25U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK (0x4000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER2_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER2_SHIFT (26U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK (0x8000000UL) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRIGER3_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRIGER3_SHIFT (27U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK (0x1000U) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_TRX_ERR_SHIFT (12U) |
| #define SEI_CTRL_IRQ_INT_FLAG_WDOG_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) >> SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) |
| #define SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK (0x4U) |
| #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT) & SEI_CTRL_IRQ_INT_FLAG_WDOG_MASK) |
| #define SEI_CTRL_IRQ_INT_FLAG_WDOG_SHIFT (2U) |
| #define SEI_CTRL_IRQ_INT_STS_EXCEPT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK) >> SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_EXCEPT_MASK (0x2U) |
| #define SEI_CTRL_IRQ_INT_STS_EXCEPT_SHIFT (1U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_MASK (0x400U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR0_END_SHIFT (10U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_MASK (0x40U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR0_ST_SHIFT (6U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_MASK (0x800U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR1_END_SHIFT (11U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_MASK (0x80U) |
| #define SEI_CTRL_IRQ_INT_STS_INSTR1_ST_SHIFT (7U) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH0_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH0_MASK (0x10000UL) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH0_SHIFT (16U) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH1_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH1_MASK (0x20000UL) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH1_SHIFT (17U) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH2_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH2_MASK (0x40000UL) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH2_SHIFT (18U) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_LATCH3_MASK) >> SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH3_MASK (0x80000UL) |
| #define SEI_CTRL_IRQ_INT_STS_LATCH3_SHIFT (19U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR0_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_PTR0_END_MASK (0x100U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR0_END_SHIFT (8U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_MASK (0x10U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR0_ST_SHIFT (4U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR1_END_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_PTR1_END_MASK (0x200U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR1_END_SHIFT (9U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK) >> SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_MASK (0x20U) |
| #define SEI_CTRL_IRQ_INT_STS_PTR1_ST_SHIFT (5U) |
| #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_MASK (0x100000UL) |
| #define SEI_CTRL_IRQ_INT_STS_SMP_ERR_SHIFT (20U) |
| #define SEI_CTRL_IRQ_INT_STS_STALL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_STALL_MASK) >> SEI_CTRL_IRQ_INT_STS_STALL_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_STALL_MASK (0x1U) |
| #define SEI_CTRL_IRQ_INT_STS_STALL_SHIFT (0U) |
| #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK) >> SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_MASK (0x2000U) |
| #define SEI_CTRL_IRQ_INT_STS_TIMEOUT_SHIFT (13U) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_MASK (0x10000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR0_SHIFT (28U) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_MASK (0x20000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR1_SHIFT (29U) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_MASK (0x40000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR2_SHIFT (30U) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_MASK (0x80000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRG_ERR3_SHIFT (31U) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER0_MASK (0x1000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER0_SHIFT (24U) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER1_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER1_MASK (0x2000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER1_SHIFT (25U) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER2_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER2_MASK (0x4000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER2_SHIFT (26U) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER3_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK) >> SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER3_MASK (0x8000000UL) |
| #define SEI_CTRL_IRQ_INT_STS_TRIGER3_SHIFT (27U) |
| #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK) >> SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_MASK (0x1000U) |
| #define SEI_CTRL_IRQ_INT_STS_TRX_ERR_SHIFT (12U) |
| #define SEI_CTRL_IRQ_INT_STS_WDOG_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_INT_STS_WDOG_MASK) >> SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT) |
| #define SEI_CTRL_IRQ_INT_STS_WDOG_MASK (0x4U) |
| #define SEI_CTRL_IRQ_INT_STS_WDOG_SHIFT (2U) |
| #define SEI_CTRL_IRQ_POINTER0_POINTER_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) |
| #define SEI_CTRL_IRQ_POINTER0_POINTER_MASK (0xFFU) |
| #define SEI_CTRL_IRQ_POINTER0_POINTER_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER0_POINTER_MASK) |
| #define SEI_CTRL_IRQ_POINTER0_POINTER_SHIFT (0U) |
| #define SEI_CTRL_IRQ_POINTER1_POINTER_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) >> SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) |
| #define SEI_CTRL_IRQ_POINTER1_POINTER_MASK (0xFFU) |
| #define SEI_CTRL_IRQ_POINTER1_POINTER_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT) & SEI_CTRL_IRQ_POINTER1_POINTER_MASK) |
| #define SEI_CTRL_IRQ_POINTER1_POINTER_SHIFT (0U) |
| #define SEI_CTRL_LATCH_CFG_DELAY_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_DELAY_MASK) >> SEI_CTRL_LATCH_CFG_DELAY_SHIFT) |
| #define SEI_CTRL_LATCH_CFG_DELAY_MASK (0xFFFFU) |
| #define SEI_CTRL_LATCH_CFG_DELAY_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_DELAY_SHIFT) & SEI_CTRL_LATCH_CFG_DELAY_MASK) |
| #define SEI_CTRL_LATCH_CFG_DELAY_SHIFT (0U) |
| #define SEI_CTRL_LATCH_CFG_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_EN_MASK) >> SEI_CTRL_LATCH_CFG_EN_SHIFT) |
| #define SEI_CTRL_LATCH_CFG_EN_MASK (0x80000000UL) |
| #define SEI_CTRL_LATCH_CFG_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_EN_SHIFT) & SEI_CTRL_LATCH_CFG_EN_MASK) |
| #define SEI_CTRL_LATCH_CFG_EN_SHIFT (31U) |
| #define SEI_CTRL_LATCH_CFG_SELECT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_CFG_SELECT_MASK) >> SEI_CTRL_LATCH_CFG_SELECT_SHIFT) |
| #define SEI_CTRL_LATCH_CFG_SELECT_MASK (0x7000000UL) |
| #define SEI_CTRL_LATCH_CFG_SELECT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_CFG_SELECT_SHIFT) & SEI_CTRL_LATCH_CFG_SELECT_MASK) |
| #define SEI_CTRL_LATCH_CFG_SELECT_SHIFT (24U) |
| #define SEI_CTRL_LATCH_STS_LAT_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_STS_LAT_CNT_MASK) >> SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT) |
| #define SEI_CTRL_LATCH_STS_LAT_CNT_MASK (0xFFFFU) |
| #define SEI_CTRL_LATCH_STS_LAT_CNT_SHIFT (0U) |
| #define SEI_CTRL_LATCH_STS_STATE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_STS_STATE_MASK) >> SEI_CTRL_LATCH_STS_STATE_SHIFT) |
| #define SEI_CTRL_LATCH_STS_STATE_MASK (0x7000000UL) |
| #define SEI_CTRL_LATCH_STS_STATE_SHIFT (24U) |
| #define SEI_CTRL_LATCH_TIME_LAT_TIME_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TIME_LAT_TIME_MASK) >> SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT) |
| #define SEI_CTRL_LATCH_TIME_LAT_TIME_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_LATCH_TIME_LAT_TIME_SHIFT (0U) |
| #define SEI_CTRL_LATCH_TRAN_0_1 (0UL) |
| #define SEI_CTRL_LATCH_TRAN_1_2 (1UL) |
| #define SEI_CTRL_LATCH_TRAN_2_3 (2UL) |
| #define SEI_CTRL_LATCH_TRAN_3_0 (3UL) |
| #define SEI_CTRL_LATCH_TRAN_CFG_CLK_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK (0xC00U) |
| #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_CLK_MASK) |
| #define SEI_CTRL_LATCH_TRAN_CFG_CLK_SHIFT (10U) |
| #define SEI_CTRL_LATCH_TRAN_CFG_PTR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK (0x300U) |
| #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_PTR_MASK) |
| #define SEI_CTRL_LATCH_TRAN_CFG_PTR_SHIFT (8U) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TM_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TM_MASK (0x30000UL) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TM_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TM_MASK) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TM_SHIFT (16U) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TXD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK (0x3000U) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_CFG_TXD_MASK) |
| #define SEI_CTRL_LATCH_TRAN_CFG_TXD_SHIFT (12U) |
| #define SEI_CTRL_LATCH_TRAN_OV_CLK_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) >> SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_OV_CLK_MASK (0x2U) |
| #define SEI_CTRL_LATCH_TRAN_OV_CLK_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_CLK_MASK) |
| #define SEI_CTRL_LATCH_TRAN_OV_CLK_SHIFT (1U) |
| #define SEI_CTRL_LATCH_TRAN_OV_PTR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) >> SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_OV_PTR_MASK (0x1U) |
| #define SEI_CTRL_LATCH_TRAN_OV_PTR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_PTR_MASK) |
| #define SEI_CTRL_LATCH_TRAN_OV_PTR_SHIFT (0U) |
| #define SEI_CTRL_LATCH_TRAN_OV_TM_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_OV_TM_MASK (0x10U) |
| #define SEI_CTRL_LATCH_TRAN_OV_TM_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TM_MASK) |
| #define SEI_CTRL_LATCH_TRAN_OV_TM_SHIFT (4U) |
| #define SEI_CTRL_LATCH_TRAN_OV_TXD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) >> SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_OV_TXD_MASK (0x4U) |
| #define SEI_CTRL_LATCH_TRAN_OV_TXD_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT) & SEI_CTRL_LATCH_TRAN_OV_TXD_MASK) |
| #define SEI_CTRL_LATCH_TRAN_OV_TXD_SHIFT (2U) |
| #define SEI_CTRL_LATCH_TRAN_POINTER_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) >> SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) |
| #define SEI_CTRL_LATCH_TRAN_POINTER_MASK (0xFF000000UL) |
| #define SEI_CTRL_LATCH_TRAN_POINTER_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_LATCH_TRAN_POINTER_SHIFT) & SEI_CTRL_LATCH_TRAN_POINTER_MASK) |
| #define SEI_CTRL_LATCH_TRAN_POINTER_SHIFT (24U) |
| #define SEI_CTRL_POS_ACC_IN_ACC_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_ACC_IN_ACC_MASK) >> SEI_CTRL_POS_ACC_IN_ACC_SHIFT) |
| #define SEI_CTRL_POS_ACC_IN_ACC_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_ACC_IN_ACC_SHIFT (0U) |
| #define SEI_CTRL_POS_POS_IN_POS_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_POS_IN_POS_MASK) >> SEI_CTRL_POS_POS_IN_POS_SHIFT) |
| #define SEI_CTRL_POS_POS_IN_POS_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_POS_IN_POS_SHIFT (0U) |
| #define SEI_CTRL_POS_REV_IN_REV_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_REV_IN_REV_MASK) >> SEI_CTRL_POS_REV_IN_REV_SHIFT) |
| #define SEI_CTRL_POS_REV_IN_REV_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_REV_IN_REV_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_ACC_ACC_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) >> SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) |
| #define SEI_CTRL_POS_SMP_ACC_ACC_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_SMP_ACC_ACC_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_ACC_ACC_SHIFT) & SEI_CTRL_POS_SMP_ACC_ACC_MASK) |
| #define SEI_CTRL_POS_SMP_ACC_ACC_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) |
| #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK (0x30000UL) |
| #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_CFG_LAT_SEL_MASK) |
| #define SEI_CTRL_POS_SMP_CFG_LAT_SEL_SHIFT (16U) |
| #define SEI_CTRL_POS_SMP_CFG_ONCE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) >> SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) |
| #define SEI_CTRL_POS_SMP_CFG_ONCE_MASK (0x1000000UL) |
| #define SEI_CTRL_POS_SMP_CFG_ONCE_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT) & SEI_CTRL_POS_SMP_CFG_ONCE_MASK) |
| #define SEI_CTRL_POS_SMP_CFG_ONCE_SHIFT (24U) |
| #define SEI_CTRL_POS_SMP_CFG_WINDOW_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) >> SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) |
| #define SEI_CTRL_POS_SMP_CFG_WINDOW_MASK (0xFFFFU) |
| #define SEI_CTRL_POS_SMP_CFG_WINDOW_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT) & SEI_CTRL_POS_SMP_CFG_WINDOW_MASK) |
| #define SEI_CTRL_POS_SMP_CFG_WINDOW_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) |
| #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_SMP_DAT_DAT_SEL_MASK) |
| #define SEI_CTRL_POS_SMP_DAT_DAT_SEL_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_EN_ACC_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_ACC_EN_MASK (0x80000000UL) |
| #define SEI_CTRL_POS_SMP_EN_ACC_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_EN_MASK) |
| #define SEI_CTRL_POS_SMP_EN_ACC_EN_SHIFT (31U) |
| #define SEI_CTRL_POS_SMP_EN_ACC_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK (0x1F000000UL) |
| #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_ACC_SEL_MASK) |
| #define SEI_CTRL_POS_SMP_EN_ACC_SEL_SHIFT (24U) |
| #define SEI_CTRL_POS_SMP_EN_POS_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) >> SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_POS_EN_MASK (0x80U) |
| #define SEI_CTRL_POS_SMP_EN_POS_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_EN_MASK) |
| #define SEI_CTRL_POS_SMP_EN_POS_EN_SHIFT (7U) |
| #define SEI_CTRL_POS_SMP_EN_POS_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_POS_SEL_MASK (0x1FU) |
| #define SEI_CTRL_POS_SMP_EN_POS_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_POS_SEL_MASK) |
| #define SEI_CTRL_POS_SMP_EN_POS_SEL_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_EN_REV_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) >> SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_REV_EN_MASK (0x8000U) |
| #define SEI_CTRL_POS_SMP_EN_REV_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_EN_MASK) |
| #define SEI_CTRL_POS_SMP_EN_REV_EN_SHIFT (15U) |
| #define SEI_CTRL_POS_SMP_EN_REV_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_REV_SEL_MASK (0x1F00U) |
| #define SEI_CTRL_POS_SMP_EN_REV_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_REV_SEL_MASK) |
| #define SEI_CTRL_POS_SMP_EN_REV_SEL_SHIFT (8U) |
| #define SEI_CTRL_POS_SMP_EN_SPD_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_SPD_EN_MASK (0x800000UL) |
| #define SEI_CTRL_POS_SMP_EN_SPD_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_EN_MASK) |
| #define SEI_CTRL_POS_SMP_EN_SPD_EN_SHIFT (23U) |
| #define SEI_CTRL_POS_SMP_EN_SPD_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) |
| #define SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK (0x1F0000UL) |
| #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_SMP_EN_SPD_SEL_MASK) |
| #define SEI_CTRL_POS_SMP_EN_SPD_SEL_SHIFT (16U) |
| #define SEI_CTRL_POS_SMP_POS_POS_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_POS_POS_MASK) >> SEI_CTRL_POS_SMP_POS_POS_SHIFT) |
| #define SEI_CTRL_POS_SMP_POS_POS_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_SMP_POS_POS_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_POS_POS_SHIFT) & SEI_CTRL_POS_SMP_POS_POS_MASK) |
| #define SEI_CTRL_POS_SMP_POS_POS_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_REV_REV_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_REV_REV_MASK) >> SEI_CTRL_POS_SMP_REV_REV_SHIFT) |
| #define SEI_CTRL_POS_SMP_REV_REV_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_SMP_REV_REV_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_REV_REV_SHIFT) & SEI_CTRL_POS_SMP_REV_REV_MASK) |
| #define SEI_CTRL_POS_SMP_REV_REV_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_SPD_SPD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) >> SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) |
| #define SEI_CTRL_POS_SMP_SPD_SPD_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_SMP_SPD_SPD_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_SMP_SPD_SPD_SHIFT) & SEI_CTRL_POS_SMP_SPD_SPD_MASK) |
| #define SEI_CTRL_POS_SMP_SPD_SPD_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_STS_OCCUR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_OCCUR_MASK) >> SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT) |
| #define SEI_CTRL_POS_SMP_STS_OCCUR_MASK (0x1000000UL) |
| #define SEI_CTRL_POS_SMP_STS_OCCUR_SHIFT (24U) |
| #define SEI_CTRL_POS_SMP_STS_WIN_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK) >> SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT) |
| #define SEI_CTRL_POS_SMP_STS_WIN_CNT_MASK (0xFFFFU) |
| #define SEI_CTRL_POS_SMP_STS_WIN_CNT_SHIFT (0U) |
| #define SEI_CTRL_POS_SMP_VAL_ACC_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_ACC_MASK) >> SEI_CTRL_POS_SMP_VAL_ACC_SHIFT) |
| #define SEI_CTRL_POS_SMP_VAL_ACC_MASK (0x80000000UL) |
| #define SEI_CTRL_POS_SMP_VAL_ACC_SHIFT (31U) |
| #define SEI_CTRL_POS_SMP_VAL_POS_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_POS_MASK) >> SEI_CTRL_POS_SMP_VAL_POS_SHIFT) |
| #define SEI_CTRL_POS_SMP_VAL_POS_MASK (0x80U) |
| #define SEI_CTRL_POS_SMP_VAL_POS_SHIFT (7U) |
| #define SEI_CTRL_POS_SMP_VAL_REV_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_REV_MASK) >> SEI_CTRL_POS_SMP_VAL_REV_SHIFT) |
| #define SEI_CTRL_POS_SMP_VAL_REV_MASK (0x8000U) |
| #define SEI_CTRL_POS_SMP_VAL_REV_SHIFT (15U) |
| #define SEI_CTRL_POS_SMP_VAL_SPD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SMP_VAL_SPD_MASK) >> SEI_CTRL_POS_SMP_VAL_SPD_SHIFT) |
| #define SEI_CTRL_POS_SMP_VAL_SPD_MASK (0x800000UL) |
| #define SEI_CTRL_POS_SMP_VAL_SPD_SHIFT (23U) |
| #define SEI_CTRL_POS_SPD_IN_SPD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_SPD_IN_SPD_MASK) >> SEI_CTRL_POS_SPD_IN_SPD_SHIFT) |
| #define SEI_CTRL_POS_SPD_IN_SPD_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_SPD_IN_SPD_SHIFT (0U) |
| #define SEI_CTRL_POS_TIME_IN_TIME_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_TIME_IN_TIME_MASK) >> SEI_CTRL_POS_TIME_IN_TIME_SHIFT) |
| #define SEI_CTRL_POS_TIME_IN_TIME_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_TIME_IN_TIME_SHIFT (0U) |
| #define SEI_CTRL_POS_UPD_ACC_ACC_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) >> SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) |
| #define SEI_CTRL_POS_UPD_ACC_ACC_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_UPD_ACC_ACC_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_ACC_ACC_SHIFT) & SEI_CTRL_POS_UPD_ACC_ACC_MASK) |
| #define SEI_CTRL_POS_UPD_ACC_ACC_SHIFT (0U) |
| #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) >> SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) |
| #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK (0x30000UL) |
| #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_CFG_LAT_SEL_MASK) |
| #define SEI_CTRL_POS_UPD_CFG_LAT_SEL_SHIFT (16U) |
| #define SEI_CTRL_POS_UPD_CFG_ONERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) >> SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) |
| #define SEI_CTRL_POS_UPD_CFG_ONERR_MASK (0x1000000UL) |
| #define SEI_CTRL_POS_UPD_CFG_ONERR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT) & SEI_CTRL_POS_UPD_CFG_ONERR_MASK) |
| #define SEI_CTRL_POS_UPD_CFG_ONERR_SHIFT (24U) |
| #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) >> SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) |
| #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK (0x80000000UL) |
| #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT) & SEI_CTRL_POS_UPD_CFG_TIME_OVRD_MASK) |
| #define SEI_CTRL_POS_UPD_CFG_TIME_OVRD_SHIFT (31U) |
| #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) >> SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) |
| #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT) & SEI_CTRL_POS_UPD_DAT_DAT_SEL_MASK) |
| #define SEI_CTRL_POS_UPD_DAT_DAT_SEL_SHIFT (0U) |
| #define SEI_CTRL_POS_UPD_EN_ACC_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_ACC_EN_MASK (0x80000000UL) |
| #define SEI_CTRL_POS_UPD_EN_ACC_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_EN_MASK) |
| #define SEI_CTRL_POS_UPD_EN_ACC_EN_SHIFT (31U) |
| #define SEI_CTRL_POS_UPD_EN_ACC_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK (0x1F000000UL) |
| #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_ACC_SEL_MASK) |
| #define SEI_CTRL_POS_UPD_EN_ACC_SEL_SHIFT (24U) |
| #define SEI_CTRL_POS_UPD_EN_POS_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) >> SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_POS_EN_MASK (0x80U) |
| #define SEI_CTRL_POS_UPD_EN_POS_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_EN_MASK) |
| #define SEI_CTRL_POS_UPD_EN_POS_EN_SHIFT (7U) |
| #define SEI_CTRL_POS_UPD_EN_POS_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_POS_SEL_MASK (0x1FU) |
| #define SEI_CTRL_POS_UPD_EN_POS_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_POS_SEL_MASK) |
| #define SEI_CTRL_POS_UPD_EN_POS_SEL_SHIFT (0U) |
| #define SEI_CTRL_POS_UPD_EN_REV_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) >> SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_REV_EN_MASK (0x8000U) |
| #define SEI_CTRL_POS_UPD_EN_REV_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_EN_MASK) |
| #define SEI_CTRL_POS_UPD_EN_REV_EN_SHIFT (15U) |
| #define SEI_CTRL_POS_UPD_EN_REV_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_REV_SEL_MASK (0x1F00U) |
| #define SEI_CTRL_POS_UPD_EN_REV_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_REV_SEL_MASK) |
| #define SEI_CTRL_POS_UPD_EN_REV_SEL_SHIFT (8U) |
| #define SEI_CTRL_POS_UPD_EN_SPD_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_SPD_EN_MASK (0x800000UL) |
| #define SEI_CTRL_POS_UPD_EN_SPD_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_EN_MASK) |
| #define SEI_CTRL_POS_UPD_EN_SPD_EN_SHIFT (23U) |
| #define SEI_CTRL_POS_UPD_EN_SPD_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) >> SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) |
| #define SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK (0x1F0000UL) |
| #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT) & SEI_CTRL_POS_UPD_EN_SPD_SEL_MASK) |
| #define SEI_CTRL_POS_UPD_EN_SPD_SEL_SHIFT (16U) |
| #define SEI_CTRL_POS_UPD_POS_POS_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_POS_POS_MASK) >> SEI_CTRL_POS_UPD_POS_POS_SHIFT) |
| #define SEI_CTRL_POS_UPD_POS_POS_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_UPD_POS_POS_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_POS_POS_SHIFT) & SEI_CTRL_POS_UPD_POS_POS_MASK) |
| #define SEI_CTRL_POS_UPD_POS_POS_SHIFT (0U) |
| #define SEI_CTRL_POS_UPD_REV_REV_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_REV_REV_MASK) >> SEI_CTRL_POS_UPD_REV_REV_SHIFT) |
| #define SEI_CTRL_POS_UPD_REV_REV_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_UPD_REV_REV_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_REV_REV_SHIFT) & SEI_CTRL_POS_UPD_REV_REV_MASK) |
| #define SEI_CTRL_POS_UPD_REV_REV_SHIFT (0U) |
| #define SEI_CTRL_POS_UPD_SPD_SPD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) >> SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) |
| #define SEI_CTRL_POS_UPD_SPD_SPD_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_UPD_SPD_SPD_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_SPD_SPD_SHIFT) & SEI_CTRL_POS_UPD_SPD_SPD_MASK) |
| #define SEI_CTRL_POS_UPD_SPD_SPD_SHIFT (0U) |
| #define SEI_CTRL_POS_UPD_STS_UPD_ERR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK) >> SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT) |
| #define SEI_CTRL_POS_UPD_STS_UPD_ERR_MASK (0x1000000UL) |
| #define SEI_CTRL_POS_UPD_STS_UPD_ERR_SHIFT (24U) |
| #define SEI_CTRL_POS_UPD_TIME_TIME_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) >> SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) |
| #define SEI_CTRL_POS_UPD_TIME_TIME_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_POS_UPD_TIME_TIME_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_POS_UPD_TIME_TIME_SHIFT) & SEI_CTRL_POS_UPD_TIME_TIME_MASK) |
| #define SEI_CTRL_POS_UPD_TIME_TIME_SHIFT (0U) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK (0x80U) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_EN_MASK) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_EN_SHIFT (7U) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK (0x7U) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN0_SEL_MASK) |
| #define SEI_CTRL_TRG_IN_CFG_IN0_SEL_SHIFT (0U) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK (0x8000U) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_EN_MASK) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_EN_SHIFT (15U) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK (0x700U) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_IN1_SEL_MASK) |
| #define SEI_CTRL_TRG_IN_CFG_IN1_SEL_SHIFT (8U) |
| #define SEI_CTRL_TRG_IN_CFG_PRD_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) >> SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) |
| #define SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK (0x800000UL) |
| #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT) & SEI_CTRL_TRG_IN_CFG_PRD_EN_MASK) |
| #define SEI_CTRL_TRG_IN_CFG_PRD_EN_SHIFT (23U) |
| #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) >> SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) |
| #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK (0x70000UL) |
| #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT) & SEI_CTRL_TRG_IN_CFG_SYNC_SEL_MASK) |
| #define SEI_CTRL_TRG_IN_CFG_SYNC_SEL_SHIFT (16U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK (0x80U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_EN_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_EN_SHIFT (7U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK (0x7U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT0_SEL_SHIFT (0U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK (0x8000U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_EN_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_EN_SHIFT (15U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK (0x700U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT1_SEL_SHIFT (8U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK (0x800000UL) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_EN_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_EN_SHIFT (23U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK (0x70000UL) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT2_SEL_SHIFT (16U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK (0x80000000UL) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_EN_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_EN_SHIFT (31U) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) >> SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK (0x7000000UL) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT) & SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_MASK) |
| #define SEI_CTRL_TRG_OUT_CFG_OUT3_SEL_SHIFT (24U) |
| #define SEI_CTRL_TRG_PRD_CFG_ARMING_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) >> SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) |
| #define SEI_CTRL_TRG_PRD_CFG_ARMING_MASK (0x10000UL) |
| #define SEI_CTRL_TRG_PRD_CFG_ARMING_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT) & SEI_CTRL_TRG_PRD_CFG_ARMING_MASK) |
| #define SEI_CTRL_TRG_PRD_CFG_ARMING_SHIFT (16U) |
| #define SEI_CTRL_TRG_PRD_CFG_SYNC_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) >> SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) |
| #define SEI_CTRL_TRG_PRD_CFG_SYNC_MASK (0x1U) |
| #define SEI_CTRL_TRG_PRD_CFG_SYNC_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT) & SEI_CTRL_TRG_PRD_CFG_SYNC_MASK) |
| #define SEI_CTRL_TRG_PRD_CFG_SYNC_SHIFT (0U) |
| #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK) >> SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT) |
| #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_TRG_PRD_CNT_PERIOD_CNT_SHIFT (0U) |
| #define SEI_CTRL_TRG_PRD_PERIOD_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_PRD_PERIOD_MASK) >> SEI_CTRL_TRG_PRD_PERIOD_SHIFT) |
| #define SEI_CTRL_TRG_PRD_PERIOD_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_TRG_PRD_PERIOD_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_PRD_PERIOD_SHIFT) & SEI_CTRL_TRG_PRD_PERIOD_MASK) |
| #define SEI_CTRL_TRG_PRD_PERIOD_SHIFT (0U) |
| #define SEI_CTRL_TRG_PRD_STS_ARMED_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_ARMED_MASK) >> SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT) |
| #define SEI_CTRL_TRG_PRD_STS_ARMED_MASK (0x10000UL) |
| #define SEI_CTRL_TRG_PRD_STS_ARMED_SHIFT (16U) |
| #define SEI_CTRL_TRG_PRD_STS_TRIGERED_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK) >> SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT) |
| #define SEI_CTRL_TRG_PRD_STS_TRIGERED_MASK (0x100000UL) |
| #define SEI_CTRL_TRG_PRD_STS_TRIGERED_SHIFT (20U) |
| #define SEI_CTRL_TRG_SW_SOFT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_SW_SOFT_MASK) >> SEI_CTRL_TRG_SW_SOFT_SHIFT) |
| #define SEI_CTRL_TRG_SW_SOFT_MASK (0x1U) |
| #define SEI_CTRL_TRG_SW_SOFT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_SW_SOFT_SHIFT) & SEI_CTRL_TRG_SW_SOFT_MASK) |
| #define SEI_CTRL_TRG_SW_SOFT_SHIFT (0U) |
| #define SEI_CTRL_TRG_TABLE_CMD_0 (0UL) |
| #define SEI_CTRL_TRG_TABLE_CMD_1 (1UL) |
| #define SEI_CTRL_TRG_TABLE_CMD_2 (2UL) |
| #define SEI_CTRL_TRG_TABLE_CMD_3 (3UL) |
| #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) >> SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) |
| #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT) & SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_MASK) |
| #define SEI_CTRL_TRG_TABLE_CMD_CMD_TRIGGER0_SHIFT (0U) |
| #define SEI_CTRL_TRG_TABLE_TIME_0 (0UL) |
| #define SEI_CTRL_TRG_TABLE_TIME_1 (1UL) |
| #define SEI_CTRL_TRG_TABLE_TIME_2 (2UL) |
| #define SEI_CTRL_TRG_TABLE_TIME_3 (3UL) |
| #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK) >> SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT) |
| #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_MASK (0xFFFFFFFFUL) |
| #define SEI_CTRL_TRG_TABLE_TIME_TRIGGER0_TIME_SHIFT (0U) |
| #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) |
| #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK (0xFFFFU) |
| #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_MASK) |
| #define SEI_CTRL_XCVR_BAUD_CFG_BAUD_DIV_SHIFT (0U) |
| #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) >> SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) |
| #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK (0xFFFF0000UL) |
| #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT) & SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_MASK) |
| #define SEI_CTRL_XCVR_BAUD_CFG_SYNC_POINT_SHIFT (16U) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK (0xFFFFU) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_MASK) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK0_POINT_SHIFT (0U) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) >> SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK (0xFFFF0000UL) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT) & SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_MASK) |
| #define SEI_CTRL_XCVR_CLK_CFG_CK1_POINT_SHIFT (16U) |
| #define SEI_CTRL_XCVR_CTRL_MODE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_MODE_MASK) >> SEI_CTRL_XCVR_CTRL_MODE_SHIFT) |
| #define SEI_CTRL_XCVR_CTRL_MODE_MASK (0x3U) |
| #define SEI_CTRL_XCVR_CTRL_MODE_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_MODE_SHIFT) & SEI_CTRL_XCVR_CTRL_MODE_MASK) |
| #define SEI_CTRL_XCVR_CTRL_MODE_SHIFT (0U) |
| #define SEI_CTRL_XCVR_CTRL_PAR_CLR_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) >> SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) |
| #define SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK (0x100U) |
| #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT) & SEI_CTRL_XCVR_CTRL_PAR_CLR_MASK) |
| #define SEI_CTRL_XCVR_CTRL_PAR_CLR_SHIFT (8U) |
| #define SEI_CTRL_XCVR_CTRL_RESTART_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) >> SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) |
| #define SEI_CTRL_XCVR_CTRL_RESTART_MASK (0x10U) |
| #define SEI_CTRL_XCVR_CTRL_RESTART_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_RESTART_SHIFT) & SEI_CTRL_XCVR_CTRL_RESTART_MASK) |
| #define SEI_CTRL_XCVR_CTRL_RESTART_SHIFT (4U) |
| #define SEI_CTRL_XCVR_CTRL_TRISMP_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) >> SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) |
| #define SEI_CTRL_XCVR_CTRL_TRISMP_MASK (0x1000U) |
| #define SEI_CTRL_XCVR_CTRL_TRISMP_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT) & SEI_CTRL_XCVR_CTRL_TRISMP_MASK) |
| #define SEI_CTRL_XCVR_CTRL_TRISMP_SHIFT (12U) |
| #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) |
| #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK (0xFFFFU) |
| #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_MASK) |
| #define SEI_CTRL_XCVR_DATA_CFG_RXD_POINT_SHIFT (0U) |
| #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) >> SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) |
| #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK (0xFFFF0000UL) |
| #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT) & SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_MASK) |
| #define SEI_CTRL_XCVR_DATA_CFG_TXD_POINT_SHIFT (16U) |
| #define SEI_CTRL_XCVR_PIN_DI_CK_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_CK_MASK) >> SEI_CTRL_XCVR_PIN_DI_CK_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DI_CK_MASK (0x2000000UL) |
| #define SEI_CTRL_XCVR_PIN_DI_CK_SHIFT (25U) |
| #define SEI_CTRL_XCVR_PIN_DI_DE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_DE_MASK) >> SEI_CTRL_XCVR_PIN_DI_DE_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DI_DE_MASK (0x200U) |
| #define SEI_CTRL_XCVR_PIN_DI_DE_SHIFT (9U) |
| #define SEI_CTRL_XCVR_PIN_DI_RX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_RX_MASK) >> SEI_CTRL_XCVR_PIN_DI_RX_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DI_RX_MASK (0x20000UL) |
| #define SEI_CTRL_XCVR_PIN_DI_RX_SHIFT (17U) |
| #define SEI_CTRL_XCVR_PIN_DI_TX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DI_TX_MASK) >> SEI_CTRL_XCVR_PIN_DI_TX_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DI_TX_MASK (0x2U) |
| #define SEI_CTRL_XCVR_PIN_DI_TX_SHIFT (1U) |
| #define SEI_CTRL_XCVR_PIN_DO_CK_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_CK_MASK) >> SEI_CTRL_XCVR_PIN_DO_CK_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DO_CK_MASK (0x1000000UL) |
| #define SEI_CTRL_XCVR_PIN_DO_CK_SHIFT (24U) |
| #define SEI_CTRL_XCVR_PIN_DO_DE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_DE_MASK) >> SEI_CTRL_XCVR_PIN_DO_DE_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DO_DE_MASK (0x100U) |
| #define SEI_CTRL_XCVR_PIN_DO_DE_SHIFT (8U) |
| #define SEI_CTRL_XCVR_PIN_DO_RX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_RX_MASK) >> SEI_CTRL_XCVR_PIN_DO_RX_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DO_RX_MASK (0x10000UL) |
| #define SEI_CTRL_XCVR_PIN_DO_RX_SHIFT (16U) |
| #define SEI_CTRL_XCVR_PIN_DO_TX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_DO_TX_MASK) >> SEI_CTRL_XCVR_PIN_DO_TX_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_DO_TX_MASK (0x1U) |
| #define SEI_CTRL_XCVR_PIN_DO_TX_SHIFT (0U) |
| #define SEI_CTRL_XCVR_PIN_OE_CK_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_CK_MASK) >> SEI_CTRL_XCVR_PIN_OE_CK_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_OE_CK_MASK (0x4000000UL) |
| #define SEI_CTRL_XCVR_PIN_OE_CK_SHIFT (26U) |
| #define SEI_CTRL_XCVR_PIN_OE_DE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_DE_MASK) >> SEI_CTRL_XCVR_PIN_OE_DE_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_OE_DE_MASK (0x400U) |
| #define SEI_CTRL_XCVR_PIN_OE_DE_SHIFT (10U) |
| #define SEI_CTRL_XCVR_PIN_OE_RX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_RX_MASK) >> SEI_CTRL_XCVR_PIN_OE_RX_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_OE_RX_MASK (0x40000UL) |
| #define SEI_CTRL_XCVR_PIN_OE_RX_SHIFT (18U) |
| #define SEI_CTRL_XCVR_PIN_OE_TX_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_PIN_OE_TX_MASK) >> SEI_CTRL_XCVR_PIN_OE_TX_SHIFT) |
| #define SEI_CTRL_XCVR_PIN_OE_TX_MASK (0x4U) |
| #define SEI_CTRL_XCVR_PIN_OE_TX_SHIFT (2U) |
| #define SEI_CTRL_XCVR_STATE_RECV_STATE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_RECV_STATE_MASK) >> SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT) |
| #define SEI_CTRL_XCVR_STATE_RECV_STATE_MASK (0x7000000UL) |
| #define SEI_CTRL_XCVR_STATE_RECV_STATE_SHIFT (24U) |
| #define SEI_CTRL_XCVR_STATE_SEND_STATE_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_STATE_SEND_STATE_MASK) >> SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT) |
| #define SEI_CTRL_XCVR_STATE_SEND_STATE_MASK (0x70000UL) |
| #define SEI_CTRL_XCVR_STATE_SEND_STATE_SHIFT (16U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK (0x1U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEV_SHIFT (0U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK (0x4U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_CK_IDLEZ_SHIFT (2U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK (0x2U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEV_SHIFT (1U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK (0x8U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DA_IDLEZ_SHIFT (3U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK (0x1F0000UL) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_DATA_LEN_SHIFT (16U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK (0x100U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_EN_SHIFT (8U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK (0x200U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_PAR_POL_SHIFT (9U) |
| #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_GET | ( | x | ) | (((uint32_t)(x) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) >> SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) |
| #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK (0xFF000000UL) |
| #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SET | ( | x | ) | (((uint32_t)(x) << SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT) & SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_MASK) |
| #define SEI_CTRL_XCVR_TYPE_CFG_WAIT_LEN_SHIFT (24U) |
| #define SEI_DAT_0 (0UL) |
| #define SEI_DAT_1 (1UL) |
| #define SEI_DAT_2 (2UL) |
| #define SEI_DAT_3 (3UL) |
| #define SEI_DAT_4 (4UL) |
| #define SEI_DAT_5 (5UL) |
| #define SEI_DAT_6 (6UL) |
| #define SEI_DAT_7 (7UL) |
| #define SEI_DAT_8 (8UL) |
| #define SEI_DAT_9 (9UL) |
| #define SEI_DAT_CLR_DATA_CLR_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_CLR_DATA_CLR_MASK) >> SEI_DAT_CLR_DATA_CLR_SHIFT) |
| #define SEI_DAT_CLR_DATA_CLR_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_CLR_DATA_CLR_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_CLR_DATA_CLR_SHIFT) & SEI_DAT_CLR_DATA_CLR_MASK) |
| #define SEI_DAT_CLR_DATA_CLR_SHIFT (0U) |
| #define SEI_DAT_CRCINIT_CRC_INIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_CRCINIT_CRC_INIT_MASK) >> SEI_DAT_CRCINIT_CRC_INIT_SHIFT) |
| #define SEI_DAT_CRCINIT_CRC_INIT_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_CRCINIT_CRC_INIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_CRCINIT_CRC_INIT_SHIFT) & SEI_DAT_CRCINIT_CRC_INIT_MASK) |
| #define SEI_DAT_CRCINIT_CRC_INIT_SHIFT (0U) |
| #define SEI_DAT_CRCPOLY_CRC_POLY_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) >> SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) |
| #define SEI_DAT_CRCPOLY_CRC_POLY_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_CRCPOLY_CRC_POLY_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_CRCPOLY_CRC_POLY_SHIFT) & SEI_DAT_CRCPOLY_CRC_POLY_MASK) |
| #define SEI_DAT_CRCPOLY_CRC_POLY_SHIFT (0U) |
| #define SEI_DAT_DATA_DATA_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_DATA_DATA_MASK) >> SEI_DAT_DATA_DATA_SHIFT) |
| #define SEI_DAT_DATA_DATA_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_DATA_DATA_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_DATA_DATA_SHIFT) & SEI_DAT_DATA_DATA_MASK) |
| #define SEI_DAT_DATA_DATA_SHIFT (0U) |
| #define SEI_DAT_GOLD_GOLD_VALUE_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_GOLD_GOLD_VALUE_MASK) >> SEI_DAT_GOLD_GOLD_VALUE_SHIFT) |
| #define SEI_DAT_GOLD_GOLD_VALUE_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_GOLD_GOLD_VALUE_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_GOLD_GOLD_VALUE_SHIFT) & SEI_DAT_GOLD_GOLD_VALUE_MASK) |
| #define SEI_DAT_GOLD_GOLD_VALUE_SHIFT (0U) |
| #define SEI_DAT_IDX_FIRST_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_IDX_FIRST_BIT_MASK) >> SEI_DAT_IDX_FIRST_BIT_SHIFT) |
| #define SEI_DAT_IDX_FIRST_BIT_MASK (0x1F0000UL) |
| #define SEI_DAT_IDX_FIRST_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_IDX_FIRST_BIT_SHIFT) & SEI_DAT_IDX_FIRST_BIT_MASK) |
| #define SEI_DAT_IDX_FIRST_BIT_SHIFT (16U) |
| #define SEI_DAT_IDX_LAST_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_IDX_LAST_BIT_MASK) >> SEI_DAT_IDX_LAST_BIT_SHIFT) |
| #define SEI_DAT_IDX_LAST_BIT_MASK (0x1F000000UL) |
| #define SEI_DAT_IDX_LAST_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_IDX_LAST_BIT_SHIFT) & SEI_DAT_IDX_LAST_BIT_MASK) |
| #define SEI_DAT_IDX_LAST_BIT_SHIFT (24U) |
| #define SEI_DAT_IDX_MAX_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_IDX_MAX_BIT_MASK) >> SEI_DAT_IDX_MAX_BIT_SHIFT) |
| #define SEI_DAT_IDX_MAX_BIT_MASK (0x1F00U) |
| #define SEI_DAT_IDX_MAX_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_IDX_MAX_BIT_SHIFT) & SEI_DAT_IDX_MAX_BIT_MASK) |
| #define SEI_DAT_IDX_MAX_BIT_SHIFT (8U) |
| #define SEI_DAT_IDX_MIN_BIT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_IDX_MIN_BIT_MASK) >> SEI_DAT_IDX_MIN_BIT_SHIFT) |
| #define SEI_DAT_IDX_MIN_BIT_MASK (0x1FU) |
| #define SEI_DAT_IDX_MIN_BIT_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_IDX_MIN_BIT_SHIFT) & SEI_DAT_IDX_MIN_BIT_MASK) |
| #define SEI_DAT_IDX_MIN_BIT_SHIFT (0U) |
| #define SEI_DAT_IN_DATA_IN_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_IN_DATA_IN_MASK) >> SEI_DAT_IN_DATA_IN_SHIFT) |
| #define SEI_DAT_IN_DATA_IN_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_IN_DATA_IN_SHIFT (0U) |
| #define SEI_DAT_INV_DATA_INV_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_INV_DATA_INV_MASK) >> SEI_DAT_INV_DATA_INV_SHIFT) |
| #define SEI_DAT_INV_DATA_INV_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_INV_DATA_INV_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_INV_DATA_INV_SHIFT) & SEI_DAT_INV_DATA_INV_MASK) |
| #define SEI_DAT_INV_DATA_INV_SHIFT (0U) |
| #define SEI_DAT_MODE_BORDER_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_BORDER_MASK) >> SEI_DAT_MODE_BORDER_SHIFT) |
| #define SEI_DAT_MODE_BORDER_MASK (0x400U) |
| #define SEI_DAT_MODE_BORDER_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_BORDER_SHIFT) & SEI_DAT_MODE_BORDER_MASK) |
| #define SEI_DAT_MODE_BORDER_SHIFT (10U) |
| #define SEI_DAT_MODE_CRC_INV_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_CRC_INV_MASK) >> SEI_DAT_MODE_CRC_INV_SHIFT) |
| #define SEI_DAT_MODE_CRC_INV_MASK (0x1000U) |
| #define SEI_DAT_MODE_CRC_INV_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_CRC_INV_SHIFT) & SEI_DAT_MODE_CRC_INV_MASK) |
| #define SEI_DAT_MODE_CRC_INV_SHIFT (12U) |
| #define SEI_DAT_MODE_CRC_LEN_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_CRC_LEN_MASK) >> SEI_DAT_MODE_CRC_LEN_SHIFT) |
| #define SEI_DAT_MODE_CRC_LEN_MASK (0x1F000000UL) |
| #define SEI_DAT_MODE_CRC_LEN_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_CRC_LEN_SHIFT) & SEI_DAT_MODE_CRC_LEN_MASK) |
| #define SEI_DAT_MODE_CRC_LEN_SHIFT (24U) |
| #define SEI_DAT_MODE_CRC_SHIFT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_CRC_SHIFT_MASK) >> SEI_DAT_MODE_CRC_SHIFT_SHIFT) |
| #define SEI_DAT_MODE_CRC_SHIFT_MASK (0x2000U) |
| #define SEI_DAT_MODE_CRC_SHIFT_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_CRC_SHIFT_SHIFT) & SEI_DAT_MODE_CRC_SHIFT_MASK) |
| #define SEI_DAT_MODE_CRC_SHIFT_SHIFT (13U) |
| #define SEI_DAT_MODE_MODE_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_MODE_MASK) >> SEI_DAT_MODE_MODE_SHIFT) |
| #define SEI_DAT_MODE_MODE_MASK (0x3U) |
| #define SEI_DAT_MODE_MODE_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_MODE_SHIFT) & SEI_DAT_MODE_MODE_MASK) |
| #define SEI_DAT_MODE_MODE_SHIFT (0U) |
| #define SEI_DAT_MODE_REWIND_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_REWIND_MASK) >> SEI_DAT_MODE_REWIND_SHIFT) |
| #define SEI_DAT_MODE_REWIND_MASK (0x100U) |
| #define SEI_DAT_MODE_REWIND_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_REWIND_SHIFT) & SEI_DAT_MODE_REWIND_MASK) |
| #define SEI_DAT_MODE_REWIND_SHIFT (8U) |
| #define SEI_DAT_MODE_SIGNED_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_SIGNED_MASK) >> SEI_DAT_MODE_SIGNED_SHIFT) |
| #define SEI_DAT_MODE_SIGNED_MASK (0x200U) |
| #define SEI_DAT_MODE_SIGNED_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_SIGNED_SHIFT) & SEI_DAT_MODE_SIGNED_MASK) |
| #define SEI_DAT_MODE_SIGNED_SHIFT (9U) |
| #define SEI_DAT_MODE_WLEN_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_WLEN_MASK) >> SEI_DAT_MODE_WLEN_SHIFT) |
| #define SEI_DAT_MODE_WLEN_MASK (0x1F0000UL) |
| #define SEI_DAT_MODE_WLEN_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_WLEN_SHIFT) & SEI_DAT_MODE_WLEN_MASK) |
| #define SEI_DAT_MODE_WLEN_SHIFT (16U) |
| #define SEI_DAT_MODE_WORDER_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_MODE_WORDER_MASK) >> SEI_DAT_MODE_WORDER_SHIFT) |
| #define SEI_DAT_MODE_WORDER_MASK (0x800U) |
| #define SEI_DAT_MODE_WORDER_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_MODE_WORDER_SHIFT) & SEI_DAT_MODE_WORDER_MASK) |
| #define SEI_DAT_MODE_WORDER_SHIFT (11U) |
| #define SEI_DAT_OUT_DATA_OUT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_OUT_DATA_OUT_MASK) >> SEI_DAT_OUT_DATA_OUT_SHIFT) |
| #define SEI_DAT_OUT_DATA_OUT_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_OUT_DATA_OUT_SHIFT (0U) |
| #define SEI_DAT_SET_DATA_SET_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_SET_DATA_SET_MASK) >> SEI_DAT_SET_DATA_SET_SHIFT) |
| #define SEI_DAT_SET_DATA_SET_MASK (0xFFFFFFFFUL) |
| #define SEI_DAT_SET_DATA_SET_SET | ( | x | ) | (((uint32_t)(x) << SEI_DAT_SET_DATA_SET_SHIFT) & SEI_DAT_SET_DATA_SET_MASK) |
| #define SEI_DAT_SET_DATA_SET_SHIFT (0U) |
| #define SEI_DAT_STS_BIT_IDX_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_STS_BIT_IDX_MASK) >> SEI_DAT_STS_BIT_IDX_SHIFT) |
| #define SEI_DAT_STS_BIT_IDX_MASK (0x1FU) |
| #define SEI_DAT_STS_BIT_IDX_SHIFT (0U) |
| #define SEI_DAT_STS_CRC_IDX_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_STS_CRC_IDX_MASK) >> SEI_DAT_STS_CRC_IDX_SHIFT) |
| #define SEI_DAT_STS_CRC_IDX_MASK (0x1F000000UL) |
| #define SEI_DAT_STS_CRC_IDX_SHIFT (24U) |
| #define SEI_DAT_STS_WORD_CNT_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_STS_WORD_CNT_MASK) >> SEI_DAT_STS_WORD_CNT_SHIFT) |
| #define SEI_DAT_STS_WORD_CNT_MASK (0x1F00U) |
| #define SEI_DAT_STS_WORD_CNT_SHIFT (8U) |
| #define SEI_DAT_STS_WORD_IDX_GET | ( | x | ) | (((uint32_t)(x) & SEI_DAT_STS_WORD_IDX_MASK) >> SEI_DAT_STS_WORD_IDX_SHIFT) |
| #define SEI_DAT_STS_WORD_IDX_MASK (0x1F0000UL) |
| #define SEI_DAT_STS_WORD_IDX_SHIFT (16U) |
| #define SEI_INSTR_0 (0UL) |
| #define SEI_INSTR_1 (1UL) |
| #define SEI_INSTR_10 (10UL) |
| #define SEI_INSTR_11 (11UL) |
| #define SEI_INSTR_12 (12UL) |
| #define SEI_INSTR_13 (13UL) |
| #define SEI_INSTR_14 (14UL) |
| #define SEI_INSTR_15 (15UL) |
| #define SEI_INSTR_16 (16UL) |
| #define SEI_INSTR_17 (17UL) |
| #define SEI_INSTR_18 (18UL) |
| #define SEI_INSTR_19 (19UL) |
| #define SEI_INSTR_2 (2UL) |
| #define SEI_INSTR_20 (20UL) |
| #define SEI_INSTR_21 (21UL) |
| #define SEI_INSTR_22 (22UL) |
| #define SEI_INSTR_23 (23UL) |
| #define SEI_INSTR_24 (24UL) |
| #define SEI_INSTR_25 (25UL) |
| #define SEI_INSTR_26 (26UL) |
| #define SEI_INSTR_27 (27UL) |
| #define SEI_INSTR_28 (28UL) |
| #define SEI_INSTR_29 (29UL) |
| #define SEI_INSTR_3 (3UL) |
| #define SEI_INSTR_30 (30UL) |
| #define SEI_INSTR_31 (31UL) |
| #define SEI_INSTR_32 (32UL) |
| #define SEI_INSTR_33 (33UL) |
| #define SEI_INSTR_34 (34UL) |
| #define SEI_INSTR_35 (35UL) |
| #define SEI_INSTR_36 (36UL) |
| #define SEI_INSTR_37 (37UL) |
| #define SEI_INSTR_38 (38UL) |
| #define SEI_INSTR_39 (39UL) |
| #define SEI_INSTR_4 (4UL) |
| #define SEI_INSTR_40 (40UL) |
| #define SEI_INSTR_41 (41UL) |
| #define SEI_INSTR_42 (42UL) |
| #define SEI_INSTR_43 (43UL) |
| #define SEI_INSTR_44 (44UL) |
| #define SEI_INSTR_45 (45UL) |
| #define SEI_INSTR_46 (46UL) |
| #define SEI_INSTR_47 (47UL) |
| #define SEI_INSTR_48 (48UL) |
| #define SEI_INSTR_49 (49UL) |
| #define SEI_INSTR_5 (5UL) |
| #define SEI_INSTR_50 (50UL) |
| #define SEI_INSTR_51 (51UL) |
| #define SEI_INSTR_52 (52UL) |
| #define SEI_INSTR_53 (53UL) |
| #define SEI_INSTR_54 (54UL) |
| #define SEI_INSTR_55 (55UL) |
| #define SEI_INSTR_56 (56UL) |
| #define SEI_INSTR_57 (57UL) |
| #define SEI_INSTR_58 (58UL) |
| #define SEI_INSTR_59 (59UL) |
| #define SEI_INSTR_6 (6UL) |
| #define SEI_INSTR_60 (60UL) |
| #define SEI_INSTR_61 (61UL) |
| #define SEI_INSTR_62 (62UL) |
| #define SEI_INSTR_63 (63UL) |
| #define SEI_INSTR_7 (7UL) |
| #define SEI_INSTR_8 (8UL) |
| #define SEI_INSTR_9 (9UL) |
| #define SEI_INSTR_CK_GET | ( | x | ) | (((uint32_t)(x) & SEI_INSTR_CK_MASK) >> SEI_INSTR_CK_SHIFT) |
| #define SEI_INSTR_CK_MASK (0x3000000UL) |
| #define SEI_INSTR_CK_SET | ( | x | ) | (((uint32_t)(x) << SEI_INSTR_CK_SHIFT) & SEI_INSTR_CK_MASK) |
| #define SEI_INSTR_CK_SHIFT (24U) |
| #define SEI_INSTR_CRC_GET | ( | x | ) | (((uint32_t)(x) & SEI_INSTR_CRC_MASK) >> SEI_INSTR_CRC_SHIFT) |
| #define SEI_INSTR_CRC_MASK (0x1F0000UL) |
| #define SEI_INSTR_CRC_SET | ( | x | ) | (((uint32_t)(x) << SEI_INSTR_CRC_SHIFT) & SEI_INSTR_CRC_MASK) |
| #define SEI_INSTR_CRC_SHIFT (16U) |
| #define SEI_INSTR_DAT_GET | ( | x | ) | (((uint32_t)(x) & SEI_INSTR_DAT_MASK) >> SEI_INSTR_DAT_SHIFT) |
| #define SEI_INSTR_DAT_MASK (0x1F00U) |
| #define SEI_INSTR_DAT_SET | ( | x | ) | (((uint32_t)(x) << SEI_INSTR_DAT_SHIFT) & SEI_INSTR_DAT_MASK) |
| #define SEI_INSTR_DAT_SHIFT (8U) |
| #define SEI_INSTR_OP_GET | ( | x | ) | (((uint32_t)(x) & SEI_INSTR_OP_MASK) >> SEI_INSTR_OP_SHIFT) |
| #define SEI_INSTR_OP_MASK (0x1C000000UL) |
| #define SEI_INSTR_OP_SET | ( | x | ) | (((uint32_t)(x) << SEI_INSTR_OP_SHIFT) & SEI_INSTR_OP_MASK) |
| #define SEI_INSTR_OP_SHIFT (26U) |
| #define SEI_INSTR_OPR_GET | ( | x | ) | (((uint32_t)(x) & SEI_INSTR_OPR_MASK) >> SEI_INSTR_OPR_SHIFT) |
| #define SEI_INSTR_OPR_MASK (0x1FU) |
| #define SEI_INSTR_OPR_SET | ( | x | ) | (((uint32_t)(x) << SEI_INSTR_OPR_SHIFT) & SEI_INSTR_OPR_MASK) |
| #define SEI_INSTR_OPR_SHIFT (0U) |
| #define SEI_LATCH_0 (0UL) |
| #define SEI_LATCH_1 (1UL) |
| #define SEI_LATCH_2 (2UL) |
| #define SEI_LATCH_3 (3UL) |