hpm_bcfg_regs.h File Reference

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Data Structures
struct	BCFG_Type

Macros
#define	BCFG_VBG_CFG_VBG_TRIMMED_MASK   (0x80000000UL)
#define	BCFG_VBG_CFG_VBG_TRIMMED_SHIFT   (31U)
#define	BCFG_VBG_CFG_VBG_TRIMMED_SET(x)   (((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK)
#define	BCFG_VBG_CFG_VBG_TRIMMED_GET(x)   (((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT)
#define	BCFG_VBG_CFG_LP_MODE_MASK   (0x2000000UL)
#define	BCFG_VBG_CFG_LP_MODE_SHIFT   (25U)
#define	BCFG_VBG_CFG_LP_MODE_SET(x)   (((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK)
#define	BCFG_VBG_CFG_LP_MODE_GET(x)   (((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT)
#define	BCFG_VBG_CFG_POWER_SAVE_MASK   (0x1000000UL)
#define	BCFG_VBG_CFG_POWER_SAVE_SHIFT   (24U)
#define	BCFG_VBG_CFG_POWER_SAVE_SET(x)   (((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK)
#define	BCFG_VBG_CFG_POWER_SAVE_GET(x)   (((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT)
#define	BCFG_VBG_CFG_VBG_1P0_MASK   (0x1F0000UL)
#define	BCFG_VBG_CFG_VBG_1P0_SHIFT   (16U)
#define	BCFG_VBG_CFG_VBG_1P0_SET(x)   (((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK)
#define	BCFG_VBG_CFG_VBG_1P0_GET(x)   (((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT)
#define	BCFG_VBG_CFG_VBG_P65_MASK   (0x1F00U)
#define	BCFG_VBG_CFG_VBG_P65_SHIFT   (8U)
#define	BCFG_VBG_CFG_VBG_P65_SET(x)   (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK)
#define	BCFG_VBG_CFG_VBG_P65_GET(x)   (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT)
#define	BCFG_VBG_CFG_VBG_P50_MASK   (0x1FU)
#define	BCFG_VBG_CFG_VBG_P50_SHIFT   (0U)
#define	BCFG_VBG_CFG_VBG_P50_SET(x)   (((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK)
#define	BCFG_VBG_CFG_VBG_P50_GET(x)   (((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT)
#define	BCFG_LDO_CFG_RES_TRIM_MASK   (0x3000000UL)
#define	BCFG_LDO_CFG_RES_TRIM_SHIFT   (24U)
#define	BCFG_LDO_CFG_RES_TRIM_SET(x)   (((uint32_t)(x) << BCFG_LDO_CFG_RES_TRIM_SHIFT) & BCFG_LDO_CFG_RES_TRIM_MASK)
#define	BCFG_LDO_CFG_RES_TRIM_GET(x)   (((uint32_t)(x) & BCFG_LDO_CFG_RES_TRIM_MASK) >> BCFG_LDO_CFG_RES_TRIM_SHIFT)
#define	BCFG_LDO_CFG_CP_TRIM_MASK   (0x300000UL)
#define	BCFG_LDO_CFG_CP_TRIM_SHIFT   (20U)
#define	BCFG_LDO_CFG_CP_TRIM_SET(x)   (((uint32_t)(x) << BCFG_LDO_CFG_CP_TRIM_SHIFT) & BCFG_LDO_CFG_CP_TRIM_MASK)
#define	BCFG_LDO_CFG_CP_TRIM_GET(x)   (((uint32_t)(x) & BCFG_LDO_CFG_CP_TRIM_MASK) >> BCFG_LDO_CFG_CP_TRIM_SHIFT)
#define	BCFG_LDO_CFG_EN_SL_MASK   (0x40000UL)
#define	BCFG_LDO_CFG_EN_SL_SHIFT   (18U)
#define	BCFG_LDO_CFG_EN_SL_SET(x)   (((uint32_t)(x) << BCFG_LDO_CFG_EN_SL_SHIFT) & BCFG_LDO_CFG_EN_SL_MASK)
#define	BCFG_LDO_CFG_EN_SL_GET(x)   (((uint32_t)(x) & BCFG_LDO_CFG_EN_SL_MASK) >> BCFG_LDO_CFG_EN_SL_SHIFT)
#define	BCFG_LDO_CFG_DIS_PD_MASK   (0x20000UL)
#define	BCFG_LDO_CFG_DIS_PD_SHIFT   (17U)
#define	BCFG_LDO_CFG_DIS_PD_SET(x)   (((uint32_t)(x) << BCFG_LDO_CFG_DIS_PD_SHIFT) & BCFG_LDO_CFG_DIS_PD_MASK)
#define	BCFG_LDO_CFG_DIS_PD_GET(x)   (((uint32_t)(x) & BCFG_LDO_CFG_DIS_PD_MASK) >> BCFG_LDO_CFG_DIS_PD_SHIFT)
#define	BCFG_LDO_CFG_ENABLE_MASK   (0x10000UL)
#define	BCFG_LDO_CFG_ENABLE_SHIFT   (16U)
#define	BCFG_LDO_CFG_ENABLE_SET(x)   (((uint32_t)(x) << BCFG_LDO_CFG_ENABLE_SHIFT) & BCFG_LDO_CFG_ENABLE_MASK)
#define	BCFG_LDO_CFG_ENABLE_GET(x)   (((uint32_t)(x) & BCFG_LDO_CFG_ENABLE_MASK) >> BCFG_LDO_CFG_ENABLE_SHIFT)
#define	BCFG_LDO_CFG_VOLT_MASK   (0xFFFU)
#define	BCFG_LDO_CFG_VOLT_SHIFT   (0U)
#define	BCFG_LDO_CFG_VOLT_SET(x)   (((uint32_t)(x) << BCFG_LDO_CFG_VOLT_SHIFT) & BCFG_LDO_CFG_VOLT_MASK)
#define	BCFG_LDO_CFG_VOLT_GET(x)   (((uint32_t)(x) & BCFG_LDO_CFG_VOLT_MASK) >> BCFG_LDO_CFG_VOLT_SHIFT)
#define	BCFG_IRC32K_CFG_IRC_TRIMMED_MASK   (0x80000000UL)
#define	BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT   (31U)
#define	BCFG_IRC32K_CFG_IRC_TRIMMED_SET(x)   (((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK)
#define	BCFG_IRC32K_CFG_IRC_TRIMMED_GET(x)   (((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT)
#define	BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK   (0x800000UL)
#define	BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT   (23U)
#define	BCFG_IRC32K_CFG_CAPEX7_TRIM_SET(x)   (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK)
#define	BCFG_IRC32K_CFG_CAPEX7_TRIM_GET(x)   (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT)
#define	BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK   (0x400000UL)
#define	BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT   (22U)
#define	BCFG_IRC32K_CFG_CAPEX6_TRIM_SET(x)   (((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK)
#define	BCFG_IRC32K_CFG_CAPEX6_TRIM_GET(x)   (((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT)
#define	BCFG_IRC32K_CFG_CAP_TRIM_MASK   (0x1FFU)
#define	BCFG_IRC32K_CFG_CAP_TRIM_SHIFT   (0U)
#define	BCFG_IRC32K_CFG_CAP_TRIM_SET(x)   (((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK)
#define	BCFG_IRC32K_CFG_CAP_TRIM_GET(x)   (((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT)
#define	BCFG_XTAL32K_CFG_HYST_EN_MASK   (0x1000U)
#define	BCFG_XTAL32K_CFG_HYST_EN_SHIFT   (12U)
#define	BCFG_XTAL32K_CFG_HYST_EN_SET(x)   (((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK)
#define	BCFG_XTAL32K_CFG_HYST_EN_GET(x)   (((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT)
#define	BCFG_XTAL32K_CFG_GMSEL_MASK   (0x300U)
#define	BCFG_XTAL32K_CFG_GMSEL_SHIFT   (8U)
#define	BCFG_XTAL32K_CFG_GMSEL_SET(x)   (((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK)
#define	BCFG_XTAL32K_CFG_GMSEL_GET(x)   (((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT)
#define	BCFG_XTAL32K_CFG_CFG_MASK   (0x10U)
#define	BCFG_XTAL32K_CFG_CFG_SHIFT   (4U)
#define	BCFG_XTAL32K_CFG_CFG_SET(x)   (((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK)
#define	BCFG_XTAL32K_CFG_CFG_GET(x)   (((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT)
#define	BCFG_XTAL32K_CFG_AMP_MASK   (0x3U)
#define	BCFG_XTAL32K_CFG_AMP_SHIFT   (0U)
#define	BCFG_XTAL32K_CFG_AMP_SET(x)   (((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK)
#define	BCFG_XTAL32K_CFG_AMP_GET(x)   (((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT)
#define	BCFG_CLK_CFG_XTAL_SEL_MASK   (0x10000000UL)
#define	BCFG_CLK_CFG_XTAL_SEL_SHIFT   (28U)
#define	BCFG_CLK_CFG_XTAL_SEL_GET(x)   (((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT)
#define	BCFG_CLK_CFG_KEEP_IRC_MASK   (0x10000UL)
#define	BCFG_CLK_CFG_KEEP_IRC_SHIFT   (16U)
#define	BCFG_CLK_CFG_KEEP_IRC_SET(x)   (((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK)
#define	BCFG_CLK_CFG_KEEP_IRC_GET(x)   (((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT)
#define	BCFG_CLK_CFG_FORCE_XTAL_MASK   (0x10U)
#define	BCFG_CLK_CFG_FORCE_XTAL_SHIFT   (4U)
#define	BCFG_CLK_CFG_FORCE_XTAL_SET(x)   (((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK)
#define	BCFG_CLK_CFG_FORCE_XTAL_GET(x)   (((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT)

Macro Definition Documentation

BCFG_CLK_CFG_FORCE_XTAL_GET

#define BCFG_CLK_CFG_FORCE_XTAL_GET

(

x

)

(((uint32_t)(x) & BCFG_CLK_CFG_FORCE_XTAL_MASK) >> BCFG_CLK_CFG_FORCE_XTAL_SHIFT)

BCFG_CLK_CFG_FORCE_XTAL_MASK

#define BCFG_CLK_CFG_FORCE_XTAL_MASK   (0x10U)

BCFG_CLK_CFG_FORCE_XTAL_SET

#define BCFG_CLK_CFG_FORCE_XTAL_SET

(

x

)

(((uint32_t)(x) << BCFG_CLK_CFG_FORCE_XTAL_SHIFT) & BCFG_CLK_CFG_FORCE_XTAL_MASK)

BCFG_CLK_CFG_FORCE_XTAL_SHIFT

#define BCFG_CLK_CFG_FORCE_XTAL_SHIFT   (4U)

BCFG_CLK_CFG_KEEP_IRC_GET

#define BCFG_CLK_CFG_KEEP_IRC_GET

(

x

)

(((uint32_t)(x) & BCFG_CLK_CFG_KEEP_IRC_MASK) >> BCFG_CLK_CFG_KEEP_IRC_SHIFT)

BCFG_CLK_CFG_KEEP_IRC_MASK

#define BCFG_CLK_CFG_KEEP_IRC_MASK   (0x10000UL)

BCFG_CLK_CFG_KEEP_IRC_SET

#define BCFG_CLK_CFG_KEEP_IRC_SET

(

x

)

(((uint32_t)(x) << BCFG_CLK_CFG_KEEP_IRC_SHIFT) & BCFG_CLK_CFG_KEEP_IRC_MASK)

BCFG_CLK_CFG_KEEP_IRC_SHIFT

#define BCFG_CLK_CFG_KEEP_IRC_SHIFT   (16U)

BCFG_CLK_CFG_XTAL_SEL_GET

#define BCFG_CLK_CFG_XTAL_SEL_GET

(

x

)

(((uint32_t)(x) & BCFG_CLK_CFG_XTAL_SEL_MASK) >> BCFG_CLK_CFG_XTAL_SEL_SHIFT)

BCFG_CLK_CFG_XTAL_SEL_MASK

#define BCFG_CLK_CFG_XTAL_SEL_MASK   (0x10000000UL)

BCFG_CLK_CFG_XTAL_SEL_SHIFT

#define BCFG_CLK_CFG_XTAL_SEL_SHIFT   (28U)

BCFG_IRC32K_CFG_CAP_TRIM_GET

#define BCFG_IRC32K_CFG_CAP_TRIM_GET

(

x

)

(((uint32_t)(x) & BCFG_IRC32K_CFG_CAP_TRIM_MASK) >> BCFG_IRC32K_CFG_CAP_TRIM_SHIFT)

BCFG_IRC32K_CFG_CAP_TRIM_MASK

#define BCFG_IRC32K_CFG_CAP_TRIM_MASK   (0x1FFU)

BCFG_IRC32K_CFG_CAP_TRIM_SET

#define BCFG_IRC32K_CFG_CAP_TRIM_SET

(

x

)

(((uint32_t)(x) << BCFG_IRC32K_CFG_CAP_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAP_TRIM_MASK)

BCFG_IRC32K_CFG_CAP_TRIM_SHIFT

#define BCFG_IRC32K_CFG_CAP_TRIM_SHIFT   (0U)

BCFG_IRC32K_CFG_CAPEX6_TRIM_GET

#define BCFG_IRC32K_CFG_CAPEX6_TRIM_GET

(

x

)

(((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT)

BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK

#define BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK   (0x400000UL)

BCFG_IRC32K_CFG_CAPEX6_TRIM_SET

#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SET

(

x

)

(((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX6_TRIM_MASK)

BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT

#define BCFG_IRC32K_CFG_CAPEX6_TRIM_SHIFT   (22U)

BCFG_IRC32K_CFG_CAPEX7_TRIM_GET

#define BCFG_IRC32K_CFG_CAPEX7_TRIM_GET

(

x

)

(((uint32_t)(x) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK) >> BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT)

BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK

#define BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK   (0x800000UL)

BCFG_IRC32K_CFG_CAPEX7_TRIM_SET

#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SET

(

x

)

(((uint32_t)(x) << BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT) & BCFG_IRC32K_CFG_CAPEX7_TRIM_MASK)

BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT

#define BCFG_IRC32K_CFG_CAPEX7_TRIM_SHIFT   (23U)

BCFG_IRC32K_CFG_IRC_TRIMMED_GET

#define BCFG_IRC32K_CFG_IRC_TRIMMED_GET

(

x

)

(((uint32_t)(x) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK) >> BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT)

BCFG_IRC32K_CFG_IRC_TRIMMED_MASK

#define BCFG_IRC32K_CFG_IRC_TRIMMED_MASK   (0x80000000UL)

BCFG_IRC32K_CFG_IRC_TRIMMED_SET

#define BCFG_IRC32K_CFG_IRC_TRIMMED_SET

(

x

)

(((uint32_t)(x) << BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT) & BCFG_IRC32K_CFG_IRC_TRIMMED_MASK)

BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT

#define BCFG_IRC32K_CFG_IRC_TRIMMED_SHIFT   (31U)

BCFG_LDO_CFG_CP_TRIM_GET

#define BCFG_LDO_CFG_CP_TRIM_GET

(

x

)

(((uint32_t)(x) & BCFG_LDO_CFG_CP_TRIM_MASK) >> BCFG_LDO_CFG_CP_TRIM_SHIFT)

BCFG_LDO_CFG_CP_TRIM_MASK

#define BCFG_LDO_CFG_CP_TRIM_MASK   (0x300000UL)

BCFG_LDO_CFG_CP_TRIM_SET

#define BCFG_LDO_CFG_CP_TRIM_SET

(

x

)

(((uint32_t)(x) << BCFG_LDO_CFG_CP_TRIM_SHIFT) & BCFG_LDO_CFG_CP_TRIM_MASK)

BCFG_LDO_CFG_CP_TRIM_SHIFT

#define BCFG_LDO_CFG_CP_TRIM_SHIFT   (20U)

BCFG_LDO_CFG_DIS_PD_GET

#define BCFG_LDO_CFG_DIS_PD_GET

(

x

)

(((uint32_t)(x) & BCFG_LDO_CFG_DIS_PD_MASK) >> BCFG_LDO_CFG_DIS_PD_SHIFT)

BCFG_LDO_CFG_DIS_PD_MASK

#define BCFG_LDO_CFG_DIS_PD_MASK   (0x20000UL)

BCFG_LDO_CFG_DIS_PD_SET

#define BCFG_LDO_CFG_DIS_PD_SET

(

x

)

(((uint32_t)(x) << BCFG_LDO_CFG_DIS_PD_SHIFT) & BCFG_LDO_CFG_DIS_PD_MASK)

BCFG_LDO_CFG_DIS_PD_SHIFT

#define BCFG_LDO_CFG_DIS_PD_SHIFT   (17U)

BCFG_LDO_CFG_EN_SL_GET

#define BCFG_LDO_CFG_EN_SL_GET

(

x

)

(((uint32_t)(x) & BCFG_LDO_CFG_EN_SL_MASK) >> BCFG_LDO_CFG_EN_SL_SHIFT)

BCFG_LDO_CFG_EN_SL_MASK

#define BCFG_LDO_CFG_EN_SL_MASK   (0x40000UL)

BCFG_LDO_CFG_EN_SL_SET

#define BCFG_LDO_CFG_EN_SL_SET

(

x

)

(((uint32_t)(x) << BCFG_LDO_CFG_EN_SL_SHIFT) & BCFG_LDO_CFG_EN_SL_MASK)

BCFG_LDO_CFG_EN_SL_SHIFT

#define BCFG_LDO_CFG_EN_SL_SHIFT   (18U)

BCFG_LDO_CFG_ENABLE_GET

#define BCFG_LDO_CFG_ENABLE_GET

(

x

)

(((uint32_t)(x) & BCFG_LDO_CFG_ENABLE_MASK) >> BCFG_LDO_CFG_ENABLE_SHIFT)

BCFG_LDO_CFG_ENABLE_MASK

#define BCFG_LDO_CFG_ENABLE_MASK   (0x10000UL)

BCFG_LDO_CFG_ENABLE_SET

#define BCFG_LDO_CFG_ENABLE_SET

(

x

)

(((uint32_t)(x) << BCFG_LDO_CFG_ENABLE_SHIFT) & BCFG_LDO_CFG_ENABLE_MASK)

BCFG_LDO_CFG_ENABLE_SHIFT

#define BCFG_LDO_CFG_ENABLE_SHIFT   (16U)

BCFG_LDO_CFG_RES_TRIM_GET

#define BCFG_LDO_CFG_RES_TRIM_GET

(

x

)

(((uint32_t)(x) & BCFG_LDO_CFG_RES_TRIM_MASK) >> BCFG_LDO_CFG_RES_TRIM_SHIFT)

BCFG_LDO_CFG_RES_TRIM_MASK

#define BCFG_LDO_CFG_RES_TRIM_MASK   (0x3000000UL)

BCFG_LDO_CFG_RES_TRIM_SET

#define BCFG_LDO_CFG_RES_TRIM_SET

(

x

)

(((uint32_t)(x) << BCFG_LDO_CFG_RES_TRIM_SHIFT) & BCFG_LDO_CFG_RES_TRIM_MASK)

BCFG_LDO_CFG_RES_TRIM_SHIFT

#define BCFG_LDO_CFG_RES_TRIM_SHIFT   (24U)

BCFG_LDO_CFG_VOLT_GET

#define BCFG_LDO_CFG_VOLT_GET

(

x

)

(((uint32_t)(x) & BCFG_LDO_CFG_VOLT_MASK) >> BCFG_LDO_CFG_VOLT_SHIFT)

BCFG_LDO_CFG_VOLT_MASK

#define BCFG_LDO_CFG_VOLT_MASK   (0xFFFU)

BCFG_LDO_CFG_VOLT_SET

#define BCFG_LDO_CFG_VOLT_SET

(

x

)

(((uint32_t)(x) << BCFG_LDO_CFG_VOLT_SHIFT) & BCFG_LDO_CFG_VOLT_MASK)

BCFG_LDO_CFG_VOLT_SHIFT

#define BCFG_LDO_CFG_VOLT_SHIFT   (0U)

BCFG_VBG_CFG_LP_MODE_GET

#define BCFG_VBG_CFG_LP_MODE_GET

(

x

)

(((uint32_t)(x) & BCFG_VBG_CFG_LP_MODE_MASK) >> BCFG_VBG_CFG_LP_MODE_SHIFT)

BCFG_VBG_CFG_LP_MODE_MASK

#define BCFG_VBG_CFG_LP_MODE_MASK   (0x2000000UL)

BCFG_VBG_CFG_LP_MODE_SET

#define BCFG_VBG_CFG_LP_MODE_SET

(

x

)

(((uint32_t)(x) << BCFG_VBG_CFG_LP_MODE_SHIFT) & BCFG_VBG_CFG_LP_MODE_MASK)

BCFG_VBG_CFG_LP_MODE_SHIFT

#define BCFG_VBG_CFG_LP_MODE_SHIFT   (25U)

BCFG_VBG_CFG_POWER_SAVE_GET

#define BCFG_VBG_CFG_POWER_SAVE_GET

(

x

)

(((uint32_t)(x) & BCFG_VBG_CFG_POWER_SAVE_MASK) >> BCFG_VBG_CFG_POWER_SAVE_SHIFT)

BCFG_VBG_CFG_POWER_SAVE_MASK

#define BCFG_VBG_CFG_POWER_SAVE_MASK   (0x1000000UL)

BCFG_VBG_CFG_POWER_SAVE_SET

#define BCFG_VBG_CFG_POWER_SAVE_SET

(

x

)

(((uint32_t)(x) << BCFG_VBG_CFG_POWER_SAVE_SHIFT) & BCFG_VBG_CFG_POWER_SAVE_MASK)

BCFG_VBG_CFG_POWER_SAVE_SHIFT

#define BCFG_VBG_CFG_POWER_SAVE_SHIFT   (24U)

BCFG_VBG_CFG_VBG_1P0_GET

#define BCFG_VBG_CFG_VBG_1P0_GET

(

x

)

(((uint32_t)(x) & BCFG_VBG_CFG_VBG_1P0_MASK) >> BCFG_VBG_CFG_VBG_1P0_SHIFT)

BCFG_VBG_CFG_VBG_1P0_MASK

#define BCFG_VBG_CFG_VBG_1P0_MASK   (0x1F0000UL)

BCFG_VBG_CFG_VBG_1P0_SET

#define BCFG_VBG_CFG_VBG_1P0_SET

(

x

)

(((uint32_t)(x) << BCFG_VBG_CFG_VBG_1P0_SHIFT) & BCFG_VBG_CFG_VBG_1P0_MASK)

BCFG_VBG_CFG_VBG_1P0_SHIFT

#define BCFG_VBG_CFG_VBG_1P0_SHIFT   (16U)

BCFG_VBG_CFG_VBG_P50_GET

#define BCFG_VBG_CFG_VBG_P50_GET

(

x

)

(((uint32_t)(x) & BCFG_VBG_CFG_VBG_P50_MASK) >> BCFG_VBG_CFG_VBG_P50_SHIFT)

BCFG_VBG_CFG_VBG_P50_MASK

#define BCFG_VBG_CFG_VBG_P50_MASK   (0x1FU)

BCFG_VBG_CFG_VBG_P50_SET

#define BCFG_VBG_CFG_VBG_P50_SET

(

x

)

(((uint32_t)(x) << BCFG_VBG_CFG_VBG_P50_SHIFT) & BCFG_VBG_CFG_VBG_P50_MASK)

BCFG_VBG_CFG_VBG_P50_SHIFT

#define BCFG_VBG_CFG_VBG_P50_SHIFT   (0U)

BCFG_VBG_CFG_VBG_P65_GET

#define BCFG_VBG_CFG_VBG_P65_GET

(

x

)

(((uint32_t)(x) & BCFG_VBG_CFG_VBG_P65_MASK) >> BCFG_VBG_CFG_VBG_P65_SHIFT)

BCFG_VBG_CFG_VBG_P65_MASK

#define BCFG_VBG_CFG_VBG_P65_MASK   (0x1F00U)

BCFG_VBG_CFG_VBG_P65_SET

#define BCFG_VBG_CFG_VBG_P65_SET

(

x

)

(((uint32_t)(x) << BCFG_VBG_CFG_VBG_P65_SHIFT) & BCFG_VBG_CFG_VBG_P65_MASK)

BCFG_VBG_CFG_VBG_P65_SHIFT

#define BCFG_VBG_CFG_VBG_P65_SHIFT   (8U)

BCFG_VBG_CFG_VBG_TRIMMED_GET

#define BCFG_VBG_CFG_VBG_TRIMMED_GET

(

x

)

(((uint32_t)(x) & BCFG_VBG_CFG_VBG_TRIMMED_MASK) >> BCFG_VBG_CFG_VBG_TRIMMED_SHIFT)

BCFG_VBG_CFG_VBG_TRIMMED_MASK

#define BCFG_VBG_CFG_VBG_TRIMMED_MASK   (0x80000000UL)

BCFG_VBG_CFG_VBG_TRIMMED_SET

#define BCFG_VBG_CFG_VBG_TRIMMED_SET

(

x

)

(((uint32_t)(x) << BCFG_VBG_CFG_VBG_TRIMMED_SHIFT) & BCFG_VBG_CFG_VBG_TRIMMED_MASK)

BCFG_VBG_CFG_VBG_TRIMMED_SHIFT

#define BCFG_VBG_CFG_VBG_TRIMMED_SHIFT   (31U)

BCFG_XTAL32K_CFG_AMP_GET

#define BCFG_XTAL32K_CFG_AMP_GET

(

x

)

(((uint32_t)(x) & BCFG_XTAL32K_CFG_AMP_MASK) >> BCFG_XTAL32K_CFG_AMP_SHIFT)

BCFG_XTAL32K_CFG_AMP_MASK

#define BCFG_XTAL32K_CFG_AMP_MASK   (0x3U)

BCFG_XTAL32K_CFG_AMP_SET

#define BCFG_XTAL32K_CFG_AMP_SET

(

x

)

(((uint32_t)(x) << BCFG_XTAL32K_CFG_AMP_SHIFT) & BCFG_XTAL32K_CFG_AMP_MASK)

BCFG_XTAL32K_CFG_AMP_SHIFT

#define BCFG_XTAL32K_CFG_AMP_SHIFT   (0U)

BCFG_XTAL32K_CFG_CFG_GET

#define BCFG_XTAL32K_CFG_CFG_GET

(

x

)

(((uint32_t)(x) & BCFG_XTAL32K_CFG_CFG_MASK) >> BCFG_XTAL32K_CFG_CFG_SHIFT)

BCFG_XTAL32K_CFG_CFG_MASK

#define BCFG_XTAL32K_CFG_CFG_MASK   (0x10U)

BCFG_XTAL32K_CFG_CFG_SET

#define BCFG_XTAL32K_CFG_CFG_SET

(

x

)

(((uint32_t)(x) << BCFG_XTAL32K_CFG_CFG_SHIFT) & BCFG_XTAL32K_CFG_CFG_MASK)

BCFG_XTAL32K_CFG_CFG_SHIFT

#define BCFG_XTAL32K_CFG_CFG_SHIFT   (4U)

BCFG_XTAL32K_CFG_GMSEL_GET

#define BCFG_XTAL32K_CFG_GMSEL_GET

(

x

)

(((uint32_t)(x) & BCFG_XTAL32K_CFG_GMSEL_MASK) >> BCFG_XTAL32K_CFG_GMSEL_SHIFT)

BCFG_XTAL32K_CFG_GMSEL_MASK

#define BCFG_XTAL32K_CFG_GMSEL_MASK   (0x300U)

BCFG_XTAL32K_CFG_GMSEL_SET

#define BCFG_XTAL32K_CFG_GMSEL_SET

(

x

)

(((uint32_t)(x) << BCFG_XTAL32K_CFG_GMSEL_SHIFT) & BCFG_XTAL32K_CFG_GMSEL_MASK)

BCFG_XTAL32K_CFG_GMSEL_SHIFT

#define BCFG_XTAL32K_CFG_GMSEL_SHIFT   (8U)

BCFG_XTAL32K_CFG_HYST_EN_GET

#define BCFG_XTAL32K_CFG_HYST_EN_GET

(

x

)

(((uint32_t)(x) & BCFG_XTAL32K_CFG_HYST_EN_MASK) >> BCFG_XTAL32K_CFG_HYST_EN_SHIFT)

BCFG_XTAL32K_CFG_HYST_EN_MASK

#define BCFG_XTAL32K_CFG_HYST_EN_MASK   (0x1000U)

BCFG_XTAL32K_CFG_HYST_EN_SET

#define BCFG_XTAL32K_CFG_HYST_EN_SET

(

x

)

(((uint32_t)(x) << BCFG_XTAL32K_CFG_HYST_EN_SHIFT) & BCFG_XTAL32K_CFG_HYST_EN_MASK)

BCFG_XTAL32K_CFG_HYST_EN_SHIFT

#define BCFG_XTAL32K_CFG_HYST_EN_SHIFT   (12U)