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Data Structures | |
| struct | LCDC_Type |
| #define LCDC_BGND_CL_B_GET | ( | x | ) | (((uint32_t)(x) & LCDC_BGND_CL_B_MASK) >> LCDC_BGND_CL_B_SHIFT) |
| #define LCDC_BGND_CL_B_MASK (0xFFU) |
| #define LCDC_BGND_CL_B_SET | ( | x | ) | (((uint32_t)(x) << LCDC_BGND_CL_B_SHIFT) & LCDC_BGND_CL_B_MASK) |
| #define LCDC_BGND_CL_B_SHIFT (0U) |
| #define LCDC_BGND_CL_G_GET | ( | x | ) | (((uint32_t)(x) & LCDC_BGND_CL_G_MASK) >> LCDC_BGND_CL_G_SHIFT) |
| #define LCDC_BGND_CL_G_MASK (0xFF00U) |
| #define LCDC_BGND_CL_G_SET | ( | x | ) | (((uint32_t)(x) << LCDC_BGND_CL_G_SHIFT) & LCDC_BGND_CL_G_MASK) |
| #define LCDC_BGND_CL_G_SHIFT (8U) |
| #define LCDC_BGND_CL_R_GET | ( | x | ) | (((uint32_t)(x) & LCDC_BGND_CL_R_MASK) >> LCDC_BGND_CL_R_SHIFT) |
| #define LCDC_BGND_CL_R_MASK (0xFF0000UL) |
| #define LCDC_BGND_CL_R_SET | ( | x | ) | (((uint32_t)(x) << LCDC_BGND_CL_R_SHIFT) & LCDC_BGND_CL_R_MASK) |
| #define LCDC_BGND_CL_R_SHIFT (16U) |
| #define LCDC_CTRL_ARQOS_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_ARQOS_MASK) >> LCDC_CTRL_ARQOS_SHIFT) |
| #define LCDC_CTRL_ARQOS_MASK (0xF00000UL) |
| #define LCDC_CTRL_ARQOS_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_ARQOS_SHIFT) & LCDC_CTRL_ARQOS_MASK) |
| #define LCDC_CTRL_ARQOS_SHIFT (20U) |
| #define LCDC_CTRL_BGDCL4CLR_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_BGDCL4CLR_MASK) >> LCDC_CTRL_BGDCL4CLR_SHIFT) |
| #define LCDC_CTRL_BGDCL4CLR_MASK (0x1000000UL) |
| #define LCDC_CTRL_BGDCL4CLR_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_BGDCL4CLR_SHIFT) & LCDC_CTRL_BGDCL4CLR_MASK) |
| #define LCDC_CTRL_BGDCL4CLR_SHIFT (24U) |
| #define LCDC_CTRL_DISP_MODE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_DISP_MODE_MASK) >> LCDC_CTRL_DISP_MODE_SHIFT) |
| #define LCDC_CTRL_DISP_MODE_MASK (0x6000000UL) |
| #define LCDC_CTRL_DISP_MODE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_DISP_MODE_SHIFT) & LCDC_CTRL_DISP_MODE_MASK) |
| #define LCDC_CTRL_DISP_MODE_SHIFT (25U) |
| #define LCDC_CTRL_DISP_ON_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_DISP_ON_MASK) >> LCDC_CTRL_DISP_ON_SHIFT) |
| #define LCDC_CTRL_DISP_ON_MASK (0x40000000UL) |
| #define LCDC_CTRL_DISP_ON_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_DISP_ON_SHIFT) & LCDC_CTRL_DISP_ON_MASK) |
| #define LCDC_CTRL_DISP_ON_SHIFT (30U) |
| #define LCDC_CTRL_INV_HREF_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_INV_HREF_MASK) >> LCDC_CTRL_INV_HREF_SHIFT) |
| #define LCDC_CTRL_INV_HREF_MASK (0x4U) |
| #define LCDC_CTRL_INV_HREF_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_INV_HREF_SHIFT) & LCDC_CTRL_INV_HREF_MASK) |
| #define LCDC_CTRL_INV_HREF_SHIFT (2U) |
| #define LCDC_CTRL_INV_HSYNC_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_INV_HSYNC_MASK) >> LCDC_CTRL_INV_HSYNC_SHIFT) |
| #define LCDC_CTRL_INV_HSYNC_MASK (0x1U) |
| #define LCDC_CTRL_INV_HSYNC_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_INV_HSYNC_SHIFT) & LCDC_CTRL_INV_HSYNC_MASK) |
| #define LCDC_CTRL_INV_HSYNC_SHIFT (0U) |
| #define LCDC_CTRL_INV_PXCLK_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_INV_PXCLK_MASK) >> LCDC_CTRL_INV_PXCLK_SHIFT) |
| #define LCDC_CTRL_INV_PXCLK_MASK (0x8U) |
| #define LCDC_CTRL_INV_PXCLK_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_INV_PXCLK_SHIFT) & LCDC_CTRL_INV_PXCLK_MASK) |
| #define LCDC_CTRL_INV_PXCLK_SHIFT (3U) |
| #define LCDC_CTRL_INV_PXDATA_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_INV_PXDATA_MASK) >> LCDC_CTRL_INV_PXDATA_SHIFT) |
| #define LCDC_CTRL_INV_PXDATA_MASK (0x10U) |
| #define LCDC_CTRL_INV_PXDATA_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_INV_PXDATA_SHIFT) & LCDC_CTRL_INV_PXDATA_MASK) |
| #define LCDC_CTRL_INV_PXDATA_SHIFT (4U) |
| #define LCDC_CTRL_INV_VSYNC_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_INV_VSYNC_MASK) >> LCDC_CTRL_INV_VSYNC_SHIFT) |
| #define LCDC_CTRL_INV_VSYNC_MASK (0x2U) |
| #define LCDC_CTRL_INV_VSYNC_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_INV_VSYNC_SHIFT) & LCDC_CTRL_INV_VSYNC_MASK) |
| #define LCDC_CTRL_INV_VSYNC_SHIFT (1U) |
| #define LCDC_CTRL_LINE_PATTERN_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_LINE_PATTERN_MASK) >> LCDC_CTRL_LINE_PATTERN_SHIFT) |
| #define LCDC_CTRL_LINE_PATTERN_MASK (0x38000000UL) |
| #define LCDC_CTRL_LINE_PATTERN_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_LINE_PATTERN_SHIFT) & LCDC_CTRL_LINE_PATTERN_MASK) |
| #define LCDC_CTRL_LINE_PATTERN_SHIFT (27U) |
| #define LCDC_CTRL_SW_RST_GET | ( | x | ) | (((uint32_t)(x) & LCDC_CTRL_SW_RST_MASK) >> LCDC_CTRL_SW_RST_SHIFT) |
| #define LCDC_CTRL_SW_RST_MASK (0x80000000UL) |
| #define LCDC_CTRL_SW_RST_SET | ( | x | ) | (((uint32_t)(x) << LCDC_CTRL_SW_RST_SHIFT) & LCDC_CTRL_SW_RST_MASK) |
| #define LCDC_CTRL_SW_RST_SHIFT (31U) |
| #define LCDC_DISP_WN_SIZE_X_GET | ( | x | ) | (((uint32_t)(x) & LCDC_DISP_WN_SIZE_X_MASK) >> LCDC_DISP_WN_SIZE_X_SHIFT) |
| #define LCDC_DISP_WN_SIZE_X_MASK (0xFFFU) |
| #define LCDC_DISP_WN_SIZE_X_SET | ( | x | ) | (((uint32_t)(x) << LCDC_DISP_WN_SIZE_X_SHIFT) & LCDC_DISP_WN_SIZE_X_MASK) |
| #define LCDC_DISP_WN_SIZE_X_SHIFT (0U) |
| #define LCDC_DISP_WN_SIZE_Y_GET | ( | x | ) | (((uint32_t)(x) & LCDC_DISP_WN_SIZE_Y_MASK) >> LCDC_DISP_WN_SIZE_Y_SHIFT) |
| #define LCDC_DISP_WN_SIZE_Y_MASK (0xFFF0000UL) |
| #define LCDC_DISP_WN_SIZE_Y_SET | ( | x | ) | (((uint32_t)(x) << LCDC_DISP_WN_SIZE_Y_SHIFT) & LCDC_DISP_WN_SIZE_Y_MASK) |
| #define LCDC_DISP_WN_SIZE_Y_SHIFT (16U) |
| #define LCDC_DMA_ST_DMA0_DONE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_DMA_ST_DMA0_DONE_MASK) >> LCDC_DMA_ST_DMA0_DONE_SHIFT) |
| #define LCDC_DMA_ST_DMA0_DONE_MASK (0xFF00U) |
| #define LCDC_DMA_ST_DMA0_DONE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_DMA_ST_DMA0_DONE_SHIFT) & LCDC_DMA_ST_DMA0_DONE_MASK) |
| #define LCDC_DMA_ST_DMA0_DONE_SHIFT (8U) |
| #define LCDC_DMA_ST_DMA1_DONE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_DMA_ST_DMA1_DONE_MASK) >> LCDC_DMA_ST_DMA1_DONE_SHIFT) |
| #define LCDC_DMA_ST_DMA1_DONE_MASK (0xFF0000UL) |
| #define LCDC_DMA_ST_DMA1_DONE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_DMA_ST_DMA1_DONE_SHIFT) & LCDC_DMA_ST_DMA1_DONE_MASK) |
| #define LCDC_DMA_ST_DMA1_DONE_SHIFT (16U) |
| #define LCDC_DMA_ST_DMA_ERR_GET | ( | x | ) | (((uint32_t)(x) & LCDC_DMA_ST_DMA_ERR_MASK) >> LCDC_DMA_ST_DMA_ERR_SHIFT) |
| #define LCDC_DMA_ST_DMA_ERR_MASK (0xFF000000UL) |
| #define LCDC_DMA_ST_DMA_ERR_SET | ( | x | ) | (((uint32_t)(x) << LCDC_DMA_ST_DMA_ERR_SHIFT) & LCDC_DMA_ST_DMA_ERR_MASK) |
| #define LCDC_DMA_ST_DMA_ERR_SHIFT (24U) |
| #define LCDC_HSYNC_PARA_BP_GET | ( | x | ) | (((uint32_t)(x) & LCDC_HSYNC_PARA_BP_MASK) >> LCDC_HSYNC_PARA_BP_SHIFT) |
| #define LCDC_HSYNC_PARA_BP_MASK (0xFF800UL) |
| #define LCDC_HSYNC_PARA_BP_SET | ( | x | ) | (((uint32_t)(x) << LCDC_HSYNC_PARA_BP_SHIFT) & LCDC_HSYNC_PARA_BP_MASK) |
| #define LCDC_HSYNC_PARA_BP_SHIFT (11U) |
| #define LCDC_HSYNC_PARA_FP_GET | ( | x | ) | (((uint32_t)(x) & LCDC_HSYNC_PARA_FP_MASK) >> LCDC_HSYNC_PARA_FP_SHIFT) |
| #define LCDC_HSYNC_PARA_FP_MASK (0x7FC00000UL) |
| #define LCDC_HSYNC_PARA_FP_SET | ( | x | ) | (((uint32_t)(x) << LCDC_HSYNC_PARA_FP_SHIFT) & LCDC_HSYNC_PARA_FP_MASK) |
| #define LCDC_HSYNC_PARA_FP_SHIFT (22U) |
| #define LCDC_HSYNC_PARA_PW_GET | ( | x | ) | (((uint32_t)(x) & LCDC_HSYNC_PARA_PW_MASK) >> LCDC_HSYNC_PARA_PW_SHIFT) |
| #define LCDC_HSYNC_PARA_PW_MASK (0x1FFU) |
| #define LCDC_HSYNC_PARA_PW_SET | ( | x | ) | (((uint32_t)(x) << LCDC_HSYNC_PARA_PW_SHIFT) & LCDC_HSYNC_PARA_PW_MASK) |
| #define LCDC_HSYNC_PARA_PW_SHIFT (0U) |
| #define LCDC_INT_EN_DMA_DONE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_INT_EN_DMA_DONE_MASK) >> LCDC_INT_EN_DMA_DONE_SHIFT) |
| #define LCDC_INT_EN_DMA_DONE_MASK (0xFF0000UL) |
| #define LCDC_INT_EN_DMA_DONE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_INT_EN_DMA_DONE_SHIFT) & LCDC_INT_EN_DMA_DONE_MASK) |
| #define LCDC_INT_EN_DMA_DONE_SHIFT (16U) |
| #define LCDC_INT_EN_DMA_ERR_GET | ( | x | ) | (((uint32_t)(x) & LCDC_INT_EN_DMA_ERR_MASK) >> LCDC_INT_EN_DMA_ERR_SHIFT) |
| #define LCDC_INT_EN_DMA_ERR_MASK (0xFF000000UL) |
| #define LCDC_INT_EN_DMA_ERR_SET | ( | x | ) | (((uint32_t)(x) << LCDC_INT_EN_DMA_ERR_SHIFT) & LCDC_INT_EN_DMA_ERR_MASK) |
| #define LCDC_INT_EN_DMA_ERR_SHIFT (24U) |
| #define LCDC_INT_EN_UNDERRUN_GET | ( | x | ) | (((uint32_t)(x) & LCDC_INT_EN_UNDERRUN_MASK) >> LCDC_INT_EN_UNDERRUN_SHIFT) |
| #define LCDC_INT_EN_UNDERRUN_MASK (0x2U) |
| #define LCDC_INT_EN_UNDERRUN_SET | ( | x | ) | (((uint32_t)(x) << LCDC_INT_EN_UNDERRUN_SHIFT) & LCDC_INT_EN_UNDERRUN_MASK) |
| #define LCDC_INT_EN_UNDERRUN_SHIFT (1U) |
| #define LCDC_INT_EN_URGENT_UNDERRUN_GET | ( | x | ) | (((uint32_t)(x) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) >> LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) |
| #define LCDC_INT_EN_URGENT_UNDERRUN_MASK (0x8U) |
| #define LCDC_INT_EN_URGENT_UNDERRUN_SET | ( | x | ) | (((uint32_t)(x) << LCDC_INT_EN_URGENT_UNDERRUN_SHIFT) & LCDC_INT_EN_URGENT_UNDERRUN_MASK) |
| #define LCDC_INT_EN_URGENT_UNDERRUN_SHIFT (3U) |
| #define LCDC_INT_EN_VS_BLANK_GET | ( | x | ) | (((uint32_t)(x) & LCDC_INT_EN_VS_BLANK_MASK) >> LCDC_INT_EN_VS_BLANK_SHIFT) |
| #define LCDC_INT_EN_VS_BLANK_MASK (0x4U) |
| #define LCDC_INT_EN_VS_BLANK_SET | ( | x | ) | (((uint32_t)(x) << LCDC_INT_EN_VS_BLANK_SHIFT) & LCDC_INT_EN_VS_BLANK_MASK) |
| #define LCDC_INT_EN_VS_BLANK_SHIFT (2U) |
| #define LCDC_INT_EN_VSYNC_GET | ( | x | ) | (((uint32_t)(x) & LCDC_INT_EN_VSYNC_MASK) >> LCDC_INT_EN_VSYNC_SHIFT) |
| #define LCDC_INT_EN_VSYNC_MASK (0x1U) |
| #define LCDC_INT_EN_VSYNC_SET | ( | x | ) | (((uint32_t)(x) << LCDC_INT_EN_VSYNC_SHIFT) & LCDC_INT_EN_VSYNC_MASK) |
| #define LCDC_INT_EN_VSYNC_SHIFT (0U) |
| #define LCDC_LAYER_0 (0UL) |
| #define LCDC_LAYER_1 (1UL) |
| #define LCDC_LAYER_2 (2UL) |
| #define LCDC_LAYER_3 (3UL) |
| #define LCDC_LAYER_4 (4UL) |
| #define LCDC_LAYER_5 (5UL) |
| #define LCDC_LAYER_6 (6UL) |
| #define LCDC_LAYER_7 (7UL) |
| #define LCDC_LAYER_ALPHAS_IND_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_ALPHAS_IND_MASK) >> LCDC_LAYER_ALPHAS_IND_SHIFT) |
| #define LCDC_LAYER_ALPHAS_IND_MASK (0xFFU) |
| #define LCDC_LAYER_ALPHAS_IND_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_ALPHAS_IND_SHIFT) & LCDC_LAYER_ALPHAS_IND_MASK) |
| #define LCDC_LAYER_ALPHAS_IND_SHIFT (0U) |
| #define LCDC_LAYER_ALPHAS_LOCD_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_ALPHAS_LOCD_MASK) >> LCDC_LAYER_ALPHAS_LOCD_SHIFT) |
| #define LCDC_LAYER_ALPHAS_LOCD_MASK (0xFF00U) |
| #define LCDC_LAYER_ALPHAS_LOCD_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_ALPHAS_LOCD_SHIFT) & LCDC_LAYER_ALPHAS_LOCD_MASK) |
| #define LCDC_LAYER_ALPHAS_LOCD_SHIFT (8U) |
| #define LCDC_LAYER_BG_CL_ARGB_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_BG_CL_ARGB_MASK) >> LCDC_LAYER_BG_CL_ARGB_SHIFT) |
| #define LCDC_LAYER_BG_CL_ARGB_MASK (0xFFFFFFFFUL) |
| #define LCDC_LAYER_BG_CL_ARGB_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_BG_CL_ARGB_SHIFT) & LCDC_LAYER_BG_CL_ARGB_MASK) |
| #define LCDC_LAYER_BG_CL_ARGB_SHIFT (0U) |
| #define LCDC_LAYER_CSC_COEF0_C0_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_C0_MASK) >> LCDC_LAYER_CSC_COEF0_C0_SHIFT) |
| #define LCDC_LAYER_CSC_COEF0_C0_MASK (0x1FFC0000UL) |
| #define LCDC_LAYER_CSC_COEF0_C0_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_C0_SHIFT) & LCDC_LAYER_CSC_COEF0_C0_MASK) |
| #define LCDC_LAYER_CSC_COEF0_C0_SHIFT (18U) |
| #define LCDC_LAYER_CSC_COEF0_ENABLE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) >> LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) |
| #define LCDC_LAYER_CSC_COEF0_ENABLE_MASK (0x40000000UL) |
| #define LCDC_LAYER_CSC_COEF0_ENABLE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT) & LCDC_LAYER_CSC_COEF0_ENABLE_MASK) |
| #define LCDC_LAYER_CSC_COEF0_ENABLE_SHIFT (30U) |
| #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) |
| #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK (0x3FE00UL) |
| #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_UV_OFFSET_MASK) |
| #define LCDC_LAYER_CSC_COEF0_UV_OFFSET_SHIFT (9U) |
| #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) >> LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) |
| #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) |
| #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT) & LCDC_LAYER_CSC_COEF0_Y_OFFSET_MASK) |
| #define LCDC_LAYER_CSC_COEF0_Y_OFFSET_SHIFT (0U) |
| #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) >> LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) |
| #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK (0x80000000UL) |
| #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT) & LCDC_LAYER_CSC_COEF0_YCBCR_MODE_MASK) |
| #define LCDC_LAYER_CSC_COEF0_YCBCR_MODE_SHIFT (31U) |
| #define LCDC_LAYER_CSC_COEF1_C1_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C1_MASK) >> LCDC_LAYER_CSC_COEF1_C1_SHIFT) |
| #define LCDC_LAYER_CSC_COEF1_C1_MASK (0x7FF0000UL) |
| #define LCDC_LAYER_CSC_COEF1_C1_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C1_SHIFT) & LCDC_LAYER_CSC_COEF1_C1_MASK) |
| #define LCDC_LAYER_CSC_COEF1_C1_SHIFT (16U) |
| #define LCDC_LAYER_CSC_COEF1_C4_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF1_C4_MASK) >> LCDC_LAYER_CSC_COEF1_C4_SHIFT) |
| #define LCDC_LAYER_CSC_COEF1_C4_MASK (0x7FFU) |
| #define LCDC_LAYER_CSC_COEF1_C4_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF1_C4_SHIFT) & LCDC_LAYER_CSC_COEF1_C4_MASK) |
| #define LCDC_LAYER_CSC_COEF1_C4_SHIFT (0U) |
| #define LCDC_LAYER_CSC_COEF2_C2_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C2_MASK) >> LCDC_LAYER_CSC_COEF2_C2_SHIFT) |
| #define LCDC_LAYER_CSC_COEF2_C2_MASK (0x7FF0000UL) |
| #define LCDC_LAYER_CSC_COEF2_C2_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C2_SHIFT) & LCDC_LAYER_CSC_COEF2_C2_MASK) |
| #define LCDC_LAYER_CSC_COEF2_C2_SHIFT (16U) |
| #define LCDC_LAYER_CSC_COEF2_C3_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_CSC_COEF2_C3_MASK) >> LCDC_LAYER_CSC_COEF2_C3_SHIFT) |
| #define LCDC_LAYER_CSC_COEF2_C3_MASK (0x7FFU) |
| #define LCDC_LAYER_CSC_COEF2_C3_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_CSC_COEF2_C3_SHIFT) & LCDC_LAYER_CSC_COEF2_C3_MASK) |
| #define LCDC_LAYER_CSC_COEF2_C3_SHIFT (0U) |
| #define LCDC_LAYER_LAYCTRL_AB_MODE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) >> LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_AB_MODE_MASK (0x3CU) |
| #define LCDC_LAYER_LAYCTRL_AB_MODE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT) & LCDC_LAYER_LAYCTRL_AB_MODE_MASK) |
| #define LCDC_LAYER_LAYCTRL_AB_MODE_SHIFT (2U) |
| #define LCDC_LAYER_LAYCTRL_EN_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_EN_MASK) >> LCDC_LAYER_LAYCTRL_EN_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_EN_MASK (0x1U) |
| #define LCDC_LAYER_LAYCTRL_EN_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_EN_SHIFT) & LCDC_LAYER_LAYCTRL_EN_MASK) |
| #define LCDC_LAYER_LAYCTRL_EN_SHIFT (0U) |
| #define LCDC_LAYER_LAYCTRL_INALPHA_OP_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK (0xC0U) |
| #define LCDC_LAYER_LAYCTRL_INALPHA_OP_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_INALPHA_OP_MASK) |
| #define LCDC_LAYER_LAYCTRL_INALPHA_OP_SHIFT (6U) |
| #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) >> LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK (0x300U) |
| #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT) & LCDC_LAYER_LAYCTRL_LOCALPHA_OP_MASK) |
| #define LCDC_LAYER_LAYCTRL_LOCALPHA_OP_SHIFT (8U) |
| #define LCDC_LAYER_LAYCTRL_PACK_DIR_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) >> LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_PACK_DIR_MASK (0x80000UL) |
| #define LCDC_LAYER_LAYCTRL_PACK_DIR_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT) & LCDC_LAYER_LAYCTRL_PACK_DIR_MASK) |
| #define LCDC_LAYER_LAYCTRL_PACK_DIR_SHIFT (19U) |
| #define LCDC_LAYER_LAYCTRL_PIXFORMAT_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) >> LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK (0x3C00U) |
| #define LCDC_LAYER_LAYCTRL_PIXFORMAT_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_PIXFORMAT_MASK) |
| #define LCDC_LAYER_LAYCTRL_PIXFORMAT_SHIFT (10U) |
| #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) >> LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK (0x10000UL) |
| #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT) & LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_MASK) |
| #define LCDC_LAYER_LAYCTRL_SHADOW_LOAD_EN_SHIFT (16U) |
| #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) >> LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) |
| #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK (0xC000U) |
| #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT) & LCDC_LAYER_LAYCTRL_YUV_FORMAT_MASK) |
| #define LCDC_LAYER_LAYCTRL_YUV_FORMAT_SHIFT (14U) |
| #define LCDC_LAYER_LAYPOS_X_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYPOS_X_MASK) >> LCDC_LAYER_LAYPOS_X_SHIFT) |
| #define LCDC_LAYER_LAYPOS_X_MASK (0xFFFFU) |
| #define LCDC_LAYER_LAYPOS_X_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYPOS_X_SHIFT) & LCDC_LAYER_LAYPOS_X_MASK) |
| #define LCDC_LAYER_LAYPOS_X_SHIFT (0U) |
| #define LCDC_LAYER_LAYPOS_Y_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYPOS_Y_MASK) >> LCDC_LAYER_LAYPOS_Y_SHIFT) |
| #define LCDC_LAYER_LAYPOS_Y_MASK (0xFFFF0000UL) |
| #define LCDC_LAYER_LAYPOS_Y_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYPOS_Y_SHIFT) & LCDC_LAYER_LAYPOS_Y_MASK) |
| #define LCDC_LAYER_LAYPOS_Y_SHIFT (16U) |
| #define LCDC_LAYER_LAYSIZE_HEIGHT_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) >> LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) |
| #define LCDC_LAYER_LAYSIZE_HEIGHT_MASK (0xFFF0000UL) |
| #define LCDC_LAYER_LAYSIZE_HEIGHT_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT) & LCDC_LAYER_LAYSIZE_HEIGHT_MASK) |
| #define LCDC_LAYER_LAYSIZE_HEIGHT_SHIFT (16U) |
| #define LCDC_LAYER_LAYSIZE_WIDTH_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) >> LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) |
| #define LCDC_LAYER_LAYSIZE_WIDTH_MASK (0xFFFU) |
| #define LCDC_LAYER_LAYSIZE_WIDTH_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LAYSIZE_WIDTH_SHIFT) & LCDC_LAYER_LAYSIZE_WIDTH_MASK) |
| #define LCDC_LAYER_LAYSIZE_WIDTH_SHIFT (0U) |
| #define LCDC_LAYER_LINECFG_MAX_OT_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LINECFG_MAX_OT_MASK) >> LCDC_LAYER_LINECFG_MAX_OT_SHIFT) |
| #define LCDC_LAYER_LINECFG_MAX_OT_MASK (0xE00000UL) |
| #define LCDC_LAYER_LINECFG_MAX_OT_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LINECFG_MAX_OT_SHIFT) & LCDC_LAYER_LINECFG_MAX_OT_MASK) |
| #define LCDC_LAYER_LINECFG_MAX_OT_SHIFT (21U) |
| #define LCDC_LAYER_LINECFG_MPT_SIZE_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) >> LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) |
| #define LCDC_LAYER_LINECFG_MPT_SIZE_MASK (0xE0000000UL) |
| #define LCDC_LAYER_LINECFG_MPT_SIZE_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT) & LCDC_LAYER_LINECFG_MPT_SIZE_MASK) |
| #define LCDC_LAYER_LINECFG_MPT_SIZE_SHIFT (29U) |
| #define LCDC_LAYER_LINECFG_PITCH_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_LINECFG_PITCH_MASK) >> LCDC_LAYER_LINECFG_PITCH_SHIFT) |
| #define LCDC_LAYER_LINECFG_PITCH_MASK (0xFFFFU) |
| #define LCDC_LAYER_LINECFG_PITCH_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_LINECFG_PITCH_SHIFT) & LCDC_LAYER_LINECFG_PITCH_MASK) |
| #define LCDC_LAYER_LINECFG_PITCH_SHIFT (0U) |
| #define LCDC_LAYER_START0_ADDR0_GET | ( | x | ) | (((uint32_t)(x) & LCDC_LAYER_START0_ADDR0_MASK) >> LCDC_LAYER_START0_ADDR0_SHIFT) |
| #define LCDC_LAYER_START0_ADDR0_MASK (0xFFFFFFFFUL) |
| #define LCDC_LAYER_START0_ADDR0_SET | ( | x | ) | (((uint32_t)(x) << LCDC_LAYER_START0_ADDR0_SHIFT) & LCDC_LAYER_START0_ADDR0_MASK) |
| #define LCDC_LAYER_START0_ADDR0_SHIFT (0U) |
| #define LCDC_ST_UNDERRUN_GET | ( | x | ) | (((uint32_t)(x) & LCDC_ST_UNDERRUN_MASK) >> LCDC_ST_UNDERRUN_SHIFT) |
| #define LCDC_ST_UNDERRUN_MASK (0x2U) |
| #define LCDC_ST_UNDERRUN_SET | ( | x | ) | (((uint32_t)(x) << LCDC_ST_UNDERRUN_SHIFT) & LCDC_ST_UNDERRUN_MASK) |
| #define LCDC_ST_UNDERRUN_SHIFT (1U) |
| #define LCDC_ST_URGENT_UNDERRUN_GET | ( | x | ) | (((uint32_t)(x) & LCDC_ST_URGENT_UNDERRUN_MASK) >> LCDC_ST_URGENT_UNDERRUN_SHIFT) |
| #define LCDC_ST_URGENT_UNDERRUN_MASK (0x8U) |
| #define LCDC_ST_URGENT_UNDERRUN_SET | ( | x | ) | (((uint32_t)(x) << LCDC_ST_URGENT_UNDERRUN_SHIFT) & LCDC_ST_URGENT_UNDERRUN_MASK) |
| #define LCDC_ST_URGENT_UNDERRUN_SHIFT (3U) |
| #define LCDC_ST_VS_BLANK_GET | ( | x | ) | (((uint32_t)(x) & LCDC_ST_VS_BLANK_MASK) >> LCDC_ST_VS_BLANK_SHIFT) |
| #define LCDC_ST_VS_BLANK_MASK (0x4U) |
| #define LCDC_ST_VS_BLANK_SET | ( | x | ) | (((uint32_t)(x) << LCDC_ST_VS_BLANK_SHIFT) & LCDC_ST_VS_BLANK_MASK) |
| #define LCDC_ST_VS_BLANK_SHIFT (2U) |
| #define LCDC_ST_VSYNC_GET | ( | x | ) | (((uint32_t)(x) & LCDC_ST_VSYNC_MASK) >> LCDC_ST_VSYNC_SHIFT) |
| #define LCDC_ST_VSYNC_MASK (0x1U) |
| #define LCDC_ST_VSYNC_SET | ( | x | ) | (((uint32_t)(x) << LCDC_ST_VSYNC_SHIFT) & LCDC_ST_VSYNC_MASK) |
| #define LCDC_ST_VSYNC_SHIFT (0U) |
| #define LCDC_TXFIFO_THRSH_GET | ( | x | ) | (((uint32_t)(x) & LCDC_TXFIFO_THRSH_MASK) >> LCDC_TXFIFO_THRSH_SHIFT) |
| #define LCDC_TXFIFO_THRSH_MASK (0xFFU) |
| #define LCDC_TXFIFO_THRSH_SET | ( | x | ) | (((uint32_t)(x) << LCDC_TXFIFO_THRSH_SHIFT) & LCDC_TXFIFO_THRSH_MASK) |
| #define LCDC_TXFIFO_THRSH_SHIFT (0U) |
| #define LCDC_VSYNC_PARA_BP_GET | ( | x | ) | (((uint32_t)(x) & LCDC_VSYNC_PARA_BP_MASK) >> LCDC_VSYNC_PARA_BP_SHIFT) |
| #define LCDC_VSYNC_PARA_BP_MASK (0xFF800UL) |
| #define LCDC_VSYNC_PARA_BP_SET | ( | x | ) | (((uint32_t)(x) << LCDC_VSYNC_PARA_BP_SHIFT) & LCDC_VSYNC_PARA_BP_MASK) |
| #define LCDC_VSYNC_PARA_BP_SHIFT (11U) |
| #define LCDC_VSYNC_PARA_FP_GET | ( | x | ) | (((uint32_t)(x) & LCDC_VSYNC_PARA_FP_MASK) >> LCDC_VSYNC_PARA_FP_SHIFT) |
| #define LCDC_VSYNC_PARA_FP_MASK (0x7FC00000UL) |
| #define LCDC_VSYNC_PARA_FP_SET | ( | x | ) | (((uint32_t)(x) << LCDC_VSYNC_PARA_FP_SHIFT) & LCDC_VSYNC_PARA_FP_MASK) |
| #define LCDC_VSYNC_PARA_FP_SHIFT (22U) |
| #define LCDC_VSYNC_PARA_PW_GET | ( | x | ) | (((uint32_t)(x) & LCDC_VSYNC_PARA_PW_MASK) >> LCDC_VSYNC_PARA_PW_SHIFT) |
| #define LCDC_VSYNC_PARA_PW_MASK (0x1FFU) |
| #define LCDC_VSYNC_PARA_PW_SET | ( | x | ) | (((uint32_t)(x) << LCDC_VSYNC_PARA_PW_SHIFT) & LCDC_VSYNC_PARA_PW_MASK) |
| #define LCDC_VSYNC_PARA_PW_SHIFT (0U) |